1 //===-- ARMAsmPrinter.cpp - Print machine code to an ARM .s file ----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains a printer that converts from our internal representation
11 // of machine-dependent LLVM code to GAS-format ARM assembly language.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "asm-printer"
17 #include "ARMAsmPrinter.h"
18 #include "ARMAddressingModes.h"
19 #include "ARMBuildAttrs.h"
20 #include "ARMBaseRegisterInfo.h"
21 #include "ARMConstantPoolValue.h"
22 #include "ARMMachineFunctionInfo.h"
23 #include "ARMTargetMachine.h"
24 #include "ARMTargetObjectFile.h"
25 #include "InstPrinter/ARMInstPrinter.h"
26 #include "llvm/Analysis/DebugInfo.h"
27 #include "llvm/Constants.h"
28 #include "llvm/Module.h"
29 #include "llvm/Type.h"
30 #include "llvm/Assembly/Writer.h"
31 #include "llvm/CodeGen/MachineModuleInfoImpls.h"
32 #include "llvm/CodeGen/MachineFunctionPass.h"
33 #include "llvm/CodeGen/MachineJumpTableInfo.h"
34 #include "llvm/MC/MCAsmInfo.h"
35 #include "llvm/MC/MCAssembler.h"
36 #include "llvm/MC/MCContext.h"
37 #include "llvm/MC/MCExpr.h"
38 #include "llvm/MC/MCInst.h"
39 #include "llvm/MC/MCSectionMachO.h"
40 #include "llvm/MC/MCObjectStreamer.h"
41 #include "llvm/MC/MCStreamer.h"
42 #include "llvm/MC/MCSymbol.h"
43 #include "llvm/Target/Mangler.h"
44 #include "llvm/Target/TargetData.h"
45 #include "llvm/Target/TargetMachine.h"
46 #include "llvm/Target/TargetOptions.h"
47 #include "llvm/Target/TargetRegistry.h"
48 #include "llvm/ADT/SmallPtrSet.h"
49 #include "llvm/ADT/SmallString.h"
50 #include "llvm/ADT/StringExtras.h"
51 #include "llvm/Support/CommandLine.h"
52 #include "llvm/Support/Debug.h"
53 #include "llvm/Support/ErrorHandling.h"
54 #include "llvm/Support/raw_ostream.h"
60 // Per section and per symbol attributes are not supported.
61 // To implement them we would need the ability to delay this emission
62 // until the assembly file is fully parsed/generated as only then do we
63 // know the symbol and section numbers.
64 class AttributeEmitter {
66 virtual void MaybeSwitchVendor(StringRef Vendor) = 0;
67 virtual void EmitAttribute(unsigned Attribute, unsigned Value) = 0;
68 virtual void Finish() = 0;
69 virtual ~AttributeEmitter() {}
72 class AsmAttributeEmitter : public AttributeEmitter {
76 AsmAttributeEmitter(MCStreamer &Streamer_) : Streamer(Streamer_) {}
77 void MaybeSwitchVendor(StringRef Vendor) { }
79 void EmitAttribute(unsigned Attribute, unsigned Value) {
80 Streamer.EmitRawText("\t.eabi_attribute " +
81 Twine(Attribute) + ", " + Twine(Value));
87 class ObjectAttributeEmitter : public AttributeEmitter {
88 MCObjectStreamer &Streamer;
89 StringRef CurrentVendor;
90 SmallString<64> Contents;
93 ObjectAttributeEmitter(MCObjectStreamer &Streamer_) :
94 Streamer(Streamer_), CurrentVendor("") { }
96 void MaybeSwitchVendor(StringRef Vendor) {
97 assert(!Vendor.empty() && "Vendor cannot be empty.");
99 if (CurrentVendor.empty())
100 CurrentVendor = Vendor;
101 else if (CurrentVendor == Vendor)
106 CurrentVendor = Vendor;
108 assert(Contents.size() == 0);
111 void EmitAttribute(unsigned Attribute, unsigned Value) {
112 // FIXME: should be ULEB
113 Contents += Attribute;
118 const size_t ContentsSize = Contents.size();
120 // Vendor size + Vendor name + '\0'
121 const size_t VendorHeaderSize = 4 + CurrentVendor.size() + 1;
124 const size_t TagHeaderSize = 1 + 4;
126 Streamer.EmitIntValue(VendorHeaderSize + TagHeaderSize + ContentsSize, 4);
127 Streamer.EmitBytes(CurrentVendor, 0);
128 Streamer.EmitIntValue(0, 1); // '\0'
130 Streamer.EmitIntValue(ARMBuildAttrs::File, 1);
131 Streamer.EmitIntValue(TagHeaderSize + ContentsSize, 4);
133 Streamer.EmitBytes(Contents, 0);
139 } // end of anonymous namespace
141 MachineLocation ARMAsmPrinter::
142 getDebugValueLocation(const MachineInstr *MI) const {
143 MachineLocation Location;
144 assert(MI->getNumOperands() == 4 && "Invalid no. of machine operands!");
145 // Frame address. Currently handles register +- offset only.
146 if (MI->getOperand(0).isReg() && MI->getOperand(1).isImm())
147 Location.set(MI->getOperand(0).getReg(), MI->getOperand(1).getImm());
149 DEBUG(dbgs() << "DBG_VALUE instruction ignored! " << *MI << "\n");
154 void ARMAsmPrinter::EmitFunctionEntryLabel() {
155 if (AFI->isThumbFunction()) {
156 OutStreamer.EmitAssemblerFlag(MCAF_Code16);
157 OutStreamer.EmitThumbFunc(Subtarget->isTargetDarwin()? CurrentFnSym : 0);
160 OutStreamer.EmitLabel(CurrentFnSym);
163 /// runOnMachineFunction - This uses the EmitInstruction()
164 /// method to print assembly for each instruction.
166 bool ARMAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
167 AFI = MF.getInfo<ARMFunctionInfo>();
168 MCP = MF.getConstantPool();
170 return AsmPrinter::runOnMachineFunction(MF);
173 void ARMAsmPrinter::printOperand(const MachineInstr *MI, int OpNum,
174 raw_ostream &O, const char *Modifier) {
175 const MachineOperand &MO = MI->getOperand(OpNum);
176 unsigned TF = MO.getTargetFlags();
178 switch (MO.getType()) {
180 assert(0 && "<unknown operand type>");
181 case MachineOperand::MO_Register: {
182 unsigned Reg = MO.getReg();
183 assert(TargetRegisterInfo::isPhysicalRegister(Reg));
184 assert(!MO.getSubReg() && "Subregs should be eliminated!");
185 O << ARMInstPrinter::getRegisterName(Reg);
188 case MachineOperand::MO_Immediate: {
189 int64_t Imm = MO.getImm();
191 if ((Modifier && strcmp(Modifier, "lo16") == 0) ||
192 (TF & ARMII::MO_LO16))
194 else if ((Modifier && strcmp(Modifier, "hi16") == 0) ||
195 (TF & ARMII::MO_HI16))
200 case MachineOperand::MO_MachineBasicBlock:
201 O << *MO.getMBB()->getSymbol();
203 case MachineOperand::MO_GlobalAddress: {
204 const GlobalValue *GV = MO.getGlobal();
205 if ((Modifier && strcmp(Modifier, "lo16") == 0) ||
206 (TF & ARMII::MO_LO16))
208 else if ((Modifier && strcmp(Modifier, "hi16") == 0) ||
209 (TF & ARMII::MO_HI16))
211 O << *Mang->getSymbol(GV);
213 printOffset(MO.getOffset(), O);
214 if (TF == ARMII::MO_PLT)
218 case MachineOperand::MO_ExternalSymbol: {
219 O << *GetExternalSymbolSymbol(MO.getSymbolName());
220 if (TF == ARMII::MO_PLT)
224 case MachineOperand::MO_ConstantPoolIndex:
225 O << *GetCPISymbol(MO.getIndex());
227 case MachineOperand::MO_JumpTableIndex:
228 O << *GetJTISymbol(MO.getIndex());
233 //===--------------------------------------------------------------------===//
235 MCSymbol *ARMAsmPrinter::
236 GetARMSetPICJumpTableLabel2(unsigned uid, unsigned uid2,
237 const MachineBasicBlock *MBB) const {
238 SmallString<60> Name;
239 raw_svector_ostream(Name) << MAI->getPrivateGlobalPrefix()
240 << getFunctionNumber() << '_' << uid << '_' << uid2
241 << "_set_" << MBB->getNumber();
242 return OutContext.GetOrCreateSymbol(Name.str());
245 MCSymbol *ARMAsmPrinter::
246 GetARMJTIPICJumpTableLabel2(unsigned uid, unsigned uid2) const {
247 SmallString<60> Name;
248 raw_svector_ostream(Name) << MAI->getPrivateGlobalPrefix() << "JTI"
249 << getFunctionNumber() << '_' << uid << '_' << uid2;
250 return OutContext.GetOrCreateSymbol(Name.str());
254 MCSymbol *ARMAsmPrinter::GetARMSJLJEHLabel(void) const {
255 SmallString<60> Name;
256 raw_svector_ostream(Name) << MAI->getPrivateGlobalPrefix() << "SJLJEH"
257 << getFunctionNumber();
258 return OutContext.GetOrCreateSymbol(Name.str());
261 bool ARMAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
262 unsigned AsmVariant, const char *ExtraCode,
264 // Does this asm operand have a single letter operand modifier?
265 if (ExtraCode && ExtraCode[0]) {
266 if (ExtraCode[1] != 0) return true; // Unknown modifier.
268 switch (ExtraCode[0]) {
269 default: return true; // Unknown modifier.
270 case 'a': // Print as a memory address.
271 if (MI->getOperand(OpNum).isReg()) {
273 << ARMInstPrinter::getRegisterName(MI->getOperand(OpNum).getReg())
278 case 'c': // Don't print "#" before an immediate operand.
279 if (!MI->getOperand(OpNum).isImm())
281 O << MI->getOperand(OpNum).getImm();
283 case 'P': // Print a VFP double precision register.
284 case 'q': // Print a NEON quad precision register.
285 printOperand(MI, OpNum, O);
290 // These modifiers are not yet supported.
295 printOperand(MI, OpNum, O);
299 bool ARMAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI,
300 unsigned OpNum, unsigned AsmVariant,
301 const char *ExtraCode,
303 if (ExtraCode && ExtraCode[0])
304 return true; // Unknown modifier.
306 const MachineOperand &MO = MI->getOperand(OpNum);
307 assert(MO.isReg() && "unexpected inline asm memory operand");
308 O << "[" << ARMInstPrinter::getRegisterName(MO.getReg()) << "]";
312 void ARMAsmPrinter::EmitStartOfAsmFile(Module &M) {
313 if (Subtarget->isTargetDarwin()) {
314 Reloc::Model RelocM = TM.getRelocationModel();
315 if (RelocM == Reloc::PIC_ || RelocM == Reloc::DynamicNoPIC) {
316 // Declare all the text sections up front (before the DWARF sections
317 // emitted by AsmPrinter::doInitialization) so the assembler will keep
318 // them together at the beginning of the object file. This helps
319 // avoid out-of-range branches that are due a fundamental limitation of
320 // the way symbol offsets are encoded with the current Darwin ARM
322 const TargetLoweringObjectFileMachO &TLOFMacho =
323 static_cast<const TargetLoweringObjectFileMachO &>(
324 getObjFileLowering());
325 OutStreamer.SwitchSection(TLOFMacho.getTextSection());
326 OutStreamer.SwitchSection(TLOFMacho.getTextCoalSection());
327 OutStreamer.SwitchSection(TLOFMacho.getConstTextCoalSection());
328 if (RelocM == Reloc::DynamicNoPIC) {
329 const MCSection *sect =
330 OutContext.getMachOSection("__TEXT", "__symbol_stub4",
331 MCSectionMachO::S_SYMBOL_STUBS,
332 12, SectionKind::getText());
333 OutStreamer.SwitchSection(sect);
335 const MCSection *sect =
336 OutContext.getMachOSection("__TEXT", "__picsymbolstub4",
337 MCSectionMachO::S_SYMBOL_STUBS,
338 16, SectionKind::getText());
339 OutStreamer.SwitchSection(sect);
341 const MCSection *StaticInitSect =
342 OutContext.getMachOSection("__TEXT", "__StaticInit",
343 MCSectionMachO::S_REGULAR |
344 MCSectionMachO::S_ATTR_PURE_INSTRUCTIONS,
345 SectionKind::getText());
346 OutStreamer.SwitchSection(StaticInitSect);
350 // Use unified assembler syntax.
351 OutStreamer.EmitAssemblerFlag(MCAF_SyntaxUnified);
353 // Emit ARM Build Attributes
354 if (Subtarget->isTargetELF()) {
361 void ARMAsmPrinter::EmitEndOfAsmFile(Module &M) {
362 if (Subtarget->isTargetDarwin()) {
363 // All darwin targets use mach-o.
364 const TargetLoweringObjectFileMachO &TLOFMacho =
365 static_cast<const TargetLoweringObjectFileMachO &>(getObjFileLowering());
366 MachineModuleInfoMachO &MMIMacho =
367 MMI->getObjFileInfo<MachineModuleInfoMachO>();
369 // Output non-lazy-pointers for external and common global variables.
370 MachineModuleInfoMachO::SymbolListTy Stubs = MMIMacho.GetGVStubList();
372 if (!Stubs.empty()) {
373 // Switch with ".non_lazy_symbol_pointer" directive.
374 OutStreamer.SwitchSection(TLOFMacho.getNonLazySymbolPointerSection());
376 for (unsigned i = 0, e = Stubs.size(); i != e; ++i) {
378 OutStreamer.EmitLabel(Stubs[i].first);
379 // .indirect_symbol _foo
380 MachineModuleInfoImpl::StubValueTy &MCSym = Stubs[i].second;
381 OutStreamer.EmitSymbolAttribute(MCSym.getPointer(),MCSA_IndirectSymbol);
384 // External to current translation unit.
385 OutStreamer.EmitIntValue(0, 4/*size*/, 0/*addrspace*/);
387 // Internal to current translation unit.
389 // When we place the LSDA into the TEXT section, the type info
390 // pointers need to be indirect and pc-rel. We accomplish this by
391 // using NLPs; however, sometimes the types are local to the file.
392 // We need to fill in the value for the NLP in those cases.
393 OutStreamer.EmitValue(MCSymbolRefExpr::Create(MCSym.getPointer(),
395 4/*size*/, 0/*addrspace*/);
399 OutStreamer.AddBlankLine();
402 Stubs = MMIMacho.GetHiddenGVStubList();
403 if (!Stubs.empty()) {
404 OutStreamer.SwitchSection(getObjFileLowering().getDataSection());
406 for (unsigned i = 0, e = Stubs.size(); i != e; ++i) {
408 OutStreamer.EmitLabel(Stubs[i].first);
410 OutStreamer.EmitValue(MCSymbolRefExpr::
411 Create(Stubs[i].second.getPointer(),
413 4/*size*/, 0/*addrspace*/);
417 OutStreamer.AddBlankLine();
420 // Funny Darwin hack: This flag tells the linker that no global symbols
421 // contain code that falls through to other global symbols (e.g. the obvious
422 // implementation of multiple entry points). If this doesn't occur, the
423 // linker can safely perform dead code stripping. Since LLVM never
424 // generates code that does this, it is always safe to set.
425 OutStreamer.EmitAssemblerFlag(MCAF_SubsectionsViaSymbols);
429 //===----------------------------------------------------------------------===//
430 // Helper routines for EmitStartOfAsmFile() and EmitEndOfAsmFile()
432 // The following seem like one-off assembler flags, but they actually need
433 // to appear in the .ARM.attributes section in ELF.
434 // Instead of subclassing the MCELFStreamer, we do the work here.
436 void ARMAsmPrinter::emitAttributes() {
438 emitARMAttributeSection();
440 AttributeEmitter *AttrEmitter;
441 if (OutStreamer.hasRawTextSupport())
442 AttrEmitter = new AsmAttributeEmitter(OutStreamer);
444 MCObjectStreamer &O = static_cast<MCObjectStreamer&>(OutStreamer);
445 AttrEmitter = new ObjectAttributeEmitter(O);
448 AttrEmitter->MaybeSwitchVendor("aeabi");
450 std::string CPUString = Subtarget->getCPUString();
451 if (OutStreamer.hasRawTextSupport()) {
452 if (CPUString != "generic")
453 OutStreamer.EmitRawText(StringRef("\t.cpu ") + CPUString);
455 assert(CPUString == "generic" && "Unsupported .cpu attribute for ELF/.o");
456 // FIXME: Why these defaults?
457 AttrEmitter->EmitAttribute(ARMBuildAttrs::CPU_arch, ARMBuildAttrs::v4T);
458 AttrEmitter->EmitAttribute(ARMBuildAttrs::ARM_ISA_use, 1);
459 AttrEmitter->EmitAttribute(ARMBuildAttrs::THUMB_ISA_use, 1);
462 // FIXME: Emit FPU type
463 if (Subtarget->hasVFP2())
464 AttrEmitter->EmitAttribute(ARMBuildAttrs::VFP_arch, 2);
466 // Signal various FP modes.
468 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_FP_denormal, 1);
469 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_FP_exceptions, 1);
472 if (NoInfsFPMath && NoNaNsFPMath)
473 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_FP_number_model, 1);
475 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_FP_number_model, 3);
477 // 8-bytes alignment stuff.
478 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_align8_needed, 1);
479 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_align8_preserved, 1);
481 // Hard float. Use both S and D registers and conform to AAPCS-VFP.
482 if (Subtarget->isAAPCS_ABI() && FloatABIType == FloatABI::Hard) {
483 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_HardFP_use, 3);
484 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_VFP_args, 1);
486 // FIXME: Should we signal R9 usage?
488 AttrEmitter->EmitAttribute(ARMBuildAttrs::DIV_use, 1);
490 AttrEmitter->Finish();
494 void ARMAsmPrinter::emitARMAttributeSection() {
496 // [ <section-length> "vendor-name"
497 // [ <file-tag> <size> <attribute>*
498 // | <section-tag> <size> <section-number>* 0 <attribute>*
499 // | <symbol-tag> <size> <symbol-number>* 0 <attribute>*
503 if (OutStreamer.hasRawTextSupport())
506 const ARMElfTargetObjectFile &TLOFELF =
507 static_cast<const ARMElfTargetObjectFile &>
508 (getObjFileLowering());
510 OutStreamer.SwitchSection(TLOFELF.getAttributesSection());
513 OutStreamer.EmitIntValue(0x41, 1);
516 //===----------------------------------------------------------------------===//
518 static MCSymbol *getPICLabel(const char *Prefix, unsigned FunctionNumber,
519 unsigned LabelId, MCContext &Ctx) {
521 MCSymbol *Label = Ctx.GetOrCreateSymbol(Twine(Prefix)
522 + "PC" + Twine(FunctionNumber) + "_" + Twine(LabelId));
526 static MCSymbolRefExpr::VariantKind
527 getModifierVariantKind(ARMCP::ARMCPModifier Modifier) {
529 default: llvm_unreachable("Unknown modifier!");
530 case ARMCP::no_modifier: return MCSymbolRefExpr::VK_None;
531 case ARMCP::TLSGD: return MCSymbolRefExpr::VK_ARM_TLSGD;
532 case ARMCP::TPOFF: return MCSymbolRefExpr::VK_ARM_TPOFF;
533 case ARMCP::GOTTPOFF: return MCSymbolRefExpr::VK_ARM_GOTTPOFF;
534 case ARMCP::GOT: return MCSymbolRefExpr::VK_ARM_GOT;
535 case ARMCP::GOTOFF: return MCSymbolRefExpr::VK_ARM_GOTOFF;
537 return MCSymbolRefExpr::VK_None;
541 EmitMachineConstantPoolValue(MachineConstantPoolValue *MCPV) {
542 int Size = TM.getTargetData()->getTypeAllocSize(MCPV->getType());
544 ARMConstantPoolValue *ACPV = static_cast<ARMConstantPoolValue*>(MCPV);
547 if (ACPV->isLSDA()) {
548 SmallString<128> Str;
549 raw_svector_ostream OS(Str);
550 OS << MAI->getPrivateGlobalPrefix() << "_LSDA_" << getFunctionNumber();
551 MCSym = OutContext.GetOrCreateSymbol(OS.str());
552 } else if (ACPV->isBlockAddress()) {
553 MCSym = GetBlockAddressSymbol(ACPV->getBlockAddress());
554 } else if (ACPV->isGlobalValue()) {
555 const GlobalValue *GV = ACPV->getGV();
556 bool isIndirect = Subtarget->isTargetDarwin() &&
557 Subtarget->GVIsIndirectSymbol(GV, TM.getRelocationModel());
559 MCSym = Mang->getSymbol(GV);
561 // FIXME: Remove this when Darwin transition to @GOT like syntax.
562 MCSym = GetSymbolWithGlobalValueBase(GV, "$non_lazy_ptr");
564 MachineModuleInfoMachO &MMIMachO =
565 MMI->getObjFileInfo<MachineModuleInfoMachO>();
566 MachineModuleInfoImpl::StubValueTy &StubSym =
567 GV->hasHiddenVisibility() ? MMIMachO.getHiddenGVStubEntry(MCSym) :
568 MMIMachO.getGVStubEntry(MCSym);
569 if (StubSym.getPointer() == 0)
570 StubSym = MachineModuleInfoImpl::
571 StubValueTy(Mang->getSymbol(GV), !GV->hasInternalLinkage());
574 assert(ACPV->isExtSymbol() && "unrecognized constant pool value");
575 MCSym = GetExternalSymbolSymbol(ACPV->getSymbol());
578 // Create an MCSymbol for the reference.
580 MCSymbolRefExpr::Create(MCSym, getModifierVariantKind(ACPV->getModifier()),
583 if (ACPV->getPCAdjustment()) {
584 MCSymbol *PCLabel = getPICLabel(MAI->getPrivateGlobalPrefix(),
588 const MCExpr *PCRelExpr = MCSymbolRefExpr::Create(PCLabel, OutContext);
590 MCBinaryExpr::CreateAdd(PCRelExpr,
591 MCConstantExpr::Create(ACPV->getPCAdjustment(),
594 if (ACPV->mustAddCurrentAddress()) {
595 // We want "(<expr> - .)", but MC doesn't have a concept of the '.'
596 // label, so just emit a local label end reference that instead.
597 MCSymbol *DotSym = OutContext.CreateTempSymbol();
598 OutStreamer.EmitLabel(DotSym);
599 const MCExpr *DotExpr = MCSymbolRefExpr::Create(DotSym, OutContext);
600 PCRelExpr = MCBinaryExpr::CreateSub(PCRelExpr, DotExpr, OutContext);
602 Expr = MCBinaryExpr::CreateSub(Expr, PCRelExpr, OutContext);
604 OutStreamer.EmitValue(Expr, Size);
607 void ARMAsmPrinter::EmitJumpTable(const MachineInstr *MI) {
608 unsigned Opcode = MI->getOpcode();
610 if (Opcode == ARM::BR_JTadd)
612 else if (Opcode == ARM::BR_JTm)
615 const MachineOperand &MO1 = MI->getOperand(OpNum);
616 const MachineOperand &MO2 = MI->getOperand(OpNum+1); // Unique Id
617 unsigned JTI = MO1.getIndex();
619 // Emit a label for the jump table.
620 MCSymbol *JTISymbol = GetARMJTIPICJumpTableLabel2(JTI, MO2.getImm());
621 OutStreamer.EmitLabel(JTISymbol);
623 // Emit each entry of the table.
624 const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
625 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
626 const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
628 for (unsigned i = 0, e = JTBBs.size(); i != e; ++i) {
629 MachineBasicBlock *MBB = JTBBs[i];
630 // Construct an MCExpr for the entry. We want a value of the form:
631 // (BasicBlockAddr - TableBeginAddr)
633 // For example, a table with entries jumping to basic blocks BB0 and BB1
636 // .word (LBB0 - LJTI_0_0)
637 // .word (LBB1 - LJTI_0_0)
638 const MCExpr *Expr = MCSymbolRefExpr::Create(MBB->getSymbol(), OutContext);
640 if (TM.getRelocationModel() == Reloc::PIC_)
641 Expr = MCBinaryExpr::CreateSub(Expr, MCSymbolRefExpr::Create(JTISymbol,
644 OutStreamer.EmitValue(Expr, 4);
648 void ARMAsmPrinter::EmitJump2Table(const MachineInstr *MI) {
649 unsigned Opcode = MI->getOpcode();
650 int OpNum = (Opcode == ARM::t2BR_JT) ? 2 : 1;
651 const MachineOperand &MO1 = MI->getOperand(OpNum);
652 const MachineOperand &MO2 = MI->getOperand(OpNum+1); // Unique Id
653 unsigned JTI = MO1.getIndex();
655 // Emit a label for the jump table.
656 MCSymbol *JTISymbol = GetARMJTIPICJumpTableLabel2(JTI, MO2.getImm());
657 OutStreamer.EmitLabel(JTISymbol);
659 // Emit each entry of the table.
660 const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
661 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
662 const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
663 unsigned OffsetWidth = 4;
664 if (MI->getOpcode() == ARM::t2TBB_JT)
666 else if (MI->getOpcode() == ARM::t2TBH_JT)
669 for (unsigned i = 0, e = JTBBs.size(); i != e; ++i) {
670 MachineBasicBlock *MBB = JTBBs[i];
671 const MCExpr *MBBSymbolExpr = MCSymbolRefExpr::Create(MBB->getSymbol(),
673 // If this isn't a TBB or TBH, the entries are direct branch instructions.
674 if (OffsetWidth == 4) {
676 BrInst.setOpcode(ARM::t2B);
677 BrInst.addOperand(MCOperand::CreateExpr(MBBSymbolExpr));
678 OutStreamer.EmitInstruction(BrInst);
681 // Otherwise it's an offset from the dispatch instruction. Construct an
682 // MCExpr for the entry. We want a value of the form:
683 // (BasicBlockAddr - TableBeginAddr) / 2
685 // For example, a TBB table with entries jumping to basic blocks BB0 and BB1
688 // .byte (LBB0 - LJTI_0_0) / 2
689 // .byte (LBB1 - LJTI_0_0) / 2
691 MCBinaryExpr::CreateSub(MBBSymbolExpr,
692 MCSymbolRefExpr::Create(JTISymbol, OutContext),
694 Expr = MCBinaryExpr::CreateDiv(Expr, MCConstantExpr::Create(2, OutContext),
696 OutStreamer.EmitValue(Expr, OffsetWidth);
700 void ARMAsmPrinter::PrintDebugValueComment(const MachineInstr *MI,
702 unsigned NOps = MI->getNumOperands();
704 OS << '\t' << MAI->getCommentString() << "DEBUG_VALUE: ";
705 // cast away const; DIetc do not take const operands for some reason.
706 DIVariable V(const_cast<MDNode *>(MI->getOperand(NOps-1).getMetadata()));
709 // Frame address. Currently handles register +- offset only.
710 assert(MI->getOperand(0).isReg() && MI->getOperand(1).isImm());
711 OS << '['; printOperand(MI, 0, OS); OS << '+'; printOperand(MI, 1, OS);
714 printOperand(MI, NOps-2, OS);
717 static void populateADROperands(MCInst &Inst, unsigned Dest,
718 const MCSymbol *Label,
719 unsigned pred, unsigned ccreg,
721 const MCExpr *SymbolExpr = MCSymbolRefExpr::Create(Label, Ctx);
722 Inst.addOperand(MCOperand::CreateReg(Dest));
723 Inst.addOperand(MCOperand::CreateExpr(SymbolExpr));
724 // Add predicate operands.
725 Inst.addOperand(MCOperand::CreateImm(pred));
726 Inst.addOperand(MCOperand::CreateReg(ccreg));
729 void ARMAsmPrinter::EmitPatchedInstruction(const MachineInstr *MI,
733 // Emit the instruction as usual, just patch the opcode.
734 LowerARMMachineInstrToMCInst(MI, TmpInst, *this);
735 TmpInst.setOpcode(Opcode);
736 OutStreamer.EmitInstruction(TmpInst);
739 void ARMAsmPrinter::EmitInstruction(const MachineInstr *MI) {
740 switch (MI->getOpcode()) {
743 case ARM::t2ADDrSPi12:
745 case ARM::t2SUBrSPi12:
746 assert ((MI->getOperand(1).getReg() == ARM::SP) &&
747 "Unexpected source register!");
750 case ARM::t2MOVi32imm: assert(0 && "Should be lowered by thumb2it pass");
751 case ARM::DBG_VALUE: {
752 if (isVerbose() && OutStreamer.hasRawTextSupport()) {
753 SmallString<128> TmpStr;
754 raw_svector_ostream OS(TmpStr);
755 PrintDebugValueComment(MI, OS);
756 OutStreamer.EmitRawText(StringRef(OS.str()));
762 TmpInst.setOpcode(ARM::tBL);
763 TmpInst.addOperand(MCOperand::CreateExpr(MCSymbolRefExpr::Create(
764 MI->getOperand(0).getMBB()->getSymbol(), OutContext)));
765 OutStreamer.EmitInstruction(TmpInst);
770 case ARM::t2LEApcrel: {
771 // FIXME: Need to also handle globals and externals
773 TmpInst.setOpcode(MI->getOpcode() == ARM::t2LEApcrel ? ARM::t2ADR
774 : (MI->getOpcode() == ARM::tLEApcrel ? ARM::tADR
776 populateADROperands(TmpInst, MI->getOperand(0).getReg(),
777 GetCPISymbol(MI->getOperand(1).getIndex()),
778 MI->getOperand(2).getImm(), MI->getOperand(3).getReg(),
780 OutStreamer.EmitInstruction(TmpInst);
783 case ARM::LEApcrelJT:
784 case ARM::tLEApcrelJT:
785 case ARM::t2LEApcrelJT: {
787 TmpInst.setOpcode(MI->getOpcode() == ARM::t2LEApcrelJT ? ARM::t2ADR
788 : (MI->getOpcode() == ARM::tLEApcrelJT ? ARM::tADR
790 populateADROperands(TmpInst, MI->getOperand(0).getReg(),
791 GetARMJTIPICJumpTableLabel2(MI->getOperand(1).getIndex(),
792 MI->getOperand(2).getImm()),
793 MI->getOperand(3).getImm(), MI->getOperand(4).getReg(),
795 OutStreamer.EmitInstruction(TmpInst);
800 TmpInst.setOpcode(ARM::MOVr);
801 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
802 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
803 // Add predicate operands.
804 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
805 TmpInst.addOperand(MCOperand::CreateReg(0));
806 // Add 's' bit operand (always reg0 for this)
807 TmpInst.addOperand(MCOperand::CreateReg(0));
808 OutStreamer.EmitInstruction(TmpInst);
815 TmpInst.setOpcode(ARM::MOVr);
816 TmpInst.addOperand(MCOperand::CreateReg(ARM::LR));
817 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
818 // Add predicate operands.
819 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
820 TmpInst.addOperand(MCOperand::CreateReg(0));
821 // Add 's' bit operand (always reg0 for this)
822 TmpInst.addOperand(MCOperand::CreateReg(0));
823 OutStreamer.EmitInstruction(TmpInst);
827 TmpInst.setOpcode(ARM::BX);
828 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
829 OutStreamer.EmitInstruction(TmpInst);
833 case ARM::BMOVPCRXr9_CALL:
834 case ARM::BMOVPCRX_CALL: {
837 TmpInst.setOpcode(ARM::MOVr);
838 TmpInst.addOperand(MCOperand::CreateReg(ARM::LR));
839 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
840 // Add predicate operands.
841 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
842 TmpInst.addOperand(MCOperand::CreateReg(0));
843 // Add 's' bit operand (always reg0 for this)
844 TmpInst.addOperand(MCOperand::CreateReg(0));
845 OutStreamer.EmitInstruction(TmpInst);
849 TmpInst.setOpcode(ARM::MOVr);
850 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
851 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
852 // Add predicate operands.
853 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
854 TmpInst.addOperand(MCOperand::CreateReg(0));
855 // Add 's' bit operand (always reg0 for this)
856 TmpInst.addOperand(MCOperand::CreateReg(0));
857 OutStreamer.EmitInstruction(TmpInst);
862 // This is a pseudo op for a label + instruction sequence, which looks like:
865 // This adds the address of LPC0 to r0.
868 OutStreamer.EmitLabel(getPICLabel(MAI->getPrivateGlobalPrefix(),
869 getFunctionNumber(), MI->getOperand(2).getImm(),
872 // Form and emit the add.
874 AddInst.setOpcode(ARM::tADDhirr);
875 AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
876 AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
877 AddInst.addOperand(MCOperand::CreateReg(ARM::PC));
878 // Add predicate operands.
879 AddInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
880 AddInst.addOperand(MCOperand::CreateReg(0));
881 OutStreamer.EmitInstruction(AddInst);
885 // This is a pseudo op for a label + instruction sequence, which looks like:
888 // This adds the address of LPC0 to r0.
891 OutStreamer.EmitLabel(getPICLabel(MAI->getPrivateGlobalPrefix(),
892 getFunctionNumber(), MI->getOperand(2).getImm(),
895 // Form and emit the add.
897 AddInst.setOpcode(ARM::ADDrr);
898 AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
899 AddInst.addOperand(MCOperand::CreateReg(ARM::PC));
900 AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
901 // Add predicate operands.
902 AddInst.addOperand(MCOperand::CreateImm(MI->getOperand(3).getImm()));
903 AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(4).getReg()));
904 // Add 's' bit operand (always reg0 for this)
905 AddInst.addOperand(MCOperand::CreateReg(0));
906 OutStreamer.EmitInstruction(AddInst);
916 case ARM::PICLDRSH: {
917 // This is a pseudo op for a label + instruction sequence, which looks like:
920 // The LCP0 label is referenced by a constant pool entry in order to get
921 // a PC-relative address at the ldr instruction.
924 OutStreamer.EmitLabel(getPICLabel(MAI->getPrivateGlobalPrefix(),
925 getFunctionNumber(), MI->getOperand(2).getImm(),
928 // Form and emit the load
930 switch (MI->getOpcode()) {
932 llvm_unreachable("Unexpected opcode!");
933 case ARM::PICSTR: Opcode = ARM::STRrs; break;
934 case ARM::PICSTRB: Opcode = ARM::STRBrs; break;
935 case ARM::PICSTRH: Opcode = ARM::STRH; break;
936 case ARM::PICLDR: Opcode = ARM::LDRrs; break;
937 case ARM::PICLDRB: Opcode = ARM::LDRBrs; break;
938 case ARM::PICLDRH: Opcode = ARM::LDRH; break;
939 case ARM::PICLDRSB: Opcode = ARM::LDRSB; break;
940 case ARM::PICLDRSH: Opcode = ARM::LDRSH; break;
943 LdStInst.setOpcode(Opcode);
944 LdStInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
945 LdStInst.addOperand(MCOperand::CreateReg(ARM::PC));
946 LdStInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
947 LdStInst.addOperand(MCOperand::CreateImm(0));
948 // Add predicate operands.
949 LdStInst.addOperand(MCOperand::CreateImm(MI->getOperand(3).getImm()));
950 LdStInst.addOperand(MCOperand::CreateReg(MI->getOperand(4).getReg()));
951 OutStreamer.EmitInstruction(LdStInst);
955 case ARM::CONSTPOOL_ENTRY: {
956 /// CONSTPOOL_ENTRY - This instruction represents a floating constant pool
957 /// in the function. The first operand is the ID# for this instruction, the
958 /// second is the index into the MachineConstantPool that this is, the third
959 /// is the size in bytes of this constant pool entry.
960 unsigned LabelId = (unsigned)MI->getOperand(0).getImm();
961 unsigned CPIdx = (unsigned)MI->getOperand(1).getIndex();
964 OutStreamer.EmitLabel(GetCPISymbol(LabelId));
966 const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPIdx];
967 if (MCPE.isMachineConstantPoolEntry())
968 EmitMachineConstantPoolValue(MCPE.Val.MachineCPVal);
970 EmitGlobalConstant(MCPE.Val.ConstVal);
975 // Lower and emit the instruction itself, then the jump table following it.
977 TmpInst.setOpcode(ARM::tMOVgpr2gpr);
978 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
979 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
980 // Add predicate operands.
981 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
982 TmpInst.addOperand(MCOperand::CreateReg(0));
983 OutStreamer.EmitInstruction(TmpInst);
984 // Output the data for the jump table itself
988 case ARM::t2TBB_JT: {
989 // Lower and emit the instruction itself, then the jump table following it.
992 TmpInst.setOpcode(ARM::t2TBB);
993 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
994 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
995 // Add predicate operands.
996 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
997 TmpInst.addOperand(MCOperand::CreateReg(0));
998 OutStreamer.EmitInstruction(TmpInst);
999 // Output the data for the jump table itself
1001 // Make sure the next instruction is 2-byte aligned.
1005 case ARM::t2TBH_JT: {
1006 // Lower and emit the instruction itself, then the jump table following it.
1009 TmpInst.setOpcode(ARM::t2TBH);
1010 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1011 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1012 // Add predicate operands.
1013 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1014 TmpInst.addOperand(MCOperand::CreateReg(0));
1015 OutStreamer.EmitInstruction(TmpInst);
1016 // Output the data for the jump table itself
1022 // Lower and emit the instruction itself, then the jump table following it.
1025 unsigned Opc = MI->getOpcode() == ARM::BR_JTr ?
1026 ARM::MOVr : ARM::tMOVgpr2gpr;
1027 TmpInst.setOpcode(Opc);
1028 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1029 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1030 // Add predicate operands.
1031 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1032 TmpInst.addOperand(MCOperand::CreateReg(0));
1033 // Add 's' bit operand (always reg0 for this)
1034 if (Opc == ARM::MOVr)
1035 TmpInst.addOperand(MCOperand::CreateReg(0));
1036 OutStreamer.EmitInstruction(TmpInst);
1038 // Make sure the Thumb jump table is 4-byte aligned.
1039 if (Opc == ARM::tMOVgpr2gpr)
1042 // Output the data for the jump table itself
1047 // Lower and emit the instruction itself, then the jump table following it.
1050 if (MI->getOperand(1).getReg() == 0) {
1052 TmpInst.setOpcode(ARM::LDRi12);
1053 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1054 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1055 TmpInst.addOperand(MCOperand::CreateImm(MI->getOperand(2).getImm()));
1057 TmpInst.setOpcode(ARM::LDRrs);
1058 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1059 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1060 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
1061 TmpInst.addOperand(MCOperand::CreateImm(0));
1063 // Add predicate operands.
1064 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1065 TmpInst.addOperand(MCOperand::CreateReg(0));
1066 OutStreamer.EmitInstruction(TmpInst);
1068 // Output the data for the jump table itself
1072 case ARM::BR_JTadd: {
1073 // Lower and emit the instruction itself, then the jump table following it.
1074 // add pc, target, idx
1076 TmpInst.setOpcode(ARM::ADDrr);
1077 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1078 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1079 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
1080 // Add predicate operands.
1081 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1082 TmpInst.addOperand(MCOperand::CreateReg(0));
1083 // Add 's' bit operand (always reg0 for this)
1084 TmpInst.addOperand(MCOperand::CreateReg(0));
1085 OutStreamer.EmitInstruction(TmpInst);
1087 // Output the data for the jump table itself
1092 // Non-Darwin binutils don't yet support the "trap" mnemonic.
1093 // FIXME: Remove this special case when they do.
1094 if (!Subtarget->isTargetDarwin()) {
1095 //.long 0xe7ffdefe @ trap
1096 uint32_t Val = 0xe7ffdefeUL;
1097 OutStreamer.AddComment("trap");
1098 OutStreamer.EmitIntValue(Val, 4);
1104 // Non-Darwin binutils don't yet support the "trap" mnemonic.
1105 // FIXME: Remove this special case when they do.
1106 if (!Subtarget->isTargetDarwin()) {
1107 //.short 57086 @ trap
1108 uint16_t Val = 0xdefe;
1109 OutStreamer.AddComment("trap");
1110 OutStreamer.EmitIntValue(Val, 2);
1115 case ARM::t2Int_eh_sjlj_setjmp:
1116 case ARM::t2Int_eh_sjlj_setjmp_nofp:
1117 case ARM::tInt_eh_sjlj_setjmp: {
1118 // Two incoming args: GPR:$src, GPR:$val
1121 // str $val, [$src, #4]
1126 unsigned SrcReg = MI->getOperand(0).getReg();
1127 unsigned ValReg = MI->getOperand(1).getReg();
1128 MCSymbol *Label = GetARMSJLJEHLabel();
1131 TmpInst.setOpcode(ARM::tMOVgpr2tgpr);
1132 TmpInst.addOperand(MCOperand::CreateReg(ValReg));
1133 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1135 TmpInst.addOperand(MCOperand::CreateReg(ARM::CPSR));
1136 OutStreamer.AddComment("eh_setjmp begin");
1137 OutStreamer.EmitInstruction(TmpInst);
1141 TmpInst.setOpcode(ARM::tADDi3);
1142 TmpInst.addOperand(MCOperand::CreateReg(ValReg));
1144 TmpInst.addOperand(MCOperand::CreateReg(ARM::CPSR));
1145 TmpInst.addOperand(MCOperand::CreateReg(ValReg));
1146 TmpInst.addOperand(MCOperand::CreateImm(7));
1148 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1149 TmpInst.addOperand(MCOperand::CreateReg(0));
1150 OutStreamer.EmitInstruction(TmpInst);
1154 TmpInst.setOpcode(ARM::tSTRi);
1155 TmpInst.addOperand(MCOperand::CreateReg(ValReg));
1156 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
1157 // The offset immediate is #4. The operand value is scaled by 4 for the
1158 // tSTR instruction.
1159 TmpInst.addOperand(MCOperand::CreateImm(1));
1161 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1162 TmpInst.addOperand(MCOperand::CreateReg(0));
1163 OutStreamer.EmitInstruction(TmpInst);
1167 TmpInst.setOpcode(ARM::tMOVi8);
1168 TmpInst.addOperand(MCOperand::CreateReg(ARM::R0));
1169 TmpInst.addOperand(MCOperand::CreateReg(ARM::CPSR));
1170 TmpInst.addOperand(MCOperand::CreateImm(0));
1172 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1173 TmpInst.addOperand(MCOperand::CreateReg(0));
1174 OutStreamer.EmitInstruction(TmpInst);
1177 const MCExpr *SymbolExpr = MCSymbolRefExpr::Create(Label, OutContext);
1179 TmpInst.setOpcode(ARM::tB);
1180 TmpInst.addOperand(MCOperand::CreateExpr(SymbolExpr));
1181 OutStreamer.EmitInstruction(TmpInst);
1185 TmpInst.setOpcode(ARM::tMOVi8);
1186 TmpInst.addOperand(MCOperand::CreateReg(ARM::R0));
1187 TmpInst.addOperand(MCOperand::CreateReg(ARM::CPSR));
1188 TmpInst.addOperand(MCOperand::CreateImm(1));
1190 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1191 TmpInst.addOperand(MCOperand::CreateReg(0));
1192 OutStreamer.AddComment("eh_setjmp end");
1193 OutStreamer.EmitInstruction(TmpInst);
1195 OutStreamer.EmitLabel(Label);
1199 case ARM::Int_eh_sjlj_setjmp_nofp:
1200 case ARM::Int_eh_sjlj_setjmp: {
1201 // Two incoming args: GPR:$src, GPR:$val
1203 // str $val, [$src, #+4]
1207 unsigned SrcReg = MI->getOperand(0).getReg();
1208 unsigned ValReg = MI->getOperand(1).getReg();
1212 TmpInst.setOpcode(ARM::ADDri);
1213 TmpInst.addOperand(MCOperand::CreateReg(ValReg));
1214 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1215 TmpInst.addOperand(MCOperand::CreateImm(8));
1217 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1218 TmpInst.addOperand(MCOperand::CreateReg(0));
1219 // 's' bit operand (always reg0 for this).
1220 TmpInst.addOperand(MCOperand::CreateReg(0));
1221 OutStreamer.AddComment("eh_setjmp begin");
1222 OutStreamer.EmitInstruction(TmpInst);
1226 TmpInst.setOpcode(ARM::STRi12);
1227 TmpInst.addOperand(MCOperand::CreateReg(ValReg));
1228 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
1229 TmpInst.addOperand(MCOperand::CreateImm(4));
1231 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1232 TmpInst.addOperand(MCOperand::CreateReg(0));
1233 OutStreamer.EmitInstruction(TmpInst);
1237 TmpInst.setOpcode(ARM::MOVi);
1238 TmpInst.addOperand(MCOperand::CreateReg(ARM::R0));
1239 TmpInst.addOperand(MCOperand::CreateImm(0));
1241 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1242 TmpInst.addOperand(MCOperand::CreateReg(0));
1243 // 's' bit operand (always reg0 for this).
1244 TmpInst.addOperand(MCOperand::CreateReg(0));
1245 OutStreamer.EmitInstruction(TmpInst);
1249 TmpInst.setOpcode(ARM::ADDri);
1250 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1251 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1252 TmpInst.addOperand(MCOperand::CreateImm(0));
1254 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1255 TmpInst.addOperand(MCOperand::CreateReg(0));
1256 // 's' bit operand (always reg0 for this).
1257 TmpInst.addOperand(MCOperand::CreateReg(0));
1258 OutStreamer.EmitInstruction(TmpInst);
1262 TmpInst.setOpcode(ARM::MOVi);
1263 TmpInst.addOperand(MCOperand::CreateReg(ARM::R0));
1264 TmpInst.addOperand(MCOperand::CreateImm(1));
1266 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1267 TmpInst.addOperand(MCOperand::CreateReg(0));
1268 // 's' bit operand (always reg0 for this).
1269 TmpInst.addOperand(MCOperand::CreateReg(0));
1270 OutStreamer.AddComment("eh_setjmp end");
1271 OutStreamer.EmitInstruction(TmpInst);
1275 case ARM::Int_eh_sjlj_longjmp: {
1276 // ldr sp, [$src, #8]
1277 // ldr $scratch, [$src, #4]
1280 unsigned SrcReg = MI->getOperand(0).getReg();
1281 unsigned ScratchReg = MI->getOperand(1).getReg();
1284 TmpInst.setOpcode(ARM::LDRi12);
1285 TmpInst.addOperand(MCOperand::CreateReg(ARM::SP));
1286 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
1287 TmpInst.addOperand(MCOperand::CreateImm(8));
1289 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1290 TmpInst.addOperand(MCOperand::CreateReg(0));
1291 OutStreamer.EmitInstruction(TmpInst);
1295 TmpInst.setOpcode(ARM::LDRi12);
1296 TmpInst.addOperand(MCOperand::CreateReg(ScratchReg));
1297 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
1298 TmpInst.addOperand(MCOperand::CreateImm(4));
1300 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1301 TmpInst.addOperand(MCOperand::CreateReg(0));
1302 OutStreamer.EmitInstruction(TmpInst);
1306 TmpInst.setOpcode(ARM::LDRi12);
1307 TmpInst.addOperand(MCOperand::CreateReg(ARM::R7));
1308 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
1309 TmpInst.addOperand(MCOperand::CreateImm(0));
1311 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1312 TmpInst.addOperand(MCOperand::CreateReg(0));
1313 OutStreamer.EmitInstruction(TmpInst);
1317 TmpInst.setOpcode(ARM::BX);
1318 TmpInst.addOperand(MCOperand::CreateReg(ScratchReg));
1320 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1321 TmpInst.addOperand(MCOperand::CreateReg(0));
1322 OutStreamer.EmitInstruction(TmpInst);
1326 case ARM::tInt_eh_sjlj_longjmp: {
1327 // ldr $scratch, [$src, #8]
1329 // ldr $scratch, [$src, #4]
1332 unsigned SrcReg = MI->getOperand(0).getReg();
1333 unsigned ScratchReg = MI->getOperand(1).getReg();
1336 TmpInst.setOpcode(ARM::tLDRi);
1337 TmpInst.addOperand(MCOperand::CreateReg(ScratchReg));
1338 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
1339 // The offset immediate is #8. The operand value is scaled by 4 for the
1340 // tLDR instruction.
1341 TmpInst.addOperand(MCOperand::CreateImm(2));
1343 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1344 TmpInst.addOperand(MCOperand::CreateReg(0));
1345 OutStreamer.EmitInstruction(TmpInst);
1349 TmpInst.setOpcode(ARM::tMOVtgpr2gpr);
1350 TmpInst.addOperand(MCOperand::CreateReg(ARM::SP));
1351 TmpInst.addOperand(MCOperand::CreateReg(ScratchReg));
1353 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1354 TmpInst.addOperand(MCOperand::CreateReg(0));
1355 OutStreamer.EmitInstruction(TmpInst);
1359 TmpInst.setOpcode(ARM::tLDRi);
1360 TmpInst.addOperand(MCOperand::CreateReg(ScratchReg));
1361 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
1362 TmpInst.addOperand(MCOperand::CreateImm(1));
1364 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1365 TmpInst.addOperand(MCOperand::CreateReg(0));
1366 OutStreamer.EmitInstruction(TmpInst);
1370 TmpInst.setOpcode(ARM::tLDRr);
1371 TmpInst.addOperand(MCOperand::CreateReg(ARM::R7));
1372 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
1373 TmpInst.addOperand(MCOperand::CreateReg(0));
1375 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1376 TmpInst.addOperand(MCOperand::CreateReg(0));
1377 OutStreamer.EmitInstruction(TmpInst);
1381 TmpInst.setOpcode(ARM::tBX_RET_vararg);
1382 TmpInst.addOperand(MCOperand::CreateReg(ScratchReg));
1384 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1385 TmpInst.addOperand(MCOperand::CreateReg(0));
1386 OutStreamer.EmitInstruction(TmpInst);
1390 // These are the pseudos created to comply with stricter operand restrictions
1391 // on ARMv5. Lower them now to "normal" instructions, since all the
1392 // restrictions are already satisfied.
1394 EmitPatchedInstruction(MI, ARM::MUL);
1397 EmitPatchedInstruction(MI, ARM::MLA);
1400 EmitPatchedInstruction(MI, ARM::SMULL);
1403 EmitPatchedInstruction(MI, ARM::UMULL);
1406 EmitPatchedInstruction(MI, ARM::SMLAL);
1409 EmitPatchedInstruction(MI, ARM::UMLAL);
1412 EmitPatchedInstruction(MI, ARM::UMAAL);
1417 LowerARMMachineInstrToMCInst(MI, TmpInst, *this);
1418 OutStreamer.EmitInstruction(TmpInst);
1421 //===----------------------------------------------------------------------===//
1422 // Target Registry Stuff
1423 //===----------------------------------------------------------------------===//
1425 static MCInstPrinter *createARMMCInstPrinter(const Target &T,
1426 unsigned SyntaxVariant,
1427 const MCAsmInfo &MAI) {
1428 if (SyntaxVariant == 0)
1429 return new ARMInstPrinter(MAI);
1433 // Force static initialization.
1434 extern "C" void LLVMInitializeARMAsmPrinter() {
1435 RegisterAsmPrinter<ARMAsmPrinter> X(TheARMTarget);
1436 RegisterAsmPrinter<ARMAsmPrinter> Y(TheThumbTarget);
1438 TargetRegistry::RegisterMCInstPrinter(TheARMTarget, createARMMCInstPrinter);
1439 TargetRegistry::RegisterMCInstPrinter(TheThumbTarget, createARMMCInstPrinter);