1 //===-- ARMAsmPrinter.cpp - Print machine code to an ARM .s file ----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains a printer that converts from our internal representation
11 // of machine-dependent LLVM code to GAS-format ARM assembly language.
13 //===----------------------------------------------------------------------===//
15 #include "ARMAsmPrinter.h"
17 #include "ARMConstantPoolValue.h"
18 #include "ARMMachineFunctionInfo.h"
19 #include "ARMTargetMachine.h"
20 #include "ARMTargetObjectFile.h"
21 #include "InstPrinter/ARMInstPrinter.h"
22 #include "MCTargetDesc/ARMAddressingModes.h"
23 #include "MCTargetDesc/ARMMCExpr.h"
24 #include "llvm/ADT/SetVector.h"
25 #include "llvm/ADT/SmallString.h"
26 #include "llvm/CodeGen/MachineFunctionPass.h"
27 #include "llvm/CodeGen/MachineJumpTableInfo.h"
28 #include "llvm/CodeGen/MachineModuleInfoImpls.h"
29 #include "llvm/IR/Constants.h"
30 #include "llvm/IR/DataLayout.h"
31 #include "llvm/IR/DebugInfo.h"
32 #include "llvm/IR/Mangler.h"
33 #include "llvm/IR/Module.h"
34 #include "llvm/IR/Type.h"
35 #include "llvm/MC/MCAsmInfo.h"
36 #include "llvm/MC/MCAssembler.h"
37 #include "llvm/MC/MCContext.h"
38 #include "llvm/MC/MCELFStreamer.h"
39 #include "llvm/MC/MCInst.h"
40 #include "llvm/MC/MCInstBuilder.h"
41 #include "llvm/MC/MCObjectStreamer.h"
42 #include "llvm/MC/MCSectionMachO.h"
43 #include "llvm/MC/MCStreamer.h"
44 #include "llvm/MC/MCSymbol.h"
45 #include "llvm/Support/ARMBuildAttributes.h"
46 #include "llvm/Support/TargetParser.h"
47 #include "llvm/Support/COFF.h"
48 #include "llvm/Support/CommandLine.h"
49 #include "llvm/Support/Debug.h"
50 #include "llvm/Support/ELF.h"
51 #include "llvm/Support/ErrorHandling.h"
52 #include "llvm/Support/TargetRegistry.h"
53 #include "llvm/Support/raw_ostream.h"
54 #include "llvm/Target/TargetMachine.h"
58 #define DEBUG_TYPE "asm-printer"
60 ARMAsmPrinter::ARMAsmPrinter(TargetMachine &TM,
61 std::unique_ptr<MCStreamer> Streamer)
62 : AsmPrinter(TM, std::move(Streamer)), AFI(nullptr), MCP(nullptr),
63 InConstantPool(false), OptimizationGoals(-1) {}
65 void ARMAsmPrinter::EmitFunctionBodyEnd() {
66 // Make sure to terminate any constant pools that were at the end
70 InConstantPool = false;
71 OutStreamer->EmitDataRegion(MCDR_DataRegionEnd);
74 void ARMAsmPrinter::EmitFunctionEntryLabel() {
75 if (AFI->isThumbFunction()) {
76 OutStreamer->EmitAssemblerFlag(MCAF_Code16);
77 OutStreamer->EmitThumbFunc(CurrentFnSym);
80 OutStreamer->EmitLabel(CurrentFnSym);
83 void ARMAsmPrinter::EmitXXStructor(const DataLayout &DL, const Constant *CV) {
84 uint64_t Size = getDataLayout().getTypeAllocSize(CV->getType());
85 assert(Size && "C++ constructor pointer had zero size!");
87 const GlobalValue *GV = dyn_cast<GlobalValue>(CV->stripPointerCasts());
88 assert(GV && "C++ constructor pointer was not a GlobalValue!");
90 const MCExpr *E = MCSymbolRefExpr::create(GetARMGVSymbol(GV,
92 (Subtarget->isTargetELF()
93 ? MCSymbolRefExpr::VK_ARM_TARGET1
94 : MCSymbolRefExpr::VK_None),
97 OutStreamer->EmitValue(E, Size);
100 /// runOnMachineFunction - This uses the EmitInstruction()
101 /// method to print assembly for each instruction.
103 bool ARMAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
104 AFI = MF.getInfo<ARMFunctionInfo>();
105 MCP = MF.getConstantPool();
106 Subtarget = &MF.getSubtarget<ARMSubtarget>();
108 SetupMachineFunction(MF);
109 const Function* F = MF.getFunction();
110 const TargetMachine& TM = MF.getTarget();
112 // Calculate this function's optimization goal.
113 unsigned OptimizationGoal;
114 if (F->hasFnAttribute(Attribute::OptimizeNone))
115 // For best debugging illusion, speed and small size sacrificed
116 OptimizationGoal = 6;
117 else if (F->optForMinSize())
118 // Aggressively for small size, speed and debug illusion sacrificed
119 OptimizationGoal = 4;
120 else if (F->optForSize())
121 // For small size, but speed and debugging illusion preserved
122 OptimizationGoal = 3;
123 else if (TM.getOptLevel() == CodeGenOpt::Aggressive)
124 // Aggressively for speed, small size and debug illusion sacrificed
125 OptimizationGoal = 2;
126 else if (TM.getOptLevel() > CodeGenOpt::None)
127 // For speed, but small size and good debug illusion preserved
128 OptimizationGoal = 1;
129 else // TM.getOptLevel() == CodeGenOpt::None
130 // For good debugging, but speed and small size preserved
131 OptimizationGoal = 5;
133 // Combine a new optimization goal with existing ones.
134 if (OptimizationGoals == -1) // uninitialized goals
135 OptimizationGoals = OptimizationGoal;
136 else if (OptimizationGoals != (int)OptimizationGoal) // conflicting goals
137 OptimizationGoals = 0;
139 if (Subtarget->isTargetCOFF()) {
140 bool Internal = F->hasInternalLinkage();
141 COFF::SymbolStorageClass Scl = Internal ? COFF::IMAGE_SYM_CLASS_STATIC
142 : COFF::IMAGE_SYM_CLASS_EXTERNAL;
143 int Type = COFF::IMAGE_SYM_DTYPE_FUNCTION << COFF::SCT_COMPLEX_TYPE_SHIFT;
145 OutStreamer->BeginCOFFSymbolDef(CurrentFnSym);
146 OutStreamer->EmitCOFFSymbolStorageClass(Scl);
147 OutStreamer->EmitCOFFSymbolType(Type);
148 OutStreamer->EndCOFFSymbolDef();
151 // Emit the rest of the function body.
154 // If we need V4T thumb mode Register Indirect Jump pads, emit them.
155 // These are created per function, rather than per TU, since it's
156 // relatively easy to exceed the thumb branch range within a TU.
157 if (! ThumbIndirectPads.empty()) {
158 OutStreamer->EmitAssemblerFlag(MCAF_Code16);
160 for (unsigned i = 0, e = ThumbIndirectPads.size(); i < e; i++) {
161 OutStreamer->EmitLabel(ThumbIndirectPads[i].second);
162 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tBX)
163 .addReg(ThumbIndirectPads[i].first)
164 // Add predicate operands.
168 ThumbIndirectPads.clear();
171 // We didn't modify anything.
175 void ARMAsmPrinter::printOperand(const MachineInstr *MI, int OpNum,
177 const MachineOperand &MO = MI->getOperand(OpNum);
178 unsigned TF = MO.getTargetFlags();
180 switch (MO.getType()) {
181 default: llvm_unreachable("<unknown operand type>");
182 case MachineOperand::MO_Register: {
183 unsigned Reg = MO.getReg();
184 assert(TargetRegisterInfo::isPhysicalRegister(Reg));
185 assert(!MO.getSubReg() && "Subregs should be eliminated!");
186 if(ARM::GPRPairRegClass.contains(Reg)) {
187 const MachineFunction &MF = *MI->getParent()->getParent();
188 const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
189 Reg = TRI->getSubReg(Reg, ARM::gsub_0);
191 O << ARMInstPrinter::getRegisterName(Reg);
194 case MachineOperand::MO_Immediate: {
195 int64_t Imm = MO.getImm();
197 if (TF == ARMII::MO_LO16)
199 else if (TF == ARMII::MO_HI16)
204 case MachineOperand::MO_MachineBasicBlock:
205 MO.getMBB()->getSymbol()->print(O, MAI);
207 case MachineOperand::MO_GlobalAddress: {
208 const GlobalValue *GV = MO.getGlobal();
209 if (TF & ARMII::MO_LO16)
211 else if (TF & ARMII::MO_HI16)
213 GetARMGVSymbol(GV, TF)->print(O, MAI);
215 printOffset(MO.getOffset(), O);
216 if (TF == ARMII::MO_PLT)
220 case MachineOperand::MO_ConstantPoolIndex:
221 GetCPISymbol(MO.getIndex())->print(O, MAI);
226 //===--------------------------------------------------------------------===//
228 MCSymbol *ARMAsmPrinter::
229 GetARMJTIPICJumpTableLabel(unsigned uid) const {
230 const DataLayout &DL = getDataLayout();
231 SmallString<60> Name;
232 raw_svector_ostream(Name) << DL.getPrivateGlobalPrefix() << "JTI"
233 << getFunctionNumber() << '_' << uid;
234 return OutContext.getOrCreateSymbol(Name);
237 bool ARMAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
238 unsigned AsmVariant, const char *ExtraCode,
240 // Does this asm operand have a single letter operand modifier?
241 if (ExtraCode && ExtraCode[0]) {
242 if (ExtraCode[1] != 0) return true; // Unknown modifier.
244 switch (ExtraCode[0]) {
246 // See if this is a generic print operand
247 return AsmPrinter::PrintAsmOperand(MI, OpNum, AsmVariant, ExtraCode, O);
248 case 'a': // Print as a memory address.
249 if (MI->getOperand(OpNum).isReg()) {
251 << ARMInstPrinter::getRegisterName(MI->getOperand(OpNum).getReg())
256 case 'c': // Don't print "#" before an immediate operand.
257 if (!MI->getOperand(OpNum).isImm())
259 O << MI->getOperand(OpNum).getImm();
261 case 'P': // Print a VFP double precision register.
262 case 'q': // Print a NEON quad precision register.
263 printOperand(MI, OpNum, O);
265 case 'y': // Print a VFP single precision register as indexed double.
266 if (MI->getOperand(OpNum).isReg()) {
267 unsigned Reg = MI->getOperand(OpNum).getReg();
268 const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
269 // Find the 'd' register that has this 's' register as a sub-register,
270 // and determine the lane number.
271 for (MCSuperRegIterator SR(Reg, TRI); SR.isValid(); ++SR) {
272 if (!ARM::DPRRegClass.contains(*SR))
274 bool Lane0 = TRI->getSubReg(*SR, ARM::ssub_0) == Reg;
275 O << ARMInstPrinter::getRegisterName(*SR) << (Lane0 ? "[0]" : "[1]");
280 case 'B': // Bitwise inverse of integer or symbol without a preceding #.
281 if (!MI->getOperand(OpNum).isImm())
283 O << ~(MI->getOperand(OpNum).getImm());
285 case 'L': // The low 16 bits of an immediate constant.
286 if (!MI->getOperand(OpNum).isImm())
288 O << (MI->getOperand(OpNum).getImm() & 0xffff);
290 case 'M': { // A register range suitable for LDM/STM.
291 if (!MI->getOperand(OpNum).isReg())
293 const MachineOperand &MO = MI->getOperand(OpNum);
294 unsigned RegBegin = MO.getReg();
295 // This takes advantage of the 2 operand-ness of ldm/stm and that we've
296 // already got the operands in registers that are operands to the
297 // inline asm statement.
299 if (ARM::GPRPairRegClass.contains(RegBegin)) {
300 const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
301 unsigned Reg0 = TRI->getSubReg(RegBegin, ARM::gsub_0);
302 O << ARMInstPrinter::getRegisterName(Reg0) << ", ";
303 RegBegin = TRI->getSubReg(RegBegin, ARM::gsub_1);
305 O << ARMInstPrinter::getRegisterName(RegBegin);
307 // FIXME: The register allocator not only may not have given us the
308 // registers in sequence, but may not be in ascending registers. This
309 // will require changes in the register allocator that'll need to be
310 // propagated down here if the operands change.
311 unsigned RegOps = OpNum + 1;
312 while (MI->getOperand(RegOps).isReg()) {
314 << ARMInstPrinter::getRegisterName(MI->getOperand(RegOps).getReg());
322 case 'R': // The most significant register of a pair.
323 case 'Q': { // The least significant register of a pair.
326 const MachineOperand &FlagsOP = MI->getOperand(OpNum - 1);
327 if (!FlagsOP.isImm())
329 unsigned Flags = FlagsOP.getImm();
331 // This operand may not be the one that actually provides the register. If
332 // it's tied to a previous one then we should refer instead to that one
333 // for registers and their classes.
335 if (InlineAsm::isUseOperandTiedToDef(Flags, TiedIdx)) {
336 for (OpNum = InlineAsm::MIOp_FirstOperand; TiedIdx; --TiedIdx) {
337 unsigned OpFlags = MI->getOperand(OpNum).getImm();
338 OpNum += InlineAsm::getNumOperandRegisters(OpFlags) + 1;
340 Flags = MI->getOperand(OpNum).getImm();
342 // Later code expects OpNum to be pointing at the register rather than
347 unsigned NumVals = InlineAsm::getNumOperandRegisters(Flags);
349 InlineAsm::hasRegClassConstraint(Flags, RC);
350 if (RC == ARM::GPRPairRegClassID) {
353 const MachineOperand &MO = MI->getOperand(OpNum);
356 const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
357 unsigned Reg = TRI->getSubReg(MO.getReg(), ExtraCode[0] == 'Q' ?
358 ARM::gsub_0 : ARM::gsub_1);
359 O << ARMInstPrinter::getRegisterName(Reg);
364 unsigned RegOp = ExtraCode[0] == 'Q' ? OpNum : OpNum + 1;
365 if (RegOp >= MI->getNumOperands())
367 const MachineOperand &MO = MI->getOperand(RegOp);
370 unsigned Reg = MO.getReg();
371 O << ARMInstPrinter::getRegisterName(Reg);
375 case 'e': // The low doubleword register of a NEON quad register.
376 case 'f': { // The high doubleword register of a NEON quad register.
377 if (!MI->getOperand(OpNum).isReg())
379 unsigned Reg = MI->getOperand(OpNum).getReg();
380 if (!ARM::QPRRegClass.contains(Reg))
382 const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
383 unsigned SubReg = TRI->getSubReg(Reg, ExtraCode[0] == 'e' ?
384 ARM::dsub_0 : ARM::dsub_1);
385 O << ARMInstPrinter::getRegisterName(SubReg);
389 // This modifier is not yet supported.
390 case 'h': // A range of VFP/NEON registers suitable for VLD1/VST1.
392 case 'H': { // The highest-numbered register of a pair.
393 const MachineOperand &MO = MI->getOperand(OpNum);
396 const MachineFunction &MF = *MI->getParent()->getParent();
397 const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
398 unsigned Reg = MO.getReg();
399 if(!ARM::GPRPairRegClass.contains(Reg))
401 Reg = TRI->getSubReg(Reg, ARM::gsub_1);
402 O << ARMInstPrinter::getRegisterName(Reg);
408 printOperand(MI, OpNum, O);
412 bool ARMAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI,
413 unsigned OpNum, unsigned AsmVariant,
414 const char *ExtraCode,
416 // Does this asm operand have a single letter operand modifier?
417 if (ExtraCode && ExtraCode[0]) {
418 if (ExtraCode[1] != 0) return true; // Unknown modifier.
420 switch (ExtraCode[0]) {
421 case 'A': // A memory operand for a VLD1/VST1 instruction.
422 default: return true; // Unknown modifier.
423 case 'm': // The base register of a memory operand.
424 if (!MI->getOperand(OpNum).isReg())
426 O << ARMInstPrinter::getRegisterName(MI->getOperand(OpNum).getReg());
431 const MachineOperand &MO = MI->getOperand(OpNum);
432 assert(MO.isReg() && "unexpected inline asm memory operand");
433 O << "[" << ARMInstPrinter::getRegisterName(MO.getReg()) << "]";
437 static bool isThumb(const MCSubtargetInfo& STI) {
438 return STI.getFeatureBits()[ARM::ModeThumb];
441 void ARMAsmPrinter::emitInlineAsmEnd(const MCSubtargetInfo &StartInfo,
442 const MCSubtargetInfo *EndInfo) const {
443 // If either end mode is unknown (EndInfo == NULL) or different than
444 // the start mode, then restore the start mode.
445 const bool WasThumb = isThumb(StartInfo);
446 if (!EndInfo || WasThumb != isThumb(*EndInfo)) {
447 OutStreamer->EmitAssemblerFlag(WasThumb ? MCAF_Code16 : MCAF_Code32);
451 void ARMAsmPrinter::EmitStartOfAsmFile(Module &M) {
452 const Triple &TT = TM.getTargetTriple();
453 // Use unified assembler syntax.
454 OutStreamer->EmitAssemblerFlag(MCAF_SyntaxUnified);
456 // Emit ARM Build Attributes
457 if (TT.isOSBinFormatELF())
460 // Use the triple's architecture and subarchitecture to determine
461 // if we're thumb for the purposes of the top level code16 assembler
463 bool isThumb = TT.getArch() == Triple::thumb ||
464 TT.getArch() == Triple::thumbeb ||
465 TT.getSubArch() == Triple::ARMSubArch_v7m ||
466 TT.getSubArch() == Triple::ARMSubArch_v6m;
467 if (!M.getModuleInlineAsm().empty() && isThumb)
468 OutStreamer->EmitAssemblerFlag(MCAF_Code16);
472 emitNonLazySymbolPointer(MCStreamer &OutStreamer, MCSymbol *StubLabel,
473 MachineModuleInfoImpl::StubValueTy &MCSym) {
475 OutStreamer.EmitLabel(StubLabel);
476 // .indirect_symbol _foo
477 OutStreamer.EmitSymbolAttribute(MCSym.getPointer(), MCSA_IndirectSymbol);
480 // External to current translation unit.
481 OutStreamer.EmitIntValue(0, 4/*size*/);
483 // Internal to current translation unit.
485 // When we place the LSDA into the TEXT section, the type info
486 // pointers need to be indirect and pc-rel. We accomplish this by
487 // using NLPs; however, sometimes the types are local to the file.
488 // We need to fill in the value for the NLP in those cases.
489 OutStreamer.EmitValue(
490 MCSymbolRefExpr::create(MCSym.getPointer(), OutStreamer.getContext()),
495 void ARMAsmPrinter::EmitEndOfAsmFile(Module &M) {
496 const Triple &TT = TM.getTargetTriple();
497 if (TT.isOSBinFormatMachO()) {
498 // All darwin targets use mach-o.
499 const TargetLoweringObjectFileMachO &TLOFMacho =
500 static_cast<const TargetLoweringObjectFileMachO &>(getObjFileLowering());
501 MachineModuleInfoMachO &MMIMacho =
502 MMI->getObjFileInfo<MachineModuleInfoMachO>();
504 // Output non-lazy-pointers for external and common global variables.
505 MachineModuleInfoMachO::SymbolListTy Stubs = MMIMacho.GetGVStubList();
507 if (!Stubs.empty()) {
508 // Switch with ".non_lazy_symbol_pointer" directive.
509 OutStreamer->SwitchSection(TLOFMacho.getNonLazySymbolPointerSection());
512 for (auto &Stub : Stubs)
513 emitNonLazySymbolPointer(*OutStreamer, Stub.first, Stub.second);
516 OutStreamer->AddBlankLine();
519 Stubs = MMIMacho.GetHiddenGVStubList();
520 if (!Stubs.empty()) {
521 OutStreamer->SwitchSection(TLOFMacho.getNonLazySymbolPointerSection());
524 for (auto &Stub : Stubs)
525 emitNonLazySymbolPointer(*OutStreamer, Stub.first, Stub.second);
528 OutStreamer->AddBlankLine();
531 // Funny Darwin hack: This flag tells the linker that no global symbols
532 // contain code that falls through to other global symbols (e.g. the obvious
533 // implementation of multiple entry points). If this doesn't occur, the
534 // linker can safely perform dead code stripping. Since LLVM never
535 // generates code that does this, it is always safe to set.
536 OutStreamer->EmitAssemblerFlag(MCAF_SubsectionsViaSymbols);
539 // The last attribute to be emitted is ABI_optimization_goals
540 MCTargetStreamer &TS = *OutStreamer->getTargetStreamer();
541 ARMTargetStreamer &ATS = static_cast<ARMTargetStreamer &>(TS);
543 if (OptimizationGoals > 0)
544 ATS.emitAttribute(ARMBuildAttrs::ABI_optimization_goals, OptimizationGoals);
545 OptimizationGoals = -1;
547 ATS.finishAttributeSection();
550 //===----------------------------------------------------------------------===//
551 // Helper routines for EmitStartOfAsmFile() and EmitEndOfAsmFile()
553 // The following seem like one-off assembler flags, but they actually need
554 // to appear in the .ARM.attributes section in ELF.
555 // Instead of subclassing the MCELFStreamer, we do the work here.
557 static ARMBuildAttrs::CPUArch getArchForCPU(StringRef CPU,
558 const ARMSubtarget *Subtarget) {
560 return ARMBuildAttrs::v5TEJ;
562 if (Subtarget->hasV8Ops())
563 return ARMBuildAttrs::v8;
564 else if (Subtarget->hasV7Ops()) {
565 if (Subtarget->isMClass() && Subtarget->hasDSP())
566 return ARMBuildAttrs::v7E_M;
567 return ARMBuildAttrs::v7;
568 } else if (Subtarget->hasV6T2Ops())
569 return ARMBuildAttrs::v6T2;
570 else if (Subtarget->hasV6MOps())
571 return ARMBuildAttrs::v6S_M;
572 else if (Subtarget->hasV6Ops())
573 return ARMBuildAttrs::v6;
574 else if (Subtarget->hasV5TEOps())
575 return ARMBuildAttrs::v5TE;
576 else if (Subtarget->hasV5TOps())
577 return ARMBuildAttrs::v5T;
578 else if (Subtarget->hasV4TOps())
579 return ARMBuildAttrs::v4T;
581 return ARMBuildAttrs::v4;
584 void ARMAsmPrinter::emitAttributes() {
585 MCTargetStreamer &TS = *OutStreamer->getTargetStreamer();
586 ARMTargetStreamer &ATS = static_cast<ARMTargetStreamer &>(TS);
588 ATS.emitTextAttribute(ARMBuildAttrs::conformance, "2.09");
590 ATS.switchVendor("aeabi");
592 // Compute ARM ELF Attributes based on the default subtarget that
593 // we'd have constructed. The existing ARM behavior isn't LTO clean
595 // FIXME: For ifunc related functions we could iterate over and look
596 // for a feature string that doesn't match the default one.
597 const Triple &TT = TM.getTargetTriple();
598 StringRef CPU = TM.getTargetCPU();
599 StringRef FS = TM.getTargetFeatureString();
600 std::string ArchFS = ARM_MC::ParseARMTriple(TT, CPU);
603 ArchFS = (Twine(ArchFS) + "," + FS).str();
607 const ARMBaseTargetMachine &ATM =
608 static_cast<const ARMBaseTargetMachine &>(TM);
609 const ARMSubtarget STI(TT, CPU, ArchFS, ATM, ATM.isLittleEndian());
611 std::string CPUString = STI.getCPUString();
613 if (CPUString.find("generic") != 0) { //CPUString doesn't start with "generic"
614 // FIXME: remove krait check when GNU tools support krait cpu
616 ATS.emitTextAttribute(ARMBuildAttrs::CPU_name, "cortex-a9");
617 // We consider krait as a "cortex-a9" + hwdiv CPU
618 // Enable hwdiv through ".arch_extension idiv"
619 if (STI.hasDivide() || STI.hasDivideInARMMode())
620 ATS.emitArchExtension(ARM::AEK_HWDIV | ARM::AEK_HWDIVARM);
622 ATS.emitTextAttribute(ARMBuildAttrs::CPU_name, CPUString);
625 ATS.emitAttribute(ARMBuildAttrs::CPU_arch, getArchForCPU(CPUString, &STI));
627 // Tag_CPU_arch_profile must have the default value of 0 when "Architecture
628 // profile is not applicable (e.g. pre v7, or cross-profile code)".
629 if (STI.hasV7Ops()) {
630 if (STI.isAClass()) {
631 ATS.emitAttribute(ARMBuildAttrs::CPU_arch_profile,
632 ARMBuildAttrs::ApplicationProfile);
633 } else if (STI.isRClass()) {
634 ATS.emitAttribute(ARMBuildAttrs::CPU_arch_profile,
635 ARMBuildAttrs::RealTimeProfile);
636 } else if (STI.isMClass()) {
637 ATS.emitAttribute(ARMBuildAttrs::CPU_arch_profile,
638 ARMBuildAttrs::MicroControllerProfile);
642 ATS.emitAttribute(ARMBuildAttrs::ARM_ISA_use,
643 STI.hasARMOps() ? ARMBuildAttrs::Allowed
644 : ARMBuildAttrs::Not_Allowed);
645 if (STI.isThumb1Only()) {
646 ATS.emitAttribute(ARMBuildAttrs::THUMB_ISA_use, ARMBuildAttrs::Allowed);
647 } else if (STI.hasThumb2()) {
648 ATS.emitAttribute(ARMBuildAttrs::THUMB_ISA_use,
649 ARMBuildAttrs::AllowThumb32);
653 /* NEON is not exactly a VFP architecture, but GAS emit one of
654 * neon/neon-fp-armv8/neon-vfpv4/vfpv3/vfpv2 for .fpu parameters */
655 if (STI.hasFPARMv8()) {
657 ATS.emitFPU(ARM::FK_CRYPTO_NEON_FP_ARMV8);
659 ATS.emitFPU(ARM::FK_NEON_FP_ARMV8);
660 } else if (STI.hasVFP4())
661 ATS.emitFPU(ARM::FK_NEON_VFPV4);
663 ATS.emitFPU(STI.hasFP16() ? ARM::FK_NEON_FP16 : ARM::FK_NEON);
664 // Emit Tag_Advanced_SIMD_arch for ARMv8 architecture
666 ATS.emitAttribute(ARMBuildAttrs::Advanced_SIMD_arch,
667 STI.hasV8_1aOps() ? ARMBuildAttrs::AllowNeonARMv8_1a:
668 ARMBuildAttrs::AllowNeonARMv8);
670 if (STI.hasFPARMv8())
671 // FPv5 and FP-ARMv8 have the same instructions, so are modeled as one
672 // FPU, but there are two different names for it depending on the CPU.
673 ATS.emitFPU(STI.hasD16()
674 ? (STI.isFPOnlySP() ? ARM::FK_FPV5_SP_D16 : ARM::FK_FPV5_D16)
676 else if (STI.hasVFP4())
677 ATS.emitFPU(STI.hasD16()
678 ? (STI.isFPOnlySP() ? ARM::FK_FPV4_SP_D16 : ARM::FK_VFPV4_D16)
680 else if (STI.hasVFP3())
681 ATS.emitFPU(STI.hasD16()
684 ? (STI.hasFP16() ? ARM::FK_VFPV3XD_FP16 : ARM::FK_VFPV3XD)
685 : (STI.hasFP16() ? ARM::FK_VFPV3_D16_FP16 : ARM::FK_VFPV3_D16))
687 : (STI.hasFP16() ? ARM::FK_VFPV3_FP16 : ARM::FK_VFPV3));
688 else if (STI.hasVFP2())
689 ATS.emitFPU(ARM::FK_VFPV2);
692 if (TM.getRelocationModel() == Reloc::PIC_) {
693 // PIC specific attributes.
694 ATS.emitAttribute(ARMBuildAttrs::ABI_PCS_RW_data,
695 ARMBuildAttrs::AddressRWPCRel);
696 ATS.emitAttribute(ARMBuildAttrs::ABI_PCS_RO_data,
697 ARMBuildAttrs::AddressROPCRel);
698 ATS.emitAttribute(ARMBuildAttrs::ABI_PCS_GOT_use,
699 ARMBuildAttrs::AddressGOT);
701 // Allow direct addressing of imported data for all other relocation models.
702 ATS.emitAttribute(ARMBuildAttrs::ABI_PCS_GOT_use,
703 ARMBuildAttrs::AddressDirect);
706 // Signal various FP modes.
707 if (!TM.Options.UnsafeFPMath) {
708 ATS.emitAttribute(ARMBuildAttrs::ABI_FP_denormal,
709 ARMBuildAttrs::IEEEDenormals);
710 ATS.emitAttribute(ARMBuildAttrs::ABI_FP_exceptions, ARMBuildAttrs::Allowed);
712 // If the user has permitted this code to choose the IEEE 754
713 // rounding at run-time, emit the rounding attribute.
714 if (TM.Options.HonorSignDependentRoundingFPMathOption)
715 ATS.emitAttribute(ARMBuildAttrs::ABI_FP_rounding, ARMBuildAttrs::Allowed);
717 if (!STI.hasVFP2()) {
718 // When the target doesn't have an FPU (by design or
719 // intention), the assumptions made on the software support
720 // mirror that of the equivalent hardware support *if it
721 // existed*. For v7 and better we indicate that denormals are
722 // flushed preserving sign, and for V6 we indicate that
723 // denormals are flushed to positive zero.
725 ATS.emitAttribute(ARMBuildAttrs::ABI_FP_denormal,
726 ARMBuildAttrs::PreserveFPSign);
727 } else if (STI.hasVFP3()) {
728 // In VFPv4, VFPv4U, VFPv3, or VFPv3U, it is preserved. That is,
729 // the sign bit of the zero matches the sign bit of the input or
730 // result that is being flushed to zero.
731 ATS.emitAttribute(ARMBuildAttrs::ABI_FP_denormal,
732 ARMBuildAttrs::PreserveFPSign);
734 // For VFPv2 implementations it is implementation defined as
735 // to whether denormals are flushed to positive zero or to
736 // whatever the sign of zero is (ARM v7AR ARM 2.7.5). Historically
737 // LLVM has chosen to flush this to positive zero (most likely for
738 // GCC compatibility), so that's the chosen value here (the
739 // absence of its emission implies zero).
742 // TM.Options.NoInfsFPMath && TM.Options.NoNaNsFPMath is the
743 // equivalent of GCC's -ffinite-math-only flag.
744 if (TM.Options.NoInfsFPMath && TM.Options.NoNaNsFPMath)
745 ATS.emitAttribute(ARMBuildAttrs::ABI_FP_number_model,
746 ARMBuildAttrs::Allowed);
748 ATS.emitAttribute(ARMBuildAttrs::ABI_FP_number_model,
749 ARMBuildAttrs::AllowIEE754);
751 if (STI.allowsUnalignedMem())
752 ATS.emitAttribute(ARMBuildAttrs::CPU_unaligned_access,
753 ARMBuildAttrs::Allowed);
755 ATS.emitAttribute(ARMBuildAttrs::CPU_unaligned_access,
756 ARMBuildAttrs::Not_Allowed);
758 // FIXME: add more flags to ARMBuildAttributes.h
759 // 8-bytes alignment stuff.
760 ATS.emitAttribute(ARMBuildAttrs::ABI_align_needed, 1);
761 ATS.emitAttribute(ARMBuildAttrs::ABI_align_preserved, 1);
763 // ABI_HardFP_use attribute to indicate single precision FP.
764 if (STI.isFPOnlySP())
765 ATS.emitAttribute(ARMBuildAttrs::ABI_HardFP_use,
766 ARMBuildAttrs::HardFPSinglePrecision);
768 // Hard float. Use both S and D registers and conform to AAPCS-VFP.
769 if (STI.isAAPCS_ABI() && TM.Options.FloatABIType == FloatABI::Hard)
770 ATS.emitAttribute(ARMBuildAttrs::ABI_VFP_args, ARMBuildAttrs::HardFPAAPCS);
772 // FIXME: Should we signal R9 usage?
775 ATS.emitAttribute(ARMBuildAttrs::FP_HP_extension, ARMBuildAttrs::AllowHPFP);
777 // FIXME: To support emitting this build attribute as GCC does, the
778 // -mfp16-format option and associated plumbing must be
779 // supported. For now the __fp16 type is exposed by default, so this
780 // attribute should be emitted with value 1.
781 ATS.emitAttribute(ARMBuildAttrs::ABI_FP_16bit_format,
782 ARMBuildAttrs::FP16FormatIEEE);
784 if (STI.hasMPExtension())
785 ATS.emitAttribute(ARMBuildAttrs::MPextension_use, ARMBuildAttrs::AllowMP);
787 // Hardware divide in ARM mode is part of base arch, starting from ARMv8.
788 // If only Thumb hwdiv is present, it must also be in base arch (ARMv7-R/M).
789 // It is not possible to produce DisallowDIV: if hwdiv is present in the base
790 // arch, supplying -hwdiv downgrades the effective arch, via ClearImpliedBits.
791 // AllowDIVExt is only emitted if hwdiv isn't available in the base arch;
792 // otherwise, the default value (AllowDIVIfExists) applies.
793 if (STI.hasDivideInARMMode() && !STI.hasV8Ops())
794 ATS.emitAttribute(ARMBuildAttrs::DIV_use, ARMBuildAttrs::AllowDIVExt);
797 if (const Module *SourceModule = MMI->getModule()) {
798 // ABI_PCS_wchar_t to indicate wchar_t width
799 // FIXME: There is no way to emit value 0 (wchar_t prohibited).
800 if (auto WCharWidthValue = mdconst::extract_or_null<ConstantInt>(
801 SourceModule->getModuleFlag("wchar_size"))) {
802 int WCharWidth = WCharWidthValue->getZExtValue();
803 assert((WCharWidth == 2 || WCharWidth == 4) &&
804 "wchar_t width must be 2 or 4 bytes");
805 ATS.emitAttribute(ARMBuildAttrs::ABI_PCS_wchar_t, WCharWidth);
808 // ABI_enum_size to indicate enum width
809 // FIXME: There is no way to emit value 0 (enums prohibited) or value 3
810 // (all enums contain a value needing 32 bits to encode).
811 if (auto EnumWidthValue = mdconst::extract_or_null<ConstantInt>(
812 SourceModule->getModuleFlag("min_enum_size"))) {
813 int EnumWidth = EnumWidthValue->getZExtValue();
814 assert((EnumWidth == 1 || EnumWidth == 4) &&
815 "Minimum enum width must be 1 or 4 bytes");
816 int EnumBuildAttr = EnumWidth == 1 ? 1 : 2;
817 ATS.emitAttribute(ARMBuildAttrs::ABI_enum_size, EnumBuildAttr);
822 // TODO: We currently only support either reserving the register, or treating
823 // it as another callee-saved register, but not as SB or a TLS pointer; It
824 // would instead be nicer to push this from the frontend as metadata, as we do
825 // for the wchar and enum size tags
826 if (STI.isR9Reserved())
827 ATS.emitAttribute(ARMBuildAttrs::ABI_PCS_R9_use, ARMBuildAttrs::R9Reserved);
829 ATS.emitAttribute(ARMBuildAttrs::ABI_PCS_R9_use, ARMBuildAttrs::R9IsGPR);
831 if (STI.hasTrustZone() && STI.hasVirtualization())
832 ATS.emitAttribute(ARMBuildAttrs::Virtualization_use,
833 ARMBuildAttrs::AllowTZVirtualization);
834 else if (STI.hasTrustZone())
835 ATS.emitAttribute(ARMBuildAttrs::Virtualization_use,
836 ARMBuildAttrs::AllowTZ);
837 else if (STI.hasVirtualization())
838 ATS.emitAttribute(ARMBuildAttrs::Virtualization_use,
839 ARMBuildAttrs::AllowVirtualization);
842 //===----------------------------------------------------------------------===//
844 static MCSymbol *getPICLabel(const char *Prefix, unsigned FunctionNumber,
845 unsigned LabelId, MCContext &Ctx) {
847 MCSymbol *Label = Ctx.getOrCreateSymbol(Twine(Prefix)
848 + "PC" + Twine(FunctionNumber) + "_" + Twine(LabelId));
852 static MCSymbolRefExpr::VariantKind
853 getModifierVariantKind(ARMCP::ARMCPModifier Modifier) {
855 case ARMCP::no_modifier: return MCSymbolRefExpr::VK_None;
856 case ARMCP::TLSGD: return MCSymbolRefExpr::VK_TLSGD;
857 case ARMCP::TPOFF: return MCSymbolRefExpr::VK_TPOFF;
858 case ARMCP::GOTTPOFF: return MCSymbolRefExpr::VK_GOTTPOFF;
859 case ARMCP::GOT_PREL: return MCSymbolRefExpr::VK_ARM_GOT_PREL;
861 llvm_unreachable("Invalid ARMCPModifier!");
864 MCSymbol *ARMAsmPrinter::GetARMGVSymbol(const GlobalValue *GV,
865 unsigned char TargetFlags) {
866 if (Subtarget->isTargetMachO()) {
867 bool IsIndirect = (TargetFlags & ARMII::MO_NONLAZY) &&
868 Subtarget->GVIsIndirectSymbol(GV, TM.getRelocationModel());
871 return getSymbol(GV);
873 // FIXME: Remove this when Darwin transition to @GOT like syntax.
874 MCSymbol *MCSym = getSymbolWithGlobalValueBase(GV, "$non_lazy_ptr");
875 MachineModuleInfoMachO &MMIMachO =
876 MMI->getObjFileInfo<MachineModuleInfoMachO>();
877 MachineModuleInfoImpl::StubValueTy &StubSym =
878 GV->hasHiddenVisibility() ? MMIMachO.getHiddenGVStubEntry(MCSym)
879 : MMIMachO.getGVStubEntry(MCSym);
880 if (!StubSym.getPointer())
881 StubSym = MachineModuleInfoImpl::StubValueTy(getSymbol(GV),
882 !GV->hasInternalLinkage());
884 } else if (Subtarget->isTargetCOFF()) {
885 assert(Subtarget->isTargetWindows() &&
886 "Windows is the only supported COFF target");
888 bool IsIndirect = (TargetFlags & ARMII::MO_DLLIMPORT);
890 return getSymbol(GV);
892 SmallString<128> Name;
894 getNameWithPrefix(Name, GV);
896 return OutContext.getOrCreateSymbol(Name);
897 } else if (Subtarget->isTargetELF()) {
898 return getSymbol(GV);
900 llvm_unreachable("unexpected target");
904 EmitMachineConstantPoolValue(MachineConstantPoolValue *MCPV) {
905 const DataLayout &DL = getDataLayout();
906 int Size = DL.getTypeAllocSize(MCPV->getType());
908 ARMConstantPoolValue *ACPV = static_cast<ARMConstantPoolValue*>(MCPV);
911 if (ACPV->isLSDA()) {
912 MCSym = getCurExceptionSym();
913 } else if (ACPV->isBlockAddress()) {
914 const BlockAddress *BA =
915 cast<ARMConstantPoolConstant>(ACPV)->getBlockAddress();
916 MCSym = GetBlockAddressSymbol(BA);
917 } else if (ACPV->isGlobalValue()) {
918 const GlobalValue *GV = cast<ARMConstantPoolConstant>(ACPV)->getGV();
920 // On Darwin, const-pool entries may get the "FOO$non_lazy_ptr" mangling, so
921 // flag the global as MO_NONLAZY.
922 unsigned char TF = Subtarget->isTargetMachO() ? ARMII::MO_NONLAZY : 0;
923 MCSym = GetARMGVSymbol(GV, TF);
924 } else if (ACPV->isMachineBasicBlock()) {
925 const MachineBasicBlock *MBB = cast<ARMConstantPoolMBB>(ACPV)->getMBB();
926 MCSym = MBB->getSymbol();
928 assert(ACPV->isExtSymbol() && "unrecognized constant pool value");
929 const char *Sym = cast<ARMConstantPoolSymbol>(ACPV)->getSymbol();
930 MCSym = GetExternalSymbolSymbol(Sym);
933 // Create an MCSymbol for the reference.
935 MCSymbolRefExpr::create(MCSym, getModifierVariantKind(ACPV->getModifier()),
938 if (ACPV->getPCAdjustment()) {
940 getPICLabel(DL.getPrivateGlobalPrefix(), getFunctionNumber(),
941 ACPV->getLabelId(), OutContext);
942 const MCExpr *PCRelExpr = MCSymbolRefExpr::create(PCLabel, OutContext);
944 MCBinaryExpr::createAdd(PCRelExpr,
945 MCConstantExpr::create(ACPV->getPCAdjustment(),
948 if (ACPV->mustAddCurrentAddress()) {
949 // We want "(<expr> - .)", but MC doesn't have a concept of the '.'
950 // label, so just emit a local label end reference that instead.
951 MCSymbol *DotSym = OutContext.createTempSymbol();
952 OutStreamer->EmitLabel(DotSym);
953 const MCExpr *DotExpr = MCSymbolRefExpr::create(DotSym, OutContext);
954 PCRelExpr = MCBinaryExpr::createSub(PCRelExpr, DotExpr, OutContext);
956 Expr = MCBinaryExpr::createSub(Expr, PCRelExpr, OutContext);
958 OutStreamer->EmitValue(Expr, Size);
961 void ARMAsmPrinter::EmitJumpTableAddrs(const MachineInstr *MI) {
962 const MachineOperand &MO1 = MI->getOperand(1);
963 unsigned JTI = MO1.getIndex();
965 // Make sure the Thumb jump table is 4-byte aligned. This will be a nop for
969 // Emit a label for the jump table.
970 MCSymbol *JTISymbol = GetARMJTIPICJumpTableLabel(JTI);
971 OutStreamer->EmitLabel(JTISymbol);
973 // Mark the jump table as data-in-code.
974 OutStreamer->EmitDataRegion(MCDR_DataRegionJT32);
976 // Emit each entry of the table.
977 const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
978 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
979 const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
981 for (unsigned i = 0, e = JTBBs.size(); i != e; ++i) {
982 MachineBasicBlock *MBB = JTBBs[i];
983 // Construct an MCExpr for the entry. We want a value of the form:
984 // (BasicBlockAddr - TableBeginAddr)
986 // For example, a table with entries jumping to basic blocks BB0 and BB1
989 // .word (LBB0 - LJTI_0_0)
990 // .word (LBB1 - LJTI_0_0)
991 const MCExpr *Expr = MCSymbolRefExpr::create(MBB->getSymbol(), OutContext);
993 if (TM.getRelocationModel() == Reloc::PIC_)
994 Expr = MCBinaryExpr::createSub(Expr, MCSymbolRefExpr::create(JTISymbol,
997 // If we're generating a table of Thumb addresses in static relocation
998 // model, we need to add one to keep interworking correctly.
999 else if (AFI->isThumbFunction())
1000 Expr = MCBinaryExpr::createAdd(Expr, MCConstantExpr::create(1,OutContext),
1002 OutStreamer->EmitValue(Expr, 4);
1004 // Mark the end of jump table data-in-code region.
1005 OutStreamer->EmitDataRegion(MCDR_DataRegionEnd);
1008 void ARMAsmPrinter::EmitJumpTableInsts(const MachineInstr *MI) {
1009 const MachineOperand &MO1 = MI->getOperand(1);
1010 unsigned JTI = MO1.getIndex();
1012 MCSymbol *JTISymbol = GetARMJTIPICJumpTableLabel(JTI);
1013 OutStreamer->EmitLabel(JTISymbol);
1015 // Emit each entry of the table.
1016 const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
1017 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
1018 const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
1020 for (unsigned i = 0, e = JTBBs.size(); i != e; ++i) {
1021 MachineBasicBlock *MBB = JTBBs[i];
1022 const MCExpr *MBBSymbolExpr = MCSymbolRefExpr::create(MBB->getSymbol(),
1024 // If this isn't a TBB or TBH, the entries are direct branch instructions.
1025 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::t2B)
1026 .addExpr(MBBSymbolExpr)
1032 void ARMAsmPrinter::EmitJumpTableTBInst(const MachineInstr *MI,
1033 unsigned OffsetWidth) {
1034 assert((OffsetWidth == 1 || OffsetWidth == 2) && "invalid tbb/tbh width");
1035 const MachineOperand &MO1 = MI->getOperand(1);
1036 unsigned JTI = MO1.getIndex();
1038 MCSymbol *JTISymbol = GetARMJTIPICJumpTableLabel(JTI);
1039 OutStreamer->EmitLabel(JTISymbol);
1041 // Emit each entry of the table.
1042 const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
1043 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
1044 const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
1046 // Mark the jump table as data-in-code.
1047 OutStreamer->EmitDataRegion(OffsetWidth == 1 ? MCDR_DataRegionJT8
1048 : MCDR_DataRegionJT16);
1050 for (auto MBB : JTBBs) {
1051 const MCExpr *MBBSymbolExpr = MCSymbolRefExpr::create(MBB->getSymbol(),
1053 // Otherwise it's an offset from the dispatch instruction. Construct an
1054 // MCExpr for the entry. We want a value of the form:
1055 // (BasicBlockAddr - TBBInstAddr + 4) / 2
1057 // For example, a TBB table with entries jumping to basic blocks BB0 and BB1
1060 // .byte (LBB0 - (LCPI0_0 + 4)) / 2
1061 // .byte (LBB1 - (LCPI0_0 + 4)) / 2
1062 // where LCPI0_0 is a label defined just before the TBB instruction using
1064 MCSymbol *TBInstPC = GetCPISymbol(MI->getOperand(0).getImm());
1065 const MCExpr *Expr = MCBinaryExpr::createAdd(
1066 MCSymbolRefExpr::create(TBInstPC, OutContext),
1067 MCConstantExpr::create(4, OutContext), OutContext);
1068 Expr = MCBinaryExpr::createSub(MBBSymbolExpr, Expr, OutContext);
1069 Expr = MCBinaryExpr::createDiv(Expr, MCConstantExpr::create(2, OutContext),
1071 OutStreamer->EmitValue(Expr, OffsetWidth);
1073 // Mark the end of jump table data-in-code region. 32-bit offsets use
1074 // actual branch instructions here, so we don't mark those as a data-region
1076 OutStreamer->EmitDataRegion(MCDR_DataRegionEnd);
1078 // Make sure the next instruction is 2-byte aligned.
1082 void ARMAsmPrinter::EmitUnwindingInstruction(const MachineInstr *MI) {
1083 assert(MI->getFlag(MachineInstr::FrameSetup) &&
1084 "Only instruction which are involved into frame setup code are allowed");
1086 MCTargetStreamer &TS = *OutStreamer->getTargetStreamer();
1087 ARMTargetStreamer &ATS = static_cast<ARMTargetStreamer &>(TS);
1088 const MachineFunction &MF = *MI->getParent()->getParent();
1089 const TargetRegisterInfo *RegInfo = MF.getSubtarget().getRegisterInfo();
1090 const ARMFunctionInfo &AFI = *MF.getInfo<ARMFunctionInfo>();
1092 unsigned FramePtr = RegInfo->getFrameRegister(MF);
1093 unsigned Opc = MI->getOpcode();
1094 unsigned SrcReg, DstReg;
1096 if (Opc == ARM::tPUSH || Opc == ARM::tLDRpci) {
1097 // Two special cases:
1098 // 1) tPUSH does not have src/dst regs.
1099 // 2) for Thumb1 code we sometimes materialize the constant via constpool
1100 // load. Yes, this is pretty fragile, but for now I don't see better
1102 SrcReg = DstReg = ARM::SP;
1104 SrcReg = MI->getOperand(1).getReg();
1105 DstReg = MI->getOperand(0).getReg();
1108 // Try to figure out the unwinding opcode out of src / dst regs.
1109 if (MI->mayStore()) {
1111 assert(DstReg == ARM::SP &&
1112 "Only stack pointer as a destination reg is supported");
1114 SmallVector<unsigned, 4> RegList;
1115 // Skip src & dst reg, and pred ops.
1116 unsigned StartOp = 2 + 2;
1117 // Use all the operands.
1118 unsigned NumOffset = 0;
1123 llvm_unreachable("Unsupported opcode for unwinding information");
1125 // Special case here: no src & dst reg, but two extra imp ops.
1126 StartOp = 2; NumOffset = 2;
1127 case ARM::STMDB_UPD:
1128 case ARM::t2STMDB_UPD:
1129 case ARM::VSTMDDB_UPD:
1130 assert(SrcReg == ARM::SP &&
1131 "Only stack pointer as a source reg is supported");
1132 for (unsigned i = StartOp, NumOps = MI->getNumOperands() - NumOffset;
1134 const MachineOperand &MO = MI->getOperand(i);
1135 // Actually, there should never be any impdef stuff here. Skip it
1136 // temporary to workaround PR11902.
1137 if (MO.isImplicit())
1139 RegList.push_back(MO.getReg());
1142 case ARM::STR_PRE_IMM:
1143 case ARM::STR_PRE_REG:
1144 case ARM::t2STR_PRE:
1145 assert(MI->getOperand(2).getReg() == ARM::SP &&
1146 "Only stack pointer as a source reg is supported");
1147 RegList.push_back(SrcReg);
1150 if (MAI->getExceptionHandlingType() == ExceptionHandling::ARM)
1151 ATS.emitRegSave(RegList, Opc == ARM::VSTMDDB_UPD);
1153 // Changes of stack / frame pointer.
1154 if (SrcReg == ARM::SP) {
1159 llvm_unreachable("Unsupported opcode for unwinding information");
1166 Offset = -MI->getOperand(2).getImm();
1170 Offset = MI->getOperand(2).getImm();
1173 Offset = MI->getOperand(2).getImm()*4;
1177 Offset = -MI->getOperand(2).getImm()*4;
1179 case ARM::tLDRpci: {
1180 // Grab the constpool index and check, whether it corresponds to
1181 // original or cloned constpool entry.
1182 unsigned CPI = MI->getOperand(1).getIndex();
1183 const MachineConstantPool *MCP = MF.getConstantPool();
1184 if (CPI >= MCP->getConstants().size())
1185 CPI = AFI.getOriginalCPIdx(CPI);
1186 assert(CPI != -1U && "Invalid constpool index");
1188 // Derive the actual offset.
1189 const MachineConstantPoolEntry &CPE = MCP->getConstants()[CPI];
1190 assert(!CPE.isMachineConstantPoolEntry() && "Invalid constpool entry");
1191 // FIXME: Check for user, it should be "add" instruction!
1192 Offset = -cast<ConstantInt>(CPE.Val.ConstVal)->getSExtValue();
1197 if (MAI->getExceptionHandlingType() == ExceptionHandling::ARM) {
1198 if (DstReg == FramePtr && FramePtr != ARM::SP)
1199 // Set-up of the frame pointer. Positive values correspond to "add"
1201 ATS.emitSetFP(FramePtr, ARM::SP, -Offset);
1202 else if (DstReg == ARM::SP) {
1203 // Change of SP by an offset. Positive values correspond to "sub"
1205 ATS.emitPad(Offset);
1207 // Move of SP to a register. Positive values correspond to an "add"
1209 ATS.emitMovSP(DstReg, -Offset);
1212 } else if (DstReg == ARM::SP) {
1214 llvm_unreachable("Unsupported opcode for unwinding information");
1218 llvm_unreachable("Unsupported opcode for unwinding information");
1223 // Simple pseudo-instructions have their lowering (with expansion to real
1224 // instructions) auto-generated.
1225 #include "ARMGenMCPseudoLowering.inc"
1227 void ARMAsmPrinter::EmitInstruction(const MachineInstr *MI) {
1228 const DataLayout &DL = getDataLayout();
1230 // If we just ended a constant pool, mark it as such.
1231 if (InConstantPool && MI->getOpcode() != ARM::CONSTPOOL_ENTRY) {
1232 OutStreamer->EmitDataRegion(MCDR_DataRegionEnd);
1233 InConstantPool = false;
1236 // Emit unwinding stuff for frame-related instructions
1237 if (Subtarget->isTargetEHABICompatible() &&
1238 MI->getFlag(MachineInstr::FrameSetup))
1239 EmitUnwindingInstruction(MI);
1241 // Do any auto-generated pseudo lowerings.
1242 if (emitPseudoExpansionLowering(*OutStreamer, MI))
1245 assert(!convertAddSubFlagsOpcode(MI->getOpcode()) &&
1246 "Pseudo flag setting opcode should be expanded early");
1248 // Check for manual lowerings.
1249 unsigned Opc = MI->getOpcode();
1251 case ARM::t2MOVi32imm: llvm_unreachable("Should be lowered by thumb2it pass");
1252 case ARM::DBG_VALUE: llvm_unreachable("Should be handled by generic printing");
1254 case ARM::tLEApcrel:
1255 case ARM::t2LEApcrel: {
1256 // FIXME: Need to also handle globals and externals
1257 MCSymbol *CPISymbol = GetCPISymbol(MI->getOperand(1).getIndex());
1258 EmitToStreamer(*OutStreamer, MCInstBuilder(MI->getOpcode() ==
1259 ARM::t2LEApcrel ? ARM::t2ADR
1260 : (MI->getOpcode() == ARM::tLEApcrel ? ARM::tADR
1262 .addReg(MI->getOperand(0).getReg())
1263 .addExpr(MCSymbolRefExpr::create(CPISymbol, OutContext))
1264 // Add predicate operands.
1265 .addImm(MI->getOperand(2).getImm())
1266 .addReg(MI->getOperand(3).getReg()));
1269 case ARM::LEApcrelJT:
1270 case ARM::tLEApcrelJT:
1271 case ARM::t2LEApcrelJT: {
1272 MCSymbol *JTIPICSymbol =
1273 GetARMJTIPICJumpTableLabel(MI->getOperand(1).getIndex());
1274 EmitToStreamer(*OutStreamer, MCInstBuilder(MI->getOpcode() ==
1275 ARM::t2LEApcrelJT ? ARM::t2ADR
1276 : (MI->getOpcode() == ARM::tLEApcrelJT ? ARM::tADR
1278 .addReg(MI->getOperand(0).getReg())
1279 .addExpr(MCSymbolRefExpr::create(JTIPICSymbol, OutContext))
1280 // Add predicate operands.
1281 .addImm(MI->getOperand(2).getImm())
1282 .addReg(MI->getOperand(3).getReg()));
1285 // Darwin call instructions are just normal call instructions with different
1286 // clobber semantics (they clobber R9).
1287 case ARM::BX_CALL: {
1288 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::MOVr)
1291 // Add predicate operands.
1294 // Add 's' bit operand (always reg0 for this)
1297 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::BX)
1298 .addReg(MI->getOperand(0).getReg()));
1301 case ARM::tBX_CALL: {
1302 if (Subtarget->hasV5TOps())
1303 llvm_unreachable("Expected BLX to be selected for v5t+");
1305 // On ARM v4t, when doing a call from thumb mode, we need to ensure
1306 // that the saved lr has its LSB set correctly (the arch doesn't
1308 // So here we generate a bl to a small jump pad that does bx rN.
1309 // The jump pads are emitted after the function body.
1311 unsigned TReg = MI->getOperand(0).getReg();
1312 MCSymbol *TRegSym = nullptr;
1313 for (unsigned i = 0, e = ThumbIndirectPads.size(); i < e; i++) {
1314 if (ThumbIndirectPads[i].first == TReg) {
1315 TRegSym = ThumbIndirectPads[i].second;
1321 TRegSym = OutContext.createTempSymbol();
1322 ThumbIndirectPads.push_back(std::make_pair(TReg, TRegSym));
1325 // Create a link-saving branch to the Reg Indirect Jump Pad.
1326 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tBL)
1327 // Predicate comes first here.
1328 .addImm(ARMCC::AL).addReg(0)
1329 .addExpr(MCSymbolRefExpr::create(TRegSym, OutContext)));
1332 case ARM::BMOVPCRX_CALL: {
1333 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::MOVr)
1336 // Add predicate operands.
1339 // Add 's' bit operand (always reg0 for this)
1342 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::MOVr)
1344 .addReg(MI->getOperand(0).getReg())
1345 // Add predicate operands.
1348 // Add 's' bit operand (always reg0 for this)
1352 case ARM::BMOVPCB_CALL: {
1353 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::MOVr)
1356 // Add predicate operands.
1359 // Add 's' bit operand (always reg0 for this)
1362 const MachineOperand &Op = MI->getOperand(0);
1363 const GlobalValue *GV = Op.getGlobal();
1364 const unsigned TF = Op.getTargetFlags();
1365 MCSymbol *GVSym = GetARMGVSymbol(GV, TF);
1366 const MCExpr *GVSymExpr = MCSymbolRefExpr::create(GVSym, OutContext);
1367 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::Bcc)
1369 // Add predicate operands.
1374 case ARM::MOVi16_ga_pcrel:
1375 case ARM::t2MOVi16_ga_pcrel: {
1377 TmpInst.setOpcode(Opc == ARM::MOVi16_ga_pcrel? ARM::MOVi16 : ARM::t2MOVi16);
1378 TmpInst.addOperand(MCOperand::createReg(MI->getOperand(0).getReg()));
1380 unsigned TF = MI->getOperand(1).getTargetFlags();
1381 const GlobalValue *GV = MI->getOperand(1).getGlobal();
1382 MCSymbol *GVSym = GetARMGVSymbol(GV, TF);
1383 const MCExpr *GVSymExpr = MCSymbolRefExpr::create(GVSym, OutContext);
1385 MCSymbol *LabelSym =
1386 getPICLabel(DL.getPrivateGlobalPrefix(), getFunctionNumber(),
1387 MI->getOperand(2).getImm(), OutContext);
1388 const MCExpr *LabelSymExpr= MCSymbolRefExpr::create(LabelSym, OutContext);
1389 unsigned PCAdj = (Opc == ARM::MOVi16_ga_pcrel) ? 8 : 4;
1390 const MCExpr *PCRelExpr =
1391 ARMMCExpr::createLower16(MCBinaryExpr::createSub(GVSymExpr,
1392 MCBinaryExpr::createAdd(LabelSymExpr,
1393 MCConstantExpr::create(PCAdj, OutContext),
1394 OutContext), OutContext), OutContext);
1395 TmpInst.addOperand(MCOperand::createExpr(PCRelExpr));
1397 // Add predicate operands.
1398 TmpInst.addOperand(MCOperand::createImm(ARMCC::AL));
1399 TmpInst.addOperand(MCOperand::createReg(0));
1400 // Add 's' bit operand (always reg0 for this)
1401 TmpInst.addOperand(MCOperand::createReg(0));
1402 EmitToStreamer(*OutStreamer, TmpInst);
1405 case ARM::MOVTi16_ga_pcrel:
1406 case ARM::t2MOVTi16_ga_pcrel: {
1408 TmpInst.setOpcode(Opc == ARM::MOVTi16_ga_pcrel
1409 ? ARM::MOVTi16 : ARM::t2MOVTi16);
1410 TmpInst.addOperand(MCOperand::createReg(MI->getOperand(0).getReg()));
1411 TmpInst.addOperand(MCOperand::createReg(MI->getOperand(1).getReg()));
1413 unsigned TF = MI->getOperand(2).getTargetFlags();
1414 const GlobalValue *GV = MI->getOperand(2).getGlobal();
1415 MCSymbol *GVSym = GetARMGVSymbol(GV, TF);
1416 const MCExpr *GVSymExpr = MCSymbolRefExpr::create(GVSym, OutContext);
1418 MCSymbol *LabelSym =
1419 getPICLabel(DL.getPrivateGlobalPrefix(), getFunctionNumber(),
1420 MI->getOperand(3).getImm(), OutContext);
1421 const MCExpr *LabelSymExpr= MCSymbolRefExpr::create(LabelSym, OutContext);
1422 unsigned PCAdj = (Opc == ARM::MOVTi16_ga_pcrel) ? 8 : 4;
1423 const MCExpr *PCRelExpr =
1424 ARMMCExpr::createUpper16(MCBinaryExpr::createSub(GVSymExpr,
1425 MCBinaryExpr::createAdd(LabelSymExpr,
1426 MCConstantExpr::create(PCAdj, OutContext),
1427 OutContext), OutContext), OutContext);
1428 TmpInst.addOperand(MCOperand::createExpr(PCRelExpr));
1429 // Add predicate operands.
1430 TmpInst.addOperand(MCOperand::createImm(ARMCC::AL));
1431 TmpInst.addOperand(MCOperand::createReg(0));
1432 // Add 's' bit operand (always reg0 for this)
1433 TmpInst.addOperand(MCOperand::createReg(0));
1434 EmitToStreamer(*OutStreamer, TmpInst);
1437 case ARM::tPICADD: {
1438 // This is a pseudo op for a label + instruction sequence, which looks like:
1441 // This adds the address of LPC0 to r0.
1444 OutStreamer->EmitLabel(getPICLabel(DL.getPrivateGlobalPrefix(),
1445 getFunctionNumber(),
1446 MI->getOperand(2).getImm(), OutContext));
1448 // Form and emit the add.
1449 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tADDhirr)
1450 .addReg(MI->getOperand(0).getReg())
1451 .addReg(MI->getOperand(0).getReg())
1453 // Add predicate operands.
1459 // This is a pseudo op for a label + instruction sequence, which looks like:
1462 // This adds the address of LPC0 to r0.
1465 OutStreamer->EmitLabel(getPICLabel(DL.getPrivateGlobalPrefix(),
1466 getFunctionNumber(),
1467 MI->getOperand(2).getImm(), OutContext));
1469 // Form and emit the add.
1470 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::ADDrr)
1471 .addReg(MI->getOperand(0).getReg())
1473 .addReg(MI->getOperand(1).getReg())
1474 // Add predicate operands.
1475 .addImm(MI->getOperand(3).getImm())
1476 .addReg(MI->getOperand(4).getReg())
1477 // Add 's' bit operand (always reg0 for this)
1488 case ARM::PICLDRSH: {
1489 // This is a pseudo op for a label + instruction sequence, which looks like:
1492 // The LCP0 label is referenced by a constant pool entry in order to get
1493 // a PC-relative address at the ldr instruction.
1496 OutStreamer->EmitLabel(getPICLabel(DL.getPrivateGlobalPrefix(),
1497 getFunctionNumber(),
1498 MI->getOperand(2).getImm(), OutContext));
1500 // Form and emit the load
1502 switch (MI->getOpcode()) {
1504 llvm_unreachable("Unexpected opcode!");
1505 case ARM::PICSTR: Opcode = ARM::STRrs; break;
1506 case ARM::PICSTRB: Opcode = ARM::STRBrs; break;
1507 case ARM::PICSTRH: Opcode = ARM::STRH; break;
1508 case ARM::PICLDR: Opcode = ARM::LDRrs; break;
1509 case ARM::PICLDRB: Opcode = ARM::LDRBrs; break;
1510 case ARM::PICLDRH: Opcode = ARM::LDRH; break;
1511 case ARM::PICLDRSB: Opcode = ARM::LDRSB; break;
1512 case ARM::PICLDRSH: Opcode = ARM::LDRSH; break;
1514 EmitToStreamer(*OutStreamer, MCInstBuilder(Opcode)
1515 .addReg(MI->getOperand(0).getReg())
1517 .addReg(MI->getOperand(1).getReg())
1519 // Add predicate operands.
1520 .addImm(MI->getOperand(3).getImm())
1521 .addReg(MI->getOperand(4).getReg()));
1525 case ARM::CONSTPOOL_ENTRY: {
1526 /// CONSTPOOL_ENTRY - This instruction represents a floating constant pool
1527 /// in the function. The first operand is the ID# for this instruction, the
1528 /// second is the index into the MachineConstantPool that this is, the third
1529 /// is the size in bytes of this constant pool entry.
1530 /// The required alignment is specified on the basic block holding this MI.
1531 unsigned LabelId = (unsigned)MI->getOperand(0).getImm();
1532 unsigned CPIdx = (unsigned)MI->getOperand(1).getIndex();
1534 // If this is the first entry of the pool, mark it.
1535 if (!InConstantPool) {
1536 OutStreamer->EmitDataRegion(MCDR_DataRegion);
1537 InConstantPool = true;
1540 OutStreamer->EmitLabel(GetCPISymbol(LabelId));
1542 const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPIdx];
1543 if (MCPE.isMachineConstantPoolEntry())
1544 EmitMachineConstantPoolValue(MCPE.Val.MachineCPVal);
1546 EmitGlobalConstant(DL, MCPE.Val.ConstVal);
1549 case ARM::JUMPTABLE_ADDRS:
1550 EmitJumpTableAddrs(MI);
1552 case ARM::JUMPTABLE_INSTS:
1553 EmitJumpTableInsts(MI);
1555 case ARM::JUMPTABLE_TBB:
1556 case ARM::JUMPTABLE_TBH:
1557 EmitJumpTableTBInst(MI, MI->getOpcode() == ARM::JUMPTABLE_TBB ? 1 : 2);
1559 case ARM::t2BR_JT: {
1560 // Lower and emit the instruction itself, then the jump table following it.
1561 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tMOVr)
1563 .addReg(MI->getOperand(0).getReg())
1564 // Add predicate operands.
1570 case ARM::t2TBH_JT: {
1571 unsigned Opc = MI->getOpcode() == ARM::t2TBB_JT ? ARM::t2TBB : ARM::t2TBH;
1572 // Lower and emit the PC label, then the instruction itself.
1573 OutStreamer->EmitLabel(GetCPISymbol(MI->getOperand(3).getImm()));
1574 EmitToStreamer(*OutStreamer, MCInstBuilder(Opc)
1575 .addReg(MI->getOperand(0).getReg())
1576 .addReg(MI->getOperand(1).getReg())
1577 // Add predicate operands.
1584 // Lower and emit the instruction itself, then the jump table following it.
1587 unsigned Opc = MI->getOpcode() == ARM::BR_JTr ?
1588 ARM::MOVr : ARM::tMOVr;
1589 TmpInst.setOpcode(Opc);
1590 TmpInst.addOperand(MCOperand::createReg(ARM::PC));
1591 TmpInst.addOperand(MCOperand::createReg(MI->getOperand(0).getReg()));
1592 // Add predicate operands.
1593 TmpInst.addOperand(MCOperand::createImm(ARMCC::AL));
1594 TmpInst.addOperand(MCOperand::createReg(0));
1595 // Add 's' bit operand (always reg0 for this)
1596 if (Opc == ARM::MOVr)
1597 TmpInst.addOperand(MCOperand::createReg(0));
1598 EmitToStreamer(*OutStreamer, TmpInst);
1602 // Lower and emit the instruction itself, then the jump table following it.
1605 if (MI->getOperand(1).getReg() == 0) {
1607 TmpInst.setOpcode(ARM::LDRi12);
1608 TmpInst.addOperand(MCOperand::createReg(ARM::PC));
1609 TmpInst.addOperand(MCOperand::createReg(MI->getOperand(0).getReg()));
1610 TmpInst.addOperand(MCOperand::createImm(MI->getOperand(2).getImm()));
1612 TmpInst.setOpcode(ARM::LDRrs);
1613 TmpInst.addOperand(MCOperand::createReg(ARM::PC));
1614 TmpInst.addOperand(MCOperand::createReg(MI->getOperand(0).getReg()));
1615 TmpInst.addOperand(MCOperand::createReg(MI->getOperand(1).getReg()));
1616 TmpInst.addOperand(MCOperand::createImm(0));
1618 // Add predicate operands.
1619 TmpInst.addOperand(MCOperand::createImm(ARMCC::AL));
1620 TmpInst.addOperand(MCOperand::createReg(0));
1621 EmitToStreamer(*OutStreamer, TmpInst);
1624 case ARM::BR_JTadd: {
1625 // Lower and emit the instruction itself, then the jump table following it.
1626 // add pc, target, idx
1627 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::ADDrr)
1629 .addReg(MI->getOperand(0).getReg())
1630 .addReg(MI->getOperand(1).getReg())
1631 // Add predicate operands.
1634 // Add 's' bit operand (always reg0 for this)
1639 OutStreamer->EmitZeros(MI->getOperand(1).getImm());
1642 // Non-Darwin binutils don't yet support the "trap" mnemonic.
1643 // FIXME: Remove this special case when they do.
1644 if (!Subtarget->isTargetMachO()) {
1645 //.long 0xe7ffdefe @ trap
1646 uint32_t Val = 0xe7ffdefeUL;
1647 OutStreamer->AddComment("trap");
1648 OutStreamer->EmitIntValue(Val, 4);
1653 case ARM::TRAPNaCl: {
1654 //.long 0xe7fedef0 @ trap
1655 uint32_t Val = 0xe7fedef0UL;
1656 OutStreamer->AddComment("trap");
1657 OutStreamer->EmitIntValue(Val, 4);
1661 // Non-Darwin binutils don't yet support the "trap" mnemonic.
1662 // FIXME: Remove this special case when they do.
1663 if (!Subtarget->isTargetMachO()) {
1664 //.short 57086 @ trap
1665 uint16_t Val = 0xdefe;
1666 OutStreamer->AddComment("trap");
1667 OutStreamer->EmitIntValue(Val, 2);
1672 case ARM::t2Int_eh_sjlj_setjmp:
1673 case ARM::t2Int_eh_sjlj_setjmp_nofp:
1674 case ARM::tInt_eh_sjlj_setjmp: {
1675 // Two incoming args: GPR:$src, GPR:$val
1678 // str $val, [$src, #4]
1683 unsigned SrcReg = MI->getOperand(0).getReg();
1684 unsigned ValReg = MI->getOperand(1).getReg();
1685 MCSymbol *Label = OutContext.createTempSymbol("SJLJEH", false, true);
1686 OutStreamer->AddComment("eh_setjmp begin");
1687 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tMOVr)
1694 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tADDi3)
1704 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tSTRi)
1707 // The offset immediate is #4. The operand value is scaled by 4 for the
1708 // tSTR instruction.
1714 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tMOVi8)
1722 const MCExpr *SymbolExpr = MCSymbolRefExpr::create(Label, OutContext);
1723 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tB)
1724 .addExpr(SymbolExpr)
1728 OutStreamer->AddComment("eh_setjmp end");
1729 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tMOVi8)
1737 OutStreamer->EmitLabel(Label);
1741 case ARM::Int_eh_sjlj_setjmp_nofp:
1742 case ARM::Int_eh_sjlj_setjmp: {
1743 // Two incoming args: GPR:$src, GPR:$val
1745 // str $val, [$src, #+4]
1749 unsigned SrcReg = MI->getOperand(0).getReg();
1750 unsigned ValReg = MI->getOperand(1).getReg();
1752 OutStreamer->AddComment("eh_setjmp begin");
1753 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::ADDri)
1760 // 's' bit operand (always reg0 for this).
1763 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::STRi12)
1771 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::MOVi)
1777 // 's' bit operand (always reg0 for this).
1780 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::ADDri)
1787 // 's' bit operand (always reg0 for this).
1790 OutStreamer->AddComment("eh_setjmp end");
1791 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::MOVi)
1797 // 's' bit operand (always reg0 for this).
1801 case ARM::Int_eh_sjlj_longjmp: {
1802 // ldr sp, [$src, #8]
1803 // ldr $scratch, [$src, #4]
1806 unsigned SrcReg = MI->getOperand(0).getReg();
1807 unsigned ScratchReg = MI->getOperand(1).getReg();
1808 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::LDRi12)
1816 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::LDRi12)
1824 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::LDRi12)
1832 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::BX)
1839 case ARM::tInt_eh_sjlj_longjmp: {
1840 // ldr $scratch, [$src, #8]
1842 // ldr $scratch, [$src, #4]
1845 unsigned SrcReg = MI->getOperand(0).getReg();
1846 unsigned ScratchReg = MI->getOperand(1).getReg();
1847 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tLDRi)
1850 // The offset immediate is #8. The operand value is scaled by 4 for the
1851 // tLDR instruction.
1857 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tMOVr)
1864 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tLDRi)
1872 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tLDRi)
1880 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tBX)
1890 LowerARMMachineInstrToMCInst(MI, TmpInst, *this);
1892 EmitToStreamer(*OutStreamer, TmpInst);
1895 //===----------------------------------------------------------------------===//
1896 // Target Registry Stuff
1897 //===----------------------------------------------------------------------===//
1899 // Force static initialization.
1900 extern "C" void LLVMInitializeARMAsmPrinter() {
1901 RegisterAsmPrinter<ARMAsmPrinter> X(TheARMLETarget);
1902 RegisterAsmPrinter<ARMAsmPrinter> Y(TheARMBETarget);
1903 RegisterAsmPrinter<ARMAsmPrinter> A(TheThumbLETarget);
1904 RegisterAsmPrinter<ARMAsmPrinter> B(TheThumbBETarget);