1 //===-- ARMAsmPrinter.cpp - Print machine code to an ARM .s file ----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains a printer that converts from our internal representation
11 // of machine-dependent LLVM code to GAS-format ARM assembly language.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "asm-printer"
16 #include "ARMAsmPrinter.h"
18 #include "ARMConstantPoolValue.h"
19 #include "ARMFPUName.h"
20 #include "ARMMachineFunctionInfo.h"
21 #include "ARMTargetMachine.h"
22 #include "ARMTargetObjectFile.h"
23 #include "InstPrinter/ARMInstPrinter.h"
24 #include "MCTargetDesc/ARMAddressingModes.h"
25 #include "MCTargetDesc/ARMMCExpr.h"
26 #include "llvm/ADT/SetVector.h"
27 #include "llvm/ADT/SmallString.h"
28 #include "llvm/CodeGen/MachineFunctionPass.h"
29 #include "llvm/CodeGen/MachineJumpTableInfo.h"
30 #include "llvm/CodeGen/MachineModuleInfoImpls.h"
31 #include "llvm/DebugInfo.h"
32 #include "llvm/IR/Constants.h"
33 #include "llvm/IR/DataLayout.h"
34 #include "llvm/IR/Mangler.h"
35 #include "llvm/IR/Module.h"
36 #include "llvm/IR/Type.h"
37 #include "llvm/MC/MCAsmInfo.h"
38 #include "llvm/MC/MCAssembler.h"
39 #include "llvm/MC/MCContext.h"
40 #include "llvm/MC/MCELFStreamer.h"
41 #include "llvm/MC/MCInst.h"
42 #include "llvm/MC/MCInstBuilder.h"
43 #include "llvm/MC/MCObjectStreamer.h"
44 #include "llvm/MC/MCSectionMachO.h"
45 #include "llvm/MC/MCStreamer.h"
46 #include "llvm/MC/MCSymbol.h"
47 #include "llvm/Support/ARMBuildAttributes.h"
48 #include "llvm/Support/CommandLine.h"
49 #include "llvm/Support/Debug.h"
50 #include "llvm/Support/ELF.h"
51 #include "llvm/Support/ErrorHandling.h"
52 #include "llvm/Support/TargetRegistry.h"
53 #include "llvm/Support/raw_ostream.h"
54 #include "llvm/Target/TargetMachine.h"
58 /// EmitDwarfRegOp - Emit dwarf register operation.
59 void ARMAsmPrinter::EmitDwarfRegOp(const MachineLocation &MLoc,
60 bool Indirect) const {
61 const TargetRegisterInfo *RI = TM.getRegisterInfo();
62 if (RI->getDwarfRegNum(MLoc.getReg(), false) != -1) {
63 AsmPrinter::EmitDwarfRegOp(MLoc, Indirect);
66 assert(MLoc.isReg() && !Indirect &&
67 "This doesn't support offset/indirection - implement it if needed");
68 unsigned Reg = MLoc.getReg();
69 if (Reg >= ARM::S0 && Reg <= ARM::S31) {
70 assert(ARM::S0 + 31 == ARM::S31 && "Unexpected ARM S register numbering");
71 // S registers are described as bit-pieces of a register
72 // S[2x] = DW_OP_regx(256 + (x>>1)) DW_OP_bit_piece(32, 0)
73 // S[2x+1] = DW_OP_regx(256 + (x>>1)) DW_OP_bit_piece(32, 32)
75 unsigned SReg = Reg - ARM::S0;
76 bool odd = SReg & 0x1;
77 unsigned Rx = 256 + (SReg >> 1);
79 OutStreamer.AddComment("DW_OP_regx for S register");
80 EmitInt8(dwarf::DW_OP_regx);
82 OutStreamer.AddComment(Twine(SReg));
86 OutStreamer.AddComment("DW_OP_bit_piece 32 32");
87 EmitInt8(dwarf::DW_OP_bit_piece);
91 OutStreamer.AddComment("DW_OP_bit_piece 32 0");
92 EmitInt8(dwarf::DW_OP_bit_piece);
96 } else if (Reg >= ARM::Q0 && Reg <= ARM::Q15) {
97 assert(ARM::Q0 + 15 == ARM::Q15 && "Unexpected ARM Q register numbering");
98 // Q registers Q0-Q15 are described by composing two D registers together.
99 // Qx = DW_OP_regx(256+2x) DW_OP_piece(8) DW_OP_regx(256+2x+1)
102 unsigned QReg = Reg - ARM::Q0;
103 unsigned D1 = 256 + 2 * QReg;
104 unsigned D2 = D1 + 1;
106 OutStreamer.AddComment("DW_OP_regx for Q register: D1");
107 EmitInt8(dwarf::DW_OP_regx);
109 OutStreamer.AddComment("DW_OP_piece 8");
110 EmitInt8(dwarf::DW_OP_piece);
113 OutStreamer.AddComment("DW_OP_regx for Q register: D2");
114 EmitInt8(dwarf::DW_OP_regx);
116 OutStreamer.AddComment("DW_OP_piece 8");
117 EmitInt8(dwarf::DW_OP_piece);
122 void ARMAsmPrinter::EmitFunctionBodyEnd() {
123 // Make sure to terminate any constant pools that were at the end
127 InConstantPool = false;
128 OutStreamer.EmitDataRegion(MCDR_DataRegionEnd);
131 void ARMAsmPrinter::EmitFunctionEntryLabel() {
132 if (AFI->isThumbFunction()) {
133 OutStreamer.EmitAssemblerFlag(MCAF_Code16);
134 OutStreamer.EmitThumbFunc(CurrentFnSym);
137 OutStreamer.EmitLabel(CurrentFnSym);
140 void ARMAsmPrinter::EmitXXStructor(const Constant *CV) {
141 uint64_t Size = TM.getDataLayout()->getTypeAllocSize(CV->getType());
142 assert(Size && "C++ constructor pointer had zero size!");
144 const GlobalValue *GV = dyn_cast<GlobalValue>(CV->stripPointerCasts());
145 assert(GV && "C++ constructor pointer was not a GlobalValue!");
147 const MCExpr *E = MCSymbolRefExpr::Create(getSymbol(GV),
148 (Subtarget->isTargetELF()
149 ? MCSymbolRefExpr::VK_ARM_TARGET1
150 : MCSymbolRefExpr::VK_None),
153 OutStreamer.EmitValue(E, Size);
156 /// runOnMachineFunction - This uses the EmitInstruction()
157 /// method to print assembly for each instruction.
159 bool ARMAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
160 AFI = MF.getInfo<ARMFunctionInfo>();
161 MCP = MF.getConstantPool();
163 return AsmPrinter::runOnMachineFunction(MF);
166 void ARMAsmPrinter::printOperand(const MachineInstr *MI, int OpNum,
167 raw_ostream &O, const char *Modifier) {
168 const MachineOperand &MO = MI->getOperand(OpNum);
169 unsigned TF = MO.getTargetFlags();
171 switch (MO.getType()) {
172 default: llvm_unreachable("<unknown operand type>");
173 case MachineOperand::MO_Register: {
174 unsigned Reg = MO.getReg();
175 assert(TargetRegisterInfo::isPhysicalRegister(Reg));
176 assert(!MO.getSubReg() && "Subregs should be eliminated!");
177 if(ARM::GPRPairRegClass.contains(Reg)) {
178 const MachineFunction &MF = *MI->getParent()->getParent();
179 const TargetRegisterInfo *TRI = MF.getTarget().getRegisterInfo();
180 Reg = TRI->getSubReg(Reg, ARM::gsub_0);
182 O << ARMInstPrinter::getRegisterName(Reg);
185 case MachineOperand::MO_Immediate: {
186 int64_t Imm = MO.getImm();
188 if ((Modifier && strcmp(Modifier, "lo16") == 0) ||
189 (TF == ARMII::MO_LO16))
191 else if ((Modifier && strcmp(Modifier, "hi16") == 0) ||
192 (TF == ARMII::MO_HI16))
197 case MachineOperand::MO_MachineBasicBlock:
198 O << *MO.getMBB()->getSymbol();
200 case MachineOperand::MO_GlobalAddress: {
201 const GlobalValue *GV = MO.getGlobal();
202 if ((Modifier && strcmp(Modifier, "lo16") == 0) ||
203 (TF & ARMII::MO_LO16))
205 else if ((Modifier && strcmp(Modifier, "hi16") == 0) ||
206 (TF & ARMII::MO_HI16))
210 printOffset(MO.getOffset(), O);
211 if (TF == ARMII::MO_PLT)
215 case MachineOperand::MO_ConstantPoolIndex:
216 O << *GetCPISymbol(MO.getIndex());
221 //===--------------------------------------------------------------------===//
223 MCSymbol *ARMAsmPrinter::
224 GetARMJTIPICJumpTableLabel2(unsigned uid, unsigned uid2) const {
225 const DataLayout *DL = TM.getDataLayout();
226 SmallString<60> Name;
227 raw_svector_ostream(Name) << DL->getPrivateGlobalPrefix() << "JTI"
228 << getFunctionNumber() << '_' << uid << '_' << uid2;
229 return OutContext.GetOrCreateSymbol(Name.str());
233 MCSymbol *ARMAsmPrinter::GetARMSJLJEHLabel() const {
234 const DataLayout *DL = TM.getDataLayout();
235 SmallString<60> Name;
236 raw_svector_ostream(Name) << DL->getPrivateGlobalPrefix() << "SJLJEH"
237 << getFunctionNumber();
238 return OutContext.GetOrCreateSymbol(Name.str());
241 bool ARMAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
242 unsigned AsmVariant, const char *ExtraCode,
244 // Does this asm operand have a single letter operand modifier?
245 if (ExtraCode && ExtraCode[0]) {
246 if (ExtraCode[1] != 0) return true; // Unknown modifier.
248 switch (ExtraCode[0]) {
250 // See if this is a generic print operand
251 return AsmPrinter::PrintAsmOperand(MI, OpNum, AsmVariant, ExtraCode, O);
252 case 'a': // Print as a memory address.
253 if (MI->getOperand(OpNum).isReg()) {
255 << ARMInstPrinter::getRegisterName(MI->getOperand(OpNum).getReg())
260 case 'c': // Don't print "#" before an immediate operand.
261 if (!MI->getOperand(OpNum).isImm())
263 O << MI->getOperand(OpNum).getImm();
265 case 'P': // Print a VFP double precision register.
266 case 'q': // Print a NEON quad precision register.
267 printOperand(MI, OpNum, O);
269 case 'y': // Print a VFP single precision register as indexed double.
270 if (MI->getOperand(OpNum).isReg()) {
271 unsigned Reg = MI->getOperand(OpNum).getReg();
272 const TargetRegisterInfo *TRI = MF->getTarget().getRegisterInfo();
273 // Find the 'd' register that has this 's' register as a sub-register,
274 // and determine the lane number.
275 for (MCSuperRegIterator SR(Reg, TRI); SR.isValid(); ++SR) {
276 if (!ARM::DPRRegClass.contains(*SR))
278 bool Lane0 = TRI->getSubReg(*SR, ARM::ssub_0) == Reg;
279 O << ARMInstPrinter::getRegisterName(*SR) << (Lane0 ? "[0]" : "[1]");
284 case 'B': // Bitwise inverse of integer or symbol without a preceding #.
285 if (!MI->getOperand(OpNum).isImm())
287 O << ~(MI->getOperand(OpNum).getImm());
289 case 'L': // The low 16 bits of an immediate constant.
290 if (!MI->getOperand(OpNum).isImm())
292 O << (MI->getOperand(OpNum).getImm() & 0xffff);
294 case 'M': { // A register range suitable for LDM/STM.
295 if (!MI->getOperand(OpNum).isReg())
297 const MachineOperand &MO = MI->getOperand(OpNum);
298 unsigned RegBegin = MO.getReg();
299 // This takes advantage of the 2 operand-ness of ldm/stm and that we've
300 // already got the operands in registers that are operands to the
301 // inline asm statement.
303 if (ARM::GPRPairRegClass.contains(RegBegin)) {
304 const TargetRegisterInfo *TRI = MF->getTarget().getRegisterInfo();
305 unsigned Reg0 = TRI->getSubReg(RegBegin, ARM::gsub_0);
306 O << ARMInstPrinter::getRegisterName(Reg0) << ", ";;
307 RegBegin = TRI->getSubReg(RegBegin, ARM::gsub_1);
309 O << ARMInstPrinter::getRegisterName(RegBegin);
311 // FIXME: The register allocator not only may not have given us the
312 // registers in sequence, but may not be in ascending registers. This
313 // will require changes in the register allocator that'll need to be
314 // propagated down here if the operands change.
315 unsigned RegOps = OpNum + 1;
316 while (MI->getOperand(RegOps).isReg()) {
318 << ARMInstPrinter::getRegisterName(MI->getOperand(RegOps).getReg());
326 case 'R': // The most significant register of a pair.
327 case 'Q': { // The least significant register of a pair.
330 const MachineOperand &FlagsOP = MI->getOperand(OpNum - 1);
331 if (!FlagsOP.isImm())
333 unsigned Flags = FlagsOP.getImm();
335 // This operand may not be the one that actually provides the register. If
336 // it's tied to a previous one then we should refer instead to that one
337 // for registers and their classes.
339 if (InlineAsm::isUseOperandTiedToDef(Flags, TiedIdx)) {
340 for (OpNum = InlineAsm::MIOp_FirstOperand; TiedIdx; --TiedIdx) {
341 unsigned OpFlags = MI->getOperand(OpNum).getImm();
342 OpNum += InlineAsm::getNumOperandRegisters(OpFlags) + 1;
344 Flags = MI->getOperand(OpNum).getImm();
346 // Later code expects OpNum to be pointing at the register rather than
351 unsigned NumVals = InlineAsm::getNumOperandRegisters(Flags);
353 InlineAsm::hasRegClassConstraint(Flags, RC);
354 if (RC == ARM::GPRPairRegClassID) {
357 const MachineOperand &MO = MI->getOperand(OpNum);
360 const TargetRegisterInfo *TRI = MF->getTarget().getRegisterInfo();
361 unsigned Reg = TRI->getSubReg(MO.getReg(), ExtraCode[0] == 'Q' ?
362 ARM::gsub_0 : ARM::gsub_1);
363 O << ARMInstPrinter::getRegisterName(Reg);
368 unsigned RegOp = ExtraCode[0] == 'Q' ? OpNum : OpNum + 1;
369 if (RegOp >= MI->getNumOperands())
371 const MachineOperand &MO = MI->getOperand(RegOp);
374 unsigned Reg = MO.getReg();
375 O << ARMInstPrinter::getRegisterName(Reg);
379 case 'e': // The low doubleword register of a NEON quad register.
380 case 'f': { // The high doubleword register of a NEON quad register.
381 if (!MI->getOperand(OpNum).isReg())
383 unsigned Reg = MI->getOperand(OpNum).getReg();
384 if (!ARM::QPRRegClass.contains(Reg))
386 const TargetRegisterInfo *TRI = MF->getTarget().getRegisterInfo();
387 unsigned SubReg = TRI->getSubReg(Reg, ExtraCode[0] == 'e' ?
388 ARM::dsub_0 : ARM::dsub_1);
389 O << ARMInstPrinter::getRegisterName(SubReg);
393 // This modifier is not yet supported.
394 case 'h': // A range of VFP/NEON registers suitable for VLD1/VST1.
396 case 'H': { // The highest-numbered register of a pair.
397 const MachineOperand &MO = MI->getOperand(OpNum);
400 const MachineFunction &MF = *MI->getParent()->getParent();
401 const TargetRegisterInfo *TRI = MF.getTarget().getRegisterInfo();
402 unsigned Reg = MO.getReg();
403 if(!ARM::GPRPairRegClass.contains(Reg))
405 Reg = TRI->getSubReg(Reg, ARM::gsub_1);
406 O << ARMInstPrinter::getRegisterName(Reg);
412 printOperand(MI, OpNum, O);
416 bool ARMAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI,
417 unsigned OpNum, unsigned AsmVariant,
418 const char *ExtraCode,
420 // Does this asm operand have a single letter operand modifier?
421 if (ExtraCode && ExtraCode[0]) {
422 if (ExtraCode[1] != 0) return true; // Unknown modifier.
424 switch (ExtraCode[0]) {
425 case 'A': // A memory operand for a VLD1/VST1 instruction.
426 default: return true; // Unknown modifier.
427 case 'm': // The base register of a memory operand.
428 if (!MI->getOperand(OpNum).isReg())
430 O << ARMInstPrinter::getRegisterName(MI->getOperand(OpNum).getReg());
435 const MachineOperand &MO = MI->getOperand(OpNum);
436 assert(MO.isReg() && "unexpected inline asm memory operand");
437 O << "[" << ARMInstPrinter::getRegisterName(MO.getReg()) << "]";
441 static bool isThumb(const MCSubtargetInfo& STI) {
442 return (STI.getFeatureBits() & ARM::ModeThumb) != 0;
445 void ARMAsmPrinter::emitInlineAsmEnd(const MCSubtargetInfo &StartInfo,
446 MCSubtargetInfo *EndInfo) const {
447 // If either end mode is unknown (EndInfo == NULL) or different than
448 // the start mode, then restore the start mode.
449 const bool WasThumb = isThumb(StartInfo);
450 if (EndInfo == NULL || WasThumb != isThumb(*EndInfo)) {
451 OutStreamer.EmitAssemblerFlag(WasThumb ? MCAF_Code16 : MCAF_Code32);
453 EndInfo->ToggleFeature(ARM::ModeThumb);
457 void ARMAsmPrinter::EmitStartOfAsmFile(Module &M) {
458 if (Subtarget->isTargetMachO()) {
459 Reloc::Model RelocM = TM.getRelocationModel();
460 if (RelocM == Reloc::PIC_ || RelocM == Reloc::DynamicNoPIC) {
461 // Declare all the text sections up front (before the DWARF sections
462 // emitted by AsmPrinter::doInitialization) so the assembler will keep
463 // them together at the beginning of the object file. This helps
464 // avoid out-of-range branches that are due a fundamental limitation of
465 // the way symbol offsets are encoded with the current Darwin ARM
467 const TargetLoweringObjectFileMachO &TLOFMacho =
468 static_cast<const TargetLoweringObjectFileMachO &>(
469 getObjFileLowering());
471 // Collect the set of sections our functions will go into.
472 SetVector<const MCSection *, SmallVector<const MCSection *, 8>,
473 SmallPtrSet<const MCSection *, 8> > TextSections;
474 // Default text section comes first.
475 TextSections.insert(TLOFMacho.getTextSection());
476 // Now any user defined text sections from function attributes.
477 for (Module::iterator F = M.begin(), e = M.end(); F != e; ++F)
478 if (!F->isDeclaration() && !F->hasAvailableExternallyLinkage())
479 TextSections.insert(TLOFMacho.SectionForGlobal(F, Mang, TM));
480 // Now the coalescable sections.
481 TextSections.insert(TLOFMacho.getTextCoalSection());
482 TextSections.insert(TLOFMacho.getConstTextCoalSection());
484 // Emit the sections in the .s file header to fix the order.
485 for (unsigned i = 0, e = TextSections.size(); i != e; ++i)
486 OutStreamer.SwitchSection(TextSections[i]);
488 if (RelocM == Reloc::DynamicNoPIC) {
489 const MCSection *sect =
490 OutContext.getMachOSection("__TEXT", "__symbol_stub4",
491 MCSectionMachO::S_SYMBOL_STUBS,
492 12, SectionKind::getText());
493 OutStreamer.SwitchSection(sect);
495 const MCSection *sect =
496 OutContext.getMachOSection("__TEXT", "__picsymbolstub4",
497 MCSectionMachO::S_SYMBOL_STUBS,
498 16, SectionKind::getText());
499 OutStreamer.SwitchSection(sect);
501 const MCSection *StaticInitSect =
502 OutContext.getMachOSection("__TEXT", "__StaticInit",
503 MCSectionMachO::S_REGULAR |
504 MCSectionMachO::S_ATTR_PURE_INSTRUCTIONS,
505 SectionKind::getText());
506 OutStreamer.SwitchSection(StaticInitSect);
509 // Compiling with debug info should not affect the code
510 // generation. Ensure the cstring section comes before the
511 // optional __DWARF secion. Otherwise, PC-relative loads would
512 // have to use different instruction sequences at "-g" in order to
513 // reach global data in the same object file.
514 OutStreamer.SwitchSection(getObjFileLowering().getCStringSection());
517 // Use unified assembler syntax.
518 OutStreamer.EmitAssemblerFlag(MCAF_SyntaxUnified);
520 // Emit ARM Build Attributes
521 if (Subtarget->isTargetELF())
526 void ARMAsmPrinter::EmitEndOfAsmFile(Module &M) {
527 if (Subtarget->isTargetMachO()) {
528 // All darwin targets use mach-o.
529 const TargetLoweringObjectFileMachO &TLOFMacho =
530 static_cast<const TargetLoweringObjectFileMachO &>(getObjFileLowering());
531 MachineModuleInfoMachO &MMIMacho =
532 MMI->getObjFileInfo<MachineModuleInfoMachO>();
534 // Output non-lazy-pointers for external and common global variables.
535 MachineModuleInfoMachO::SymbolListTy Stubs = MMIMacho.GetGVStubList();
537 if (!Stubs.empty()) {
538 // Switch with ".non_lazy_symbol_pointer" directive.
539 OutStreamer.SwitchSection(TLOFMacho.getNonLazySymbolPointerSection());
541 for (unsigned i = 0, e = Stubs.size(); i != e; ++i) {
543 OutStreamer.EmitLabel(Stubs[i].first);
544 // .indirect_symbol _foo
545 MachineModuleInfoImpl::StubValueTy &MCSym = Stubs[i].second;
546 OutStreamer.EmitSymbolAttribute(MCSym.getPointer(),MCSA_IndirectSymbol);
549 // External to current translation unit.
550 OutStreamer.EmitIntValue(0, 4/*size*/);
552 // Internal to current translation unit.
554 // When we place the LSDA into the TEXT section, the type info
555 // pointers need to be indirect and pc-rel. We accomplish this by
556 // using NLPs; however, sometimes the types are local to the file.
557 // We need to fill in the value for the NLP in those cases.
558 OutStreamer.EmitValue(MCSymbolRefExpr::Create(MCSym.getPointer(),
564 OutStreamer.AddBlankLine();
567 Stubs = MMIMacho.GetHiddenGVStubList();
568 if (!Stubs.empty()) {
569 OutStreamer.SwitchSection(getObjFileLowering().getDataSection());
571 for (unsigned i = 0, e = Stubs.size(); i != e; ++i) {
573 OutStreamer.EmitLabel(Stubs[i].first);
575 OutStreamer.EmitValue(MCSymbolRefExpr::
576 Create(Stubs[i].second.getPointer(),
582 OutStreamer.AddBlankLine();
585 // Funny Darwin hack: This flag tells the linker that no global symbols
586 // contain code that falls through to other global symbols (e.g. the obvious
587 // implementation of multiple entry points). If this doesn't occur, the
588 // linker can safely perform dead code stripping. Since LLVM never
589 // generates code that does this, it is always safe to set.
590 OutStreamer.EmitAssemblerFlag(MCAF_SubsectionsViaSymbols);
594 //===----------------------------------------------------------------------===//
595 // Helper routines for EmitStartOfAsmFile() and EmitEndOfAsmFile()
597 // The following seem like one-off assembler flags, but they actually need
598 // to appear in the .ARM.attributes section in ELF.
599 // Instead of subclassing the MCELFStreamer, we do the work here.
601 static ARMBuildAttrs::CPUArch getArchForCPU(StringRef CPU,
602 const ARMSubtarget *Subtarget) {
604 return ARMBuildAttrs::v5TEJ;
606 if (Subtarget->hasV8Ops())
607 return ARMBuildAttrs::v8;
608 else if (Subtarget->hasV7Ops()) {
609 if (Subtarget->isMClass() && Subtarget->hasThumb2DSP())
610 return ARMBuildAttrs::v7E_M;
611 return ARMBuildAttrs::v7;
612 } else if (Subtarget->hasV6T2Ops())
613 return ARMBuildAttrs::v6T2;
614 else if (Subtarget->hasV6MOps())
615 return ARMBuildAttrs::v6S_M;
616 else if (Subtarget->hasV6Ops())
617 return ARMBuildAttrs::v6;
618 else if (Subtarget->hasV5TEOps())
619 return ARMBuildAttrs::v5TE;
620 else if (Subtarget->hasV5TOps())
621 return ARMBuildAttrs::v5T;
622 else if (Subtarget->hasV4TOps())
623 return ARMBuildAttrs::v4T;
625 return ARMBuildAttrs::v4;
628 void ARMAsmPrinter::emitAttributes() {
629 MCTargetStreamer &TS = *OutStreamer.getTargetStreamer();
630 ARMTargetStreamer &ATS = static_cast<ARMTargetStreamer &>(TS);
632 ATS.switchVendor("aeabi");
634 std::string CPUString = Subtarget->getCPUString();
636 // FIXME: remove krait check when GNU tools support krait cpu
637 if (CPUString != "generic" && CPUString != "krait")
638 ATS.emitTextAttribute(ARMBuildAttrs::CPU_name, CPUString);
640 ATS.emitAttribute(ARMBuildAttrs::CPU_arch,
641 getArchForCPU(CPUString, Subtarget));
643 // Tag_CPU_arch_profile must have the default value of 0 when "Architecture
644 // profile is not applicable (e.g. pre v7, or cross-profile code)".
645 if (Subtarget->hasV7Ops()) {
646 if (Subtarget->isAClass()) {
647 ATS.emitAttribute(ARMBuildAttrs::CPU_arch_profile,
648 ARMBuildAttrs::ApplicationProfile);
649 } else if (Subtarget->isRClass()) {
650 ATS.emitAttribute(ARMBuildAttrs::CPU_arch_profile,
651 ARMBuildAttrs::RealTimeProfile);
652 } else if (Subtarget->isMClass()) {
653 ATS.emitAttribute(ARMBuildAttrs::CPU_arch_profile,
654 ARMBuildAttrs::MicroControllerProfile);
658 ATS.emitAttribute(ARMBuildAttrs::ARM_ISA_use, Subtarget->hasARMOps() ?
659 ARMBuildAttrs::Allowed : ARMBuildAttrs::Not_Allowed);
660 if (Subtarget->isThumb1Only()) {
661 ATS.emitAttribute(ARMBuildAttrs::THUMB_ISA_use,
662 ARMBuildAttrs::Allowed);
663 } else if (Subtarget->hasThumb2()) {
664 ATS.emitAttribute(ARMBuildAttrs::THUMB_ISA_use,
665 ARMBuildAttrs::AllowThumb32);
668 if (Subtarget->hasNEON()) {
669 /* NEON is not exactly a VFP architecture, but GAS emit one of
670 * neon/neon-fp-armv8/neon-vfpv4/vfpv3/vfpv2 for .fpu parameters */
671 if (Subtarget->hasFPARMv8()) {
672 if (Subtarget->hasCrypto())
673 ATS.emitFPU(ARM::CRYPTO_NEON_FP_ARMV8);
675 ATS.emitFPU(ARM::NEON_FP_ARMV8);
677 else if (Subtarget->hasVFP4())
678 ATS.emitFPU(ARM::NEON_VFPV4);
680 ATS.emitFPU(ARM::NEON);
681 // Emit Tag_Advanced_SIMD_arch for ARMv8 architecture
682 if (Subtarget->hasV8Ops())
683 ATS.emitAttribute(ARMBuildAttrs::Advanced_SIMD_arch,
684 ARMBuildAttrs::AllowNeonARMv8);
686 if (Subtarget->hasFPARMv8())
687 ATS.emitFPU(ARM::FP_ARMV8);
688 else if (Subtarget->hasVFP4())
689 ATS.emitFPU(Subtarget->hasD16() ? ARM::VFPV4_D16 : ARM::VFPV4);
690 else if (Subtarget->hasVFP3())
691 ATS.emitFPU(Subtarget->hasD16() ? ARM::VFPV3_D16 : ARM::VFPV3);
692 else if (Subtarget->hasVFP2())
693 ATS.emitFPU(ARM::VFPV2);
696 // Signal various FP modes.
697 if (!TM.Options.UnsafeFPMath) {
698 ATS.emitAttribute(ARMBuildAttrs::ABI_FP_denormal, ARMBuildAttrs::Allowed);
699 ATS.emitAttribute(ARMBuildAttrs::ABI_FP_exceptions,
700 ARMBuildAttrs::Allowed);
703 if (TM.Options.NoInfsFPMath && TM.Options.NoNaNsFPMath)
704 ATS.emitAttribute(ARMBuildAttrs::ABI_FP_number_model,
705 ARMBuildAttrs::Allowed);
707 ATS.emitAttribute(ARMBuildAttrs::ABI_FP_number_model,
708 ARMBuildAttrs::AllowIEE754);
710 // FIXME: add more flags to ARMBuildAttributes.h
711 // 8-bytes alignment stuff.
712 ATS.emitAttribute(ARMBuildAttrs::ABI_align_needed, 1);
713 ATS.emitAttribute(ARMBuildAttrs::ABI_align_preserved, 1);
715 // ABI_HardFP_use attribute to indicate single precision FP.
716 if (Subtarget->isFPOnlySP())
717 ATS.emitAttribute(ARMBuildAttrs::ABI_HardFP_use,
718 ARMBuildAttrs::HardFPSinglePrecision);
720 // Hard float. Use both S and D registers and conform to AAPCS-VFP.
721 if (Subtarget->isAAPCS_ABI() && TM.Options.FloatABIType == FloatABI::Hard)
722 ATS.emitAttribute(ARMBuildAttrs::ABI_VFP_args, ARMBuildAttrs::HardFPAAPCS);
724 // FIXME: Should we signal R9 usage?
726 if (Subtarget->hasFP16())
727 ATS.emitAttribute(ARMBuildAttrs::FP_HP_extension, ARMBuildAttrs::AllowHPFP);
729 if (Subtarget->hasMPExtension())
730 ATS.emitAttribute(ARMBuildAttrs::MPextension_use, ARMBuildAttrs::AllowMP);
732 // Hardware divide in ARM mode is part of base arch, starting from ARMv8.
733 // If only Thumb hwdiv is present, it must also be in base arch (ARMv7-R/M).
734 // It is not possible to produce DisallowDIV: if hwdiv is present in the base
735 // arch, supplying -hwdiv downgrades the effective arch, via ClearImpliedBits.
736 // AllowDIVExt is only emitted if hwdiv isn't available in the base arch;
737 // otherwise, the default value (AllowDIVIfExists) applies.
738 if (Subtarget->hasDivideInARMMode() && !Subtarget->hasV8Ops())
739 ATS.emitAttribute(ARMBuildAttrs::DIV_use, ARMBuildAttrs::AllowDIVExt);
741 if (Subtarget->hasTrustZone() && Subtarget->hasVirtualization())
742 ATS.emitAttribute(ARMBuildAttrs::Virtualization_use,
743 ARMBuildAttrs::AllowTZVirtualization);
744 else if (Subtarget->hasTrustZone())
745 ATS.emitAttribute(ARMBuildAttrs::Virtualization_use,
746 ARMBuildAttrs::AllowTZ);
747 else if (Subtarget->hasVirtualization())
748 ATS.emitAttribute(ARMBuildAttrs::Virtualization_use,
749 ARMBuildAttrs::AllowVirtualization);
751 ATS.finishAttributeSection();
754 //===----------------------------------------------------------------------===//
756 static MCSymbol *getPICLabel(const char *Prefix, unsigned FunctionNumber,
757 unsigned LabelId, MCContext &Ctx) {
759 MCSymbol *Label = Ctx.GetOrCreateSymbol(Twine(Prefix)
760 + "PC" + Twine(FunctionNumber) + "_" + Twine(LabelId));
764 static MCSymbolRefExpr::VariantKind
765 getModifierVariantKind(ARMCP::ARMCPModifier Modifier) {
767 case ARMCP::no_modifier: return MCSymbolRefExpr::VK_None;
768 case ARMCP::TLSGD: return MCSymbolRefExpr::VK_TLSGD;
769 case ARMCP::TPOFF: return MCSymbolRefExpr::VK_TPOFF;
770 case ARMCP::GOTTPOFF: return MCSymbolRefExpr::VK_GOTTPOFF;
771 case ARMCP::GOT: return MCSymbolRefExpr::VK_GOT;
772 case ARMCP::GOTOFF: return MCSymbolRefExpr::VK_GOTOFF;
774 llvm_unreachable("Invalid ARMCPModifier!");
777 MCSymbol *ARMAsmPrinter::GetARMGVSymbol(const GlobalValue *GV,
778 unsigned char TargetFlags) {
779 bool isIndirect = Subtarget->isTargetMachO() &&
780 (TargetFlags & ARMII::MO_NONLAZY) &&
781 Subtarget->GVIsIndirectSymbol(GV, TM.getRelocationModel());
783 return getSymbol(GV);
785 // FIXME: Remove this when Darwin transition to @GOT like syntax.
786 MCSymbol *MCSym = getSymbolWithGlobalValueBase(GV, "$non_lazy_ptr");
787 MachineModuleInfoMachO &MMIMachO =
788 MMI->getObjFileInfo<MachineModuleInfoMachO>();
789 MachineModuleInfoImpl::StubValueTy &StubSym =
790 GV->hasHiddenVisibility() ? MMIMachO.getHiddenGVStubEntry(MCSym) :
791 MMIMachO.getGVStubEntry(MCSym);
792 if (StubSym.getPointer() == 0)
793 StubSym = MachineModuleInfoImpl::
794 StubValueTy(getSymbol(GV), !GV->hasInternalLinkage());
799 EmitMachineConstantPoolValue(MachineConstantPoolValue *MCPV) {
800 const DataLayout *DL = TM.getDataLayout();
801 int Size = TM.getDataLayout()->getTypeAllocSize(MCPV->getType());
803 ARMConstantPoolValue *ACPV = static_cast<ARMConstantPoolValue*>(MCPV);
806 if (ACPV->isLSDA()) {
807 SmallString<128> Str;
808 raw_svector_ostream OS(Str);
809 OS << DL->getPrivateGlobalPrefix() << "_LSDA_" << getFunctionNumber();
810 MCSym = OutContext.GetOrCreateSymbol(OS.str());
811 } else if (ACPV->isBlockAddress()) {
812 const BlockAddress *BA =
813 cast<ARMConstantPoolConstant>(ACPV)->getBlockAddress();
814 MCSym = GetBlockAddressSymbol(BA);
815 } else if (ACPV->isGlobalValue()) {
816 const GlobalValue *GV = cast<ARMConstantPoolConstant>(ACPV)->getGV();
818 // On Darwin, const-pool entries may get the "FOO$non_lazy_ptr" mangling, so
819 // flag the global as MO_NONLAZY.
820 unsigned char TF = Subtarget->isTargetMachO() ? ARMII::MO_NONLAZY : 0;
821 MCSym = GetARMGVSymbol(GV, TF);
822 } else if (ACPV->isMachineBasicBlock()) {
823 const MachineBasicBlock *MBB = cast<ARMConstantPoolMBB>(ACPV)->getMBB();
824 MCSym = MBB->getSymbol();
826 assert(ACPV->isExtSymbol() && "unrecognized constant pool value");
827 const char *Sym = cast<ARMConstantPoolSymbol>(ACPV)->getSymbol();
828 MCSym = GetExternalSymbolSymbol(Sym);
831 // Create an MCSymbol for the reference.
833 MCSymbolRefExpr::Create(MCSym, getModifierVariantKind(ACPV->getModifier()),
836 if (ACPV->getPCAdjustment()) {
837 MCSymbol *PCLabel = getPICLabel(DL->getPrivateGlobalPrefix(),
841 const MCExpr *PCRelExpr = MCSymbolRefExpr::Create(PCLabel, OutContext);
843 MCBinaryExpr::CreateAdd(PCRelExpr,
844 MCConstantExpr::Create(ACPV->getPCAdjustment(),
847 if (ACPV->mustAddCurrentAddress()) {
848 // We want "(<expr> - .)", but MC doesn't have a concept of the '.'
849 // label, so just emit a local label end reference that instead.
850 MCSymbol *DotSym = OutContext.CreateTempSymbol();
851 OutStreamer.EmitLabel(DotSym);
852 const MCExpr *DotExpr = MCSymbolRefExpr::Create(DotSym, OutContext);
853 PCRelExpr = MCBinaryExpr::CreateSub(PCRelExpr, DotExpr, OutContext);
855 Expr = MCBinaryExpr::CreateSub(Expr, PCRelExpr, OutContext);
857 OutStreamer.EmitValue(Expr, Size);
860 void ARMAsmPrinter::EmitJumpTable(const MachineInstr *MI) {
861 unsigned Opcode = MI->getOpcode();
863 if (Opcode == ARM::BR_JTadd)
865 else if (Opcode == ARM::BR_JTm)
868 const MachineOperand &MO1 = MI->getOperand(OpNum);
869 const MachineOperand &MO2 = MI->getOperand(OpNum+1); // Unique Id
870 unsigned JTI = MO1.getIndex();
872 // Emit a label for the jump table.
873 MCSymbol *JTISymbol = GetARMJTIPICJumpTableLabel2(JTI, MO2.getImm());
874 OutStreamer.EmitLabel(JTISymbol);
876 // Mark the jump table as data-in-code.
877 OutStreamer.EmitDataRegion(MCDR_DataRegionJT32);
879 // Emit each entry of the table.
880 const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
881 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
882 const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
884 for (unsigned i = 0, e = JTBBs.size(); i != e; ++i) {
885 MachineBasicBlock *MBB = JTBBs[i];
886 // Construct an MCExpr for the entry. We want a value of the form:
887 // (BasicBlockAddr - TableBeginAddr)
889 // For example, a table with entries jumping to basic blocks BB0 and BB1
892 // .word (LBB0 - LJTI_0_0)
893 // .word (LBB1 - LJTI_0_0)
894 const MCExpr *Expr = MCSymbolRefExpr::Create(MBB->getSymbol(), OutContext);
896 if (TM.getRelocationModel() == Reloc::PIC_)
897 Expr = MCBinaryExpr::CreateSub(Expr, MCSymbolRefExpr::Create(JTISymbol,
900 // If we're generating a table of Thumb addresses in static relocation
901 // model, we need to add one to keep interworking correctly.
902 else if (AFI->isThumbFunction())
903 Expr = MCBinaryExpr::CreateAdd(Expr, MCConstantExpr::Create(1,OutContext),
905 OutStreamer.EmitValue(Expr, 4);
907 // Mark the end of jump table data-in-code region.
908 OutStreamer.EmitDataRegion(MCDR_DataRegionEnd);
911 void ARMAsmPrinter::EmitJump2Table(const MachineInstr *MI) {
912 unsigned Opcode = MI->getOpcode();
913 int OpNum = (Opcode == ARM::t2BR_JT) ? 2 : 1;
914 const MachineOperand &MO1 = MI->getOperand(OpNum);
915 const MachineOperand &MO2 = MI->getOperand(OpNum+1); // Unique Id
916 unsigned JTI = MO1.getIndex();
918 MCSymbol *JTISymbol = GetARMJTIPICJumpTableLabel2(JTI, MO2.getImm());
919 OutStreamer.EmitLabel(JTISymbol);
921 // Emit each entry of the table.
922 const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
923 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
924 const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
925 unsigned OffsetWidth = 4;
926 if (MI->getOpcode() == ARM::t2TBB_JT) {
928 // Mark the jump table as data-in-code.
929 OutStreamer.EmitDataRegion(MCDR_DataRegionJT8);
930 } else if (MI->getOpcode() == ARM::t2TBH_JT) {
932 // Mark the jump table as data-in-code.
933 OutStreamer.EmitDataRegion(MCDR_DataRegionJT16);
936 for (unsigned i = 0, e = JTBBs.size(); i != e; ++i) {
937 MachineBasicBlock *MBB = JTBBs[i];
938 const MCExpr *MBBSymbolExpr = MCSymbolRefExpr::Create(MBB->getSymbol(),
940 // If this isn't a TBB or TBH, the entries are direct branch instructions.
941 if (OffsetWidth == 4) {
942 OutStreamer.EmitInstruction(MCInstBuilder(ARM::t2B)
943 .addExpr(MBBSymbolExpr)
948 // Otherwise it's an offset from the dispatch instruction. Construct an
949 // MCExpr for the entry. We want a value of the form:
950 // (BasicBlockAddr - TableBeginAddr) / 2
952 // For example, a TBB table with entries jumping to basic blocks BB0 and BB1
955 // .byte (LBB0 - LJTI_0_0) / 2
956 // .byte (LBB1 - LJTI_0_0) / 2
958 MCBinaryExpr::CreateSub(MBBSymbolExpr,
959 MCSymbolRefExpr::Create(JTISymbol, OutContext),
961 Expr = MCBinaryExpr::CreateDiv(Expr, MCConstantExpr::Create(2, OutContext),
963 OutStreamer.EmitValue(Expr, OffsetWidth);
965 // Mark the end of jump table data-in-code region. 32-bit offsets use
966 // actual branch instructions here, so we don't mark those as a data-region
968 if (OffsetWidth != 4)
969 OutStreamer.EmitDataRegion(MCDR_DataRegionEnd);
972 void ARMAsmPrinter::EmitUnwindingInstruction(const MachineInstr *MI) {
973 assert(MI->getFlag(MachineInstr::FrameSetup) &&
974 "Only instruction which are involved into frame setup code are allowed");
976 MCTargetStreamer &TS = *OutStreamer.getTargetStreamer();
977 ARMTargetStreamer &ATS = static_cast<ARMTargetStreamer &>(TS);
978 const MachineFunction &MF = *MI->getParent()->getParent();
979 const TargetRegisterInfo *RegInfo = MF.getTarget().getRegisterInfo();
980 const ARMFunctionInfo &AFI = *MF.getInfo<ARMFunctionInfo>();
982 unsigned FramePtr = RegInfo->getFrameRegister(MF);
983 unsigned Opc = MI->getOpcode();
984 unsigned SrcReg, DstReg;
986 if (Opc == ARM::tPUSH || Opc == ARM::tLDRpci) {
987 // Two special cases:
988 // 1) tPUSH does not have src/dst regs.
989 // 2) for Thumb1 code we sometimes materialize the constant via constpool
990 // load. Yes, this is pretty fragile, but for now I don't see better
992 SrcReg = DstReg = ARM::SP;
994 SrcReg = MI->getOperand(1).getReg();
995 DstReg = MI->getOperand(0).getReg();
998 // Try to figure out the unwinding opcode out of src / dst regs.
999 if (MI->mayStore()) {
1001 assert(DstReg == ARM::SP &&
1002 "Only stack pointer as a destination reg is supported");
1004 SmallVector<unsigned, 4> RegList;
1005 // Skip src & dst reg, and pred ops.
1006 unsigned StartOp = 2 + 2;
1007 // Use all the operands.
1008 unsigned NumOffset = 0;
1013 llvm_unreachable("Unsupported opcode for unwinding information");
1015 // Special case here: no src & dst reg, but two extra imp ops.
1016 StartOp = 2; NumOffset = 2;
1017 case ARM::STMDB_UPD:
1018 case ARM::t2STMDB_UPD:
1019 case ARM::VSTMDDB_UPD:
1020 assert(SrcReg == ARM::SP &&
1021 "Only stack pointer as a source reg is supported");
1022 for (unsigned i = StartOp, NumOps = MI->getNumOperands() - NumOffset;
1024 const MachineOperand &MO = MI->getOperand(i);
1025 // Actually, there should never be any impdef stuff here. Skip it
1026 // temporary to workaround PR11902.
1027 if (MO.isImplicit())
1029 RegList.push_back(MO.getReg());
1032 case ARM::STR_PRE_IMM:
1033 case ARM::STR_PRE_REG:
1034 case ARM::t2STR_PRE:
1035 assert(MI->getOperand(2).getReg() == ARM::SP &&
1036 "Only stack pointer as a source reg is supported");
1037 RegList.push_back(SrcReg);
1040 ATS.emitRegSave(RegList, Opc == ARM::VSTMDDB_UPD);
1042 // Changes of stack / frame pointer.
1043 if (SrcReg == ARM::SP) {
1048 llvm_unreachable("Unsupported opcode for unwinding information");
1054 Offset = -MI->getOperand(2).getImm();
1058 Offset = MI->getOperand(2).getImm();
1061 Offset = MI->getOperand(2).getImm()*4;
1065 Offset = -MI->getOperand(2).getImm()*4;
1067 case ARM::tLDRpci: {
1068 // Grab the constpool index and check, whether it corresponds to
1069 // original or cloned constpool entry.
1070 unsigned CPI = MI->getOperand(1).getIndex();
1071 const MachineConstantPool *MCP = MF.getConstantPool();
1072 if (CPI >= MCP->getConstants().size())
1073 CPI = AFI.getOriginalCPIdx(CPI);
1074 assert(CPI != -1U && "Invalid constpool index");
1076 // Derive the actual offset.
1077 const MachineConstantPoolEntry &CPE = MCP->getConstants()[CPI];
1078 assert(!CPE.isMachineConstantPoolEntry() && "Invalid constpool entry");
1079 // FIXME: Check for user, it should be "add" instruction!
1080 Offset = -cast<ConstantInt>(CPE.Val.ConstVal)->getSExtValue();
1085 if (DstReg == FramePtr && FramePtr != ARM::SP)
1086 // Set-up of the frame pointer. Positive values correspond to "add"
1088 ATS.emitSetFP(FramePtr, ARM::SP, -Offset);
1089 else if (DstReg == ARM::SP) {
1090 // Change of SP by an offset. Positive values correspond to "sub"
1092 ATS.emitPad(Offset);
1095 llvm_unreachable("Unsupported opcode for unwinding information");
1097 } else if (DstReg == ARM::SP) {
1098 // FIXME: .movsp goes here
1100 llvm_unreachable("Unsupported opcode for unwinding information");
1104 llvm_unreachable("Unsupported opcode for unwinding information");
1109 extern cl::opt<bool> EnableARMEHABI;
1111 // Simple pseudo-instructions have their lowering (with expansion to real
1112 // instructions) auto-generated.
1113 #include "ARMGenMCPseudoLowering.inc"
1115 void ARMAsmPrinter::EmitInstruction(const MachineInstr *MI) {
1116 const DataLayout *DL = TM.getDataLayout();
1118 // If we just ended a constant pool, mark it as such.
1119 if (InConstantPool && MI->getOpcode() != ARM::CONSTPOOL_ENTRY) {
1120 OutStreamer.EmitDataRegion(MCDR_DataRegionEnd);
1121 InConstantPool = false;
1124 // Emit unwinding stuff for frame-related instructions
1125 if (EnableARMEHABI && MI->getFlag(MachineInstr::FrameSetup))
1126 EmitUnwindingInstruction(MI);
1128 // Do any auto-generated pseudo lowerings.
1129 if (emitPseudoExpansionLowering(OutStreamer, MI))
1132 assert(!convertAddSubFlagsOpcode(MI->getOpcode()) &&
1133 "Pseudo flag setting opcode should be expanded early");
1135 // Check for manual lowerings.
1136 unsigned Opc = MI->getOpcode();
1138 case ARM::t2MOVi32imm: llvm_unreachable("Should be lowered by thumb2it pass");
1139 case ARM::DBG_VALUE: llvm_unreachable("Should be handled by generic printing");
1141 case ARM::tLEApcrel:
1142 case ARM::t2LEApcrel: {
1143 // FIXME: Need to also handle globals and externals
1144 MCSymbol *CPISymbol = GetCPISymbol(MI->getOperand(1).getIndex());
1145 OutStreamer.EmitInstruction(MCInstBuilder(MI->getOpcode() ==
1146 ARM::t2LEApcrel ? ARM::t2ADR
1147 : (MI->getOpcode() == ARM::tLEApcrel ? ARM::tADR
1149 .addReg(MI->getOperand(0).getReg())
1150 .addExpr(MCSymbolRefExpr::Create(CPISymbol, OutContext))
1151 // Add predicate operands.
1152 .addImm(MI->getOperand(2).getImm())
1153 .addReg(MI->getOperand(3).getReg()));
1156 case ARM::LEApcrelJT:
1157 case ARM::tLEApcrelJT:
1158 case ARM::t2LEApcrelJT: {
1159 MCSymbol *JTIPICSymbol =
1160 GetARMJTIPICJumpTableLabel2(MI->getOperand(1).getIndex(),
1161 MI->getOperand(2).getImm());
1162 OutStreamer.EmitInstruction(MCInstBuilder(MI->getOpcode() ==
1163 ARM::t2LEApcrelJT ? ARM::t2ADR
1164 : (MI->getOpcode() == ARM::tLEApcrelJT ? ARM::tADR
1166 .addReg(MI->getOperand(0).getReg())
1167 .addExpr(MCSymbolRefExpr::Create(JTIPICSymbol, OutContext))
1168 // Add predicate operands.
1169 .addImm(MI->getOperand(3).getImm())
1170 .addReg(MI->getOperand(4).getReg()));
1173 // Darwin call instructions are just normal call instructions with different
1174 // clobber semantics (they clobber R9).
1175 case ARM::BX_CALL: {
1176 OutStreamer.EmitInstruction(MCInstBuilder(ARM::MOVr)
1179 // Add predicate operands.
1182 // Add 's' bit operand (always reg0 for this)
1185 OutStreamer.EmitInstruction(MCInstBuilder(ARM::BX)
1186 .addReg(MI->getOperand(0).getReg()));
1189 case ARM::tBX_CALL: {
1190 OutStreamer.EmitInstruction(MCInstBuilder(ARM::tMOVr)
1193 // Add predicate operands.
1197 OutStreamer.EmitInstruction(MCInstBuilder(ARM::tBX)
1198 .addReg(MI->getOperand(0).getReg())
1199 // Add predicate operands.
1204 case ARM::BMOVPCRX_CALL: {
1205 OutStreamer.EmitInstruction(MCInstBuilder(ARM::MOVr)
1208 // Add predicate operands.
1211 // Add 's' bit operand (always reg0 for this)
1214 OutStreamer.EmitInstruction(MCInstBuilder(ARM::MOVr)
1216 .addReg(MI->getOperand(0).getReg())
1217 // Add predicate operands.
1220 // Add 's' bit operand (always reg0 for this)
1224 case ARM::BMOVPCB_CALL: {
1225 OutStreamer.EmitInstruction(MCInstBuilder(ARM::MOVr)
1228 // Add predicate operands.
1231 // Add 's' bit operand (always reg0 for this)
1234 const GlobalValue *GV = MI->getOperand(0).getGlobal();
1235 MCSymbol *GVSym = getSymbol(GV);
1236 const MCExpr *GVSymExpr = MCSymbolRefExpr::Create(GVSym, OutContext);
1237 OutStreamer.EmitInstruction(MCInstBuilder(ARM::Bcc)
1239 // Add predicate operands.
1244 case ARM::MOVi16_ga_pcrel:
1245 case ARM::t2MOVi16_ga_pcrel: {
1247 TmpInst.setOpcode(Opc == ARM::MOVi16_ga_pcrel? ARM::MOVi16 : ARM::t2MOVi16);
1248 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1250 unsigned TF = MI->getOperand(1).getTargetFlags();
1251 const GlobalValue *GV = MI->getOperand(1).getGlobal();
1252 MCSymbol *GVSym = GetARMGVSymbol(GV, TF);
1253 const MCExpr *GVSymExpr = MCSymbolRefExpr::Create(GVSym, OutContext);
1255 MCSymbol *LabelSym = getPICLabel(DL->getPrivateGlobalPrefix(),
1256 getFunctionNumber(),
1257 MI->getOperand(2).getImm(), OutContext);
1258 const MCExpr *LabelSymExpr= MCSymbolRefExpr::Create(LabelSym, OutContext);
1259 unsigned PCAdj = (Opc == ARM::MOVi16_ga_pcrel) ? 8 : 4;
1260 const MCExpr *PCRelExpr =
1261 ARMMCExpr::CreateLower16(MCBinaryExpr::CreateSub(GVSymExpr,
1262 MCBinaryExpr::CreateAdd(LabelSymExpr,
1263 MCConstantExpr::Create(PCAdj, OutContext),
1264 OutContext), OutContext), OutContext);
1265 TmpInst.addOperand(MCOperand::CreateExpr(PCRelExpr));
1267 // Add predicate operands.
1268 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1269 TmpInst.addOperand(MCOperand::CreateReg(0));
1270 // Add 's' bit operand (always reg0 for this)
1271 TmpInst.addOperand(MCOperand::CreateReg(0));
1272 OutStreamer.EmitInstruction(TmpInst);
1275 case ARM::MOVTi16_ga_pcrel:
1276 case ARM::t2MOVTi16_ga_pcrel: {
1278 TmpInst.setOpcode(Opc == ARM::MOVTi16_ga_pcrel
1279 ? ARM::MOVTi16 : ARM::t2MOVTi16);
1280 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1281 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
1283 unsigned TF = MI->getOperand(2).getTargetFlags();
1284 const GlobalValue *GV = MI->getOperand(2).getGlobal();
1285 MCSymbol *GVSym = GetARMGVSymbol(GV, TF);
1286 const MCExpr *GVSymExpr = MCSymbolRefExpr::Create(GVSym, OutContext);
1288 MCSymbol *LabelSym = getPICLabel(DL->getPrivateGlobalPrefix(),
1289 getFunctionNumber(),
1290 MI->getOperand(3).getImm(), OutContext);
1291 const MCExpr *LabelSymExpr= MCSymbolRefExpr::Create(LabelSym, OutContext);
1292 unsigned PCAdj = (Opc == ARM::MOVTi16_ga_pcrel) ? 8 : 4;
1293 const MCExpr *PCRelExpr =
1294 ARMMCExpr::CreateUpper16(MCBinaryExpr::CreateSub(GVSymExpr,
1295 MCBinaryExpr::CreateAdd(LabelSymExpr,
1296 MCConstantExpr::Create(PCAdj, OutContext),
1297 OutContext), OutContext), OutContext);
1298 TmpInst.addOperand(MCOperand::CreateExpr(PCRelExpr));
1299 // Add predicate operands.
1300 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1301 TmpInst.addOperand(MCOperand::CreateReg(0));
1302 // Add 's' bit operand (always reg0 for this)
1303 TmpInst.addOperand(MCOperand::CreateReg(0));
1304 OutStreamer.EmitInstruction(TmpInst);
1307 case ARM::tPICADD: {
1308 // This is a pseudo op for a label + instruction sequence, which looks like:
1311 // This adds the address of LPC0 to r0.
1314 OutStreamer.EmitLabel(getPICLabel(DL->getPrivateGlobalPrefix(),
1315 getFunctionNumber(), MI->getOperand(2).getImm(),
1318 // Form and emit the add.
1319 OutStreamer.EmitInstruction(MCInstBuilder(ARM::tADDhirr)
1320 .addReg(MI->getOperand(0).getReg())
1321 .addReg(MI->getOperand(0).getReg())
1323 // Add predicate operands.
1329 // This is a pseudo op for a label + instruction sequence, which looks like:
1332 // This adds the address of LPC0 to r0.
1335 OutStreamer.EmitLabel(getPICLabel(DL->getPrivateGlobalPrefix(),
1336 getFunctionNumber(), MI->getOperand(2).getImm(),
1339 // Form and emit the add.
1340 OutStreamer.EmitInstruction(MCInstBuilder(ARM::ADDrr)
1341 .addReg(MI->getOperand(0).getReg())
1343 .addReg(MI->getOperand(1).getReg())
1344 // Add predicate operands.
1345 .addImm(MI->getOperand(3).getImm())
1346 .addReg(MI->getOperand(4).getReg())
1347 // Add 's' bit operand (always reg0 for this)
1358 case ARM::PICLDRSH: {
1359 // This is a pseudo op for a label + instruction sequence, which looks like:
1362 // The LCP0 label is referenced by a constant pool entry in order to get
1363 // a PC-relative address at the ldr instruction.
1366 OutStreamer.EmitLabel(getPICLabel(DL->getPrivateGlobalPrefix(),
1367 getFunctionNumber(), MI->getOperand(2).getImm(),
1370 // Form and emit the load
1372 switch (MI->getOpcode()) {
1374 llvm_unreachable("Unexpected opcode!");
1375 case ARM::PICSTR: Opcode = ARM::STRrs; break;
1376 case ARM::PICSTRB: Opcode = ARM::STRBrs; break;
1377 case ARM::PICSTRH: Opcode = ARM::STRH; break;
1378 case ARM::PICLDR: Opcode = ARM::LDRrs; break;
1379 case ARM::PICLDRB: Opcode = ARM::LDRBrs; break;
1380 case ARM::PICLDRH: Opcode = ARM::LDRH; break;
1381 case ARM::PICLDRSB: Opcode = ARM::LDRSB; break;
1382 case ARM::PICLDRSH: Opcode = ARM::LDRSH; break;
1384 OutStreamer.EmitInstruction(MCInstBuilder(Opcode)
1385 .addReg(MI->getOperand(0).getReg())
1387 .addReg(MI->getOperand(1).getReg())
1389 // Add predicate operands.
1390 .addImm(MI->getOperand(3).getImm())
1391 .addReg(MI->getOperand(4).getReg()));
1395 case ARM::CONSTPOOL_ENTRY: {
1396 /// CONSTPOOL_ENTRY - This instruction represents a floating constant pool
1397 /// in the function. The first operand is the ID# for this instruction, the
1398 /// second is the index into the MachineConstantPool that this is, the third
1399 /// is the size in bytes of this constant pool entry.
1400 /// The required alignment is specified on the basic block holding this MI.
1401 unsigned LabelId = (unsigned)MI->getOperand(0).getImm();
1402 unsigned CPIdx = (unsigned)MI->getOperand(1).getIndex();
1404 // If this is the first entry of the pool, mark it.
1405 if (!InConstantPool) {
1406 OutStreamer.EmitDataRegion(MCDR_DataRegion);
1407 InConstantPool = true;
1410 OutStreamer.EmitLabel(GetCPISymbol(LabelId));
1412 const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPIdx];
1413 if (MCPE.isMachineConstantPoolEntry())
1414 EmitMachineConstantPoolValue(MCPE.Val.MachineCPVal);
1416 EmitGlobalConstant(MCPE.Val.ConstVal);
1419 case ARM::t2BR_JT: {
1420 // Lower and emit the instruction itself, then the jump table following it.
1421 OutStreamer.EmitInstruction(MCInstBuilder(ARM::tMOVr)
1423 .addReg(MI->getOperand(0).getReg())
1424 // Add predicate operands.
1428 // Output the data for the jump table itself
1432 case ARM::t2TBB_JT: {
1433 // Lower and emit the instruction itself, then the jump table following it.
1434 OutStreamer.EmitInstruction(MCInstBuilder(ARM::t2TBB)
1436 .addReg(MI->getOperand(0).getReg())
1437 // Add predicate operands.
1441 // Output the data for the jump table itself
1443 // Make sure the next instruction is 2-byte aligned.
1447 case ARM::t2TBH_JT: {
1448 // Lower and emit the instruction itself, then the jump table following it.
1449 OutStreamer.EmitInstruction(MCInstBuilder(ARM::t2TBH)
1451 .addReg(MI->getOperand(0).getReg())
1452 // Add predicate operands.
1456 // Output the data for the jump table itself
1462 // Lower and emit the instruction itself, then the jump table following it.
1465 unsigned Opc = MI->getOpcode() == ARM::BR_JTr ?
1466 ARM::MOVr : ARM::tMOVr;
1467 TmpInst.setOpcode(Opc);
1468 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1469 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1470 // Add predicate operands.
1471 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1472 TmpInst.addOperand(MCOperand::CreateReg(0));
1473 // Add 's' bit operand (always reg0 for this)
1474 if (Opc == ARM::MOVr)
1475 TmpInst.addOperand(MCOperand::CreateReg(0));
1476 OutStreamer.EmitInstruction(TmpInst);
1478 // Make sure the Thumb jump table is 4-byte aligned.
1479 if (Opc == ARM::tMOVr)
1482 // Output the data for the jump table itself
1487 // Lower and emit the instruction itself, then the jump table following it.
1490 if (MI->getOperand(1).getReg() == 0) {
1492 TmpInst.setOpcode(ARM::LDRi12);
1493 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1494 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1495 TmpInst.addOperand(MCOperand::CreateImm(MI->getOperand(2).getImm()));
1497 TmpInst.setOpcode(ARM::LDRrs);
1498 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1499 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1500 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
1501 TmpInst.addOperand(MCOperand::CreateImm(0));
1503 // Add predicate operands.
1504 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1505 TmpInst.addOperand(MCOperand::CreateReg(0));
1506 OutStreamer.EmitInstruction(TmpInst);
1508 // Output the data for the jump table itself
1512 case ARM::BR_JTadd: {
1513 // Lower and emit the instruction itself, then the jump table following it.
1514 // add pc, target, idx
1515 OutStreamer.EmitInstruction(MCInstBuilder(ARM::ADDrr)
1517 .addReg(MI->getOperand(0).getReg())
1518 .addReg(MI->getOperand(1).getReg())
1519 // Add predicate operands.
1522 // Add 's' bit operand (always reg0 for this)
1525 // Output the data for the jump table itself
1530 // Non-Darwin binutils don't yet support the "trap" mnemonic.
1531 // FIXME: Remove this special case when they do.
1532 if (!Subtarget->isTargetMachO()) {
1533 //.long 0xe7ffdefe @ trap
1534 uint32_t Val = 0xe7ffdefeUL;
1535 OutStreamer.AddComment("trap");
1536 OutStreamer.EmitIntValue(Val, 4);
1541 case ARM::TRAPNaCl: {
1542 //.long 0xe7fedef0 @ trap
1543 uint32_t Val = 0xe7fedef0UL;
1544 OutStreamer.AddComment("trap");
1545 OutStreamer.EmitIntValue(Val, 4);
1549 // Non-Darwin binutils don't yet support the "trap" mnemonic.
1550 // FIXME: Remove this special case when they do.
1551 if (!Subtarget->isTargetMachO()) {
1552 //.short 57086 @ trap
1553 uint16_t Val = 0xdefe;
1554 OutStreamer.AddComment("trap");
1555 OutStreamer.EmitIntValue(Val, 2);
1560 case ARM::t2Int_eh_sjlj_setjmp:
1561 case ARM::t2Int_eh_sjlj_setjmp_nofp:
1562 case ARM::tInt_eh_sjlj_setjmp: {
1563 // Two incoming args: GPR:$src, GPR:$val
1566 // str $val, [$src, #4]
1571 unsigned SrcReg = MI->getOperand(0).getReg();
1572 unsigned ValReg = MI->getOperand(1).getReg();
1573 MCSymbol *Label = GetARMSJLJEHLabel();
1574 OutStreamer.AddComment("eh_setjmp begin");
1575 OutStreamer.EmitInstruction(MCInstBuilder(ARM::tMOVr)
1582 OutStreamer.EmitInstruction(MCInstBuilder(ARM::tADDi3)
1592 OutStreamer.EmitInstruction(MCInstBuilder(ARM::tSTRi)
1595 // The offset immediate is #4. The operand value is scaled by 4 for the
1596 // tSTR instruction.
1602 OutStreamer.EmitInstruction(MCInstBuilder(ARM::tMOVi8)
1610 const MCExpr *SymbolExpr = MCSymbolRefExpr::Create(Label, OutContext);
1611 OutStreamer.EmitInstruction(MCInstBuilder(ARM::tB)
1612 .addExpr(SymbolExpr)
1616 OutStreamer.AddComment("eh_setjmp end");
1617 OutStreamer.EmitInstruction(MCInstBuilder(ARM::tMOVi8)
1625 OutStreamer.EmitLabel(Label);
1629 case ARM::Int_eh_sjlj_setjmp_nofp:
1630 case ARM::Int_eh_sjlj_setjmp: {
1631 // Two incoming args: GPR:$src, GPR:$val
1633 // str $val, [$src, #+4]
1637 unsigned SrcReg = MI->getOperand(0).getReg();
1638 unsigned ValReg = MI->getOperand(1).getReg();
1640 OutStreamer.AddComment("eh_setjmp begin");
1641 OutStreamer.EmitInstruction(MCInstBuilder(ARM::ADDri)
1648 // 's' bit operand (always reg0 for this).
1651 OutStreamer.EmitInstruction(MCInstBuilder(ARM::STRi12)
1659 OutStreamer.EmitInstruction(MCInstBuilder(ARM::MOVi)
1665 // 's' bit operand (always reg0 for this).
1668 OutStreamer.EmitInstruction(MCInstBuilder(ARM::ADDri)
1675 // 's' bit operand (always reg0 for this).
1678 OutStreamer.AddComment("eh_setjmp end");
1679 OutStreamer.EmitInstruction(MCInstBuilder(ARM::MOVi)
1685 // 's' bit operand (always reg0 for this).
1689 case ARM::Int_eh_sjlj_longjmp: {
1690 // ldr sp, [$src, #8]
1691 // ldr $scratch, [$src, #4]
1694 unsigned SrcReg = MI->getOperand(0).getReg();
1695 unsigned ScratchReg = MI->getOperand(1).getReg();
1696 OutStreamer.EmitInstruction(MCInstBuilder(ARM::LDRi12)
1704 OutStreamer.EmitInstruction(MCInstBuilder(ARM::LDRi12)
1712 OutStreamer.EmitInstruction(MCInstBuilder(ARM::LDRi12)
1720 OutStreamer.EmitInstruction(MCInstBuilder(ARM::BX)
1727 case ARM::tInt_eh_sjlj_longjmp: {
1728 // ldr $scratch, [$src, #8]
1730 // ldr $scratch, [$src, #4]
1733 unsigned SrcReg = MI->getOperand(0).getReg();
1734 unsigned ScratchReg = MI->getOperand(1).getReg();
1735 OutStreamer.EmitInstruction(MCInstBuilder(ARM::tLDRi)
1738 // The offset immediate is #8. The operand value is scaled by 4 for the
1739 // tLDR instruction.
1745 OutStreamer.EmitInstruction(MCInstBuilder(ARM::tMOVr)
1752 OutStreamer.EmitInstruction(MCInstBuilder(ARM::tLDRi)
1760 OutStreamer.EmitInstruction(MCInstBuilder(ARM::tLDRi)
1768 OutStreamer.EmitInstruction(MCInstBuilder(ARM::tBX)
1778 LowerARMMachineInstrToMCInst(MI, TmpInst, *this);
1780 OutStreamer.EmitInstruction(TmpInst);
1783 //===----------------------------------------------------------------------===//
1784 // Target Registry Stuff
1785 //===----------------------------------------------------------------------===//
1787 // Force static initialization.
1788 extern "C" void LLVMInitializeARMAsmPrinter() {
1789 RegisterAsmPrinter<ARMAsmPrinter> X(TheARMTarget);
1790 RegisterAsmPrinter<ARMAsmPrinter> Y(TheThumbTarget);