1 //===-- ARMAsmPrinter.cpp - Print machine code to an ARM .s file ----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains a printer that converts from our internal representation
11 // of machine-dependent LLVM code to GAS-format ARM assembly language.
13 //===----------------------------------------------------------------------===//
15 #include "ARMAsmPrinter.h"
17 #include "ARMConstantPoolValue.h"
18 #include "ARMFPUName.h"
19 #include "ARMMachineFunctionInfo.h"
20 #include "ARMTargetMachine.h"
21 #include "ARMTargetObjectFile.h"
22 #include "InstPrinter/ARMInstPrinter.h"
23 #include "MCTargetDesc/ARMAddressingModes.h"
24 #include "MCTargetDesc/ARMMCExpr.h"
25 #include "llvm/ADT/SetVector.h"
26 #include "llvm/ADT/SmallString.h"
27 #include "llvm/CodeGen/MachineFunctionPass.h"
28 #include "llvm/CodeGen/MachineJumpTableInfo.h"
29 #include "llvm/CodeGen/MachineModuleInfoImpls.h"
30 #include "llvm/IR/Constants.h"
31 #include "llvm/IR/DataLayout.h"
32 #include "llvm/IR/DebugInfo.h"
33 #include "llvm/IR/Mangler.h"
34 #include "llvm/IR/Module.h"
35 #include "llvm/IR/Type.h"
36 #include "llvm/MC/MCAsmInfo.h"
37 #include "llvm/MC/MCAssembler.h"
38 #include "llvm/MC/MCContext.h"
39 #include "llvm/MC/MCELFStreamer.h"
40 #include "llvm/MC/MCInst.h"
41 #include "llvm/MC/MCInstBuilder.h"
42 #include "llvm/MC/MCObjectStreamer.h"
43 #include "llvm/MC/MCSectionMachO.h"
44 #include "llvm/MC/MCStreamer.h"
45 #include "llvm/MC/MCSymbol.h"
46 #include "llvm/Support/ARMBuildAttributes.h"
47 #include "llvm/Support/COFF.h"
48 #include "llvm/Support/CommandLine.h"
49 #include "llvm/Support/Debug.h"
50 #include "llvm/Support/ELF.h"
51 #include "llvm/Support/ErrorHandling.h"
52 #include "llvm/Support/TargetRegistry.h"
53 #include "llvm/Support/raw_ostream.h"
54 #include "llvm/Target/TargetMachine.h"
58 #define DEBUG_TYPE "asm-printer"
60 void ARMAsmPrinter::EmitFunctionBodyEnd() {
61 // Make sure to terminate any constant pools that were at the end
65 InConstantPool = false;
66 OutStreamer.EmitDataRegion(MCDR_DataRegionEnd);
69 void ARMAsmPrinter::EmitFunctionEntryLabel() {
70 if (AFI->isThumbFunction()) {
71 OutStreamer.EmitAssemblerFlag(MCAF_Code16);
72 OutStreamer.EmitThumbFunc(CurrentFnSym);
75 OutStreamer.EmitLabel(CurrentFnSym);
78 void ARMAsmPrinter::EmitXXStructor(const Constant *CV) {
80 TM.getSubtargetImpl()->getDataLayout()->getTypeAllocSize(CV->getType());
81 assert(Size && "C++ constructor pointer had zero size!");
83 const GlobalValue *GV = dyn_cast<GlobalValue>(CV->stripPointerCasts());
84 assert(GV && "C++ constructor pointer was not a GlobalValue!");
86 const MCExpr *E = MCSymbolRefExpr::Create(GetARMGVSymbol(GV,
88 (Subtarget->isTargetELF()
89 ? MCSymbolRefExpr::VK_ARM_TARGET1
90 : MCSymbolRefExpr::VK_None),
93 OutStreamer.EmitValue(E, Size);
96 /// runOnMachineFunction - This uses the EmitInstruction()
97 /// method to print assembly for each instruction.
99 bool ARMAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
100 AFI = MF.getInfo<ARMFunctionInfo>();
101 MCP = MF.getConstantPool();
103 SetupMachineFunction(MF);
105 if (Subtarget->isTargetCOFF()) {
106 bool Internal = MF.getFunction()->hasInternalLinkage();
107 COFF::SymbolStorageClass Scl = Internal ? COFF::IMAGE_SYM_CLASS_STATIC
108 : COFF::IMAGE_SYM_CLASS_EXTERNAL;
109 int Type = COFF::IMAGE_SYM_DTYPE_FUNCTION << COFF::SCT_COMPLEX_TYPE_SHIFT;
111 OutStreamer.BeginCOFFSymbolDef(CurrentFnSym);
112 OutStreamer.EmitCOFFSymbolStorageClass(Scl);
113 OutStreamer.EmitCOFFSymbolType(Type);
114 OutStreamer.EndCOFFSymbolDef();
117 // Have common code print out the function header with linkage info etc.
118 EmitFunctionHeader();
120 // Emit the rest of the function body.
123 // We didn't modify anything.
127 void ARMAsmPrinter::printOperand(const MachineInstr *MI, int OpNum,
128 raw_ostream &O, const char *Modifier) {
129 const MachineOperand &MO = MI->getOperand(OpNum);
130 unsigned TF = MO.getTargetFlags();
132 switch (MO.getType()) {
133 default: llvm_unreachable("<unknown operand type>");
134 case MachineOperand::MO_Register: {
135 unsigned Reg = MO.getReg();
136 assert(TargetRegisterInfo::isPhysicalRegister(Reg));
137 assert(!MO.getSubReg() && "Subregs should be eliminated!");
138 if(ARM::GPRPairRegClass.contains(Reg)) {
139 const MachineFunction &MF = *MI->getParent()->getParent();
140 const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
141 Reg = TRI->getSubReg(Reg, ARM::gsub_0);
143 O << ARMInstPrinter::getRegisterName(Reg);
146 case MachineOperand::MO_Immediate: {
147 int64_t Imm = MO.getImm();
149 if ((Modifier && strcmp(Modifier, "lo16") == 0) ||
150 (TF == ARMII::MO_LO16))
152 else if ((Modifier && strcmp(Modifier, "hi16") == 0) ||
153 (TF == ARMII::MO_HI16))
158 case MachineOperand::MO_MachineBasicBlock:
159 O << *MO.getMBB()->getSymbol();
161 case MachineOperand::MO_GlobalAddress: {
162 const GlobalValue *GV = MO.getGlobal();
163 if ((Modifier && strcmp(Modifier, "lo16") == 0) ||
164 (TF & ARMII::MO_LO16))
166 else if ((Modifier && strcmp(Modifier, "hi16") == 0) ||
167 (TF & ARMII::MO_HI16))
169 O << *GetARMGVSymbol(GV, TF);
171 printOffset(MO.getOffset(), O);
172 if (TF == ARMII::MO_PLT)
176 case MachineOperand::MO_ConstantPoolIndex:
177 O << *GetCPISymbol(MO.getIndex());
182 //===--------------------------------------------------------------------===//
184 MCSymbol *ARMAsmPrinter::
185 GetARMJTIPICJumpTableLabel2(unsigned uid, unsigned uid2) const {
186 const DataLayout *DL = TM.getSubtargetImpl()->getDataLayout();
187 SmallString<60> Name;
188 raw_svector_ostream(Name) << DL->getPrivateGlobalPrefix() << "JTI"
189 << getFunctionNumber() << '_' << uid << '_' << uid2;
190 return OutContext.GetOrCreateSymbol(Name.str());
194 MCSymbol *ARMAsmPrinter::GetARMSJLJEHLabel() const {
195 const DataLayout *DL = TM.getSubtargetImpl()->getDataLayout();
196 SmallString<60> Name;
197 raw_svector_ostream(Name) << DL->getPrivateGlobalPrefix() << "SJLJEH"
198 << getFunctionNumber();
199 return OutContext.GetOrCreateSymbol(Name.str());
202 bool ARMAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
203 unsigned AsmVariant, const char *ExtraCode,
205 // Does this asm operand have a single letter operand modifier?
206 if (ExtraCode && ExtraCode[0]) {
207 if (ExtraCode[1] != 0) return true; // Unknown modifier.
209 switch (ExtraCode[0]) {
211 // See if this is a generic print operand
212 return AsmPrinter::PrintAsmOperand(MI, OpNum, AsmVariant, ExtraCode, O);
213 case 'a': // Print as a memory address.
214 if (MI->getOperand(OpNum).isReg()) {
216 << ARMInstPrinter::getRegisterName(MI->getOperand(OpNum).getReg())
221 case 'c': // Don't print "#" before an immediate operand.
222 if (!MI->getOperand(OpNum).isImm())
224 O << MI->getOperand(OpNum).getImm();
226 case 'P': // Print a VFP double precision register.
227 case 'q': // Print a NEON quad precision register.
228 printOperand(MI, OpNum, O);
230 case 'y': // Print a VFP single precision register as indexed double.
231 if (MI->getOperand(OpNum).isReg()) {
232 unsigned Reg = MI->getOperand(OpNum).getReg();
233 const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
234 // Find the 'd' register that has this 's' register as a sub-register,
235 // and determine the lane number.
236 for (MCSuperRegIterator SR(Reg, TRI); SR.isValid(); ++SR) {
237 if (!ARM::DPRRegClass.contains(*SR))
239 bool Lane0 = TRI->getSubReg(*SR, ARM::ssub_0) == Reg;
240 O << ARMInstPrinter::getRegisterName(*SR) << (Lane0 ? "[0]" : "[1]");
245 case 'B': // Bitwise inverse of integer or symbol without a preceding #.
246 if (!MI->getOperand(OpNum).isImm())
248 O << ~(MI->getOperand(OpNum).getImm());
250 case 'L': // The low 16 bits of an immediate constant.
251 if (!MI->getOperand(OpNum).isImm())
253 O << (MI->getOperand(OpNum).getImm() & 0xffff);
255 case 'M': { // A register range suitable for LDM/STM.
256 if (!MI->getOperand(OpNum).isReg())
258 const MachineOperand &MO = MI->getOperand(OpNum);
259 unsigned RegBegin = MO.getReg();
260 // This takes advantage of the 2 operand-ness of ldm/stm and that we've
261 // already got the operands in registers that are operands to the
262 // inline asm statement.
264 if (ARM::GPRPairRegClass.contains(RegBegin)) {
265 const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
266 unsigned Reg0 = TRI->getSubReg(RegBegin, ARM::gsub_0);
267 O << ARMInstPrinter::getRegisterName(Reg0) << ", ";
268 RegBegin = TRI->getSubReg(RegBegin, ARM::gsub_1);
270 O << ARMInstPrinter::getRegisterName(RegBegin);
272 // FIXME: The register allocator not only may not have given us the
273 // registers in sequence, but may not be in ascending registers. This
274 // will require changes in the register allocator that'll need to be
275 // propagated down here if the operands change.
276 unsigned RegOps = OpNum + 1;
277 while (MI->getOperand(RegOps).isReg()) {
279 << ARMInstPrinter::getRegisterName(MI->getOperand(RegOps).getReg());
287 case 'R': // The most significant register of a pair.
288 case 'Q': { // The least significant register of a pair.
291 const MachineOperand &FlagsOP = MI->getOperand(OpNum - 1);
292 if (!FlagsOP.isImm())
294 unsigned Flags = FlagsOP.getImm();
296 // This operand may not be the one that actually provides the register. If
297 // it's tied to a previous one then we should refer instead to that one
298 // for registers and their classes.
300 if (InlineAsm::isUseOperandTiedToDef(Flags, TiedIdx)) {
301 for (OpNum = InlineAsm::MIOp_FirstOperand; TiedIdx; --TiedIdx) {
302 unsigned OpFlags = MI->getOperand(OpNum).getImm();
303 OpNum += InlineAsm::getNumOperandRegisters(OpFlags) + 1;
305 Flags = MI->getOperand(OpNum).getImm();
307 // Later code expects OpNum to be pointing at the register rather than
312 unsigned NumVals = InlineAsm::getNumOperandRegisters(Flags);
314 InlineAsm::hasRegClassConstraint(Flags, RC);
315 if (RC == ARM::GPRPairRegClassID) {
318 const MachineOperand &MO = MI->getOperand(OpNum);
321 const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
322 unsigned Reg = TRI->getSubReg(MO.getReg(), ExtraCode[0] == 'Q' ?
323 ARM::gsub_0 : ARM::gsub_1);
324 O << ARMInstPrinter::getRegisterName(Reg);
329 unsigned RegOp = ExtraCode[0] == 'Q' ? OpNum : OpNum + 1;
330 if (RegOp >= MI->getNumOperands())
332 const MachineOperand &MO = MI->getOperand(RegOp);
335 unsigned Reg = MO.getReg();
336 O << ARMInstPrinter::getRegisterName(Reg);
340 case 'e': // The low doubleword register of a NEON quad register.
341 case 'f': { // The high doubleword register of a NEON quad register.
342 if (!MI->getOperand(OpNum).isReg())
344 unsigned Reg = MI->getOperand(OpNum).getReg();
345 if (!ARM::QPRRegClass.contains(Reg))
347 const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
348 unsigned SubReg = TRI->getSubReg(Reg, ExtraCode[0] == 'e' ?
349 ARM::dsub_0 : ARM::dsub_1);
350 O << ARMInstPrinter::getRegisterName(SubReg);
354 // This modifier is not yet supported.
355 case 'h': // A range of VFP/NEON registers suitable for VLD1/VST1.
357 case 'H': { // The highest-numbered register of a pair.
358 const MachineOperand &MO = MI->getOperand(OpNum);
361 const MachineFunction &MF = *MI->getParent()->getParent();
362 const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
363 unsigned Reg = MO.getReg();
364 if(!ARM::GPRPairRegClass.contains(Reg))
366 Reg = TRI->getSubReg(Reg, ARM::gsub_1);
367 O << ARMInstPrinter::getRegisterName(Reg);
373 printOperand(MI, OpNum, O);
377 bool ARMAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI,
378 unsigned OpNum, unsigned AsmVariant,
379 const char *ExtraCode,
381 // Does this asm operand have a single letter operand modifier?
382 if (ExtraCode && ExtraCode[0]) {
383 if (ExtraCode[1] != 0) return true; // Unknown modifier.
385 switch (ExtraCode[0]) {
386 case 'A': // A memory operand for a VLD1/VST1 instruction.
387 default: return true; // Unknown modifier.
388 case 'm': // The base register of a memory operand.
389 if (!MI->getOperand(OpNum).isReg())
391 O << ARMInstPrinter::getRegisterName(MI->getOperand(OpNum).getReg());
396 const MachineOperand &MO = MI->getOperand(OpNum);
397 assert(MO.isReg() && "unexpected inline asm memory operand");
398 O << "[" << ARMInstPrinter::getRegisterName(MO.getReg()) << "]";
402 static bool isThumb(const MCSubtargetInfo& STI) {
403 return (STI.getFeatureBits() & ARM::ModeThumb) != 0;
406 void ARMAsmPrinter::emitInlineAsmEnd(const MCSubtargetInfo &StartInfo,
407 const MCSubtargetInfo *EndInfo) const {
408 // If either end mode is unknown (EndInfo == NULL) or different than
409 // the start mode, then restore the start mode.
410 const bool WasThumb = isThumb(StartInfo);
411 if (!EndInfo || WasThumb != isThumb(*EndInfo)) {
412 OutStreamer.EmitAssemblerFlag(WasThumb ? MCAF_Code16 : MCAF_Code32);
416 void ARMAsmPrinter::EmitStartOfAsmFile(Module &M) {
417 if (Subtarget->isTargetMachO()) {
418 Reloc::Model RelocM = TM.getRelocationModel();
419 if (RelocM == Reloc::PIC_ || RelocM == Reloc::DynamicNoPIC) {
420 // Declare all the text sections up front (before the DWARF sections
421 // emitted by AsmPrinter::doInitialization) so the assembler will keep
422 // them together at the beginning of the object file. This helps
423 // avoid out-of-range branches that are due a fundamental limitation of
424 // the way symbol offsets are encoded with the current Darwin ARM
426 const TargetLoweringObjectFileMachO &TLOFMacho =
427 static_cast<const TargetLoweringObjectFileMachO &>(
428 getObjFileLowering());
430 // Collect the set of sections our functions will go into.
431 SetVector<const MCSection *, SmallVector<const MCSection *, 8>,
432 SmallPtrSet<const MCSection *, 8> > TextSections;
433 // Default text section comes first.
434 TextSections.insert(TLOFMacho.getTextSection());
435 // Now any user defined text sections from function attributes.
436 for (Module::iterator F = M.begin(), e = M.end(); F != e; ++F)
437 if (!F->isDeclaration() && !F->hasAvailableExternallyLinkage())
438 TextSections.insert(TLOFMacho.SectionForGlobal(F, *Mang, TM));
439 // Now the coalescable sections.
440 TextSections.insert(TLOFMacho.getTextCoalSection());
441 TextSections.insert(TLOFMacho.getConstTextCoalSection());
443 // Emit the sections in the .s file header to fix the order.
444 for (unsigned i = 0, e = TextSections.size(); i != e; ++i)
445 OutStreamer.SwitchSection(TextSections[i]);
447 if (RelocM == Reloc::DynamicNoPIC) {
448 const MCSection *sect =
449 OutContext.getMachOSection("__TEXT", "__symbol_stub4",
450 MachO::S_SYMBOL_STUBS,
451 12, SectionKind::getText());
452 OutStreamer.SwitchSection(sect);
454 const MCSection *sect =
455 OutContext.getMachOSection("__TEXT", "__picsymbolstub4",
456 MachO::S_SYMBOL_STUBS,
457 16, SectionKind::getText());
458 OutStreamer.SwitchSection(sect);
460 const MCSection *StaticInitSect =
461 OutContext.getMachOSection("__TEXT", "__StaticInit",
463 MachO::S_ATTR_PURE_INSTRUCTIONS,
464 SectionKind::getText());
465 OutStreamer.SwitchSection(StaticInitSect);
468 // Compiling with debug info should not affect the code
469 // generation. Ensure the cstring section comes before the
470 // optional __DWARF secion. Otherwise, PC-relative loads would
471 // have to use different instruction sequences at "-g" in order to
472 // reach global data in the same object file.
473 OutStreamer.SwitchSection(getObjFileLowering().getCStringSection());
476 // Use unified assembler syntax.
477 OutStreamer.EmitAssemblerFlag(MCAF_SyntaxUnified);
479 // Emit ARM Build Attributes
480 if (Subtarget->isTargetELF())
483 if (!M.getModuleInlineAsm().empty() && Subtarget->isThumb())
484 OutStreamer.EmitAssemblerFlag(MCAF_Code16);
488 emitNonLazySymbolPointer(MCStreamer &OutStreamer, MCSymbol *StubLabel,
489 MachineModuleInfoImpl::StubValueTy &MCSym) {
491 OutStreamer.EmitLabel(StubLabel);
492 // .indirect_symbol _foo
493 OutStreamer.EmitSymbolAttribute(MCSym.getPointer(), MCSA_IndirectSymbol);
496 // External to current translation unit.
497 OutStreamer.EmitIntValue(0, 4/*size*/);
499 // Internal to current translation unit.
501 // When we place the LSDA into the TEXT section, the type info
502 // pointers need to be indirect and pc-rel. We accomplish this by
503 // using NLPs; however, sometimes the types are local to the file.
504 // We need to fill in the value for the NLP in those cases.
505 OutStreamer.EmitValue(
506 MCSymbolRefExpr::Create(MCSym.getPointer(), OutStreamer.getContext()),
511 void ARMAsmPrinter::EmitEndOfAsmFile(Module &M) {
512 if (Subtarget->isTargetMachO()) {
513 // All darwin targets use mach-o.
514 const TargetLoweringObjectFileMachO &TLOFMacho =
515 static_cast<const TargetLoweringObjectFileMachO &>(getObjFileLowering());
516 MachineModuleInfoMachO &MMIMacho =
517 MMI->getObjFileInfo<MachineModuleInfoMachO>();
519 // Output non-lazy-pointers for external and common global variables.
520 MachineModuleInfoMachO::SymbolListTy Stubs = MMIMacho.GetGVStubList();
522 if (!Stubs.empty()) {
523 // Switch with ".non_lazy_symbol_pointer" directive.
524 OutStreamer.SwitchSection(TLOFMacho.getNonLazySymbolPointerSection());
527 for (auto &Stub : Stubs)
528 emitNonLazySymbolPointer(OutStreamer, Stub.first, Stub.second);
531 OutStreamer.AddBlankLine();
534 Stubs = MMIMacho.GetHiddenGVStubList();
535 if (!Stubs.empty()) {
536 OutStreamer.SwitchSection(TLOFMacho.getNonLazySymbolPointerSection());
539 for (auto &Stub : Stubs)
540 emitNonLazySymbolPointer(OutStreamer, Stub.first, Stub.second);
543 OutStreamer.AddBlankLine();
546 // Funny Darwin hack: This flag tells the linker that no global symbols
547 // contain code that falls through to other global symbols (e.g. the obvious
548 // implementation of multiple entry points). If this doesn't occur, the
549 // linker can safely perform dead code stripping. Since LLVM never
550 // generates code that does this, it is always safe to set.
551 OutStreamer.EmitAssemblerFlag(MCAF_SubsectionsViaSymbols);
554 // Emit a .data.rel section containing any stubs that were created.
555 if (Subtarget->isTargetELF()) {
556 const TargetLoweringObjectFileELF &TLOFELF =
557 static_cast<const TargetLoweringObjectFileELF &>(getObjFileLowering());
559 MachineModuleInfoELF &MMIELF = MMI->getObjFileInfo<MachineModuleInfoELF>();
561 // Output stubs for external and common global variables.
562 MachineModuleInfoELF::SymbolListTy Stubs = MMIELF.GetGVStubList();
563 if (!Stubs.empty()) {
564 OutStreamer.SwitchSection(TLOFELF.getDataRelSection());
565 const DataLayout *TD = TM.getSubtargetImpl()->getDataLayout();
567 for (auto &stub: Stubs) {
568 OutStreamer.EmitLabel(stub.first);
569 OutStreamer.EmitSymbolValue(stub.second.getPointer(),
570 TD->getPointerSize(0));
577 //===----------------------------------------------------------------------===//
578 // Helper routines for EmitStartOfAsmFile() and EmitEndOfAsmFile()
580 // The following seem like one-off assembler flags, but they actually need
581 // to appear in the .ARM.attributes section in ELF.
582 // Instead of subclassing the MCELFStreamer, we do the work here.
584 static ARMBuildAttrs::CPUArch getArchForCPU(StringRef CPU,
585 const ARMSubtarget *Subtarget) {
587 return ARMBuildAttrs::v5TEJ;
589 if (Subtarget->hasV8Ops())
590 return ARMBuildAttrs::v8;
591 else if (Subtarget->hasV7Ops()) {
592 if (Subtarget->isMClass() && Subtarget->hasThumb2DSP())
593 return ARMBuildAttrs::v7E_M;
594 return ARMBuildAttrs::v7;
595 } else if (Subtarget->hasV6T2Ops())
596 return ARMBuildAttrs::v6T2;
597 else if (Subtarget->hasV6MOps())
598 return ARMBuildAttrs::v6S_M;
599 else if (Subtarget->hasV6Ops())
600 return ARMBuildAttrs::v6;
601 else if (Subtarget->hasV5TEOps())
602 return ARMBuildAttrs::v5TE;
603 else if (Subtarget->hasV5TOps())
604 return ARMBuildAttrs::v5T;
605 else if (Subtarget->hasV4TOps())
606 return ARMBuildAttrs::v4T;
608 return ARMBuildAttrs::v4;
611 void ARMAsmPrinter::emitAttributes() {
612 MCTargetStreamer &TS = *OutStreamer.getTargetStreamer();
613 ARMTargetStreamer &ATS = static_cast<ARMTargetStreamer &>(TS);
615 ATS.switchVendor("aeabi");
617 std::string CPUString = Subtarget->getCPUString();
619 // FIXME: remove krait check when GNU tools support krait cpu
620 if (CPUString != "generic" && CPUString != "krait")
621 ATS.emitTextAttribute(ARMBuildAttrs::CPU_name, CPUString);
623 ATS.emitAttribute(ARMBuildAttrs::CPU_arch,
624 getArchForCPU(CPUString, Subtarget));
626 // Tag_CPU_arch_profile must have the default value of 0 when "Architecture
627 // profile is not applicable (e.g. pre v7, or cross-profile code)".
628 if (Subtarget->hasV7Ops()) {
629 if (Subtarget->isAClass()) {
630 ATS.emitAttribute(ARMBuildAttrs::CPU_arch_profile,
631 ARMBuildAttrs::ApplicationProfile);
632 } else if (Subtarget->isRClass()) {
633 ATS.emitAttribute(ARMBuildAttrs::CPU_arch_profile,
634 ARMBuildAttrs::RealTimeProfile);
635 } else if (Subtarget->isMClass()) {
636 ATS.emitAttribute(ARMBuildAttrs::CPU_arch_profile,
637 ARMBuildAttrs::MicroControllerProfile);
641 ATS.emitAttribute(ARMBuildAttrs::ARM_ISA_use, Subtarget->hasARMOps() ?
642 ARMBuildAttrs::Allowed : ARMBuildAttrs::Not_Allowed);
643 if (Subtarget->isThumb1Only()) {
644 ATS.emitAttribute(ARMBuildAttrs::THUMB_ISA_use,
645 ARMBuildAttrs::Allowed);
646 } else if (Subtarget->hasThumb2()) {
647 ATS.emitAttribute(ARMBuildAttrs::THUMB_ISA_use,
648 ARMBuildAttrs::AllowThumb32);
651 if (Subtarget->hasNEON()) {
652 /* NEON is not exactly a VFP architecture, but GAS emit one of
653 * neon/neon-fp-armv8/neon-vfpv4/vfpv3/vfpv2 for .fpu parameters */
654 if (Subtarget->hasFPARMv8()) {
655 if (Subtarget->hasCrypto())
656 ATS.emitFPU(ARM::CRYPTO_NEON_FP_ARMV8);
658 ATS.emitFPU(ARM::NEON_FP_ARMV8);
660 else if (Subtarget->hasVFP4())
661 ATS.emitFPU(ARM::NEON_VFPV4);
663 ATS.emitFPU(ARM::NEON);
664 // Emit Tag_Advanced_SIMD_arch for ARMv8 architecture
665 if (Subtarget->hasV8Ops())
666 ATS.emitAttribute(ARMBuildAttrs::Advanced_SIMD_arch,
667 ARMBuildAttrs::AllowNeonARMv8);
669 if (Subtarget->hasFPARMv8())
670 // FPv5 and FP-ARMv8 have the same instructions, so are modeled as one
671 // FPU, but there are two different names for it depending on the CPU.
672 ATS.emitFPU(Subtarget->hasD16() ? ARM::FPV5_D16 : ARM::FP_ARMV8);
673 else if (Subtarget->hasVFP4())
674 ATS.emitFPU(Subtarget->hasD16() ? ARM::VFPV4_D16 : ARM::VFPV4);
675 else if (Subtarget->hasVFP3())
676 ATS.emitFPU(Subtarget->hasD16() ? ARM::VFPV3_D16 : ARM::VFPV3);
677 else if (Subtarget->hasVFP2())
678 ATS.emitFPU(ARM::VFPV2);
681 if (TM.getRelocationModel() == Reloc::PIC_) {
682 // PIC specific attributes.
683 ATS.emitAttribute(ARMBuildAttrs::ABI_PCS_RW_data,
684 ARMBuildAttrs::AddressRWPCRel);
685 ATS.emitAttribute(ARMBuildAttrs::ABI_PCS_RO_data,
686 ARMBuildAttrs::AddressROPCRel);
687 ATS.emitAttribute(ARMBuildAttrs::ABI_PCS_GOT_use,
688 ARMBuildAttrs::AddressGOT);
690 // Allow direct addressing of imported data for all other relocation models.
691 ATS.emitAttribute(ARMBuildAttrs::ABI_PCS_GOT_use,
692 ARMBuildAttrs::AddressDirect);
695 // Signal various FP modes.
696 if (!TM.Options.UnsafeFPMath) {
697 ATS.emitAttribute(ARMBuildAttrs::ABI_FP_denormal,
698 ARMBuildAttrs::IEEEDenormals);
699 ATS.emitAttribute(ARMBuildAttrs::ABI_FP_exceptions,
700 ARMBuildAttrs::Allowed);
702 // If the user has permitted this code to choose the IEEE 754
703 // rounding at run-time, emit the rounding attribute.
704 if (TM.Options.HonorSignDependentRoundingFPMathOption)
705 ATS.emitAttribute(ARMBuildAttrs::ABI_FP_rounding,
706 ARMBuildAttrs::Allowed);
708 if (!Subtarget->hasVFP2()) {
709 // When the target doesn't have an FPU (by design or
710 // intention), the assumptions made on the software support
711 // mirror that of the equivalent hardware support *if it
712 // existed*. For v7 and better we indicate that denormals are
713 // flushed preserving sign, and for V6 we indicate that
714 // denormals are flushed to positive zero.
715 if (Subtarget->hasV7Ops())
716 ATS.emitAttribute(ARMBuildAttrs::ABI_FP_denormal,
717 ARMBuildAttrs::PreserveFPSign);
718 } else if (Subtarget->hasVFP3()) {
719 // In VFPv4, VFPv4U, VFPv3, or VFPv3U, it is preserved. That is,
720 // the sign bit of the zero matches the sign bit of the input or
721 // result that is being flushed to zero.
722 ATS.emitAttribute(ARMBuildAttrs::ABI_FP_denormal,
723 ARMBuildAttrs::PreserveFPSign);
725 // For VFPv2 implementations it is implementation defined as
726 // to whether denormals are flushed to positive zero or to
727 // whatever the sign of zero is (ARM v7AR ARM 2.7.5). Historically
728 // LLVM has chosen to flush this to positive zero (most likely for
729 // GCC compatibility), so that's the chosen value here (the
730 // absence of its emission implies zero).
733 if (TM.Options.NoInfsFPMath && TM.Options.NoNaNsFPMath)
734 ATS.emitAttribute(ARMBuildAttrs::ABI_FP_number_model,
735 ARMBuildAttrs::Allowed);
737 ATS.emitAttribute(ARMBuildAttrs::ABI_FP_number_model,
738 ARMBuildAttrs::AllowIEE754);
740 if (Subtarget->allowsUnalignedMem())
741 ATS.emitAttribute(ARMBuildAttrs::CPU_unaligned_access,
742 ARMBuildAttrs::Allowed);
744 ATS.emitAttribute(ARMBuildAttrs::CPU_unaligned_access,
745 ARMBuildAttrs::Not_Allowed);
747 // FIXME: add more flags to ARMBuildAttributes.h
748 // 8-bytes alignment stuff.
749 ATS.emitAttribute(ARMBuildAttrs::ABI_align_needed, 1);
750 ATS.emitAttribute(ARMBuildAttrs::ABI_align_preserved, 1);
752 // ABI_HardFP_use attribute to indicate single precision FP.
753 if (Subtarget->isFPOnlySP())
754 ATS.emitAttribute(ARMBuildAttrs::ABI_HardFP_use,
755 ARMBuildAttrs::HardFPSinglePrecision);
757 // Hard float. Use both S and D registers and conform to AAPCS-VFP.
758 if (Subtarget->isAAPCS_ABI() && TM.Options.FloatABIType == FloatABI::Hard)
759 ATS.emitAttribute(ARMBuildAttrs::ABI_VFP_args, ARMBuildAttrs::HardFPAAPCS);
761 // FIXME: Should we signal R9 usage?
763 if (Subtarget->hasFP16())
764 ATS.emitAttribute(ARMBuildAttrs::FP_HP_extension, ARMBuildAttrs::AllowHPFP);
766 if (Subtarget->hasMPExtension())
767 ATS.emitAttribute(ARMBuildAttrs::MPextension_use, ARMBuildAttrs::AllowMP);
769 // Hardware divide in ARM mode is part of base arch, starting from ARMv8.
770 // If only Thumb hwdiv is present, it must also be in base arch (ARMv7-R/M).
771 // It is not possible to produce DisallowDIV: if hwdiv is present in the base
772 // arch, supplying -hwdiv downgrades the effective arch, via ClearImpliedBits.
773 // AllowDIVExt is only emitted if hwdiv isn't available in the base arch;
774 // otherwise, the default value (AllowDIVIfExists) applies.
775 if (Subtarget->hasDivideInARMMode() && !Subtarget->hasV8Ops())
776 ATS.emitAttribute(ARMBuildAttrs::DIV_use, ARMBuildAttrs::AllowDIVExt);
779 if (const Module *SourceModule = MMI->getModule()) {
780 // ABI_PCS_wchar_t to indicate wchar_t width
781 // FIXME: There is no way to emit value 0 (wchar_t prohibited).
782 if (auto WCharWidthValue = cast_or_null<ConstantInt>(
783 SourceModule->getModuleFlag("wchar_size"))) {
784 int WCharWidth = WCharWidthValue->getZExtValue();
785 assert((WCharWidth == 2 || WCharWidth == 4) &&
786 "wchar_t width must be 2 or 4 bytes");
787 ATS.emitAttribute(ARMBuildAttrs::ABI_PCS_wchar_t, WCharWidth);
790 // ABI_enum_size to indicate enum width
791 // FIXME: There is no way to emit value 0 (enums prohibited) or value 3
792 // (all enums contain a value needing 32 bits to encode).
793 if (auto EnumWidthValue = cast_or_null<ConstantInt>(
794 SourceModule->getModuleFlag("min_enum_size"))) {
795 int EnumWidth = EnumWidthValue->getZExtValue();
796 assert((EnumWidth == 1 || EnumWidth == 4) &&
797 "Minimum enum width must be 1 or 4 bytes");
798 int EnumBuildAttr = EnumWidth == 1 ? 1 : 2;
799 ATS.emitAttribute(ARMBuildAttrs::ABI_enum_size, EnumBuildAttr);
804 // TODO: We currently only support either reserving the register, or treating
805 // it as another callee-saved register, but not as SB or a TLS pointer; It
806 // would instead be nicer to push this from the frontend as metadata, as we do
807 // for the wchar and enum size tags
808 if (Subtarget->isR9Reserved())
809 ATS.emitAttribute(ARMBuildAttrs::ABI_PCS_R9_use,
810 ARMBuildAttrs::R9Reserved);
812 ATS.emitAttribute(ARMBuildAttrs::ABI_PCS_R9_use,
813 ARMBuildAttrs::R9IsGPR);
815 if (Subtarget->hasTrustZone() && Subtarget->hasVirtualization())
816 ATS.emitAttribute(ARMBuildAttrs::Virtualization_use,
817 ARMBuildAttrs::AllowTZVirtualization);
818 else if (Subtarget->hasTrustZone())
819 ATS.emitAttribute(ARMBuildAttrs::Virtualization_use,
820 ARMBuildAttrs::AllowTZ);
821 else if (Subtarget->hasVirtualization())
822 ATS.emitAttribute(ARMBuildAttrs::Virtualization_use,
823 ARMBuildAttrs::AllowVirtualization);
825 ATS.finishAttributeSection();
828 //===----------------------------------------------------------------------===//
830 static MCSymbol *getPICLabel(const char *Prefix, unsigned FunctionNumber,
831 unsigned LabelId, MCContext &Ctx) {
833 MCSymbol *Label = Ctx.GetOrCreateSymbol(Twine(Prefix)
834 + "PC" + Twine(FunctionNumber) + "_" + Twine(LabelId));
838 static MCSymbolRefExpr::VariantKind
839 getModifierVariantKind(ARMCP::ARMCPModifier Modifier) {
841 case ARMCP::no_modifier: return MCSymbolRefExpr::VK_None;
842 case ARMCP::TLSGD: return MCSymbolRefExpr::VK_TLSGD;
843 case ARMCP::TPOFF: return MCSymbolRefExpr::VK_TPOFF;
844 case ARMCP::GOTTPOFF: return MCSymbolRefExpr::VK_GOTTPOFF;
845 case ARMCP::GOT: return MCSymbolRefExpr::VK_GOT;
846 case ARMCP::GOTOFF: return MCSymbolRefExpr::VK_GOTOFF;
848 llvm_unreachable("Invalid ARMCPModifier!");
851 MCSymbol *ARMAsmPrinter::GetARMGVSymbol(const GlobalValue *GV,
852 unsigned char TargetFlags) {
853 if (Subtarget->isTargetMachO()) {
854 bool IsIndirect = (TargetFlags & ARMII::MO_NONLAZY) &&
855 Subtarget->GVIsIndirectSymbol(GV, TM.getRelocationModel());
858 return getSymbol(GV);
860 // FIXME: Remove this when Darwin transition to @GOT like syntax.
861 MCSymbol *MCSym = getSymbolWithGlobalValueBase(GV, "$non_lazy_ptr");
862 MachineModuleInfoMachO &MMIMachO =
863 MMI->getObjFileInfo<MachineModuleInfoMachO>();
864 MachineModuleInfoImpl::StubValueTy &StubSym =
865 GV->hasHiddenVisibility() ? MMIMachO.getHiddenGVStubEntry(MCSym)
866 : MMIMachO.getGVStubEntry(MCSym);
867 if (!StubSym.getPointer())
868 StubSym = MachineModuleInfoImpl::StubValueTy(getSymbol(GV),
869 !GV->hasInternalLinkage());
871 } else if (Subtarget->isTargetCOFF()) {
872 assert(Subtarget->isTargetWindows() &&
873 "Windows is the only supported COFF target");
875 bool IsIndirect = (TargetFlags & ARMII::MO_DLLIMPORT);
877 return getSymbol(GV);
879 SmallString<128> Name;
881 getNameWithPrefix(Name, GV);
883 return OutContext.GetOrCreateSymbol(Name);
884 } else if (Subtarget->isTargetELF()) {
885 return getSymbol(GV);
887 llvm_unreachable("unexpected target");
891 EmitMachineConstantPoolValue(MachineConstantPoolValue *MCPV) {
892 const DataLayout *DL = TM.getSubtargetImpl()->getDataLayout();
894 TM.getSubtargetImpl()->getDataLayout()->getTypeAllocSize(MCPV->getType());
896 ARMConstantPoolValue *ACPV = static_cast<ARMConstantPoolValue*>(MCPV);
899 if (ACPV->isLSDA()) {
900 SmallString<128> Str;
901 raw_svector_ostream OS(Str);
902 OS << DL->getPrivateGlobalPrefix() << "_LSDA_" << getFunctionNumber();
903 MCSym = OutContext.GetOrCreateSymbol(OS.str());
904 } else if (ACPV->isBlockAddress()) {
905 const BlockAddress *BA =
906 cast<ARMConstantPoolConstant>(ACPV)->getBlockAddress();
907 MCSym = GetBlockAddressSymbol(BA);
908 } else if (ACPV->isGlobalValue()) {
909 const GlobalValue *GV = cast<ARMConstantPoolConstant>(ACPV)->getGV();
911 // On Darwin, const-pool entries may get the "FOO$non_lazy_ptr" mangling, so
912 // flag the global as MO_NONLAZY.
913 unsigned char TF = Subtarget->isTargetMachO() ? ARMII::MO_NONLAZY : 0;
914 MCSym = GetARMGVSymbol(GV, TF);
915 } else if (ACPV->isMachineBasicBlock()) {
916 const MachineBasicBlock *MBB = cast<ARMConstantPoolMBB>(ACPV)->getMBB();
917 MCSym = MBB->getSymbol();
919 assert(ACPV->isExtSymbol() && "unrecognized constant pool value");
920 const char *Sym = cast<ARMConstantPoolSymbol>(ACPV)->getSymbol();
921 MCSym = GetExternalSymbolSymbol(Sym);
924 // Create an MCSymbol for the reference.
926 MCSymbolRefExpr::Create(MCSym, getModifierVariantKind(ACPV->getModifier()),
929 if (ACPV->getPCAdjustment()) {
930 MCSymbol *PCLabel = getPICLabel(DL->getPrivateGlobalPrefix(),
934 const MCExpr *PCRelExpr = MCSymbolRefExpr::Create(PCLabel, OutContext);
936 MCBinaryExpr::CreateAdd(PCRelExpr,
937 MCConstantExpr::Create(ACPV->getPCAdjustment(),
940 if (ACPV->mustAddCurrentAddress()) {
941 // We want "(<expr> - .)", but MC doesn't have a concept of the '.'
942 // label, so just emit a local label end reference that instead.
943 MCSymbol *DotSym = OutContext.CreateTempSymbol();
944 OutStreamer.EmitLabel(DotSym);
945 const MCExpr *DotExpr = MCSymbolRefExpr::Create(DotSym, OutContext);
946 PCRelExpr = MCBinaryExpr::CreateSub(PCRelExpr, DotExpr, OutContext);
948 Expr = MCBinaryExpr::CreateSub(Expr, PCRelExpr, OutContext);
950 OutStreamer.EmitValue(Expr, Size);
953 void ARMAsmPrinter::EmitJumpTable(const MachineInstr *MI) {
954 unsigned Opcode = MI->getOpcode();
956 if (Opcode == ARM::BR_JTadd)
958 else if (Opcode == ARM::BR_JTm)
961 const MachineOperand &MO1 = MI->getOperand(OpNum);
962 const MachineOperand &MO2 = MI->getOperand(OpNum+1); // Unique Id
963 unsigned JTI = MO1.getIndex();
965 // Emit a label for the jump table.
966 MCSymbol *JTISymbol = GetARMJTIPICJumpTableLabel2(JTI, MO2.getImm());
967 OutStreamer.EmitLabel(JTISymbol);
969 // Mark the jump table as data-in-code.
970 OutStreamer.EmitDataRegion(MCDR_DataRegionJT32);
972 // Emit each entry of the table.
973 const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
974 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
975 const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
977 for (unsigned i = 0, e = JTBBs.size(); i != e; ++i) {
978 MachineBasicBlock *MBB = JTBBs[i];
979 // Construct an MCExpr for the entry. We want a value of the form:
980 // (BasicBlockAddr - TableBeginAddr)
982 // For example, a table with entries jumping to basic blocks BB0 and BB1
985 // .word (LBB0 - LJTI_0_0)
986 // .word (LBB1 - LJTI_0_0)
987 const MCExpr *Expr = MCSymbolRefExpr::Create(MBB->getSymbol(), OutContext);
989 if (TM.getRelocationModel() == Reloc::PIC_)
990 Expr = MCBinaryExpr::CreateSub(Expr, MCSymbolRefExpr::Create(JTISymbol,
993 // If we're generating a table of Thumb addresses in static relocation
994 // model, we need to add one to keep interworking correctly.
995 else if (AFI->isThumbFunction())
996 Expr = MCBinaryExpr::CreateAdd(Expr, MCConstantExpr::Create(1,OutContext),
998 OutStreamer.EmitValue(Expr, 4);
1000 // Mark the end of jump table data-in-code region.
1001 OutStreamer.EmitDataRegion(MCDR_DataRegionEnd);
1004 void ARMAsmPrinter::EmitJump2Table(const MachineInstr *MI) {
1005 unsigned Opcode = MI->getOpcode();
1006 int OpNum = (Opcode == ARM::t2BR_JT) ? 2 : 1;
1007 const MachineOperand &MO1 = MI->getOperand(OpNum);
1008 const MachineOperand &MO2 = MI->getOperand(OpNum+1); // Unique Id
1009 unsigned JTI = MO1.getIndex();
1011 MCSymbol *JTISymbol = GetARMJTIPICJumpTableLabel2(JTI, MO2.getImm());
1012 OutStreamer.EmitLabel(JTISymbol);
1014 // Emit each entry of the table.
1015 const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
1016 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
1017 const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
1018 unsigned OffsetWidth = 4;
1019 if (MI->getOpcode() == ARM::t2TBB_JT) {
1021 // Mark the jump table as data-in-code.
1022 OutStreamer.EmitDataRegion(MCDR_DataRegionJT8);
1023 } else if (MI->getOpcode() == ARM::t2TBH_JT) {
1025 // Mark the jump table as data-in-code.
1026 OutStreamer.EmitDataRegion(MCDR_DataRegionJT16);
1029 for (unsigned i = 0, e = JTBBs.size(); i != e; ++i) {
1030 MachineBasicBlock *MBB = JTBBs[i];
1031 const MCExpr *MBBSymbolExpr = MCSymbolRefExpr::Create(MBB->getSymbol(),
1033 // If this isn't a TBB or TBH, the entries are direct branch instructions.
1034 if (OffsetWidth == 4) {
1035 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::t2B)
1036 .addExpr(MBBSymbolExpr)
1041 // Otherwise it's an offset from the dispatch instruction. Construct an
1042 // MCExpr for the entry. We want a value of the form:
1043 // (BasicBlockAddr - TableBeginAddr) / 2
1045 // For example, a TBB table with entries jumping to basic blocks BB0 and BB1
1048 // .byte (LBB0 - LJTI_0_0) / 2
1049 // .byte (LBB1 - LJTI_0_0) / 2
1050 const MCExpr *Expr =
1051 MCBinaryExpr::CreateSub(MBBSymbolExpr,
1052 MCSymbolRefExpr::Create(JTISymbol, OutContext),
1054 Expr = MCBinaryExpr::CreateDiv(Expr, MCConstantExpr::Create(2, OutContext),
1056 OutStreamer.EmitValue(Expr, OffsetWidth);
1058 // Mark the end of jump table data-in-code region. 32-bit offsets use
1059 // actual branch instructions here, so we don't mark those as a data-region
1061 if (OffsetWidth != 4)
1062 OutStreamer.EmitDataRegion(MCDR_DataRegionEnd);
1065 void ARMAsmPrinter::EmitUnwindingInstruction(const MachineInstr *MI) {
1066 assert(MI->getFlag(MachineInstr::FrameSetup) &&
1067 "Only instruction which are involved into frame setup code are allowed");
1069 MCTargetStreamer &TS = *OutStreamer.getTargetStreamer();
1070 ARMTargetStreamer &ATS = static_cast<ARMTargetStreamer &>(TS);
1071 const MachineFunction &MF = *MI->getParent()->getParent();
1072 const TargetRegisterInfo *RegInfo = MF.getSubtarget().getRegisterInfo();
1073 const ARMFunctionInfo &AFI = *MF.getInfo<ARMFunctionInfo>();
1075 unsigned FramePtr = RegInfo->getFrameRegister(MF);
1076 unsigned Opc = MI->getOpcode();
1077 unsigned SrcReg, DstReg;
1079 if (Opc == ARM::tPUSH || Opc == ARM::tLDRpci) {
1080 // Two special cases:
1081 // 1) tPUSH does not have src/dst regs.
1082 // 2) for Thumb1 code we sometimes materialize the constant via constpool
1083 // load. Yes, this is pretty fragile, but for now I don't see better
1085 SrcReg = DstReg = ARM::SP;
1087 SrcReg = MI->getOperand(1).getReg();
1088 DstReg = MI->getOperand(0).getReg();
1091 // Try to figure out the unwinding opcode out of src / dst regs.
1092 if (MI->mayStore()) {
1094 assert(DstReg == ARM::SP &&
1095 "Only stack pointer as a destination reg is supported");
1097 SmallVector<unsigned, 4> RegList;
1098 // Skip src & dst reg, and pred ops.
1099 unsigned StartOp = 2 + 2;
1100 // Use all the operands.
1101 unsigned NumOffset = 0;
1106 llvm_unreachable("Unsupported opcode for unwinding information");
1108 // Special case here: no src & dst reg, but two extra imp ops.
1109 StartOp = 2; NumOffset = 2;
1110 case ARM::STMDB_UPD:
1111 case ARM::t2STMDB_UPD:
1112 case ARM::VSTMDDB_UPD:
1113 assert(SrcReg == ARM::SP &&
1114 "Only stack pointer as a source reg is supported");
1115 for (unsigned i = StartOp, NumOps = MI->getNumOperands() - NumOffset;
1117 const MachineOperand &MO = MI->getOperand(i);
1118 // Actually, there should never be any impdef stuff here. Skip it
1119 // temporary to workaround PR11902.
1120 if (MO.isImplicit())
1122 RegList.push_back(MO.getReg());
1125 case ARM::STR_PRE_IMM:
1126 case ARM::STR_PRE_REG:
1127 case ARM::t2STR_PRE:
1128 assert(MI->getOperand(2).getReg() == ARM::SP &&
1129 "Only stack pointer as a source reg is supported");
1130 RegList.push_back(SrcReg);
1133 if (MAI->getExceptionHandlingType() == ExceptionHandling::ARM)
1134 ATS.emitRegSave(RegList, Opc == ARM::VSTMDDB_UPD);
1136 // Changes of stack / frame pointer.
1137 if (SrcReg == ARM::SP) {
1142 llvm_unreachable("Unsupported opcode for unwinding information");
1148 Offset = -MI->getOperand(2).getImm();
1152 Offset = MI->getOperand(2).getImm();
1155 Offset = MI->getOperand(2).getImm()*4;
1159 Offset = -MI->getOperand(2).getImm()*4;
1161 case ARM::tLDRpci: {
1162 // Grab the constpool index and check, whether it corresponds to
1163 // original or cloned constpool entry.
1164 unsigned CPI = MI->getOperand(1).getIndex();
1165 const MachineConstantPool *MCP = MF.getConstantPool();
1166 if (CPI >= MCP->getConstants().size())
1167 CPI = AFI.getOriginalCPIdx(CPI);
1168 assert(CPI != -1U && "Invalid constpool index");
1170 // Derive the actual offset.
1171 const MachineConstantPoolEntry &CPE = MCP->getConstants()[CPI];
1172 assert(!CPE.isMachineConstantPoolEntry() && "Invalid constpool entry");
1173 // FIXME: Check for user, it should be "add" instruction!
1174 Offset = -cast<ConstantInt>(CPE.Val.ConstVal)->getSExtValue();
1179 if (MAI->getExceptionHandlingType() == ExceptionHandling::ARM) {
1180 if (DstReg == FramePtr && FramePtr != ARM::SP)
1181 // Set-up of the frame pointer. Positive values correspond to "add"
1183 ATS.emitSetFP(FramePtr, ARM::SP, -Offset);
1184 else if (DstReg == ARM::SP) {
1185 // Change of SP by an offset. Positive values correspond to "sub"
1187 ATS.emitPad(Offset);
1189 // Move of SP to a register. Positive values correspond to an "add"
1191 ATS.emitMovSP(DstReg, -Offset);
1194 } else if (DstReg == ARM::SP) {
1196 llvm_unreachable("Unsupported opcode for unwinding information");
1200 llvm_unreachable("Unsupported opcode for unwinding information");
1205 // Simple pseudo-instructions have their lowering (with expansion to real
1206 // instructions) auto-generated.
1207 #include "ARMGenMCPseudoLowering.inc"
1209 void ARMAsmPrinter::EmitInstruction(const MachineInstr *MI) {
1210 const DataLayout *DL = TM.getSubtargetImpl()->getDataLayout();
1212 // If we just ended a constant pool, mark it as such.
1213 if (InConstantPool && MI->getOpcode() != ARM::CONSTPOOL_ENTRY) {
1214 OutStreamer.EmitDataRegion(MCDR_DataRegionEnd);
1215 InConstantPool = false;
1218 // Emit unwinding stuff for frame-related instructions
1219 if (Subtarget->isTargetEHABICompatible() &&
1220 MI->getFlag(MachineInstr::FrameSetup))
1221 EmitUnwindingInstruction(MI);
1223 // Do any auto-generated pseudo lowerings.
1224 if (emitPseudoExpansionLowering(OutStreamer, MI))
1227 assert(!convertAddSubFlagsOpcode(MI->getOpcode()) &&
1228 "Pseudo flag setting opcode should be expanded early");
1230 // Check for manual lowerings.
1231 unsigned Opc = MI->getOpcode();
1233 case ARM::t2MOVi32imm: llvm_unreachable("Should be lowered by thumb2it pass");
1234 case ARM::DBG_VALUE: llvm_unreachable("Should be handled by generic printing");
1236 case ARM::tLEApcrel:
1237 case ARM::t2LEApcrel: {
1238 // FIXME: Need to also handle globals and externals
1239 MCSymbol *CPISymbol = GetCPISymbol(MI->getOperand(1).getIndex());
1240 EmitToStreamer(OutStreamer, MCInstBuilder(MI->getOpcode() ==
1241 ARM::t2LEApcrel ? ARM::t2ADR
1242 : (MI->getOpcode() == ARM::tLEApcrel ? ARM::tADR
1244 .addReg(MI->getOperand(0).getReg())
1245 .addExpr(MCSymbolRefExpr::Create(CPISymbol, OutContext))
1246 // Add predicate operands.
1247 .addImm(MI->getOperand(2).getImm())
1248 .addReg(MI->getOperand(3).getReg()));
1251 case ARM::LEApcrelJT:
1252 case ARM::tLEApcrelJT:
1253 case ARM::t2LEApcrelJT: {
1254 MCSymbol *JTIPICSymbol =
1255 GetARMJTIPICJumpTableLabel2(MI->getOperand(1).getIndex(),
1256 MI->getOperand(2).getImm());
1257 EmitToStreamer(OutStreamer, MCInstBuilder(MI->getOpcode() ==
1258 ARM::t2LEApcrelJT ? ARM::t2ADR
1259 : (MI->getOpcode() == ARM::tLEApcrelJT ? ARM::tADR
1261 .addReg(MI->getOperand(0).getReg())
1262 .addExpr(MCSymbolRefExpr::Create(JTIPICSymbol, OutContext))
1263 // Add predicate operands.
1264 .addImm(MI->getOperand(3).getImm())
1265 .addReg(MI->getOperand(4).getReg()));
1268 // Darwin call instructions are just normal call instructions with different
1269 // clobber semantics (they clobber R9).
1270 case ARM::BX_CALL: {
1271 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::MOVr)
1274 // Add predicate operands.
1277 // Add 's' bit operand (always reg0 for this)
1280 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::BX)
1281 .addReg(MI->getOperand(0).getReg()));
1284 case ARM::tBX_CALL: {
1285 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tMOVr)
1288 // Add predicate operands.
1292 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tBX)
1293 .addReg(MI->getOperand(0).getReg())
1294 // Add predicate operands.
1299 case ARM::BMOVPCRX_CALL: {
1300 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::MOVr)
1303 // Add predicate operands.
1306 // Add 's' bit operand (always reg0 for this)
1309 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::MOVr)
1311 .addReg(MI->getOperand(0).getReg())
1312 // Add predicate operands.
1315 // Add 's' bit operand (always reg0 for this)
1319 case ARM::BMOVPCB_CALL: {
1320 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::MOVr)
1323 // Add predicate operands.
1326 // Add 's' bit operand (always reg0 for this)
1329 const MachineOperand &Op = MI->getOperand(0);
1330 const GlobalValue *GV = Op.getGlobal();
1331 const unsigned TF = Op.getTargetFlags();
1332 MCSymbol *GVSym = GetARMGVSymbol(GV, TF);
1333 const MCExpr *GVSymExpr = MCSymbolRefExpr::Create(GVSym, OutContext);
1334 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::Bcc)
1336 // Add predicate operands.
1341 case ARM::MOVi16_ga_pcrel:
1342 case ARM::t2MOVi16_ga_pcrel: {
1344 TmpInst.setOpcode(Opc == ARM::MOVi16_ga_pcrel? ARM::MOVi16 : ARM::t2MOVi16);
1345 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1347 unsigned TF = MI->getOperand(1).getTargetFlags();
1348 const GlobalValue *GV = MI->getOperand(1).getGlobal();
1349 MCSymbol *GVSym = GetARMGVSymbol(GV, TF);
1350 const MCExpr *GVSymExpr = MCSymbolRefExpr::Create(GVSym, OutContext);
1352 MCSymbol *LabelSym = getPICLabel(DL->getPrivateGlobalPrefix(),
1353 getFunctionNumber(),
1354 MI->getOperand(2).getImm(), OutContext);
1355 const MCExpr *LabelSymExpr= MCSymbolRefExpr::Create(LabelSym, OutContext);
1356 unsigned PCAdj = (Opc == ARM::MOVi16_ga_pcrel) ? 8 : 4;
1357 const MCExpr *PCRelExpr =
1358 ARMMCExpr::CreateLower16(MCBinaryExpr::CreateSub(GVSymExpr,
1359 MCBinaryExpr::CreateAdd(LabelSymExpr,
1360 MCConstantExpr::Create(PCAdj, OutContext),
1361 OutContext), OutContext), OutContext);
1362 TmpInst.addOperand(MCOperand::CreateExpr(PCRelExpr));
1364 // Add predicate operands.
1365 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1366 TmpInst.addOperand(MCOperand::CreateReg(0));
1367 // Add 's' bit operand (always reg0 for this)
1368 TmpInst.addOperand(MCOperand::CreateReg(0));
1369 EmitToStreamer(OutStreamer, TmpInst);
1372 case ARM::MOVTi16_ga_pcrel:
1373 case ARM::t2MOVTi16_ga_pcrel: {
1375 TmpInst.setOpcode(Opc == ARM::MOVTi16_ga_pcrel
1376 ? ARM::MOVTi16 : ARM::t2MOVTi16);
1377 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1378 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
1380 unsigned TF = MI->getOperand(2).getTargetFlags();
1381 const GlobalValue *GV = MI->getOperand(2).getGlobal();
1382 MCSymbol *GVSym = GetARMGVSymbol(GV, TF);
1383 const MCExpr *GVSymExpr = MCSymbolRefExpr::Create(GVSym, OutContext);
1385 MCSymbol *LabelSym = getPICLabel(DL->getPrivateGlobalPrefix(),
1386 getFunctionNumber(),
1387 MI->getOperand(3).getImm(), OutContext);
1388 const MCExpr *LabelSymExpr= MCSymbolRefExpr::Create(LabelSym, OutContext);
1389 unsigned PCAdj = (Opc == ARM::MOVTi16_ga_pcrel) ? 8 : 4;
1390 const MCExpr *PCRelExpr =
1391 ARMMCExpr::CreateUpper16(MCBinaryExpr::CreateSub(GVSymExpr,
1392 MCBinaryExpr::CreateAdd(LabelSymExpr,
1393 MCConstantExpr::Create(PCAdj, OutContext),
1394 OutContext), OutContext), OutContext);
1395 TmpInst.addOperand(MCOperand::CreateExpr(PCRelExpr));
1396 // Add predicate operands.
1397 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1398 TmpInst.addOperand(MCOperand::CreateReg(0));
1399 // Add 's' bit operand (always reg0 for this)
1400 TmpInst.addOperand(MCOperand::CreateReg(0));
1401 EmitToStreamer(OutStreamer, TmpInst);
1404 case ARM::tPICADD: {
1405 // This is a pseudo op for a label + instruction sequence, which looks like:
1408 // This adds the address of LPC0 to r0.
1411 OutStreamer.EmitLabel(getPICLabel(DL->getPrivateGlobalPrefix(),
1412 getFunctionNumber(), MI->getOperand(2).getImm(),
1415 // Form and emit the add.
1416 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tADDhirr)
1417 .addReg(MI->getOperand(0).getReg())
1418 .addReg(MI->getOperand(0).getReg())
1420 // Add predicate operands.
1426 // This is a pseudo op for a label + instruction sequence, which looks like:
1429 // This adds the address of LPC0 to r0.
1432 OutStreamer.EmitLabel(getPICLabel(DL->getPrivateGlobalPrefix(),
1433 getFunctionNumber(), MI->getOperand(2).getImm(),
1436 // Form and emit the add.
1437 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::ADDrr)
1438 .addReg(MI->getOperand(0).getReg())
1440 .addReg(MI->getOperand(1).getReg())
1441 // Add predicate operands.
1442 .addImm(MI->getOperand(3).getImm())
1443 .addReg(MI->getOperand(4).getReg())
1444 // Add 's' bit operand (always reg0 for this)
1455 case ARM::PICLDRSH: {
1456 // This is a pseudo op for a label + instruction sequence, which looks like:
1459 // The LCP0 label is referenced by a constant pool entry in order to get
1460 // a PC-relative address at the ldr instruction.
1463 OutStreamer.EmitLabel(getPICLabel(DL->getPrivateGlobalPrefix(),
1464 getFunctionNumber(), MI->getOperand(2).getImm(),
1467 // Form and emit the load
1469 switch (MI->getOpcode()) {
1471 llvm_unreachable("Unexpected opcode!");
1472 case ARM::PICSTR: Opcode = ARM::STRrs; break;
1473 case ARM::PICSTRB: Opcode = ARM::STRBrs; break;
1474 case ARM::PICSTRH: Opcode = ARM::STRH; break;
1475 case ARM::PICLDR: Opcode = ARM::LDRrs; break;
1476 case ARM::PICLDRB: Opcode = ARM::LDRBrs; break;
1477 case ARM::PICLDRH: Opcode = ARM::LDRH; break;
1478 case ARM::PICLDRSB: Opcode = ARM::LDRSB; break;
1479 case ARM::PICLDRSH: Opcode = ARM::LDRSH; break;
1481 EmitToStreamer(OutStreamer, MCInstBuilder(Opcode)
1482 .addReg(MI->getOperand(0).getReg())
1484 .addReg(MI->getOperand(1).getReg())
1486 // Add predicate operands.
1487 .addImm(MI->getOperand(3).getImm())
1488 .addReg(MI->getOperand(4).getReg()));
1492 case ARM::CONSTPOOL_ENTRY: {
1493 /// CONSTPOOL_ENTRY - This instruction represents a floating constant pool
1494 /// in the function. The first operand is the ID# for this instruction, the
1495 /// second is the index into the MachineConstantPool that this is, the third
1496 /// is the size in bytes of this constant pool entry.
1497 /// The required alignment is specified on the basic block holding this MI.
1498 unsigned LabelId = (unsigned)MI->getOperand(0).getImm();
1499 unsigned CPIdx = (unsigned)MI->getOperand(1).getIndex();
1501 // If this is the first entry of the pool, mark it.
1502 if (!InConstantPool) {
1503 OutStreamer.EmitDataRegion(MCDR_DataRegion);
1504 InConstantPool = true;
1507 OutStreamer.EmitLabel(GetCPISymbol(LabelId));
1509 const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPIdx];
1510 if (MCPE.isMachineConstantPoolEntry())
1511 EmitMachineConstantPoolValue(MCPE.Val.MachineCPVal);
1513 EmitGlobalConstant(MCPE.Val.ConstVal);
1516 case ARM::t2BR_JT: {
1517 // Lower and emit the instruction itself, then the jump table following it.
1518 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tMOVr)
1520 .addReg(MI->getOperand(0).getReg())
1521 // Add predicate operands.
1525 // Output the data for the jump table itself
1529 case ARM::t2TBB_JT: {
1530 // Lower and emit the instruction itself, then the jump table following it.
1531 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::t2TBB)
1533 .addReg(MI->getOperand(0).getReg())
1534 // Add predicate operands.
1538 // Output the data for the jump table itself
1540 // Make sure the next instruction is 2-byte aligned.
1544 case ARM::t2TBH_JT: {
1545 // Lower and emit the instruction itself, then the jump table following it.
1546 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::t2TBH)
1548 .addReg(MI->getOperand(0).getReg())
1549 // Add predicate operands.
1553 // Output the data for the jump table itself
1559 // Lower and emit the instruction itself, then the jump table following it.
1562 unsigned Opc = MI->getOpcode() == ARM::BR_JTr ?
1563 ARM::MOVr : ARM::tMOVr;
1564 TmpInst.setOpcode(Opc);
1565 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1566 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1567 // Add predicate operands.
1568 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1569 TmpInst.addOperand(MCOperand::CreateReg(0));
1570 // Add 's' bit operand (always reg0 for this)
1571 if (Opc == ARM::MOVr)
1572 TmpInst.addOperand(MCOperand::CreateReg(0));
1573 EmitToStreamer(OutStreamer, TmpInst);
1575 // Make sure the Thumb jump table is 4-byte aligned.
1576 if (Opc == ARM::tMOVr)
1579 // Output the data for the jump table itself
1584 // Lower and emit the instruction itself, then the jump table following it.
1587 if (MI->getOperand(1).getReg() == 0) {
1589 TmpInst.setOpcode(ARM::LDRi12);
1590 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1591 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1592 TmpInst.addOperand(MCOperand::CreateImm(MI->getOperand(2).getImm()));
1594 TmpInst.setOpcode(ARM::LDRrs);
1595 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1596 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1597 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
1598 TmpInst.addOperand(MCOperand::CreateImm(0));
1600 // Add predicate operands.
1601 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1602 TmpInst.addOperand(MCOperand::CreateReg(0));
1603 EmitToStreamer(OutStreamer, TmpInst);
1605 // Output the data for the jump table itself
1609 case ARM::BR_JTadd: {
1610 // Lower and emit the instruction itself, then the jump table following it.
1611 // add pc, target, idx
1612 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::ADDrr)
1614 .addReg(MI->getOperand(0).getReg())
1615 .addReg(MI->getOperand(1).getReg())
1616 // Add predicate operands.
1619 // Add 's' bit operand (always reg0 for this)
1622 // Output the data for the jump table itself
1627 OutStreamer.EmitZeros(MI->getOperand(1).getImm());
1630 // Non-Darwin binutils don't yet support the "trap" mnemonic.
1631 // FIXME: Remove this special case when they do.
1632 if (!Subtarget->isTargetMachO()) {
1633 //.long 0xe7ffdefe @ trap
1634 uint32_t Val = 0xe7ffdefeUL;
1635 OutStreamer.AddComment("trap");
1636 OutStreamer.EmitIntValue(Val, 4);
1641 case ARM::TRAPNaCl: {
1642 //.long 0xe7fedef0 @ trap
1643 uint32_t Val = 0xe7fedef0UL;
1644 OutStreamer.AddComment("trap");
1645 OutStreamer.EmitIntValue(Val, 4);
1649 // Non-Darwin binutils don't yet support the "trap" mnemonic.
1650 // FIXME: Remove this special case when they do.
1651 if (!Subtarget->isTargetMachO()) {
1652 //.short 57086 @ trap
1653 uint16_t Val = 0xdefe;
1654 OutStreamer.AddComment("trap");
1655 OutStreamer.EmitIntValue(Val, 2);
1660 case ARM::t2Int_eh_sjlj_setjmp:
1661 case ARM::t2Int_eh_sjlj_setjmp_nofp:
1662 case ARM::tInt_eh_sjlj_setjmp: {
1663 // Two incoming args: GPR:$src, GPR:$val
1666 // str $val, [$src, #4]
1671 unsigned SrcReg = MI->getOperand(0).getReg();
1672 unsigned ValReg = MI->getOperand(1).getReg();
1673 MCSymbol *Label = GetARMSJLJEHLabel();
1674 OutStreamer.AddComment("eh_setjmp begin");
1675 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tMOVr)
1682 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tADDi3)
1692 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tSTRi)
1695 // The offset immediate is #4. The operand value is scaled by 4 for the
1696 // tSTR instruction.
1702 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tMOVi8)
1710 const MCExpr *SymbolExpr = MCSymbolRefExpr::Create(Label, OutContext);
1711 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tB)
1712 .addExpr(SymbolExpr)
1716 OutStreamer.AddComment("eh_setjmp end");
1717 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tMOVi8)
1725 OutStreamer.EmitLabel(Label);
1729 case ARM::Int_eh_sjlj_setjmp_nofp:
1730 case ARM::Int_eh_sjlj_setjmp: {
1731 // Two incoming args: GPR:$src, GPR:$val
1733 // str $val, [$src, #+4]
1737 unsigned SrcReg = MI->getOperand(0).getReg();
1738 unsigned ValReg = MI->getOperand(1).getReg();
1740 OutStreamer.AddComment("eh_setjmp begin");
1741 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::ADDri)
1748 // 's' bit operand (always reg0 for this).
1751 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::STRi12)
1759 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::MOVi)
1765 // 's' bit operand (always reg0 for this).
1768 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::ADDri)
1775 // 's' bit operand (always reg0 for this).
1778 OutStreamer.AddComment("eh_setjmp end");
1779 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::MOVi)
1785 // 's' bit operand (always reg0 for this).
1789 case ARM::Int_eh_sjlj_longjmp: {
1790 // ldr sp, [$src, #8]
1791 // ldr $scratch, [$src, #4]
1794 unsigned SrcReg = MI->getOperand(0).getReg();
1795 unsigned ScratchReg = MI->getOperand(1).getReg();
1796 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::LDRi12)
1804 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::LDRi12)
1812 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::LDRi12)
1820 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::BX)
1827 case ARM::tInt_eh_sjlj_longjmp: {
1828 // ldr $scratch, [$src, #8]
1830 // ldr $scratch, [$src, #4]
1833 unsigned SrcReg = MI->getOperand(0).getReg();
1834 unsigned ScratchReg = MI->getOperand(1).getReg();
1835 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tLDRi)
1838 // The offset immediate is #8. The operand value is scaled by 4 for the
1839 // tLDR instruction.
1845 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tMOVr)
1852 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tLDRi)
1860 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tLDRi)
1868 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tBX)
1878 LowerARMMachineInstrToMCInst(MI, TmpInst, *this);
1880 EmitToStreamer(OutStreamer, TmpInst);
1883 //===----------------------------------------------------------------------===//
1884 // Target Registry Stuff
1885 //===----------------------------------------------------------------------===//
1887 // Force static initialization.
1888 extern "C" void LLVMInitializeARMAsmPrinter() {
1889 RegisterAsmPrinter<ARMAsmPrinter> X(TheARMLETarget);
1890 RegisterAsmPrinter<ARMAsmPrinter> Y(TheARMBETarget);
1891 RegisterAsmPrinter<ARMAsmPrinter> A(TheThumbLETarget);
1892 RegisterAsmPrinter<ARMAsmPrinter> B(TheThumbBETarget);