1 //===-- ARMAsmPrinter.cpp - Print machine code to an ARM .s file ----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains a printer that converts from our internal representation
11 // of machine-dependent LLVM code to GAS-format ARM assembly language.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "asm-printer"
17 #include "ARMAsmPrinter.h"
18 #include "ARMAddressingModes.h"
19 #include "ARMBuildAttrs.h"
20 #include "ARMBaseRegisterInfo.h"
21 #include "ARMConstantPoolValue.h"
22 #include "ARMMachineFunctionInfo.h"
23 #include "ARMMCExpr.h"
24 #include "ARMTargetMachine.h"
25 #include "ARMTargetObjectFile.h"
26 #include "InstPrinter/ARMInstPrinter.h"
27 #include "llvm/Analysis/DebugInfo.h"
28 #include "llvm/Constants.h"
29 #include "llvm/Module.h"
30 #include "llvm/Type.h"
31 #include "llvm/Assembly/Writer.h"
32 #include "llvm/CodeGen/MachineModuleInfoImpls.h"
33 #include "llvm/CodeGen/MachineFunctionPass.h"
34 #include "llvm/CodeGen/MachineJumpTableInfo.h"
35 #include "llvm/MC/MCAsmInfo.h"
36 #include "llvm/MC/MCAssembler.h"
37 #include "llvm/MC/MCContext.h"
38 #include "llvm/MC/MCExpr.h"
39 #include "llvm/MC/MCInst.h"
40 #include "llvm/MC/MCSectionMachO.h"
41 #include "llvm/MC/MCObjectStreamer.h"
42 #include "llvm/MC/MCStreamer.h"
43 #include "llvm/MC/MCSymbol.h"
44 #include "llvm/Target/Mangler.h"
45 #include "llvm/Target/TargetData.h"
46 #include "llvm/Target/TargetMachine.h"
47 #include "llvm/Target/TargetOptions.h"
48 #include "llvm/Target/TargetRegistry.h"
49 #include "llvm/ADT/SmallPtrSet.h"
50 #include "llvm/ADT/SmallString.h"
51 #include "llvm/ADT/StringExtras.h"
52 #include "llvm/Support/CommandLine.h"
53 #include "llvm/Support/Debug.h"
54 #include "llvm/Support/ErrorHandling.h"
55 #include "llvm/Support/raw_ostream.h"
61 // Per section and per symbol attributes are not supported.
62 // To implement them we would need the ability to delay this emission
63 // until the assembly file is fully parsed/generated as only then do we
64 // know the symbol and section numbers.
65 class AttributeEmitter {
67 virtual void MaybeSwitchVendor(StringRef Vendor) = 0;
68 virtual void EmitAttribute(unsigned Attribute, unsigned Value) = 0;
69 virtual void EmitTextAttribute(unsigned Attribute, StringRef String) = 0;
70 virtual void Finish() = 0;
71 virtual ~AttributeEmitter() {}
74 class AsmAttributeEmitter : public AttributeEmitter {
78 AsmAttributeEmitter(MCStreamer &Streamer_) : Streamer(Streamer_) {}
79 void MaybeSwitchVendor(StringRef Vendor) { }
81 void EmitAttribute(unsigned Attribute, unsigned Value) {
82 Streamer.EmitRawText("\t.eabi_attribute " +
83 Twine(Attribute) + ", " + Twine(Value));
86 void EmitTextAttribute(unsigned Attribute, StringRef String) {
88 case ARMBuildAttrs::CPU_name:
89 Streamer.EmitRawText(StringRef("\t.cpu ") + LowercaseString(String));
91 /* GAS requires .fpu to be emitted regardless of EABI attribute */
92 case ARMBuildAttrs::Advanced_SIMD_arch:
93 case ARMBuildAttrs::VFP_arch:
94 Streamer.EmitRawText(StringRef("\t.fpu ") + LowercaseString(String));
96 default: assert(0 && "Unsupported Text attribute in ASM Mode"); break;
102 class ObjectAttributeEmitter : public AttributeEmitter {
103 MCObjectStreamer &Streamer;
104 StringRef CurrentVendor;
105 SmallString<64> Contents;
108 ObjectAttributeEmitter(MCObjectStreamer &Streamer_) :
109 Streamer(Streamer_), CurrentVendor("") { }
111 void MaybeSwitchVendor(StringRef Vendor) {
112 assert(!Vendor.empty() && "Vendor cannot be empty.");
114 if (CurrentVendor.empty())
115 CurrentVendor = Vendor;
116 else if (CurrentVendor == Vendor)
121 CurrentVendor = Vendor;
123 assert(Contents.size() == 0);
126 void EmitAttribute(unsigned Attribute, unsigned Value) {
127 // FIXME: should be ULEB
128 Contents += Attribute;
132 void EmitTextAttribute(unsigned Attribute, StringRef String) {
133 Contents += Attribute;
134 Contents += UppercaseString(String);
139 const size_t ContentsSize = Contents.size();
141 // Vendor size + Vendor name + '\0'
142 const size_t VendorHeaderSize = 4 + CurrentVendor.size() + 1;
145 const size_t TagHeaderSize = 1 + 4;
147 Streamer.EmitIntValue(VendorHeaderSize + TagHeaderSize + ContentsSize, 4);
148 Streamer.EmitBytes(CurrentVendor, 0);
149 Streamer.EmitIntValue(0, 1); // '\0'
151 Streamer.EmitIntValue(ARMBuildAttrs::File, 1);
152 Streamer.EmitIntValue(TagHeaderSize + ContentsSize, 4);
154 Streamer.EmitBytes(Contents, 0);
160 } // end of anonymous namespace
162 MachineLocation ARMAsmPrinter::
163 getDebugValueLocation(const MachineInstr *MI) const {
164 MachineLocation Location;
165 assert(MI->getNumOperands() == 4 && "Invalid no. of machine operands!");
166 // Frame address. Currently handles register +- offset only.
167 if (MI->getOperand(0).isReg() && MI->getOperand(1).isImm())
168 Location.set(MI->getOperand(0).getReg(), MI->getOperand(1).getImm());
170 DEBUG(dbgs() << "DBG_VALUE instruction ignored! " << *MI << "\n");
175 /// EmitDwarfRegOp - Emit dwarf register operation.
176 void ARMAsmPrinter::EmitDwarfRegOp(const MachineLocation &MLoc) const {
177 const TargetRegisterInfo *RI = TM.getRegisterInfo();
178 if (RI->getDwarfRegNum(MLoc.getReg(), false) != -1)
179 AsmPrinter::EmitDwarfRegOp(MLoc);
181 unsigned Reg = MLoc.getReg();
182 if (Reg >= ARM::S0 && Reg <= ARM::S31) {
183 // S registers are described as bit-pieces of a register
184 // S[2x] = DW_OP_regx(256 + (x>>1)) DW_OP_bit_piece(32, 0)
185 // S[2x+1] = DW_OP_regx(256 + (x>>1)) DW_OP_bit_piece(32, 32)
187 unsigned SReg = Reg - ARM::S0;
188 bool odd = SReg & 0x1;
189 unsigned Rx = 256 + (SReg >> 1);
190 OutStreamer.AddComment("Loc expr size");
191 // DW_OP_regx + ULEB + DW_OP_bit_piece + ULEB + ULEB
192 // 1 + ULEB(Rx) + 1 + 1 + 1
193 EmitInt16(4 + MCAsmInfo::getULEB128Size(Rx));
195 OutStreamer.AddComment("DW_OP_regx for S register");
196 EmitInt8(dwarf::DW_OP_regx);
198 OutStreamer.AddComment(Twine(SReg));
202 OutStreamer.AddComment("DW_OP_bit_piece 32 32");
203 EmitInt8(dwarf::DW_OP_bit_piece);
207 OutStreamer.AddComment("DW_OP_bit_piece 32 0");
208 EmitInt8(dwarf::DW_OP_bit_piece);
212 } else if (Reg >= ARM::Q0 && Reg <= ARM::Q15) {
213 // Q registers Q0-Q15 are described by composing two D registers together.
214 // Qx = DW_OP_regx(256+2x) DW_OP_piece(8) DW_OP_regx(256+2x+1) DW_OP_piece(8)
216 unsigned QReg = Reg - ARM::Q0;
217 unsigned D1 = 256 + 2 * QReg;
218 unsigned D2 = D1 + 1;
220 OutStreamer.AddComment("Loc expr size");
221 // DW_OP_regx + ULEB + DW_OP_piece + ULEB(8) +
222 // DW_OP_regx + ULEB + DW_OP_piece + ULEB(8);
223 // 6 + ULEB(D1) + ULEB(D2)
224 EmitInt16(6 + MCAsmInfo::getULEB128Size(D1) + MCAsmInfo::getULEB128Size(D2));
226 OutStreamer.AddComment("DW_OP_regx for Q register: D1");
227 EmitInt8(dwarf::DW_OP_regx);
229 OutStreamer.AddComment("DW_OP_piece 8");
230 EmitInt8(dwarf::DW_OP_piece);
233 OutStreamer.AddComment("DW_OP_regx for Q register: D2");
234 EmitInt8(dwarf::DW_OP_regx);
236 OutStreamer.AddComment("DW_OP_piece 8");
237 EmitInt8(dwarf::DW_OP_piece);
243 void ARMAsmPrinter::EmitFunctionEntryLabel() {
244 if (AFI->isThumbFunction()) {
245 OutStreamer.EmitAssemblerFlag(MCAF_Code16);
246 OutStreamer.EmitThumbFunc(Subtarget->isTargetDarwin()? CurrentFnSym : 0);
249 OutStreamer.EmitLabel(CurrentFnSym);
252 /// runOnMachineFunction - This uses the EmitInstruction()
253 /// method to print assembly for each instruction.
255 bool ARMAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
256 AFI = MF.getInfo<ARMFunctionInfo>();
257 MCP = MF.getConstantPool();
259 return AsmPrinter::runOnMachineFunction(MF);
262 void ARMAsmPrinter::printOperand(const MachineInstr *MI, int OpNum,
263 raw_ostream &O, const char *Modifier) {
264 const MachineOperand &MO = MI->getOperand(OpNum);
265 unsigned TF = MO.getTargetFlags();
267 switch (MO.getType()) {
269 assert(0 && "<unknown operand type>");
270 case MachineOperand::MO_Register: {
271 unsigned Reg = MO.getReg();
272 assert(TargetRegisterInfo::isPhysicalRegister(Reg));
273 assert(!MO.getSubReg() && "Subregs should be eliminated!");
274 O << ARMInstPrinter::getRegisterName(Reg);
277 case MachineOperand::MO_Immediate: {
278 int64_t Imm = MO.getImm();
280 if ((Modifier && strcmp(Modifier, "lo16") == 0) ||
281 (TF == ARMII::MO_LO16))
283 else if ((Modifier && strcmp(Modifier, "hi16") == 0) ||
284 (TF == ARMII::MO_HI16))
289 case MachineOperand::MO_MachineBasicBlock:
290 O << *MO.getMBB()->getSymbol();
292 case MachineOperand::MO_GlobalAddress: {
293 const GlobalValue *GV = MO.getGlobal();
294 if ((Modifier && strcmp(Modifier, "lo16") == 0) ||
295 (TF & ARMII::MO_LO16))
297 else if ((Modifier && strcmp(Modifier, "hi16") == 0) ||
298 (TF & ARMII::MO_HI16))
300 O << *Mang->getSymbol(GV);
302 printOffset(MO.getOffset(), O);
303 if (TF == ARMII::MO_PLT)
307 case MachineOperand::MO_ExternalSymbol: {
308 O << *GetExternalSymbolSymbol(MO.getSymbolName());
309 if (TF == ARMII::MO_PLT)
313 case MachineOperand::MO_ConstantPoolIndex:
314 O << *GetCPISymbol(MO.getIndex());
316 case MachineOperand::MO_JumpTableIndex:
317 O << *GetJTISymbol(MO.getIndex());
322 //===--------------------------------------------------------------------===//
324 MCSymbol *ARMAsmPrinter::
325 GetARMSetPICJumpTableLabel2(unsigned uid, unsigned uid2,
326 const MachineBasicBlock *MBB) const {
327 SmallString<60> Name;
328 raw_svector_ostream(Name) << MAI->getPrivateGlobalPrefix()
329 << getFunctionNumber() << '_' << uid << '_' << uid2
330 << "_set_" << MBB->getNumber();
331 return OutContext.GetOrCreateSymbol(Name.str());
334 MCSymbol *ARMAsmPrinter::
335 GetARMJTIPICJumpTableLabel2(unsigned uid, unsigned uid2) const {
336 SmallString<60> Name;
337 raw_svector_ostream(Name) << MAI->getPrivateGlobalPrefix() << "JTI"
338 << getFunctionNumber() << '_' << uid << '_' << uid2;
339 return OutContext.GetOrCreateSymbol(Name.str());
343 MCSymbol *ARMAsmPrinter::GetARMSJLJEHLabel(void) const {
344 SmallString<60> Name;
345 raw_svector_ostream(Name) << MAI->getPrivateGlobalPrefix() << "SJLJEH"
346 << getFunctionNumber();
347 return OutContext.GetOrCreateSymbol(Name.str());
350 bool ARMAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
351 unsigned AsmVariant, const char *ExtraCode,
353 // Does this asm operand have a single letter operand modifier?
354 if (ExtraCode && ExtraCode[0]) {
355 if (ExtraCode[1] != 0) return true; // Unknown modifier.
357 switch (ExtraCode[0]) {
358 default: return true; // Unknown modifier.
359 case 'a': // Print as a memory address.
360 if (MI->getOperand(OpNum).isReg()) {
362 << ARMInstPrinter::getRegisterName(MI->getOperand(OpNum).getReg())
367 case 'c': // Don't print "#" before an immediate operand.
368 if (!MI->getOperand(OpNum).isImm())
370 O << MI->getOperand(OpNum).getImm();
372 case 'P': // Print a VFP double precision register.
373 case 'q': // Print a NEON quad precision register.
374 printOperand(MI, OpNum, O);
379 // These modifiers are not yet supported.
384 printOperand(MI, OpNum, O);
388 bool ARMAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI,
389 unsigned OpNum, unsigned AsmVariant,
390 const char *ExtraCode,
392 if (ExtraCode && ExtraCode[0])
393 return true; // Unknown modifier.
395 const MachineOperand &MO = MI->getOperand(OpNum);
396 assert(MO.isReg() && "unexpected inline asm memory operand");
397 O << "[" << ARMInstPrinter::getRegisterName(MO.getReg()) << "]";
401 void ARMAsmPrinter::EmitStartOfAsmFile(Module &M) {
402 if (Subtarget->isTargetDarwin()) {
403 Reloc::Model RelocM = TM.getRelocationModel();
404 if (RelocM == Reloc::PIC_ || RelocM == Reloc::DynamicNoPIC) {
405 // Declare all the text sections up front (before the DWARF sections
406 // emitted by AsmPrinter::doInitialization) so the assembler will keep
407 // them together at the beginning of the object file. This helps
408 // avoid out-of-range branches that are due a fundamental limitation of
409 // the way symbol offsets are encoded with the current Darwin ARM
411 const TargetLoweringObjectFileMachO &TLOFMacho =
412 static_cast<const TargetLoweringObjectFileMachO &>(
413 getObjFileLowering());
414 OutStreamer.SwitchSection(TLOFMacho.getTextSection());
415 OutStreamer.SwitchSection(TLOFMacho.getTextCoalSection());
416 OutStreamer.SwitchSection(TLOFMacho.getConstTextCoalSection());
417 if (RelocM == Reloc::DynamicNoPIC) {
418 const MCSection *sect =
419 OutContext.getMachOSection("__TEXT", "__symbol_stub4",
420 MCSectionMachO::S_SYMBOL_STUBS,
421 12, SectionKind::getText());
422 OutStreamer.SwitchSection(sect);
424 const MCSection *sect =
425 OutContext.getMachOSection("__TEXT", "__picsymbolstub4",
426 MCSectionMachO::S_SYMBOL_STUBS,
427 16, SectionKind::getText());
428 OutStreamer.SwitchSection(sect);
430 const MCSection *StaticInitSect =
431 OutContext.getMachOSection("__TEXT", "__StaticInit",
432 MCSectionMachO::S_REGULAR |
433 MCSectionMachO::S_ATTR_PURE_INSTRUCTIONS,
434 SectionKind::getText());
435 OutStreamer.SwitchSection(StaticInitSect);
439 // Use unified assembler syntax.
440 OutStreamer.EmitAssemblerFlag(MCAF_SyntaxUnified);
442 // Emit ARM Build Attributes
443 if (Subtarget->isTargetELF()) {
450 void ARMAsmPrinter::EmitEndOfAsmFile(Module &M) {
451 if (Subtarget->isTargetDarwin()) {
452 // All darwin targets use mach-o.
453 const TargetLoweringObjectFileMachO &TLOFMacho =
454 static_cast<const TargetLoweringObjectFileMachO &>(getObjFileLowering());
455 MachineModuleInfoMachO &MMIMacho =
456 MMI->getObjFileInfo<MachineModuleInfoMachO>();
458 // Output non-lazy-pointers for external and common global variables.
459 MachineModuleInfoMachO::SymbolListTy Stubs = MMIMacho.GetGVStubList();
461 if (!Stubs.empty()) {
462 // Switch with ".non_lazy_symbol_pointer" directive.
463 OutStreamer.SwitchSection(TLOFMacho.getNonLazySymbolPointerSection());
465 for (unsigned i = 0, e = Stubs.size(); i != e; ++i) {
467 OutStreamer.EmitLabel(Stubs[i].first);
468 // .indirect_symbol _foo
469 MachineModuleInfoImpl::StubValueTy &MCSym = Stubs[i].second;
470 OutStreamer.EmitSymbolAttribute(MCSym.getPointer(),MCSA_IndirectSymbol);
473 // External to current translation unit.
474 OutStreamer.EmitIntValue(0, 4/*size*/, 0/*addrspace*/);
476 // Internal to current translation unit.
478 // When we place the LSDA into the TEXT section, the type info
479 // pointers need to be indirect and pc-rel. We accomplish this by
480 // using NLPs; however, sometimes the types are local to the file.
481 // We need to fill in the value for the NLP in those cases.
482 OutStreamer.EmitValue(MCSymbolRefExpr::Create(MCSym.getPointer(),
484 4/*size*/, 0/*addrspace*/);
488 OutStreamer.AddBlankLine();
491 Stubs = MMIMacho.GetHiddenGVStubList();
492 if (!Stubs.empty()) {
493 OutStreamer.SwitchSection(getObjFileLowering().getDataSection());
495 for (unsigned i = 0, e = Stubs.size(); i != e; ++i) {
497 OutStreamer.EmitLabel(Stubs[i].first);
499 OutStreamer.EmitValue(MCSymbolRefExpr::
500 Create(Stubs[i].second.getPointer(),
502 4/*size*/, 0/*addrspace*/);
506 OutStreamer.AddBlankLine();
509 // Funny Darwin hack: This flag tells the linker that no global symbols
510 // contain code that falls through to other global symbols (e.g. the obvious
511 // implementation of multiple entry points). If this doesn't occur, the
512 // linker can safely perform dead code stripping. Since LLVM never
513 // generates code that does this, it is always safe to set.
514 OutStreamer.EmitAssemblerFlag(MCAF_SubsectionsViaSymbols);
518 //===----------------------------------------------------------------------===//
519 // Helper routines for EmitStartOfAsmFile() and EmitEndOfAsmFile()
521 // The following seem like one-off assembler flags, but they actually need
522 // to appear in the .ARM.attributes section in ELF.
523 // Instead of subclassing the MCELFStreamer, we do the work here.
525 void ARMAsmPrinter::emitAttributes() {
527 emitARMAttributeSection();
529 /* GAS expect .fpu to be emitted, regardless of VFP build attribute */
530 bool emitFPU = false;
531 AttributeEmitter *AttrEmitter;
532 if (OutStreamer.hasRawTextSupport()) {
533 AttrEmitter = new AsmAttributeEmitter(OutStreamer);
536 MCObjectStreamer &O = static_cast<MCObjectStreamer&>(OutStreamer);
537 AttrEmitter = new ObjectAttributeEmitter(O);
540 AttrEmitter->MaybeSwitchVendor("aeabi");
542 std::string CPUString = Subtarget->getCPUString();
544 if (CPUString == "cortex-a8" ||
545 Subtarget->isCortexA8()) {
546 AttrEmitter->EmitTextAttribute(ARMBuildAttrs::CPU_name, "cortex-a8");
547 AttrEmitter->EmitAttribute(ARMBuildAttrs::CPU_arch, ARMBuildAttrs::v7);
548 AttrEmitter->EmitAttribute(ARMBuildAttrs::CPU_arch_profile,
549 ARMBuildAttrs::ApplicationProfile);
550 AttrEmitter->EmitAttribute(ARMBuildAttrs::ARM_ISA_use,
551 ARMBuildAttrs::Allowed);
552 AttrEmitter->EmitAttribute(ARMBuildAttrs::THUMB_ISA_use,
553 ARMBuildAttrs::AllowThumb32);
554 // Fixme: figure out when this is emitted.
555 //AttrEmitter->EmitAttribute(ARMBuildAttrs::WMMX_arch,
556 // ARMBuildAttrs::AllowWMMXv1);
559 /// ADD additional Else-cases here!
560 } else if (CPUString == "generic") {
561 // FIXME: Why these defaults?
562 AttrEmitter->EmitAttribute(ARMBuildAttrs::CPU_arch, ARMBuildAttrs::v4T);
563 AttrEmitter->EmitAttribute(ARMBuildAttrs::ARM_ISA_use,
564 ARMBuildAttrs::Allowed);
565 AttrEmitter->EmitAttribute(ARMBuildAttrs::THUMB_ISA_use,
566 ARMBuildAttrs::Allowed);
569 if (Subtarget->hasNEON() && emitFPU) {
570 /* NEON is not exactly a VFP architecture, but GAS emit one of
571 * neon/vfpv3/vfpv2 for .fpu parameters */
572 AttrEmitter->EmitTextAttribute(ARMBuildAttrs::Advanced_SIMD_arch, "neon");
573 /* If emitted for NEON, omit from VFP below, since you can have both
574 * NEON and VFP in build attributes but only one .fpu */
579 if (Subtarget->hasVFP3()) {
580 AttrEmitter->EmitAttribute(ARMBuildAttrs::VFP_arch,
581 ARMBuildAttrs::AllowFPv3A);
583 AttrEmitter->EmitTextAttribute(ARMBuildAttrs::VFP_arch, "vfpv3");
586 } else if (Subtarget->hasVFP2()) {
587 AttrEmitter->EmitAttribute(ARMBuildAttrs::VFP_arch,
588 ARMBuildAttrs::AllowFPv2);
590 AttrEmitter->EmitTextAttribute(ARMBuildAttrs::VFP_arch, "vfpv2");
593 /* TODO: ARMBuildAttrs::Allowed is not completely accurate,
594 * since NEON can have 1 (allowed) or 2 (fused MAC operations) */
595 if (Subtarget->hasNEON()) {
596 AttrEmitter->EmitAttribute(ARMBuildAttrs::Advanced_SIMD_arch,
597 ARMBuildAttrs::Allowed);
600 // Signal various FP modes.
602 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_FP_denormal,
603 ARMBuildAttrs::Allowed);
604 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_FP_exceptions,
605 ARMBuildAttrs::Allowed);
608 if (NoInfsFPMath && NoNaNsFPMath)
609 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_FP_number_model,
610 ARMBuildAttrs::Allowed);
612 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_FP_number_model,
613 ARMBuildAttrs::AllowIEE754);
615 // FIXME: add more flags to ARMBuildAttrs.h
616 // 8-bytes alignment stuff.
617 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_align8_needed, 1);
618 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_align8_preserved, 1);
620 // Hard float. Use both S and D registers and conform to AAPCS-VFP.
621 if (Subtarget->isAAPCS_ABI() && FloatABIType == FloatABI::Hard) {
622 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_HardFP_use, 3);
623 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_VFP_args, 1);
625 // FIXME: Should we signal R9 usage?
627 if (Subtarget->hasDivide())
628 AttrEmitter->EmitAttribute(ARMBuildAttrs::DIV_use, 1);
630 AttrEmitter->Finish();
634 void ARMAsmPrinter::emitARMAttributeSection() {
636 // [ <section-length> "vendor-name"
637 // [ <file-tag> <size> <attribute>*
638 // | <section-tag> <size> <section-number>* 0 <attribute>*
639 // | <symbol-tag> <size> <symbol-number>* 0 <attribute>*
643 if (OutStreamer.hasRawTextSupport())
646 const ARMElfTargetObjectFile &TLOFELF =
647 static_cast<const ARMElfTargetObjectFile &>
648 (getObjFileLowering());
650 OutStreamer.SwitchSection(TLOFELF.getAttributesSection());
653 OutStreamer.EmitIntValue(0x41, 1);
656 //===----------------------------------------------------------------------===//
658 static MCSymbol *getPICLabel(const char *Prefix, unsigned FunctionNumber,
659 unsigned LabelId, MCContext &Ctx) {
661 MCSymbol *Label = Ctx.GetOrCreateSymbol(Twine(Prefix)
662 + "PC" + Twine(FunctionNumber) + "_" + Twine(LabelId));
666 static MCSymbolRefExpr::VariantKind
667 getModifierVariantKind(ARMCP::ARMCPModifier Modifier) {
669 default: llvm_unreachable("Unknown modifier!");
670 case ARMCP::no_modifier: return MCSymbolRefExpr::VK_None;
671 case ARMCP::TLSGD: return MCSymbolRefExpr::VK_ARM_TLSGD;
672 case ARMCP::TPOFF: return MCSymbolRefExpr::VK_ARM_TPOFF;
673 case ARMCP::GOTTPOFF: return MCSymbolRefExpr::VK_ARM_GOTTPOFF;
674 case ARMCP::GOT: return MCSymbolRefExpr::VK_ARM_GOT;
675 case ARMCP::GOTOFF: return MCSymbolRefExpr::VK_ARM_GOTOFF;
677 return MCSymbolRefExpr::VK_None;
680 MCSymbol *ARMAsmPrinter::GetARMGVSymbol(const GlobalValue *GV) {
681 bool isIndirect = Subtarget->isTargetDarwin() &&
682 Subtarget->GVIsIndirectSymbol(GV, TM.getRelocationModel());
684 return Mang->getSymbol(GV);
686 // FIXME: Remove this when Darwin transition to @GOT like syntax.
687 MCSymbol *MCSym = GetSymbolWithGlobalValueBase(GV, "$non_lazy_ptr");
688 MachineModuleInfoMachO &MMIMachO =
689 MMI->getObjFileInfo<MachineModuleInfoMachO>();
690 MachineModuleInfoImpl::StubValueTy &StubSym =
691 GV->hasHiddenVisibility() ? MMIMachO.getHiddenGVStubEntry(MCSym) :
692 MMIMachO.getGVStubEntry(MCSym);
693 if (StubSym.getPointer() == 0)
694 StubSym = MachineModuleInfoImpl::
695 StubValueTy(Mang->getSymbol(GV), !GV->hasInternalLinkage());
700 EmitMachineConstantPoolValue(MachineConstantPoolValue *MCPV) {
701 int Size = TM.getTargetData()->getTypeAllocSize(MCPV->getType());
703 ARMConstantPoolValue *ACPV = static_cast<ARMConstantPoolValue*>(MCPV);
706 if (ACPV->isLSDA()) {
707 SmallString<128> Str;
708 raw_svector_ostream OS(Str);
709 OS << MAI->getPrivateGlobalPrefix() << "_LSDA_" << getFunctionNumber();
710 MCSym = OutContext.GetOrCreateSymbol(OS.str());
711 } else if (ACPV->isBlockAddress()) {
712 MCSym = GetBlockAddressSymbol(ACPV->getBlockAddress());
713 } else if (ACPV->isGlobalValue()) {
714 const GlobalValue *GV = ACPV->getGV();
715 MCSym = GetARMGVSymbol(GV);
717 assert(ACPV->isExtSymbol() && "unrecognized constant pool value");
718 MCSym = GetExternalSymbolSymbol(ACPV->getSymbol());
721 // Create an MCSymbol for the reference.
723 MCSymbolRefExpr::Create(MCSym, getModifierVariantKind(ACPV->getModifier()),
726 if (ACPV->getPCAdjustment()) {
727 MCSymbol *PCLabel = getPICLabel(MAI->getPrivateGlobalPrefix(),
731 const MCExpr *PCRelExpr = MCSymbolRefExpr::Create(PCLabel, OutContext);
733 MCBinaryExpr::CreateAdd(PCRelExpr,
734 MCConstantExpr::Create(ACPV->getPCAdjustment(),
737 if (ACPV->mustAddCurrentAddress()) {
738 // We want "(<expr> - .)", but MC doesn't have a concept of the '.'
739 // label, so just emit a local label end reference that instead.
740 MCSymbol *DotSym = OutContext.CreateTempSymbol();
741 OutStreamer.EmitLabel(DotSym);
742 const MCExpr *DotExpr = MCSymbolRefExpr::Create(DotSym, OutContext);
743 PCRelExpr = MCBinaryExpr::CreateSub(PCRelExpr, DotExpr, OutContext);
745 Expr = MCBinaryExpr::CreateSub(Expr, PCRelExpr, OutContext);
747 OutStreamer.EmitValue(Expr, Size);
750 void ARMAsmPrinter::EmitJumpTable(const MachineInstr *MI) {
751 unsigned Opcode = MI->getOpcode();
753 if (Opcode == ARM::BR_JTadd)
755 else if (Opcode == ARM::BR_JTm)
758 const MachineOperand &MO1 = MI->getOperand(OpNum);
759 const MachineOperand &MO2 = MI->getOperand(OpNum+1); // Unique Id
760 unsigned JTI = MO1.getIndex();
762 // Emit a label for the jump table.
763 MCSymbol *JTISymbol = GetARMJTIPICJumpTableLabel2(JTI, MO2.getImm());
764 OutStreamer.EmitLabel(JTISymbol);
766 // Emit each entry of the table.
767 const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
768 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
769 const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
771 for (unsigned i = 0, e = JTBBs.size(); i != e; ++i) {
772 MachineBasicBlock *MBB = JTBBs[i];
773 // Construct an MCExpr for the entry. We want a value of the form:
774 // (BasicBlockAddr - TableBeginAddr)
776 // For example, a table with entries jumping to basic blocks BB0 and BB1
779 // .word (LBB0 - LJTI_0_0)
780 // .word (LBB1 - LJTI_0_0)
781 const MCExpr *Expr = MCSymbolRefExpr::Create(MBB->getSymbol(), OutContext);
783 if (TM.getRelocationModel() == Reloc::PIC_)
784 Expr = MCBinaryExpr::CreateSub(Expr, MCSymbolRefExpr::Create(JTISymbol,
787 OutStreamer.EmitValue(Expr, 4);
791 void ARMAsmPrinter::EmitJump2Table(const MachineInstr *MI) {
792 unsigned Opcode = MI->getOpcode();
793 int OpNum = (Opcode == ARM::t2BR_JT) ? 2 : 1;
794 const MachineOperand &MO1 = MI->getOperand(OpNum);
795 const MachineOperand &MO2 = MI->getOperand(OpNum+1); // Unique Id
796 unsigned JTI = MO1.getIndex();
798 // Emit a label for the jump table.
799 MCSymbol *JTISymbol = GetARMJTIPICJumpTableLabel2(JTI, MO2.getImm());
800 OutStreamer.EmitLabel(JTISymbol);
802 // Emit each entry of the table.
803 const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
804 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
805 const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
806 unsigned OffsetWidth = 4;
807 if (MI->getOpcode() == ARM::t2TBB_JT)
809 else if (MI->getOpcode() == ARM::t2TBH_JT)
812 for (unsigned i = 0, e = JTBBs.size(); i != e; ++i) {
813 MachineBasicBlock *MBB = JTBBs[i];
814 const MCExpr *MBBSymbolExpr = MCSymbolRefExpr::Create(MBB->getSymbol(),
816 // If this isn't a TBB or TBH, the entries are direct branch instructions.
817 if (OffsetWidth == 4) {
819 BrInst.setOpcode(ARM::t2B);
820 BrInst.addOperand(MCOperand::CreateExpr(MBBSymbolExpr));
821 OutStreamer.EmitInstruction(BrInst);
824 // Otherwise it's an offset from the dispatch instruction. Construct an
825 // MCExpr for the entry. We want a value of the form:
826 // (BasicBlockAddr - TableBeginAddr) / 2
828 // For example, a TBB table with entries jumping to basic blocks BB0 and BB1
831 // .byte (LBB0 - LJTI_0_0) / 2
832 // .byte (LBB1 - LJTI_0_0) / 2
834 MCBinaryExpr::CreateSub(MBBSymbolExpr,
835 MCSymbolRefExpr::Create(JTISymbol, OutContext),
837 Expr = MCBinaryExpr::CreateDiv(Expr, MCConstantExpr::Create(2, OutContext),
839 OutStreamer.EmitValue(Expr, OffsetWidth);
843 void ARMAsmPrinter::PrintDebugValueComment(const MachineInstr *MI,
845 unsigned NOps = MI->getNumOperands();
847 OS << '\t' << MAI->getCommentString() << "DEBUG_VALUE: ";
848 // cast away const; DIetc do not take const operands for some reason.
849 DIVariable V(const_cast<MDNode *>(MI->getOperand(NOps-1).getMetadata()));
852 // Frame address. Currently handles register +- offset only.
853 assert(MI->getOperand(0).isReg() && MI->getOperand(1).isImm());
854 OS << '['; printOperand(MI, 0, OS); OS << '+'; printOperand(MI, 1, OS);
857 printOperand(MI, NOps-2, OS);
860 static void populateADROperands(MCInst &Inst, unsigned Dest,
861 const MCSymbol *Label,
862 unsigned pred, unsigned ccreg,
864 const MCExpr *SymbolExpr = MCSymbolRefExpr::Create(Label, Ctx);
865 Inst.addOperand(MCOperand::CreateReg(Dest));
866 Inst.addOperand(MCOperand::CreateExpr(SymbolExpr));
867 // Add predicate operands.
868 Inst.addOperand(MCOperand::CreateImm(pred));
869 Inst.addOperand(MCOperand::CreateReg(ccreg));
872 void ARMAsmPrinter::EmitPatchedInstruction(const MachineInstr *MI,
876 // Emit the instruction as usual, just patch the opcode.
877 LowerARMMachineInstrToMCInst(MI, TmpInst, *this);
878 TmpInst.setOpcode(Opcode);
879 OutStreamer.EmitInstruction(TmpInst);
882 void ARMAsmPrinter::EmitUnwindingInstruction(const MachineInstr *MI) {
883 assert(MI->getFlag(MachineInstr::FrameSetup) &&
884 "Only instruction which are involved into frame setup code are allowed");
886 const MachineFunction &MF = *MI->getParent()->getParent();
887 const TargetRegisterInfo *RegInfo = MF.getTarget().getRegisterInfo();
888 const ARMFunctionInfo &AFI = *MF.getInfo<ARMFunctionInfo>();
890 unsigned FramePtr = RegInfo->getFrameRegister(MF);
891 unsigned Opc = MI->getOpcode();
892 unsigned SrcReg, DstReg;
894 if (Opc == ARM::tPUSH || Opc == ARM::tLDRpci) {
895 // Two special cases:
896 // 1) tPUSH does not have src/dst regs.
897 // 2) for Thumb1 code we sometimes materialize the constant via constpool
898 // load. Yes, this is pretty fragile, but for now I don't see better
900 SrcReg = DstReg = ARM::SP;
902 SrcReg = MI->getOperand(1).getReg();
903 DstReg = MI->getOperand(0).getReg();
906 // Try to figure out the unwinding opcode out of src / dst regs.
907 if (MI->getDesc().mayStore()) {
909 assert(DstReg == ARM::SP &&
910 "Only stack pointer as a destination reg is supported");
912 SmallVector<unsigned, 4> RegList;
913 // Skip src & dst reg, and pred ops.
914 unsigned StartOp = 2 + 2;
915 // Use all the operands.
916 unsigned NumOffset = 0;
921 assert(0 && "Unsupported opcode for unwinding information");
923 // Special case here: no src & dst reg, but two extra imp ops.
924 StartOp = 2; NumOffset = 2;
926 case ARM::t2STMDB_UPD:
927 case ARM::VSTMDDB_UPD:
928 assert(SrcReg == ARM::SP &&
929 "Only stack pointer as a source reg is supported");
930 for (unsigned i = StartOp, NumOps = MI->getNumOperands() - NumOffset;
932 RegList.push_back(MI->getOperand(i).getReg());
935 assert(MI->getOperand(2).getReg() == ARM::SP &&
936 "Only stack pointer as a source reg is supported");
937 RegList.push_back(SrcReg);
940 OutStreamer.EmitRegSave(RegList, Opc == ARM::VSTMDDB_UPD);
942 // Changes of stack / frame pointer.
943 if (SrcReg == ARM::SP) {
948 assert(0 && "Unsupported opcode for unwinding information");
950 case ARM::tMOVgpr2gpr:
951 case ARM::tMOVgpr2tgpr:
955 Offset = -MI->getOperand(2).getImm();
959 Offset = MI->getOperand(2).getImm();
962 Offset = MI->getOperand(2).getImm()*4;
966 Offset = -MI->getOperand(2).getImm()*4;
969 // Grab the constpool index and check, whether it corresponds to
970 // original or cloned constpool entry.
971 unsigned CPI = MI->getOperand(1).getIndex();
972 const MachineConstantPool *MCP = MF.getConstantPool();
973 if (CPI >= MCP->getConstants().size())
974 CPI = AFI.getOriginalCPIdx(CPI);
975 assert(CPI != -1U && "Invalid constpool index");
977 // Derive the actual offset.
978 const MachineConstantPoolEntry &CPE = MCP->getConstants()[CPI];
979 assert(!CPE.isMachineConstantPoolEntry() && "Invalid constpool entry");
980 // FIXME: Check for user, it should be "add" instruction!
981 Offset = -cast<ConstantInt>(CPE.Val.ConstVal)->getSExtValue();
986 if (DstReg == FramePtr && FramePtr != ARM::SP)
987 // Set-up of the frame pointer. Positive values correspond to "add"
989 OutStreamer.EmitSetFP(FramePtr, ARM::SP, -Offset);
990 else if (DstReg == ARM::SP) {
991 // Change of SP by an offset. Positive values correspond to "sub"
993 OutStreamer.EmitPad(Offset);
996 assert(0 && "Unsupported opcode for unwinding information");
998 } else if (DstReg == ARM::SP) {
999 // FIXME: .movsp goes here
1001 assert(0 && "Unsupported opcode for unwinding information");
1005 assert(0 && "Unsupported opcode for unwinding information");
1010 extern cl::opt<bool> EnableARMEHABI;
1012 void ARMAsmPrinter::EmitInstruction(const MachineInstr *MI) {
1013 unsigned Opc = MI->getOpcode();
1017 // B is just a Bcc with an 'always' predicate.
1019 LowerARMMachineInstrToMCInst(MI, TmpInst, *this);
1020 TmpInst.setOpcode(ARM::Bcc);
1021 // Add predicate operands.
1022 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1023 TmpInst.addOperand(MCOperand::CreateReg(0));
1024 OutStreamer.EmitInstruction(TmpInst);
1027 case ARM::LDMIA_RET: {
1028 // LDMIA_RET is just a normal LDMIA_UPD instruction that targets PC and as
1029 // such has additional code-gen properties and scheduling information.
1030 // To emit it, we just construct as normal and set the opcode to LDMIA_UPD.
1032 LowerARMMachineInstrToMCInst(MI, TmpInst, *this);
1033 TmpInst.setOpcode(ARM::LDMIA_UPD);
1034 OutStreamer.EmitInstruction(TmpInst);
1037 case ARM::t2ADDrSPi:
1038 case ARM::t2ADDrSPi12:
1039 case ARM::t2SUBrSPi:
1040 case ARM::t2SUBrSPi12:
1041 assert ((MI->getOperand(1).getReg() == ARM::SP) &&
1042 "Unexpected source register!");
1045 case ARM::t2MOVi32imm: assert(0 && "Should be lowered by thumb2it pass");
1046 case ARM::DBG_VALUE: {
1047 if (isVerbose() && OutStreamer.hasRawTextSupport()) {
1048 SmallString<128> TmpStr;
1049 raw_svector_ostream OS(TmpStr);
1050 PrintDebugValueComment(MI, OS);
1051 OutStreamer.EmitRawText(StringRef(OS.str()));
1057 TmpInst.setOpcode(ARM::tBL);
1058 TmpInst.addOperand(MCOperand::CreateExpr(MCSymbolRefExpr::Create(
1059 MI->getOperand(0).getMBB()->getSymbol(), OutContext)));
1060 OutStreamer.EmitInstruction(TmpInst);
1064 case ARM::tLEApcrel:
1065 case ARM::t2LEApcrel: {
1066 // FIXME: Need to also handle globals and externals
1068 TmpInst.setOpcode(MI->getOpcode() == ARM::t2LEApcrel ? ARM::t2ADR
1069 : (MI->getOpcode() == ARM::tLEApcrel ? ARM::tADR
1071 populateADROperands(TmpInst, MI->getOperand(0).getReg(),
1072 GetCPISymbol(MI->getOperand(1).getIndex()),
1073 MI->getOperand(2).getImm(), MI->getOperand(3).getReg(),
1075 OutStreamer.EmitInstruction(TmpInst);
1078 case ARM::LEApcrelJT:
1079 case ARM::tLEApcrelJT:
1080 case ARM::t2LEApcrelJT: {
1082 TmpInst.setOpcode(MI->getOpcode() == ARM::t2LEApcrelJT ? ARM::t2ADR
1083 : (MI->getOpcode() == ARM::tLEApcrelJT ? ARM::tADR
1085 populateADROperands(TmpInst, MI->getOperand(0).getReg(),
1086 GetARMJTIPICJumpTableLabel2(MI->getOperand(1).getIndex(),
1087 MI->getOperand(2).getImm()),
1088 MI->getOperand(3).getImm(), MI->getOperand(4).getReg(),
1090 OutStreamer.EmitInstruction(TmpInst);
1093 case ARM::MOVPCRX: {
1095 TmpInst.setOpcode(ARM::MOVr);
1096 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1097 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1098 // Add predicate operands.
1099 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1100 TmpInst.addOperand(MCOperand::CreateReg(0));
1101 // Add 's' bit operand (always reg0 for this)
1102 TmpInst.addOperand(MCOperand::CreateReg(0));
1103 OutStreamer.EmitInstruction(TmpInst);
1106 // Darwin call instructions are just normal call instructions with different
1107 // clobber semantics (they clobber R9).
1109 case ARM::BLr9_pred:
1111 case ARM::BLXr9_pred: {
1115 case ARM::BLr9: newOpc = ARM::BL; break;
1116 case ARM::BLr9_pred: newOpc = ARM::BL_pred; break;
1117 case ARM::BLXr9: newOpc = ARM::BLX; break;
1118 case ARM::BLXr9_pred: newOpc = ARM::BLX_pred; break;
1121 LowerARMMachineInstrToMCInst(MI, TmpInst, *this);
1122 TmpInst.setOpcode(newOpc);
1123 OutStreamer.EmitInstruction(TmpInst);
1126 case ARM::BXr9_CALL:
1127 case ARM::BX_CALL: {
1130 TmpInst.setOpcode(ARM::MOVr);
1131 TmpInst.addOperand(MCOperand::CreateReg(ARM::LR));
1132 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1133 // Add predicate operands.
1134 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1135 TmpInst.addOperand(MCOperand::CreateReg(0));
1136 // Add 's' bit operand (always reg0 for this)
1137 TmpInst.addOperand(MCOperand::CreateReg(0));
1138 OutStreamer.EmitInstruction(TmpInst);
1142 TmpInst.setOpcode(ARM::BX);
1143 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1144 OutStreamer.EmitInstruction(TmpInst);
1148 case ARM::BMOVPCRXr9_CALL:
1149 case ARM::BMOVPCRX_CALL: {
1152 TmpInst.setOpcode(ARM::MOVr);
1153 TmpInst.addOperand(MCOperand::CreateReg(ARM::LR));
1154 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1155 // Add predicate operands.
1156 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1157 TmpInst.addOperand(MCOperand::CreateReg(0));
1158 // Add 's' bit operand (always reg0 for this)
1159 TmpInst.addOperand(MCOperand::CreateReg(0));
1160 OutStreamer.EmitInstruction(TmpInst);
1164 TmpInst.setOpcode(ARM::MOVr);
1165 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1166 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1167 // Add predicate operands.
1168 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1169 TmpInst.addOperand(MCOperand::CreateReg(0));
1170 // Add 's' bit operand (always reg0 for this)
1171 TmpInst.addOperand(MCOperand::CreateReg(0));
1172 OutStreamer.EmitInstruction(TmpInst);
1176 case ARM::MOVi16_ga_pcrel:
1177 case ARM::t2MOVi16_ga_pcrel: {
1179 TmpInst.setOpcode(Opc == ARM::MOVi16_ga_pcrel? ARM::MOVi16 : ARM::t2MOVi16);
1180 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1182 unsigned TF = MI->getOperand(1).getTargetFlags();
1183 bool isPIC = TF == ARMII::MO_LO16_NONLAZY_PIC;
1184 const GlobalValue *GV = MI->getOperand(1).getGlobal();
1185 MCSymbol *GVSym = GetARMGVSymbol(GV);
1186 const MCExpr *GVSymExpr = MCSymbolRefExpr::Create(GVSym, OutContext);
1188 MCSymbol *LabelSym = getPICLabel(MAI->getPrivateGlobalPrefix(),
1189 getFunctionNumber(),
1190 MI->getOperand(2).getImm(), OutContext);
1191 const MCExpr *LabelSymExpr= MCSymbolRefExpr::Create(LabelSym, OutContext);
1192 unsigned PCAdj = (Opc == ARM::MOVi16_ga_pcrel) ? 8 : 4;
1193 const MCExpr *PCRelExpr =
1194 ARMMCExpr::CreateLower16(MCBinaryExpr::CreateSub(GVSymExpr,
1195 MCBinaryExpr::CreateAdd(LabelSymExpr,
1196 MCConstantExpr::Create(PCAdj, OutContext),
1197 OutContext), OutContext), OutContext);
1198 TmpInst.addOperand(MCOperand::CreateExpr(PCRelExpr));
1200 const MCExpr *RefExpr= ARMMCExpr::CreateLower16(GVSymExpr, OutContext);
1201 TmpInst.addOperand(MCOperand::CreateExpr(RefExpr));
1204 // Add predicate operands.
1205 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1206 TmpInst.addOperand(MCOperand::CreateReg(0));
1207 // Add 's' bit operand (always reg0 for this)
1208 TmpInst.addOperand(MCOperand::CreateReg(0));
1209 OutStreamer.EmitInstruction(TmpInst);
1212 case ARM::MOVTi16_ga_pcrel:
1213 case ARM::t2MOVTi16_ga_pcrel: {
1215 TmpInst.setOpcode(Opc == ARM::MOVTi16_ga_pcrel
1216 ? ARM::MOVTi16 : ARM::t2MOVTi16);
1217 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1218 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
1220 unsigned TF = MI->getOperand(2).getTargetFlags();
1221 bool isPIC = TF == ARMII::MO_HI16_NONLAZY_PIC;
1222 const GlobalValue *GV = MI->getOperand(2).getGlobal();
1223 MCSymbol *GVSym = GetARMGVSymbol(GV);
1224 const MCExpr *GVSymExpr = MCSymbolRefExpr::Create(GVSym, OutContext);
1226 MCSymbol *LabelSym = getPICLabel(MAI->getPrivateGlobalPrefix(),
1227 getFunctionNumber(),
1228 MI->getOperand(3).getImm(), OutContext);
1229 const MCExpr *LabelSymExpr= MCSymbolRefExpr::Create(LabelSym, OutContext);
1230 unsigned PCAdj = (Opc == ARM::MOVTi16_ga_pcrel) ? 8 : 4;
1231 const MCExpr *PCRelExpr =
1232 ARMMCExpr::CreateUpper16(MCBinaryExpr::CreateSub(GVSymExpr,
1233 MCBinaryExpr::CreateAdd(LabelSymExpr,
1234 MCConstantExpr::Create(PCAdj, OutContext),
1235 OutContext), OutContext), OutContext);
1236 TmpInst.addOperand(MCOperand::CreateExpr(PCRelExpr));
1238 const MCExpr *RefExpr= ARMMCExpr::CreateUpper16(GVSymExpr, OutContext);
1239 TmpInst.addOperand(MCOperand::CreateExpr(RefExpr));
1241 // Add predicate operands.
1242 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1243 TmpInst.addOperand(MCOperand::CreateReg(0));
1244 // Add 's' bit operand (always reg0 for this)
1245 TmpInst.addOperand(MCOperand::CreateReg(0));
1246 OutStreamer.EmitInstruction(TmpInst);
1249 case ARM::tPICADD: {
1250 // This is a pseudo op for a label + instruction sequence, which looks like:
1253 // This adds the address of LPC0 to r0.
1256 OutStreamer.EmitLabel(getPICLabel(MAI->getPrivateGlobalPrefix(),
1257 getFunctionNumber(), MI->getOperand(2).getImm(),
1260 // Form and emit the add.
1262 AddInst.setOpcode(ARM::tADDhirr);
1263 AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1264 AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1265 AddInst.addOperand(MCOperand::CreateReg(ARM::PC));
1266 // Add predicate operands.
1267 AddInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1268 AddInst.addOperand(MCOperand::CreateReg(0));
1269 OutStreamer.EmitInstruction(AddInst);
1273 // This is a pseudo op for a label + instruction sequence, which looks like:
1276 // This adds the address of LPC0 to r0.
1279 OutStreamer.EmitLabel(getPICLabel(MAI->getPrivateGlobalPrefix(),
1280 getFunctionNumber(), MI->getOperand(2).getImm(),
1283 // Form and emit the add.
1285 AddInst.setOpcode(ARM::ADDrr);
1286 AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1287 AddInst.addOperand(MCOperand::CreateReg(ARM::PC));
1288 AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
1289 // Add predicate operands.
1290 AddInst.addOperand(MCOperand::CreateImm(MI->getOperand(3).getImm()));
1291 AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(4).getReg()));
1292 // Add 's' bit operand (always reg0 for this)
1293 AddInst.addOperand(MCOperand::CreateReg(0));
1294 OutStreamer.EmitInstruction(AddInst);
1304 case ARM::PICLDRSH: {
1305 // This is a pseudo op for a label + instruction sequence, which looks like:
1308 // The LCP0 label is referenced by a constant pool entry in order to get
1309 // a PC-relative address at the ldr instruction.
1312 OutStreamer.EmitLabel(getPICLabel(MAI->getPrivateGlobalPrefix(),
1313 getFunctionNumber(), MI->getOperand(2).getImm(),
1316 // Form and emit the load
1318 switch (MI->getOpcode()) {
1320 llvm_unreachable("Unexpected opcode!");
1321 case ARM::PICSTR: Opcode = ARM::STRrs; break;
1322 case ARM::PICSTRB: Opcode = ARM::STRBrs; break;
1323 case ARM::PICSTRH: Opcode = ARM::STRH; break;
1324 case ARM::PICLDR: Opcode = ARM::LDRrs; break;
1325 case ARM::PICLDRB: Opcode = ARM::LDRBrs; break;
1326 case ARM::PICLDRH: Opcode = ARM::LDRH; break;
1327 case ARM::PICLDRSB: Opcode = ARM::LDRSB; break;
1328 case ARM::PICLDRSH: Opcode = ARM::LDRSH; break;
1331 LdStInst.setOpcode(Opcode);
1332 LdStInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1333 LdStInst.addOperand(MCOperand::CreateReg(ARM::PC));
1334 LdStInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
1335 LdStInst.addOperand(MCOperand::CreateImm(0));
1336 // Add predicate operands.
1337 LdStInst.addOperand(MCOperand::CreateImm(MI->getOperand(3).getImm()));
1338 LdStInst.addOperand(MCOperand::CreateReg(MI->getOperand(4).getReg()));
1339 OutStreamer.EmitInstruction(LdStInst);
1343 case ARM::CONSTPOOL_ENTRY: {
1344 /// CONSTPOOL_ENTRY - This instruction represents a floating constant pool
1345 /// in the function. The first operand is the ID# for this instruction, the
1346 /// second is the index into the MachineConstantPool that this is, the third
1347 /// is the size in bytes of this constant pool entry.
1348 unsigned LabelId = (unsigned)MI->getOperand(0).getImm();
1349 unsigned CPIdx = (unsigned)MI->getOperand(1).getIndex();
1352 OutStreamer.EmitLabel(GetCPISymbol(LabelId));
1354 const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPIdx];
1355 if (MCPE.isMachineConstantPoolEntry())
1356 EmitMachineConstantPoolValue(MCPE.Val.MachineCPVal);
1358 EmitGlobalConstant(MCPE.Val.ConstVal);
1362 case ARM::t2BR_JT: {
1363 // Lower and emit the instruction itself, then the jump table following it.
1365 TmpInst.setOpcode(ARM::tMOVgpr2gpr);
1366 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1367 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1368 // Add predicate operands.
1369 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1370 TmpInst.addOperand(MCOperand::CreateReg(0));
1371 OutStreamer.EmitInstruction(TmpInst);
1372 // Output the data for the jump table itself
1376 case ARM::t2TBB_JT: {
1377 // Lower and emit the instruction itself, then the jump table following it.
1380 TmpInst.setOpcode(ARM::t2TBB);
1381 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1382 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1383 // Add predicate operands.
1384 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1385 TmpInst.addOperand(MCOperand::CreateReg(0));
1386 OutStreamer.EmitInstruction(TmpInst);
1387 // Output the data for the jump table itself
1389 // Make sure the next instruction is 2-byte aligned.
1393 case ARM::t2TBH_JT: {
1394 // Lower and emit the instruction itself, then the jump table following it.
1397 TmpInst.setOpcode(ARM::t2TBH);
1398 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1399 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1400 // Add predicate operands.
1401 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1402 TmpInst.addOperand(MCOperand::CreateReg(0));
1403 OutStreamer.EmitInstruction(TmpInst);
1404 // Output the data for the jump table itself
1410 // Lower and emit the instruction itself, then the jump table following it.
1413 unsigned Opc = MI->getOpcode() == ARM::BR_JTr ?
1414 ARM::MOVr : ARM::tMOVgpr2gpr;
1415 TmpInst.setOpcode(Opc);
1416 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1417 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1418 // Add predicate operands.
1419 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1420 TmpInst.addOperand(MCOperand::CreateReg(0));
1421 // Add 's' bit operand (always reg0 for this)
1422 if (Opc == ARM::MOVr)
1423 TmpInst.addOperand(MCOperand::CreateReg(0));
1424 OutStreamer.EmitInstruction(TmpInst);
1426 // Make sure the Thumb jump table is 4-byte aligned.
1427 if (Opc == ARM::tMOVgpr2gpr)
1430 // Output the data for the jump table itself
1435 // Lower and emit the instruction itself, then the jump table following it.
1438 if (MI->getOperand(1).getReg() == 0) {
1440 TmpInst.setOpcode(ARM::LDRi12);
1441 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1442 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1443 TmpInst.addOperand(MCOperand::CreateImm(MI->getOperand(2).getImm()));
1445 TmpInst.setOpcode(ARM::LDRrs);
1446 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1447 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1448 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
1449 TmpInst.addOperand(MCOperand::CreateImm(0));
1451 // Add predicate operands.
1452 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1453 TmpInst.addOperand(MCOperand::CreateReg(0));
1454 OutStreamer.EmitInstruction(TmpInst);
1456 // Output the data for the jump table itself
1460 case ARM::BR_JTadd: {
1461 // Lower and emit the instruction itself, then the jump table following it.
1462 // add pc, target, idx
1464 TmpInst.setOpcode(ARM::ADDrr);
1465 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1466 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1467 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
1468 // Add predicate operands.
1469 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1470 TmpInst.addOperand(MCOperand::CreateReg(0));
1471 // Add 's' bit operand (always reg0 for this)
1472 TmpInst.addOperand(MCOperand::CreateReg(0));
1473 OutStreamer.EmitInstruction(TmpInst);
1475 // Output the data for the jump table itself
1480 // Non-Darwin binutils don't yet support the "trap" mnemonic.
1481 // FIXME: Remove this special case when they do.
1482 if (!Subtarget->isTargetDarwin()) {
1483 //.long 0xe7ffdefe @ trap
1484 uint32_t Val = 0xe7ffdefeUL;
1485 OutStreamer.AddComment("trap");
1486 OutStreamer.EmitIntValue(Val, 4);
1492 // Non-Darwin binutils don't yet support the "trap" mnemonic.
1493 // FIXME: Remove this special case when they do.
1494 if (!Subtarget->isTargetDarwin()) {
1495 //.short 57086 @ trap
1496 uint16_t Val = 0xdefe;
1497 OutStreamer.AddComment("trap");
1498 OutStreamer.EmitIntValue(Val, 2);
1503 case ARM::t2Int_eh_sjlj_setjmp:
1504 case ARM::t2Int_eh_sjlj_setjmp_nofp:
1505 case ARM::tInt_eh_sjlj_setjmp: {
1506 // Two incoming args: GPR:$src, GPR:$val
1509 // str $val, [$src, #4]
1514 unsigned SrcReg = MI->getOperand(0).getReg();
1515 unsigned ValReg = MI->getOperand(1).getReg();
1516 MCSymbol *Label = GetARMSJLJEHLabel();
1519 TmpInst.setOpcode(ARM::tMOVgpr2tgpr);
1520 TmpInst.addOperand(MCOperand::CreateReg(ValReg));
1521 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1523 TmpInst.addOperand(MCOperand::CreateReg(ARM::CPSR));
1524 OutStreamer.AddComment("eh_setjmp begin");
1525 OutStreamer.EmitInstruction(TmpInst);
1529 TmpInst.setOpcode(ARM::tADDi3);
1530 TmpInst.addOperand(MCOperand::CreateReg(ValReg));
1532 TmpInst.addOperand(MCOperand::CreateReg(ARM::CPSR));
1533 TmpInst.addOperand(MCOperand::CreateReg(ValReg));
1534 TmpInst.addOperand(MCOperand::CreateImm(7));
1536 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1537 TmpInst.addOperand(MCOperand::CreateReg(0));
1538 OutStreamer.EmitInstruction(TmpInst);
1542 TmpInst.setOpcode(ARM::tSTRi);
1543 TmpInst.addOperand(MCOperand::CreateReg(ValReg));
1544 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
1545 // The offset immediate is #4. The operand value is scaled by 4 for the
1546 // tSTR instruction.
1547 TmpInst.addOperand(MCOperand::CreateImm(1));
1549 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1550 TmpInst.addOperand(MCOperand::CreateReg(0));
1551 OutStreamer.EmitInstruction(TmpInst);
1555 TmpInst.setOpcode(ARM::tMOVi8);
1556 TmpInst.addOperand(MCOperand::CreateReg(ARM::R0));
1557 TmpInst.addOperand(MCOperand::CreateReg(ARM::CPSR));
1558 TmpInst.addOperand(MCOperand::CreateImm(0));
1560 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1561 TmpInst.addOperand(MCOperand::CreateReg(0));
1562 OutStreamer.EmitInstruction(TmpInst);
1565 const MCExpr *SymbolExpr = MCSymbolRefExpr::Create(Label, OutContext);
1567 TmpInst.setOpcode(ARM::tB);
1568 TmpInst.addOperand(MCOperand::CreateExpr(SymbolExpr));
1569 OutStreamer.EmitInstruction(TmpInst);
1573 TmpInst.setOpcode(ARM::tMOVi8);
1574 TmpInst.addOperand(MCOperand::CreateReg(ARM::R0));
1575 TmpInst.addOperand(MCOperand::CreateReg(ARM::CPSR));
1576 TmpInst.addOperand(MCOperand::CreateImm(1));
1578 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1579 TmpInst.addOperand(MCOperand::CreateReg(0));
1580 OutStreamer.AddComment("eh_setjmp end");
1581 OutStreamer.EmitInstruction(TmpInst);
1583 OutStreamer.EmitLabel(Label);
1587 case ARM::Int_eh_sjlj_setjmp_nofp:
1588 case ARM::Int_eh_sjlj_setjmp: {
1589 // Two incoming args: GPR:$src, GPR:$val
1591 // str $val, [$src, #+4]
1595 unsigned SrcReg = MI->getOperand(0).getReg();
1596 unsigned ValReg = MI->getOperand(1).getReg();
1600 TmpInst.setOpcode(ARM::ADDri);
1601 TmpInst.addOperand(MCOperand::CreateReg(ValReg));
1602 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1603 TmpInst.addOperand(MCOperand::CreateImm(8));
1605 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1606 TmpInst.addOperand(MCOperand::CreateReg(0));
1607 // 's' bit operand (always reg0 for this).
1608 TmpInst.addOperand(MCOperand::CreateReg(0));
1609 OutStreamer.AddComment("eh_setjmp begin");
1610 OutStreamer.EmitInstruction(TmpInst);
1614 TmpInst.setOpcode(ARM::STRi12);
1615 TmpInst.addOperand(MCOperand::CreateReg(ValReg));
1616 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
1617 TmpInst.addOperand(MCOperand::CreateImm(4));
1619 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1620 TmpInst.addOperand(MCOperand::CreateReg(0));
1621 OutStreamer.EmitInstruction(TmpInst);
1625 TmpInst.setOpcode(ARM::MOVi);
1626 TmpInst.addOperand(MCOperand::CreateReg(ARM::R0));
1627 TmpInst.addOperand(MCOperand::CreateImm(0));
1629 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1630 TmpInst.addOperand(MCOperand::CreateReg(0));
1631 // 's' bit operand (always reg0 for this).
1632 TmpInst.addOperand(MCOperand::CreateReg(0));
1633 OutStreamer.EmitInstruction(TmpInst);
1637 TmpInst.setOpcode(ARM::ADDri);
1638 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1639 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1640 TmpInst.addOperand(MCOperand::CreateImm(0));
1642 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1643 TmpInst.addOperand(MCOperand::CreateReg(0));
1644 // 's' bit operand (always reg0 for this).
1645 TmpInst.addOperand(MCOperand::CreateReg(0));
1646 OutStreamer.EmitInstruction(TmpInst);
1650 TmpInst.setOpcode(ARM::MOVi);
1651 TmpInst.addOperand(MCOperand::CreateReg(ARM::R0));
1652 TmpInst.addOperand(MCOperand::CreateImm(1));
1654 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1655 TmpInst.addOperand(MCOperand::CreateReg(0));
1656 // 's' bit operand (always reg0 for this).
1657 TmpInst.addOperand(MCOperand::CreateReg(0));
1658 OutStreamer.AddComment("eh_setjmp end");
1659 OutStreamer.EmitInstruction(TmpInst);
1663 case ARM::Int_eh_sjlj_longjmp: {
1664 // ldr sp, [$src, #8]
1665 // ldr $scratch, [$src, #4]
1668 unsigned SrcReg = MI->getOperand(0).getReg();
1669 unsigned ScratchReg = MI->getOperand(1).getReg();
1672 TmpInst.setOpcode(ARM::LDRi12);
1673 TmpInst.addOperand(MCOperand::CreateReg(ARM::SP));
1674 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
1675 TmpInst.addOperand(MCOperand::CreateImm(8));
1677 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1678 TmpInst.addOperand(MCOperand::CreateReg(0));
1679 OutStreamer.EmitInstruction(TmpInst);
1683 TmpInst.setOpcode(ARM::LDRi12);
1684 TmpInst.addOperand(MCOperand::CreateReg(ScratchReg));
1685 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
1686 TmpInst.addOperand(MCOperand::CreateImm(4));
1688 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1689 TmpInst.addOperand(MCOperand::CreateReg(0));
1690 OutStreamer.EmitInstruction(TmpInst);
1694 TmpInst.setOpcode(ARM::LDRi12);
1695 TmpInst.addOperand(MCOperand::CreateReg(ARM::R7));
1696 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
1697 TmpInst.addOperand(MCOperand::CreateImm(0));
1699 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1700 TmpInst.addOperand(MCOperand::CreateReg(0));
1701 OutStreamer.EmitInstruction(TmpInst);
1705 TmpInst.setOpcode(ARM::BX);
1706 TmpInst.addOperand(MCOperand::CreateReg(ScratchReg));
1708 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1709 TmpInst.addOperand(MCOperand::CreateReg(0));
1710 OutStreamer.EmitInstruction(TmpInst);
1714 case ARM::tInt_eh_sjlj_longjmp: {
1715 // ldr $scratch, [$src, #8]
1717 // ldr $scratch, [$src, #4]
1720 unsigned SrcReg = MI->getOperand(0).getReg();
1721 unsigned ScratchReg = MI->getOperand(1).getReg();
1724 TmpInst.setOpcode(ARM::tLDRi);
1725 TmpInst.addOperand(MCOperand::CreateReg(ScratchReg));
1726 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
1727 // The offset immediate is #8. The operand value is scaled by 4 for the
1728 // tLDR instruction.
1729 TmpInst.addOperand(MCOperand::CreateImm(2));
1731 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1732 TmpInst.addOperand(MCOperand::CreateReg(0));
1733 OutStreamer.EmitInstruction(TmpInst);
1737 TmpInst.setOpcode(ARM::tMOVtgpr2gpr);
1738 TmpInst.addOperand(MCOperand::CreateReg(ARM::SP));
1739 TmpInst.addOperand(MCOperand::CreateReg(ScratchReg));
1741 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1742 TmpInst.addOperand(MCOperand::CreateReg(0));
1743 OutStreamer.EmitInstruction(TmpInst);
1747 TmpInst.setOpcode(ARM::tLDRi);
1748 TmpInst.addOperand(MCOperand::CreateReg(ScratchReg));
1749 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
1750 TmpInst.addOperand(MCOperand::CreateImm(1));
1752 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1753 TmpInst.addOperand(MCOperand::CreateReg(0));
1754 OutStreamer.EmitInstruction(TmpInst);
1758 TmpInst.setOpcode(ARM::tLDRr);
1759 TmpInst.addOperand(MCOperand::CreateReg(ARM::R7));
1760 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
1761 TmpInst.addOperand(MCOperand::CreateReg(0));
1763 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1764 TmpInst.addOperand(MCOperand::CreateReg(0));
1765 OutStreamer.EmitInstruction(TmpInst);
1769 TmpInst.setOpcode(ARM::tBX_RET_vararg);
1770 TmpInst.addOperand(MCOperand::CreateReg(ScratchReg));
1772 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1773 TmpInst.addOperand(MCOperand::CreateReg(0));
1774 OutStreamer.EmitInstruction(TmpInst);
1778 // Tail jump branches are really just branch instructions with additional
1779 // code-gen attributes. Convert them to the canonical form here.
1781 case ARM::TAILJMPdND: {
1782 MCInst TmpInst, TmpInst2;
1783 // Lower the instruction as-is to get the operands properly converted.
1784 LowerARMMachineInstrToMCInst(MI, TmpInst2, *this);
1785 TmpInst.setOpcode(ARM::Bcc);
1786 TmpInst.addOperand(TmpInst2.getOperand(0));
1787 // Add predicate operands.
1788 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1789 TmpInst.addOperand(MCOperand::CreateReg(0));
1790 OutStreamer.AddComment("TAILCALL");
1791 OutStreamer.EmitInstruction(TmpInst);
1794 case ARM::tTAILJMPd:
1795 case ARM::tTAILJMPdND: {
1796 MCInst TmpInst, TmpInst2;
1797 LowerARMMachineInstrToMCInst(MI, TmpInst2, *this);
1798 TmpInst.setOpcode(ARM::tB);
1799 TmpInst.addOperand(TmpInst2.getOperand(0));
1800 OutStreamer.AddComment("TAILCALL");
1801 OutStreamer.EmitInstruction(TmpInst);
1804 case ARM::TAILJMPrND:
1805 case ARM::tTAILJMPrND:
1807 case ARM::tTAILJMPr: {
1808 unsigned newOpc = (Opc == ARM::TAILJMPr || Opc == ARM::TAILJMPrND)
1809 ? ARM::BX : ARM::tBX;
1811 TmpInst.setOpcode(newOpc);
1812 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1814 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1815 TmpInst.addOperand(MCOperand::CreateReg(0));
1816 OutStreamer.AddComment("TAILCALL");
1817 OutStreamer.EmitInstruction(TmpInst);
1821 // These are the pseudos created to comply with stricter operand restrictions
1822 // on ARMv5. Lower them now to "normal" instructions, since all the
1823 // restrictions are already satisfied.
1825 EmitPatchedInstruction(MI, ARM::MUL);
1828 EmitPatchedInstruction(MI, ARM::MLA);
1831 EmitPatchedInstruction(MI, ARM::SMULL);
1834 EmitPatchedInstruction(MI, ARM::UMULL);
1837 EmitPatchedInstruction(MI, ARM::SMLAL);
1840 EmitPatchedInstruction(MI, ARM::UMLAL);
1843 EmitPatchedInstruction(MI, ARM::UMAAL);
1848 LowerARMMachineInstrToMCInst(MI, TmpInst, *this);
1850 // Emit unwinding stuff for frame-related instructions
1851 if (EnableARMEHABI && MI->getFlag(MachineInstr::FrameSetup))
1852 EmitUnwindingInstruction(MI);
1854 OutStreamer.EmitInstruction(TmpInst);
1857 //===----------------------------------------------------------------------===//
1858 // Target Registry Stuff
1859 //===----------------------------------------------------------------------===//
1861 static MCInstPrinter *createARMMCInstPrinter(const Target &T,
1863 unsigned SyntaxVariant,
1864 const MCAsmInfo &MAI) {
1865 if (SyntaxVariant == 0)
1866 return new ARMInstPrinter(TM, MAI);
1870 // Force static initialization.
1871 extern "C" void LLVMInitializeARMAsmPrinter() {
1872 RegisterAsmPrinter<ARMAsmPrinter> X(TheARMTarget);
1873 RegisterAsmPrinter<ARMAsmPrinter> Y(TheThumbTarget);
1875 TargetRegistry::RegisterMCInstPrinter(TheARMTarget, createARMMCInstPrinter);
1876 TargetRegistry::RegisterMCInstPrinter(TheThumbTarget, createARMMCInstPrinter);