1 //===-- ARMAsmBackend.cpp - ARM Assembler Backend -------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #include "llvm/Target/TargetAsmBackend.h"
12 #include "ARMFixupKinds.h"
13 #include "llvm/ADT/Twine.h"
14 #include "llvm/MC/ELFObjectWriter.h"
15 #include "llvm/MC/MCAssembler.h"
16 #include "llvm/MC/MCExpr.h"
17 #include "llvm/MC/MCObjectFormat.h"
18 #include "llvm/MC/MCObjectWriter.h"
19 #include "llvm/MC/MCSectionELF.h"
20 #include "llvm/MC/MCSectionMachO.h"
21 #include "llvm/MC/MachObjectWriter.h"
22 #include "llvm/Support/ELF.h"
23 #include "llvm/Support/MachO.h"
24 #include "llvm/Support/ErrorHandling.h"
25 #include "llvm/Support/raw_ostream.h"
26 #include "llvm/Target/TargetRegistry.h"
27 #include "llvm/Target/TargetAsmBackend.h"
31 class ARMAsmBackend : public TargetAsmBackend {
33 ARMAsmBackend(const Target &T)
34 : TargetAsmBackend(T) {
37 bool MayNeedRelaxation(const MCInst &Inst) const;
39 void RelaxInstruction(const MCInst &Inst, MCInst &Res) const;
41 bool WriteNopData(uint64_t Count, MCObjectWriter *OW) const;
43 unsigned getPointerSize() const {
48 bool ARMAsmBackend::MayNeedRelaxation(const MCInst &Inst) const {
49 // FIXME: Thumb targets, different move constant targets..
53 void ARMAsmBackend::RelaxInstruction(const MCInst &Inst, MCInst &Res) const {
54 assert(0 && "ARMAsmBackend::RelaxInstruction() unimplemented");
58 bool ARMAsmBackend::WriteNopData(uint64_t Count, MCObjectWriter *OW) const {
59 // if ((Count % 4) != 0) {
60 // // Fixme: % 2 for Thumb?
63 // FIXME: Zero fill for now. That's not right, but at least will get the
64 // section size right.
65 for (uint64_t i = 0; i != Count; ++i)
69 } // end anonymous namespace
72 // FIXME: This should be in a separate file.
73 // ELF is an ELF of course...
74 class ELFARMAsmBackend : public ARMAsmBackend {
75 MCELFObjectFormat Format;
78 Triple::OSType OSType;
79 ELFARMAsmBackend(const Target &T, Triple::OSType _OSType)
80 : ARMAsmBackend(T), OSType(_OSType) {
81 HasScatteredSymbols = true;
84 virtual const MCObjectFormat &getObjectFormat() const {
88 void ApplyFixup(const MCFixup &Fixup, MCDataFragment &DF,
89 uint64_t Value) const;
91 bool isVirtualSection(const MCSection &Section) const {
92 const MCSectionELF &SE = static_cast<const MCSectionELF&>(Section);
93 return SE.getType() == MCSectionELF::SHT_NOBITS;
96 MCObjectWriter *createObjectWriter(raw_ostream &OS) const {
97 return new ELFObjectWriter(OS, /*Is64Bit=*/false,
99 /*IsLittleEndian=*/true,
100 /*HasRelocationAddend=*/false);
104 // Fixme: can we raise this to share code between Darwin and ELF?
105 void ELFARMAsmBackend::ApplyFixup(const MCFixup &Fixup, MCDataFragment &DF,
106 uint64_t Value) const {
107 assert(0 && "ELFARMAsmBackend::ApplyFixup() unimplemented");
110 // FIXME: This should be in a separate file.
111 class DarwinARMAsmBackend : public ARMAsmBackend {
112 MCMachOObjectFormat Format;
115 DarwinARMAsmBackend(const Target &T)
117 HasScatteredSymbols = true;
120 virtual const MCObjectFormat &getObjectFormat() const {
124 void ApplyFixup(const MCFixup &Fixup, MCDataFragment &DF,
125 uint64_t Value) const;
127 bool isVirtualSection(const MCSection &Section) const {
128 const MCSectionMachO &SMO = static_cast<const MCSectionMachO&>(Section);
129 return (SMO.getType() == MCSectionMachO::S_ZEROFILL ||
130 SMO.getType() == MCSectionMachO::S_GB_ZEROFILL ||
131 SMO.getType() == MCSectionMachO::S_THREAD_LOCAL_ZEROFILL);
134 MCObjectWriter *createObjectWriter(raw_ostream &OS) const {
135 // FIXME: Subtarget info should be derived. Force v7 for now.
136 return new MachObjectWriter(OS, /*Is64Bit=*/false, MachO::CPUTypeARM,
137 MachO::CPUSubType_ARM_V7);
140 virtual bool doesSectionRequireSymbols(const MCSection &Section) const {
145 static unsigned getFixupKindNumBytes(unsigned Kind) {
147 default: llvm_unreachable("Unknown fixup kind!");
148 case FK_Data_4: return 4;
149 case ARM::fixup_arm_pcrel_12: return 2;
150 case ARM::fixup_arm_vfp_pcrel_12: return 1;
151 case ARM::fixup_arm_branch: return 3;
155 static unsigned adjustFixupValue(unsigned Kind, uint64_t Value) {
158 llvm_unreachable("Unknown fixup kind!");
161 case ARM::fixup_arm_pcrel_12:
162 // ARM PC-relative values are offset by 8.
164 case ARM::fixup_arm_branch:
165 case ARM::fixup_arm_vfp_pcrel_12:
166 // These values don't encode the low two bits since they're always zero.
167 // Offset by 8 just as above.
168 return (Value - 8) >> 2;
172 void DarwinARMAsmBackend::ApplyFixup(const MCFixup &Fixup, MCDataFragment &DF,
173 uint64_t Value) const {
174 unsigned NumBytes = getFixupKindNumBytes(Fixup.getKind());
175 Value = adjustFixupValue(Fixup.getKind(), Value);
177 assert(Fixup.getOffset() + NumBytes <= DF.getContents().size() &&
178 "Invalid fixup offset!");
179 // For each byte of the fragment that the fixup touches, mask in the
180 // bits from the fixup value.
181 for (unsigned i = 0; i != NumBytes; ++i)
182 DF.getContents()[Fixup.getOffset() + i] |= uint8_t(Value >> (i * 8));
184 } // end anonymous namespace
186 TargetAsmBackend *llvm::createARMAsmBackend(const Target &T,
187 const std::string &TT) {
188 switch (Triple(TT).getOS()) {
190 return new DarwinARMAsmBackend(T);
191 case Triple::MinGW32:
194 assert(0 && "Windows not supported on ARM");
196 return new ELFARMAsmBackend(T, Triple(TT).getOS());