lib/Target/ARM/ARM.td

   1 //===-- ARM.td - Describe the ARM Target Machine -----------*- tablegen -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 //
  11 //===----------------------------------------------------------------------===//
  12
  13 //===----------------------------------------------------------------------===//
  14 // Target-independent interfaces which we are implementing
  15 //===----------------------------------------------------------------------===//
  16
  17 include "llvm/Target/Target.td"
  18
  19 //===----------------------------------------------------------------------===//
  20 // ARM Subtarget state.
  21 //
  22
  23 def ModeThumb  : SubtargetFeature<"thumb-mode", "InThumbMode", "true",
  24                                   "Thumb mode">;
  25
  26 //===----------------------------------------------------------------------===//
  27 // ARM Subtarget features.
  28 //
  29
  30 def FeatureVFP2 : SubtargetFeature<"vfp2", "HasVFPv2", "true",
  31                                    "Enable VFP2 instructions">;
  32 def FeatureVFP3 : SubtargetFeature<"vfp3", "HasVFPv3", "true",
  33                                    "Enable VFP3 instructions",
  34                                    [FeatureVFP2]>;
  35 def FeatureNEON : SubtargetFeature<"neon", "HasNEON", "true",
  36                                    "Enable NEON instructions",
  37                                    [FeatureVFP3]>;
  38 def FeatureThumb2 : SubtargetFeature<"thumb2", "HasThumb2", "true",
  39                                      "Enable Thumb2 instructions">;
  40 def FeatureNoARM  : SubtargetFeature<"noarm", "NoARM", "true",
  41                                      "Does not support ARM mode execution",
  42                                      [ModeThumb]>;
  43 def FeatureFP16   : SubtargetFeature<"fp16", "HasFP16", "true",
  44                                      "Enable half-precision floating point">;
  45 def FeatureVFP4   : SubtargetFeature<"vfp4", "HasVFPv4", "true",
  46                                      "Enable VFP4 instructions",
  47                                      [FeatureVFP3, FeatureFP16]>;
  48 def FeatureFPARMv8 : SubtargetFeature<"fp-armv8", "HasFPARMv8",
  49                                    "true", "Enable ARMv8 FP",
  50                                    [FeatureVFP4]>;
  51 def FeatureD16    : SubtargetFeature<"d16", "HasD16", "true",
  52                                      "Restrict VFP3 to 16 double registers">;
  53 def FeatureHWDiv  : SubtargetFeature<"hwdiv", "HasHardwareDivide", "true",
  54                                      "Enable divide instructions">;
  55 def FeatureHWDivARM  : SubtargetFeature<"hwdiv-arm",
  56                                         "HasHardwareDivideInARM", "true",
  57                                       "Enable divide instructions in ARM mode">;
  58 def FeatureT2XtPk : SubtargetFeature<"t2xtpk", "HasT2ExtractPack", "true",
  59                                  "Enable Thumb2 extract and pack instructions">;
  60 def FeatureDB     : SubtargetFeature<"db", "HasDataBarrier", "true",
  61                                    "Has data barrier (dmb / dsb) instructions">;
  62 def FeatureSlowFPBrcc : SubtargetFeature<"slow-fp-brcc", "SlowFPBrcc", "true",
  63                                          "FP compare + branch is slow">;
  64 def FeatureVFPOnlySP : SubtargetFeature<"fp-only-sp", "FPOnlySP", "true",
  65                           "Floating point unit supports single precision only">;
  66 def FeaturePerfMon : SubtargetFeature<"perfmon", "HasPerfMon", "true",
  67                            "Enable support for Performance Monitor extensions">;
  68 def FeatureTrustZone : SubtargetFeature<"trustzone", "HasTrustZone", "true",
  69                           "Enable support for TrustZone security extensions">;
  70 def FeatureCrypto : SubtargetFeature<"crypto", "HasCrypto", "true",
  71                           "Enable support for Cryptography extensions",
  72                           [FeatureNEON]>;
  73
  74 // Some processors have FP multiply-accumulate instructions that don't
  75 // play nicely with other VFP / NEON instructions, and it's generally better
  76 // to just not use them.
  77 def FeatureHasSlowFPVMLx : SubtargetFeature<"slowfpvmlx", "SlowFPVMLx", "true",
  78                                          "Disable VFP / NEON MAC instructions">;
  79
  80 // Cortex-A8 / A9 Advanced SIMD has multiplier accumulator forwarding.
  81 def FeatureVMLxForwarding : SubtargetFeature<"vmlx-forwarding",
  82                                        "HasVMLxForwarding", "true",
  83                                        "Has multiplier accumulator forwarding">;
  84
  85 // Some processors benefit from using NEON instructions for scalar
  86 // single-precision FP operations.
  87 def FeatureNEONForFP : SubtargetFeature<"neonfp", "UseNEONForSinglePrecisionFP",
  88                                         "true",
  89                                         "Use NEON for single precision FP">;
  90
  91 // Disable 32-bit to 16-bit narrowing for experimentation.
  92 def FeaturePref32BitThumb : SubtargetFeature<"32bit", "Pref32BitThumb", "true",
  93                                              "Prefer 32-bit Thumb instrs">;
  94
  95 /// Some instructions update CPSR partially, which can add false dependency for
  96 /// out-of-order implementation, e.g. Cortex-A9, unless each individual bit is
  97 /// mapped to a separate physical register. Avoid partial CPSR update for these
  98 /// processors.
  99 def FeatureAvoidPartialCPSR : SubtargetFeature<"avoid-partial-cpsr",
 100                                                "AvoidCPSRPartialUpdate", "true",
 101                                  "Avoid CPSR partial update for OOO execution">;
 102
 103 def FeatureAvoidMOVsShOp : SubtargetFeature<"avoid-movs-shop",
 104                                             "AvoidMOVsShifterOperand", "true",
 105                                 "Avoid movs instructions with shifter operand">;
 106
 107 // Some processors perform return stack prediction. CodeGen should avoid issue
 108 // "normal" call instructions to callees which do not return.
 109 def FeatureHasRAS : SubtargetFeature<"ras", "HasRAS", "true",
 110                                      "Has return address stack">;
 111
 112 /// Some M architectures don't have the DSP extension (v7E-M vs. v7M)
 113 def FeatureDSPThumb2 : SubtargetFeature<"t2dsp", "Thumb2DSP", "true",
 114                                  "Supports v7 DSP instructions in Thumb2">;
 115
 116 // Multiprocessing extension.
 117 def FeatureMP : SubtargetFeature<"mp", "HasMPExtension", "true",
 118                                  "Supports Multiprocessing extension">;
 119
 120 // M-series ISA?
 121 def FeatureMClass : SubtargetFeature<"mclass", "IsMClass", "true",
 122                                      "Is microcontroller profile ('M' series)">;
 123
 124 // Special TRAP encoding for NaCl, which looks like a TRAP in Thumb too.
 125 // See ARMInstrInfo.td for details.
 126 def FeatureNaClTrap : SubtargetFeature<"nacl-trap", "UseNaClTrap", "true",
 127                                        "NaCl trap">;
 128
 129 // ARM ISAs.
 130 def HasV4TOps   : SubtargetFeature<"v4t", "HasV4TOps", "true",
 131                                    "Support ARM v4T instructions">;
 132 def HasV5TOps   : SubtargetFeature<"v5t", "HasV5TOps", "true",
 133                                    "Support ARM v5T instructions",
 134                                    [HasV4TOps]>;
 135 def HasV5TEOps  : SubtargetFeature<"v5te", "HasV5TEOps", "true",
 136                              "Support ARM v5TE, v5TEj, and v5TExp instructions",
 137                                    [HasV5TOps]>;
 138 def HasV6Ops    : SubtargetFeature<"v6", "HasV6Ops", "true",
 139                                    "Support ARM v6 instructions",
 140                                    [HasV5TEOps]>;
 141 def HasV6T2Ops  : SubtargetFeature<"v6t2", "HasV6T2Ops", "true",
 142                                    "Support ARM v6t2 instructions",
 143                                    [HasV6Ops, FeatureThumb2]>;
 144 def HasV7Ops    : SubtargetFeature<"v7", "HasV7Ops", "true",
 145                                    "Support ARM v7 instructions",
 146                                    [HasV6T2Ops, FeaturePerfMon]>;
 147 def HasV8Ops    : SubtargetFeature<"v8", "HasV8Ops", "true",
 148                                    "Support ARM v8 instructions",
 149                                    [HasV7Ops]>;
 150
 151 //===----------------------------------------------------------------------===//
 152 // ARM Processors supported.
 153 //
 154
 155 include "ARMSchedule.td"
 156
 157 // ARM processor families.
 158 def ProcA5      : SubtargetFeature<"a5", "ARMProcFamily", "CortexA5",
 159                                    "Cortex-A5 ARM processors",
 160                                    [FeatureSlowFPBrcc, FeatureHasSlowFPVMLx,
 161                                     FeatureVMLxForwarding, FeatureT2XtPk,
 162                                     FeatureTrustZone]>;
 163 def ProcA8      : SubtargetFeature<"a8", "ARMProcFamily", "CortexA8",
 164                                    "Cortex-A8 ARM processors",
 165                                    [FeatureSlowFPBrcc, FeatureHasSlowFPVMLx,
 166                                     FeatureVMLxForwarding, FeatureT2XtPk,
 167                                     FeatureTrustZone]>;
 168 def ProcA9      : SubtargetFeature<"a9", "ARMProcFamily", "CortexA9",
 169                                    "Cortex-A9 ARM processors",
 170                                    [FeatureVMLxForwarding,
 171                                     FeatureT2XtPk, FeatureFP16,
 172                                     FeatureAvoidPartialCPSR,
 173                                     FeatureTrustZone]>;
 174 def ProcSwift   : SubtargetFeature<"swift", "ARMProcFamily", "Swift",
 175                                    "Swift ARM processors",
 176                                    [FeatureNEONForFP, FeatureT2XtPk,
 177                                     FeatureVFP4, FeatureMP, FeatureHWDiv,
 178                                     FeatureHWDivARM, FeatureAvoidPartialCPSR,
 179                                     FeatureAvoidMOVsShOp,
 180                                     FeatureHasSlowFPVMLx, FeatureTrustZone]>;
 181
 182 // FIXME: It has not been determined if A15 has these features.
 183 def ProcA15      : SubtargetFeature<"a15", "ARMProcFamily", "CortexA15",
 184                                    "Cortex-A15 ARM processors",
 185                                    [FeatureT2XtPk, FeatureVFP4,
 186                                     FeatureAvoidPartialCPSR,
 187                                     FeatureTrustZone]>;
 188 def ProcR5      : SubtargetFeature<"r5", "ARMProcFamily", "CortexR5",
 189                                    "Cortex-R5 ARM processors",
 190                                    [FeatureSlowFPBrcc,
 191                                     FeatureHWDiv, FeatureHWDivARM,
 192                                     FeatureHasSlowFPVMLx,
 193                                     FeatureAvoidPartialCPSR,
 194                                     FeatureT2XtPk]>;
 195
 196 class ProcNoItin<string Name, list<SubtargetFeature> Features>
 197  : Processor<Name, NoItineraries, Features>;
 198
 199 // V4 Processors.
 200 def : ProcNoItin<"generic",         []>;
 201 def : ProcNoItin<"arm8",            []>;
 202 def : ProcNoItin<"arm810",          []>;
 203 def : ProcNoItin<"strongarm",       []>;
 204 def : ProcNoItin<"strongarm110",    []>;
 205 def : ProcNoItin<"strongarm1100",   []>;
 206 def : ProcNoItin<"strongarm1110",   []>;
 207
 208 // V4T Processors.
 209 def : ProcNoItin<"arm7tdmi",        [HasV4TOps]>;
 210 def : ProcNoItin<"arm7tdmi-s",      [HasV4TOps]>;
 211 def : ProcNoItin<"arm710t",         [HasV4TOps]>;
 212 def : ProcNoItin<"arm720t",         [HasV4TOps]>;
 213 def : ProcNoItin<"arm9",            [HasV4TOps]>;
 214 def : ProcNoItin<"arm9tdmi",        [HasV4TOps]>;
 215 def : ProcNoItin<"arm920",          [HasV4TOps]>;
 216 def : ProcNoItin<"arm920t",         [HasV4TOps]>;
 217 def : ProcNoItin<"arm922t",         [HasV4TOps]>;
 218 def : ProcNoItin<"arm940t",         [HasV4TOps]>;
 219 def : ProcNoItin<"ep9312",          [HasV4TOps]>;
 220
 221 // V5T Processors.
 222 def : ProcNoItin<"arm10tdmi",       [HasV5TOps]>;
 223 def : ProcNoItin<"arm1020t",        [HasV5TOps]>;
 224
 225 // V5TE Processors.
 226 def : ProcNoItin<"arm9e",           [HasV5TEOps]>;
 227 def : ProcNoItin<"arm926ej-s",      [HasV5TEOps]>;
 228 def : ProcNoItin<"arm946e-s",       [HasV5TEOps]>;
 229 def : ProcNoItin<"arm966e-s",       [HasV5TEOps]>;
 230 def : ProcNoItin<"arm968e-s",       [HasV5TEOps]>;
 231 def : ProcNoItin<"arm10e",          [HasV5TEOps]>;
 232 def : ProcNoItin<"arm1020e",        [HasV5TEOps]>;
 233 def : ProcNoItin<"arm1022e",        [HasV5TEOps]>;
 234 def : ProcNoItin<"xscale",          [HasV5TEOps]>;
 235 def : ProcNoItin<"iwmmxt",          [HasV5TEOps]>;
 236
 237 // V6 Processors.
 238 def : Processor<"arm1136j-s",       ARMV6Itineraries, [HasV6Ops]>;
 239 def : Processor<"arm1136jf-s",      ARMV6Itineraries, [HasV6Ops, FeatureVFP2,
 240                                                        FeatureHasSlowFPVMLx]>;
 241 def : Processor<"arm1176jz-s",      ARMV6Itineraries, [HasV6Ops]>;
 242 def : Processor<"arm1176jzf-s",     ARMV6Itineraries, [HasV6Ops, FeatureVFP2,
 243                                                        FeatureHasSlowFPVMLx]>;
 244 def : Processor<"mpcorenovfp",      ARMV6Itineraries, [HasV6Ops]>;
 245 def : Processor<"mpcore",           ARMV6Itineraries, [HasV6Ops, FeatureVFP2,
 246                                                        FeatureHasSlowFPVMLx]>;
 247
 248 // V6M Processors.
 249 def : Processor<"cortex-m0",        ARMV6Itineraries, [HasV6Ops, FeatureNoARM,
 250                                                        FeatureDB, FeatureMClass]>;
 251
 252 // V6T2 Processors.
 253 def : Processor<"arm1156t2-s",      ARMV6Itineraries, [HasV6T2Ops,
 254                                                        FeatureDSPThumb2]>;
 255 def : Processor<"arm1156t2f-s",     ARMV6Itineraries, [HasV6T2Ops, FeatureVFP2,
 256                                                        FeatureHasSlowFPVMLx,
 257                                                        FeatureDSPThumb2]>;
 258
 259 // V7a Processors.
 260 // FIXME: A5 has currently the same Schedule model as A8
 261 def : ProcessorModel<"cortex-a5",   CortexA8Model,
 262                                     [ProcA5, HasV7Ops, FeatureNEON, FeatureDB,
 263                                      FeatureVFP4, FeatureDSPThumb2,
 264                                      FeatureHasRAS]>;
 265 def : ProcessorModel<"cortex-a8",   CortexA8Model,
 266                                     [ProcA8, HasV7Ops, FeatureNEON, FeatureDB,
 267                                      FeatureDSPThumb2, FeatureHasRAS]>;
 268 def : ProcessorModel<"cortex-a9",   CortexA9Model,
 269                                     [ProcA9, HasV7Ops, FeatureNEON, FeatureDB,
 270                                      FeatureDSPThumb2, FeatureHasRAS]>;
 271 def : ProcessorModel<"cortex-a9-mp", CortexA9Model,
 272                                     [ProcA9, HasV7Ops, FeatureNEON, FeatureDB,
 273                                      FeatureDSPThumb2, FeatureMP,
 274                                      FeatureHasRAS]>;
 275 // FIXME: A15 has currently the same ProcessorModel as A9.
 276 def : ProcessorModel<"cortex-a15",   CortexA9Model,
 277                                     [ProcA15, HasV7Ops, FeatureNEON, FeatureDB,
 278                                      FeatureDSPThumb2, FeatureHasRAS]>;
 279 // FIXME: R5 has currently the same ProcessorModel as A8.
 280 def : ProcessorModel<"cortex-r5",   CortexA8Model,
 281                                     [ProcR5, HasV7Ops, FeatureDB,
 282                                      FeatureVFP3, FeatureDSPThumb2,
 283                                      FeatureHasRAS]>;
 284
 285 // V7M Processors.
 286 def : ProcNoItin<"cortex-m3",       [HasV7Ops,
 287                                      FeatureThumb2, FeatureNoARM, FeatureDB,
 288                                      FeatureHWDiv, FeatureMClass]>;
 289
 290 // V7EM Processors.
 291 def : ProcNoItin<"cortex-m4",       [HasV7Ops,
 292                                      FeatureThumb2, FeatureNoARM, FeatureDB,
 293                                      FeatureHWDiv, FeatureDSPThumb2,
 294                                      FeatureT2XtPk, FeatureVFP4,
 295                                      FeatureVFPOnlySP, FeatureMClass]>;
 296
 297 // Swift uArch Processors.
 298 def : ProcessorModel<"swift",       SwiftModel,
 299                                     [ProcSwift, HasV7Ops, FeatureNEON,
 300                                      FeatureDB, FeatureDSPThumb2,
 301                                      FeatureHasRAS]>;
 302
 303 // V8 Processors
 304 def : ProcNoItin<"cortex-a53",      [HasV8Ops]>;
 305
 306 //===----------------------------------------------------------------------===//
 307 // Register File Description
 308 //===----------------------------------------------------------------------===//
 309
 310 include "ARMRegisterInfo.td"
 311
 312 include "ARMCallingConv.td"
 313
 314 //===----------------------------------------------------------------------===//
 315 // Instruction Descriptions
 316 //===----------------------------------------------------------------------===//
 317
 318 include "ARMInstrInfo.td"
 319
 320 def ARMInstrInfo : InstrInfo;
 321
 322
 323 //===----------------------------------------------------------------------===//
 324 // Assembly printer
 325 //===----------------------------------------------------------------------===//
 326 // ARM Uses the MC printer for asm output, so make sure the TableGen
 327 // AsmWriter bits get associated with the correct class.
 328 def ARMAsmWriter : AsmWriter {
 329   string AsmWriterClassName  = "InstPrinter";
 330   bit isMCAsmWriter = 1;
 331 }
 332
 333 //===----------------------------------------------------------------------===//
 334 // Declare the target which we are implementing
 335 //===----------------------------------------------------------------------===//
 336
 337 def ARM : Target {
 338   // Pull in Instruction Info:
 339   let InstructionSet = ARMInstrInfo;
 340
 341   let AssemblyWriters = [ARMAsmWriter];
 342 }