lib/Target/ARM/ARM.td

   1 //===- ARM.td - Describe the ARM Target Machine ------------*- tablegen -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 //
  11 //===----------------------------------------------------------------------===//
  12
  13 //===----------------------------------------------------------------------===//
  14 // Target-independent interfaces which we are implementing
  15 //===----------------------------------------------------------------------===//
  16
  17 include "llvm/Target/Target.td"
  18
  19 //===----------------------------------------------------------------------===//
  20 // ARM Subtarget features.
  21 //
  22
  23 def FeatureVFP2 : SubtargetFeature<"vfp2", "ARMFPUType", "VFPv2",
  24                                    "Enable VFP2 instructions">;
  25 def FeatureVFP3 : SubtargetFeature<"vfp3", "ARMFPUType", "VFPv3",
  26                                    "Enable VFP3 instructions">;
  27 def FeatureNEON : SubtargetFeature<"neon", "ARMFPUType", "NEON",
  28                                    "Enable NEON instructions">;
  29 def FeatureThumb2 : SubtargetFeature<"thumb2", "ThumbMode", "Thumb2",
  30                                      "Enable Thumb2 instructions">;
  31 def FeatureNoARM  : SubtargetFeature<"noarm", "NoARM", "true",
  32                                      "Does not support ARM mode execution">;
  33 def FeatureFP16   : SubtargetFeature<"fp16", "HasFP16", "true",
  34                                      "Enable half-precision floating point">;
  35 def FeatureHWDiv  : SubtargetFeature<"hwdiv", "HasHardwareDivide", "true",
  36                                      "Enable divide instructions">;
  37 def FeatureT2XtPk : SubtargetFeature<"t2xtpk", "HasT2ExtractPack", "true",
  38                                  "Enable Thumb2 extract and pack instructions">;
  39 def FeatureDB     : SubtargetFeature<"db", "HasDataBarrier", "true",
  40                                    "Has data barrier (dmb / dsb) instructions">;
  41 def FeatureSlowFPBrcc : SubtargetFeature<"slow-fp-brcc", "SlowFPBrcc", "true",
  42                                          "FP compare + branch is slow">;
  43 def FeatureVFPOnlySP : SubtargetFeature<"fp-only-sp", "FPOnlySP", "true",
  44                           "Floating point unit supports single precision only">;
  45
  46 // Some processors have multiply-accumulate instructions that don't
  47 // play nicely with other VFP instructions, and it's generally better
  48 // to just not use them.
  49 // FIXME: Currently, this is only flagged for Cortex-A8. It may be true for
  50 // others as well. We should do more benchmarking and confirm one way or
  51 // the other.
  52 def FeatureHasSlowVMLx : SubtargetFeature<"vmlx", "SlowVMLx", "true",
  53                                           "Disable VFP MAC instructions">;
  54 // Some processors benefit from using NEON instructions for scalar
  55 // single-precision FP operations.
  56 def FeatureNEONForFP : SubtargetFeature<"neonfp", "UseNEONForSinglePrecisionFP",
  57                                         "true",
  58                                         "Use NEON for single precision FP">;
  59
  60 // Disable 32-bit to 16-bit narrowing for experimentation.
  61 def FeaturePref32BitThumb : SubtargetFeature<"32bit", "Pref32BitThumb", "true",
  62                                              "Prefer 32-bit Thumb instrs">;
  63
  64
  65 // ARM architectures.
  66 def ArchV4T     : SubtargetFeature<"v4t", "ARMArchVersion", "V4T",
  67                                    "ARM v4T">;
  68 def ArchV5T     : SubtargetFeature<"v5t", "ARMArchVersion", "V5T",
  69                                    "ARM v5T">;
  70 def ArchV5TE    : SubtargetFeature<"v5te", "ARMArchVersion", "V5TE",
  71                                    "ARM v5TE, v5TEj, v5TExp">;
  72 def ArchV6      : SubtargetFeature<"v6", "ARMArchVersion", "V6",
  73                                    "ARM v6">;
  74 def ArchV6M     : SubtargetFeature<"v6m", "ARMArchVersion", "V6M",
  75                                    "ARM v6m",
  76                                    [FeatureNoARM, FeatureDB]>;
  77 def ArchV6T2    : SubtargetFeature<"v6t2", "ARMArchVersion", "V6T2",
  78                                    "ARM v6t2",
  79                                    [FeatureThumb2]>;
  80 def ArchV7A     : SubtargetFeature<"v7a", "ARMArchVersion", "V7A",
  81                                    "ARM v7A",
  82                                    [FeatureThumb2, FeatureNEON, FeatureDB]>;
  83 def ArchV7M     : SubtargetFeature<"v7m", "ARMArchVersion", "V7M",
  84                                    "ARM v7M",
  85                                    [FeatureThumb2, FeatureNoARM, FeatureDB,
  86                                     FeatureHWDiv]>;
  87
  88 //===----------------------------------------------------------------------===//
  89 // ARM Processors supported.
  90 //
  91
  92 include "ARMSchedule.td"
  93
  94 // ARM processor families.
  95 def ProcOthers  : SubtargetFeature<"others", "ARMProcFamily", "Others",
  96                                    "One of the other ARM processor families">;
  97 def ProcA8      : SubtargetFeature<"a8", "ARMProcFamily", "CortexA8",
  98                                    "Cortex-A8 ARM processors",
  99                                    [FeatureSlowFPBrcc, FeatureNEONForFP]>;
 100 def ProcA9      : SubtargetFeature<"a9", "ARMProcFamily", "CortexA9",
 101                                    "Cortex-A9 ARM processors">;
 102
 103 class ProcNoItin<string Name, list<SubtargetFeature> Features>
 104  : Processor<Name, GenericItineraries, Features>;
 105
 106 // V4 Processors.
 107 def : ProcNoItin<"generic",         []>;
 108 def : ProcNoItin<"arm8",            []>;
 109 def : ProcNoItin<"arm810",          []>;
 110 def : ProcNoItin<"strongarm",       []>;
 111 def : ProcNoItin<"strongarm110",    []>;
 112 def : ProcNoItin<"strongarm1100",   []>;
 113 def : ProcNoItin<"strongarm1110",   []>;
 114
 115 // V4T Processors.
 116 def : ProcNoItin<"arm7tdmi",        [ArchV4T]>;
 117 def : ProcNoItin<"arm7tdmi-s",      [ArchV4T]>;
 118 def : ProcNoItin<"arm710t",         [ArchV4T]>;
 119 def : ProcNoItin<"arm720t",         [ArchV4T]>;
 120 def : ProcNoItin<"arm9",            [ArchV4T]>;
 121 def : ProcNoItin<"arm9tdmi",        [ArchV4T]>;
 122 def : ProcNoItin<"arm920",          [ArchV4T]>;
 123 def : ProcNoItin<"arm920t",         [ArchV4T]>;
 124 def : ProcNoItin<"arm922t",         [ArchV4T]>;
 125 def : ProcNoItin<"arm940t",         [ArchV4T]>;
 126 def : ProcNoItin<"ep9312",          [ArchV4T]>;
 127
 128 // V5T Processors.
 129 def : ProcNoItin<"arm10tdmi",       [ArchV5T]>;
 130 def : ProcNoItin<"arm1020t",        [ArchV5T]>;
 131
 132 // V5TE Processors.
 133 def : ProcNoItin<"arm9e",           [ArchV5TE]>;
 134 def : ProcNoItin<"arm926ej-s",      [ArchV5TE]>;
 135 def : ProcNoItin<"arm946e-s",       [ArchV5TE]>;
 136 def : ProcNoItin<"arm966e-s",       [ArchV5TE]>;
 137 def : ProcNoItin<"arm968e-s",       [ArchV5TE]>;
 138 def : ProcNoItin<"arm10e",          [ArchV5TE]>;
 139 def : ProcNoItin<"arm1020e",        [ArchV5TE]>;
 140 def : ProcNoItin<"arm1022e",        [ArchV5TE]>;
 141 def : ProcNoItin<"xscale",          [ArchV5TE]>;
 142 def : ProcNoItin<"iwmmxt",          [ArchV5TE]>;
 143
 144 // V6 Processors.
 145 def : Processor<"arm1136j-s",       ARMV6Itineraries, [ArchV6]>;
 146 def : Processor<"arm1136jf-s",      ARMV6Itineraries, [ArchV6, FeatureVFP2,
 147                                                        FeatureHasSlowVMLx]>;
 148 def : Processor<"arm1176jz-s",      ARMV6Itineraries, [ArchV6]>;
 149 def : Processor<"arm1176jzf-s",     ARMV6Itineraries, [ArchV6, FeatureVFP2]>;
 150 def : Processor<"mpcorenovfp",      ARMV6Itineraries, [ArchV6]>;
 151 def : Processor<"mpcore",           ARMV6Itineraries, [ArchV6, FeatureVFP2]>;
 152
 153 // V6M Processors.
 154 def : Processor<"cortex-m0",        ARMV6Itineraries, [ArchV6M]>;
 155
 156 // V6T2 Processors.
 157 def : Processor<"arm1156t2-s",      ARMV6Itineraries, [ArchV6T2]>;
 158 def : Processor<"arm1156t2f-s",     ARMV6Itineraries, [ArchV6T2, FeatureVFP2]>;
 159
 160 // V7 Processors.
 161 def : Processor<"cortex-a8",        CortexA8Itineraries,
 162                                     [ArchV7A, ProcA8,
 163                                      FeatureHasSlowVMLx, FeatureT2XtPk]>;
 164 def : Processor<"cortex-a9",        CortexA9Itineraries,
 165                                     [ArchV7A, ProcA9, FeatureT2XtPk]>;
 166
 167 // V7M Processors.
 168 def : ProcNoItin<"cortex-m3",       [ArchV7M]>;
 169 def : ProcNoItin<"cortex-m4",       [ArchV7M, FeatureVFP2, FeatureVFPOnlySP]>;
 170
 171 //===----------------------------------------------------------------------===//
 172 // Register File Description
 173 //===----------------------------------------------------------------------===//
 174
 175 include "ARMRegisterInfo.td"
 176
 177 include "ARMCallingConv.td"
 178
 179 //===----------------------------------------------------------------------===//
 180 // Instruction Descriptions
 181 //===----------------------------------------------------------------------===//
 182
 183 include "ARMInstrInfo.td"
 184
 185 def ARMInstrInfo : InstrInfo;
 186
 187 //===----------------------------------------------------------------------===//
 188 // Declare the target which we are implementing
 189 //===----------------------------------------------------------------------===//
 190
 191 def ARM : Target {
 192   // Pull in Instruction Info:
 193   let InstructionSet = ARMInstrInfo;
 194 }