lib/Target/ARM/ARM.td

   1 //===- ARM.td - Describe the ARM Target Machine -----------------*- C++ -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 //
  11 //===----------------------------------------------------------------------===//
  12
  13 //===----------------------------------------------------------------------===//
  14 // Target-independent interfaces which we are implementing
  15 //===----------------------------------------------------------------------===//
  16
  17 include "llvm/Target/Target.td"
  18
  19 //===----------------------------------------------------------------------===//
  20 // ARM Subtarget features.
  21 //
  22
  23 def ArchV4T     : SubtargetFeature<"v4t", "ARMArchVersion", "V4T",
  24                                    "ARM v4T">;
  25 def ArchV5T     : SubtargetFeature<"v5t", "ARMArchVersion", "V5T",
  26                                    "ARM v5T">;
  27 def ArchV5TE    : SubtargetFeature<"v5te", "ARMArchVersion", "V5TE",
  28                                    "ARM v5TE, v5TEj, v5TExp">;
  29 def ArchV6      : SubtargetFeature<"v6", "ARMArchVersion", "V6",
  30                                    "ARM v6">;
  31 def ArchV6T2    : SubtargetFeature<"v6t2", "ARMArchVersion", "V6T2",
  32                                    "ARM v6t2">;
  33 def ArchV7A     : SubtargetFeature<"v7a", "ARMArchVersion", "V7A",
  34                                    "ARM v7A">;
  35 def ArchV7M     : SubtargetFeature<"v7m", "ARMArchVersion", "V7M",
  36                                    "ARM v7M">;
  37 def FeatureVFP2 : SubtargetFeature<"vfp2", "ARMFPUType", "VFPv2",
  38                                    "Enable VFP2 instructions">;
  39 def FeatureVFP3 : SubtargetFeature<"vfp3", "ARMFPUType", "VFPv3",
  40                                    "Enable VFP3 instructions">;
  41 def FeatureNEON : SubtargetFeature<"neon", "ARMFPUType", "NEON",
  42                                    "Enable NEON instructions">;
  43 def FeatureThumb2 : SubtargetFeature<"thumb2", "ThumbMode", "Thumb2",
  44                                      "Enable Thumb2 instructions">;
  45 def FeatureFP16   : SubtargetFeature<"fp16", "HasFP16", "true",
  46                                      "Enable half-precision floating point">;
  47 def FeatureHWDiv  : SubtargetFeature<"hwdiv", "HasHardwareDivide", "true",
  48                                      "Enable divide instructions">;
  49 def FeatureT2ExtractPack: SubtargetFeature<"t2xtpk", "HasT2ExtractPack", "true",
  50                                  "Enable Thumb2 extract and pack instructions">;
  51
  52 // Some processors have multiply-accumulate instructions that don't
  53 // play nicely with other VFP instructions, and it's generally better
  54 // to just not use them.
  55 // FIXME: Currently, this is only flagged for Cortex-A8. It may be true for
  56 // others as well. We should do more benchmarking and confirm one way or
  57 // the other.
  58 def FeatureHasSlowVMLx   : SubtargetFeature<"vmlx", "SlowVMLx", "true",
  59                                             "Disable VFP MAC instructions">;
  60 // Some processors benefit from using NEON instructions for scalar
  61 // single-precision FP operations.
  62 def FeatureNEONForFP : SubtargetFeature<"neonfp", "UseNEONForSinglePrecisionFP",
  63                                         "true",
  64                                         "Use NEON for single precision FP">;
  65
  66
  67 //===----------------------------------------------------------------------===//
  68 // ARM Processors supported.
  69 //
  70
  71 include "ARMSchedule.td"
  72
  73 class ProcNoItin<string Name, list<SubtargetFeature> Features>
  74  : Processor<Name, GenericItineraries, Features>;
  75
  76 // V4 Processors.
  77 def : ProcNoItin<"generic",         []>;
  78 def : ProcNoItin<"arm8",            []>;
  79 def : ProcNoItin<"arm810",          []>;
  80 def : ProcNoItin<"strongarm",       []>;
  81 def : ProcNoItin<"strongarm110",    []>;
  82 def : ProcNoItin<"strongarm1100",   []>;
  83 def : ProcNoItin<"strongarm1110",   []>;
  84
  85 // V4T Processors.
  86 def : ProcNoItin<"arm7tdmi",        [ArchV4T]>;
  87 def : ProcNoItin<"arm7tdmi-s",      [ArchV4T]>;
  88 def : ProcNoItin<"arm710t",         [ArchV4T]>;
  89 def : ProcNoItin<"arm720t",         [ArchV4T]>;
  90 def : ProcNoItin<"arm9",            [ArchV4T]>;
  91 def : ProcNoItin<"arm9tdmi",        [ArchV4T]>;
  92 def : ProcNoItin<"arm920",          [ArchV4T]>;
  93 def : ProcNoItin<"arm920t",         [ArchV4T]>;
  94 def : ProcNoItin<"arm922t",         [ArchV4T]>;
  95 def : ProcNoItin<"arm940t",         [ArchV4T]>;
  96 def : ProcNoItin<"ep9312",          [ArchV4T]>;
  97
  98 // V5T Processors.
  99 def : ProcNoItin<"arm10tdmi",       [ArchV5T]>;
 100 def : ProcNoItin<"arm1020t",        [ArchV5T]>;
 101
 102 // V5TE Processors.
 103 def : ProcNoItin<"arm9e",           [ArchV5TE]>;
 104 def : ProcNoItin<"arm926ej-s",      [ArchV5TE]>;
 105 def : ProcNoItin<"arm946e-s",       [ArchV5TE]>;
 106 def : ProcNoItin<"arm966e-s",       [ArchV5TE]>;
 107 def : ProcNoItin<"arm968e-s",       [ArchV5TE]>;
 108 def : ProcNoItin<"arm10e",          [ArchV5TE]>;
 109 def : ProcNoItin<"arm1020e",        [ArchV5TE]>;
 110 def : ProcNoItin<"arm1022e",        [ArchV5TE]>;
 111 def : ProcNoItin<"xscale",          [ArchV5TE]>;
 112 def : ProcNoItin<"iwmmxt",          [ArchV5TE]>;
 113
 114 // V6 Processors.
 115 def : Processor<"arm1136j-s",       ARMV6Itineraries, [ArchV6]>;
 116 def : Processor<"arm1136jf-s",      ARMV6Itineraries, [ArchV6, FeatureVFP2,
 117                                                        FeatureHasSlowVMLx]>;
 118 def : Processor<"arm1176jz-s",      ARMV6Itineraries, [ArchV6]>;
 119 def : Processor<"arm1176jzf-s",     ARMV6Itineraries, [ArchV6, FeatureVFP2]>;
 120 def : Processor<"mpcorenovfp",      ARMV6Itineraries, [ArchV6]>;
 121 def : Processor<"mpcore",           ARMV6Itineraries, [ArchV6, FeatureVFP2]>;
 122
 123 // V6T2 Processors.
 124 def : Processor<"arm1156t2-s",     ARMV6Itineraries,
 125                  [ArchV6T2, FeatureThumb2]>;
 126 def : Processor<"arm1156t2f-s",    ARMV6Itineraries,
 127                  [ArchV6T2, FeatureThumb2, FeatureVFP2]>;
 128
 129 // V7 Processors.
 130 def : Processor<"cortex-a8",        CortexA8Itineraries,
 131                 [ArchV7A, FeatureThumb2, FeatureNEON, FeatureHasSlowVMLx,
 132                  FeatureNEONForFP, FeatureT2ExtractPack]>;
 133 def : Processor<"cortex-a9",        CortexA9Itineraries,
 134                 [ArchV7A, FeatureThumb2, FeatureNEON, FeatureT2ExtractPack]>;
 135 def : ProcNoItin<"cortex-m3",       [ArchV7M, FeatureThumb2, FeatureHWDiv]>;
 136 def : ProcNoItin<"cortex-m4",       [ArchV7M, FeatureThumb2, FeatureHWDiv]>;
 137
 138 //===----------------------------------------------------------------------===//
 139 // Register File Description
 140 //===----------------------------------------------------------------------===//
 141
 142 include "ARMRegisterInfo.td"
 143
 144 include "ARMCallingConv.td"
 145
 146 //===----------------------------------------------------------------------===//
 147 // Instruction Descriptions
 148 //===----------------------------------------------------------------------===//
 149
 150 include "ARMInstrInfo.td"
 151
 152 def ARMInstrInfo : InstrInfo;
 153
 154 //===----------------------------------------------------------------------===//
 155 // Declare the target which we are implementing
 156 //===----------------------------------------------------------------------===//
 157
 158 def ARM : Target {
 159   // Pull in Instruction Info:
 160   let InstructionSet = ARMInstrInfo;
 161 }