1 //===- ARM.td - Describe the ARM Target Machine ------------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
13 //===----------------------------------------------------------------------===//
14 // Target-independent interfaces which we are implementing
15 //===----------------------------------------------------------------------===//
17 include "llvm/Target/Target.td"
20 //===----------------------------------------------------------------------===//
21 // ARM Subtarget features.
24 def FeatureVFP2 : SubtargetFeature<"vfp2", "ARMFPUType", "VFPv2",
25 "Enable VFP2 instructions">;
26 def FeatureVFP3 : SubtargetFeature<"vfp3", "ARMFPUType", "VFPv3",
27 "Enable VFP3 instructions">;
28 def FeatureNEON : SubtargetFeature<"neon", "ARMFPUType", "NEON",
29 "Enable NEON instructions">;
30 def FeatureThumb2 : SubtargetFeature<"thumb2", "ThumbMode", "Thumb2",
31 "Enable Thumb2 instructions">;
32 def FeatureNoARM : SubtargetFeature<"noarm", "NoARM", "true",
33 "Does not support ARM mode execution">;
34 def FeatureFP16 : SubtargetFeature<"fp16", "HasFP16", "true",
35 "Enable half-precision floating point">;
36 def FeatureD16 : SubtargetFeature<"d16", "HasD16", "true",
37 "Restrict VFP3 to 16 double registers">;
38 def FeatureHWDiv : SubtargetFeature<"hwdiv", "HasHardwareDivide", "true",
39 "Enable divide instructions">;
40 def FeatureT2XtPk : SubtargetFeature<"t2xtpk", "HasT2ExtractPack", "true",
41 "Enable Thumb2 extract and pack instructions">;
42 def FeatureDB : SubtargetFeature<"db", "HasDataBarrier", "true",
43 "Has data barrier (dmb / dsb) instructions">;
44 def FeatureSlowFPBrcc : SubtargetFeature<"slow-fp-brcc", "SlowFPBrcc", "true",
45 "FP compare + branch is slow">;
46 def FeatureVFPOnlySP : SubtargetFeature<"fp-only-sp", "FPOnlySP", "true",
47 "Floating point unit supports single precision only">;
49 // Some processors have FP multiply-accumulate instructions that don't
50 // play nicely with other VFP / NEON instructions, and it's generally better
51 // to just not use them.
52 def FeatureHasSlowFPVMLx : SubtargetFeature<"slowfpvmlx", "SlowFPVMLx", "true",
53 "Disable VFP / NEON MAC instructions">;
55 // Cortex-A8 / A9 Advanced SIMD has multiplier accumulator forwarding.
56 def FeatureVMLxForwarding : SubtargetFeature<"vmlx-forwarding",
57 "HasVMLxForwarding", "true",
58 "Has multiplier accumulator forwarding">;
60 // Some processors benefit from using NEON instructions for scalar
61 // single-precision FP operations.
62 def FeatureNEONForFP : SubtargetFeature<"neonfp", "UseNEONForSinglePrecisionFP",
64 "Use NEON for single precision FP">;
66 // Disable 32-bit to 16-bit narrowing for experimentation.
67 def FeaturePref32BitThumb : SubtargetFeature<"32bit", "Pref32BitThumb", "true",
68 "Prefer 32-bit Thumb instrs">;
70 // Multiprocessing extension.
71 def FeatureMP : SubtargetFeature<"mp", "HasMPExtension", "true",
72 "Supports Multiprocessing extension">;
75 def ArchV4T : SubtargetFeature<"v4t", "ARMArchVersion", "V4T",
77 def ArchV5T : SubtargetFeature<"v5t", "ARMArchVersion", "V5T",
79 def ArchV5TE : SubtargetFeature<"v5te", "ARMArchVersion", "V5TE",
80 "ARM v5TE, v5TEj, v5TExp">;
81 def ArchV6 : SubtargetFeature<"v6", "ARMArchVersion", "V6",
83 def ArchV6M : SubtargetFeature<"v6m", "ARMArchVersion", "V6M",
85 [FeatureNoARM, FeatureDB]>;
86 def ArchV6T2 : SubtargetFeature<"v6t2", "ARMArchVersion", "V6T2",
89 def ArchV7A : SubtargetFeature<"v7a", "ARMArchVersion", "V7A",
91 [FeatureThumb2, FeatureNEON, FeatureDB]>;
92 def ArchV7M : SubtargetFeature<"v7m", "ARMArchVersion", "V7M",
94 [FeatureThumb2, FeatureNoARM, FeatureDB,
97 //===----------------------------------------------------------------------===//
98 // ARM Processors supported.
101 include "ARMSchedule.td"
103 // ARM processor families.
104 def ProcOthers : SubtargetFeature<"others", "ARMProcFamily", "Others",
105 "One of the other ARM processor families">;
106 def ProcA8 : SubtargetFeature<"a8", "ARMProcFamily", "CortexA8",
107 "Cortex-A8 ARM processors",
108 [FeatureSlowFPBrcc, FeatureNEONForFP,
109 FeatureHasSlowFPVMLx, FeatureVMLxForwarding,
111 def ProcA9 : SubtargetFeature<"a9", "ARMProcFamily", "CortexA9",
112 "Cortex-A9 ARM processors",
113 [FeatureHasSlowFPVMLx, FeatureVMLxForwarding,
114 FeatureT2XtPk, FeatureFP16]>;
116 class ProcNoItin<string Name, list<SubtargetFeature> Features>
117 : Processor<Name, GenericItineraries, Features>;
120 def : ProcNoItin<"generic", []>;
121 def : ProcNoItin<"arm8", []>;
122 def : ProcNoItin<"arm810", []>;
123 def : ProcNoItin<"strongarm", []>;
124 def : ProcNoItin<"strongarm110", []>;
125 def : ProcNoItin<"strongarm1100", []>;
126 def : ProcNoItin<"strongarm1110", []>;
129 def : ProcNoItin<"arm7tdmi", [ArchV4T]>;
130 def : ProcNoItin<"arm7tdmi-s", [ArchV4T]>;
131 def : ProcNoItin<"arm710t", [ArchV4T]>;
132 def : ProcNoItin<"arm720t", [ArchV4T]>;
133 def : ProcNoItin<"arm9", [ArchV4T]>;
134 def : ProcNoItin<"arm9tdmi", [ArchV4T]>;
135 def : ProcNoItin<"arm920", [ArchV4T]>;
136 def : ProcNoItin<"arm920t", [ArchV4T]>;
137 def : ProcNoItin<"arm922t", [ArchV4T]>;
138 def : ProcNoItin<"arm940t", [ArchV4T]>;
139 def : ProcNoItin<"ep9312", [ArchV4T]>;
142 def : ProcNoItin<"arm10tdmi", [ArchV5T]>;
143 def : ProcNoItin<"arm1020t", [ArchV5T]>;
146 def : ProcNoItin<"arm9e", [ArchV5TE]>;
147 def : ProcNoItin<"arm926ej-s", [ArchV5TE]>;
148 def : ProcNoItin<"arm946e-s", [ArchV5TE]>;
149 def : ProcNoItin<"arm966e-s", [ArchV5TE]>;
150 def : ProcNoItin<"arm968e-s", [ArchV5TE]>;
151 def : ProcNoItin<"arm10e", [ArchV5TE]>;
152 def : ProcNoItin<"arm1020e", [ArchV5TE]>;
153 def : ProcNoItin<"arm1022e", [ArchV5TE]>;
154 def : ProcNoItin<"xscale", [ArchV5TE]>;
155 def : ProcNoItin<"iwmmxt", [ArchV5TE]>;
158 def : Processor<"arm1136j-s", ARMV6Itineraries, [ArchV6]>;
159 def : Processor<"arm1136jf-s", ARMV6Itineraries, [ArchV6, FeatureVFP2,
160 FeatureHasSlowFPVMLx]>;
161 def : Processor<"arm1176jz-s", ARMV6Itineraries, [ArchV6]>;
162 def : Processor<"arm1176jzf-s", ARMV6Itineraries, [ArchV6, FeatureVFP2,
163 FeatureHasSlowFPVMLx]>;
164 def : Processor<"mpcorenovfp", ARMV6Itineraries, [ArchV6]>;
165 def : Processor<"mpcore", ARMV6Itineraries, [ArchV6, FeatureVFP2,
166 FeatureHasSlowFPVMLx]>;
169 def : Processor<"cortex-m0", ARMV6Itineraries, [ArchV6M]>;
172 def : Processor<"arm1156t2-s", ARMV6Itineraries, [ArchV6T2]>;
173 def : Processor<"arm1156t2f-s", ARMV6Itineraries, [ArchV6T2, FeatureVFP2,
174 FeatureHasSlowFPVMLx]>;
177 def : Processor<"cortex-a8", CortexA8Itineraries,
179 def : Processor<"cortex-a9", CortexA9Itineraries,
183 def : ProcNoItin<"cortex-m3", [ArchV7M]>;
184 def : ProcNoItin<"cortex-m4", [ArchV7M, FeatureVFP2, FeatureVFPOnlySP]>;
186 //===----------------------------------------------------------------------===//
187 // Register File Description
188 //===----------------------------------------------------------------------===//
190 include "ARMRegisterInfo.td"
192 include "ARMCallingConv.td"
194 //===----------------------------------------------------------------------===//
195 // Instruction Descriptions
196 //===----------------------------------------------------------------------===//
198 include "ARMInstrInfo.td"
200 def ARMInstrInfo : InstrInfo;
203 //===----------------------------------------------------------------------===//
205 //===----------------------------------------------------------------------===//
206 // ARM Uses the MC printer for asm output, so make sure the TableGen
207 // AsmWriter bits get associated with the correct class.
208 def ARMAsmWriter : AsmWriter {
209 string AsmWriterClassName = "InstPrinter";
210 bit isMCAsmWriter = 1;
213 //===----------------------------------------------------------------------===//
214 // Declare the target which we are implementing
215 //===----------------------------------------------------------------------===//
218 // Pull in Instruction Info:
219 let InstructionSet = ARMInstrInfo;
221 let AssemblyWriters = [ARMAsmWriter];