1 //===-- ARM.td - Describe the ARM Target Machine -----------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
13 //===----------------------------------------------------------------------===//
14 // Target-independent interfaces which we are implementing
15 //===----------------------------------------------------------------------===//
17 include "llvm/Target/Target.td"
19 //===----------------------------------------------------------------------===//
20 // ARM Subtarget state.
23 def ModeThumb : SubtargetFeature<"thumb-mode", "InThumbMode", "true",
26 //===----------------------------------------------------------------------===//
27 // ARM Subtarget features.
30 def FeatureVFP2 : SubtargetFeature<"vfp2", "HasVFPv2", "true",
31 "Enable VFP2 instructions">;
32 def FeatureVFP3 : SubtargetFeature<"vfp3", "HasVFPv3", "true",
33 "Enable VFP3 instructions",
35 def FeatureNEON : SubtargetFeature<"neon", "HasNEON", "true",
36 "Enable NEON instructions",
38 def FeatureThumb2 : SubtargetFeature<"thumb2", "HasThumb2", "true",
39 "Enable Thumb2 instructions">;
40 def FeatureNoARM : SubtargetFeature<"noarm", "NoARM", "true",
41 "Does not support ARM mode execution",
43 def FeatureFP16 : SubtargetFeature<"fp16", "HasFP16", "true",
44 "Enable half-precision floating point">;
45 def FeatureVFP4 : SubtargetFeature<"vfp4", "HasVFPv4", "true",
46 "Enable VFP4 instructions",
47 [FeatureVFP3, FeatureFP16]>;
48 def FeatureFPARMv8 : SubtargetFeature<"fp-armv8", "HasFPARMv8",
49 "true", "Enable ARMv8 FP",
51 def FeatureD16 : SubtargetFeature<"d16", "HasD16", "true",
52 "Restrict VFP3 to 16 double registers">;
53 def FeatureHWDiv : SubtargetFeature<"hwdiv", "HasHardwareDivide", "true",
54 "Enable divide instructions">;
55 def FeatureHWDivARM : SubtargetFeature<"hwdiv-arm",
56 "HasHardwareDivideInARM", "true",
57 "Enable divide instructions in ARM mode">;
58 def FeatureT2XtPk : SubtargetFeature<"t2xtpk", "HasT2ExtractPack", "true",
59 "Enable Thumb2 extract and pack instructions">;
60 def FeatureDB : SubtargetFeature<"db", "HasDataBarrier", "true",
61 "Has data barrier (dmb / dsb) instructions">;
62 def FeatureSlowFPBrcc : SubtargetFeature<"slow-fp-brcc", "SlowFPBrcc", "true",
63 "FP compare + branch is slow">;
64 def FeatureVFPOnlySP : SubtargetFeature<"fp-only-sp", "FPOnlySP", "true",
65 "Floating point unit supports single precision only">;
66 def FeaturePerfMon : SubtargetFeature<"perfmon", "HasPerfMon", "true",
67 "Enable support for Performance Monitor extensions">;
68 def FeatureTrustZone : SubtargetFeature<"trustzone", "HasTrustZone", "true",
69 "Enable support for TrustZone security extensions">;
70 def FeatureCrypto : SubtargetFeature<"crypto", "HasCrypto", "true",
71 "Enable support for Cryptography extensions",
73 def FeatureCRC : SubtargetFeature<"crc", "HasCRC", "true",
74 "Enable support for CRC instructions">;
76 // Cyclone has preferred instructions for zeroing VFP registers, which can
77 // execute in 0 cycles.
78 def FeatureZCZeroing : SubtargetFeature<"zcz", "HasZeroCycleZeroing", "true",
79 "Has zero-cycle zeroing instructions">;
81 // Some processors have FP multiply-accumulate instructions that don't
82 // play nicely with other VFP / NEON instructions, and it's generally better
83 // to just not use them.
84 def FeatureHasSlowFPVMLx : SubtargetFeature<"slowfpvmlx", "SlowFPVMLx", "true",
85 "Disable VFP / NEON MAC instructions">;
87 // Cortex-A8 / A9 Advanced SIMD has multiplier accumulator forwarding.
88 def FeatureVMLxForwarding : SubtargetFeature<"vmlx-forwarding",
89 "HasVMLxForwarding", "true",
90 "Has multiplier accumulator forwarding">;
92 // Some processors benefit from using NEON instructions for scalar
93 // single-precision FP operations.
94 def FeatureNEONForFP : SubtargetFeature<"neonfp", "UseNEONForSinglePrecisionFP",
96 "Use NEON for single precision FP">;
98 // Disable 32-bit to 16-bit narrowing for experimentation.
99 def FeaturePref32BitThumb : SubtargetFeature<"32bit", "Pref32BitThumb", "true",
100 "Prefer 32-bit Thumb instrs">;
102 /// Some instructions update CPSR partially, which can add false dependency for
103 /// out-of-order implementation, e.g. Cortex-A9, unless each individual bit is
104 /// mapped to a separate physical register. Avoid partial CPSR update for these
106 def FeatureAvoidPartialCPSR : SubtargetFeature<"avoid-partial-cpsr",
107 "AvoidCPSRPartialUpdate", "true",
108 "Avoid CPSR partial update for OOO execution">;
110 def FeatureAvoidMOVsShOp : SubtargetFeature<"avoid-movs-shop",
111 "AvoidMOVsShifterOperand", "true",
112 "Avoid movs instructions with shifter operand">;
114 // Some processors perform return stack prediction. CodeGen should avoid issue
115 // "normal" call instructions to callees which do not return.
116 def FeatureHasRAS : SubtargetFeature<"ras", "HasRAS", "true",
117 "Has return address stack">;
119 /// Some M architectures don't have the DSP extension (v7E-M vs. v7M)
120 def FeatureDSPThumb2 : SubtargetFeature<"t2dsp", "Thumb2DSP", "true",
121 "Supports v7 DSP instructions in Thumb2">;
123 // Multiprocessing extension.
124 def FeatureMP : SubtargetFeature<"mp", "HasMPExtension", "true",
125 "Supports Multiprocessing extension">;
127 // Virtualization extension - requires HW divide (ARMv7-AR ARMARM - 4.4.8).
128 def FeatureVirtualization : SubtargetFeature<"virtualization",
129 "HasVirtualization", "true",
130 "Supports Virtualization extension",
131 [FeatureHWDiv, FeatureHWDivARM]>;
134 def FeatureMClass : SubtargetFeature<"mclass", "ARMProcClass", "MClass",
135 "Is microcontroller profile ('M' series)">;
138 def FeatureRClass : SubtargetFeature<"rclass", "ARMProcClass", "RClass",
139 "Is realtime profile ('R' series)">;
142 def FeatureAClass : SubtargetFeature<"aclass", "ARMProcClass", "AClass",
143 "Is application profile ('A' series)">;
145 // Special TRAP encoding for NaCl, which looks like a TRAP in Thumb too.
146 // See ARMInstrInfo.td for details.
147 def FeatureNaClTrap : SubtargetFeature<"nacl-trap", "UseNaClTrap", "true",
151 def HasV4TOps : SubtargetFeature<"v4t", "HasV4TOps", "true",
152 "Support ARM v4T instructions">;
153 def HasV5TOps : SubtargetFeature<"v5t", "HasV5TOps", "true",
154 "Support ARM v5T instructions",
156 def HasV5TEOps : SubtargetFeature<"v5te", "HasV5TEOps", "true",
157 "Support ARM v5TE, v5TEj, and v5TExp instructions",
159 def HasV6Ops : SubtargetFeature<"v6", "HasV6Ops", "true",
160 "Support ARM v6 instructions",
162 def HasV6MOps : SubtargetFeature<"v6m", "HasV6MOps", "true",
163 "Support ARM v6M instructions",
165 def HasV6KOps : SubtargetFeature<"v6k", "HasV6KOps", "true",
166 "Support ARM v6k instructions",
168 def HasV6T2Ops : SubtargetFeature<"v6t2", "HasV6T2Ops", "true",
169 "Support ARM v6t2 instructions",
170 [HasV6MOps, HasV6KOps, FeatureThumb2]>;
171 def HasV7Ops : SubtargetFeature<"v7", "HasV7Ops", "true",
172 "Support ARM v7 instructions",
173 [HasV6T2Ops, FeaturePerfMon]>;
174 def HasV8Ops : SubtargetFeature<"v8", "HasV8Ops", "true",
175 "Support ARM v8 instructions",
176 [HasV7Ops, FeatureVirtualization,
178 def HasV8_1aOps : SubtargetFeature<"v8.1a", "HasV8_1aOps", "true",
179 "Support ARM v8.1a instructions",
180 [HasV8Ops, FeatureAClass, FeatureCRC]>;
182 //===----------------------------------------------------------------------===//
183 // ARM Processors supported.
186 include "ARMSchedule.td"
188 // ARM processor families.
189 def ProcA5 : SubtargetFeature<"a5", "ARMProcFamily", "CortexA5",
190 "Cortex-A5 ARM processors",
191 [FeatureSlowFPBrcc, FeatureHasSlowFPVMLx,
192 FeatureVMLxForwarding, FeatureT2XtPk,
193 FeatureTrustZone, FeatureMP]>;
194 def ProcA7 : SubtargetFeature<"a7", "ARMProcFamily", "CortexA7",
195 "Cortex-A7 ARM processors",
196 [FeatureSlowFPBrcc, FeatureHasSlowFPVMLx,
197 FeatureVMLxForwarding, FeatureT2XtPk,
198 FeatureVFP4, FeatureMP,
199 FeatureHWDiv, FeatureHWDivARM,
200 FeatureTrustZone, FeatureVirtualization]>;
201 def ProcA8 : SubtargetFeature<"a8", "ARMProcFamily", "CortexA8",
202 "Cortex-A8 ARM processors",
203 [FeatureSlowFPBrcc, FeatureHasSlowFPVMLx,
204 FeatureVMLxForwarding, FeatureT2XtPk,
206 def ProcA9 : SubtargetFeature<"a9", "ARMProcFamily", "CortexA9",
207 "Cortex-A9 ARM processors",
208 [FeatureVMLxForwarding,
209 FeatureT2XtPk, FeatureFP16,
210 FeatureAvoidPartialCPSR,
212 def ProcSwift : SubtargetFeature<"swift", "ARMProcFamily", "Swift",
213 "Swift ARM processors",
214 [FeatureNEONForFP, FeatureT2XtPk,
215 FeatureVFP4, FeatureMP, FeatureHWDiv,
216 FeatureHWDivARM, FeatureAvoidPartialCPSR,
217 FeatureAvoidMOVsShOp,
218 FeatureHasSlowFPVMLx, FeatureTrustZone]>;
219 def ProcA12 : SubtargetFeature<"a12", "ARMProcFamily", "CortexA12",
220 "Cortex-A12 ARM processors",
221 [FeatureVMLxForwarding,
222 FeatureT2XtPk, FeatureVFP4,
223 FeatureHWDiv, FeatureHWDivARM,
224 FeatureAvoidPartialCPSR,
225 FeatureVirtualization,
229 // FIXME: It has not been determined if A15 has these features.
230 def ProcA15 : SubtargetFeature<"a15", "ARMProcFamily", "CortexA15",
231 "Cortex-A15 ARM processors",
232 [FeatureT2XtPk, FeatureVFP4,
233 FeatureMP, FeatureHWDiv, FeatureHWDivARM,
234 FeatureAvoidPartialCPSR,
235 FeatureTrustZone, FeatureVirtualization]>;
237 def ProcA17 : SubtargetFeature<"a17", "ARMProcFamily", "CortexA17",
238 "Cortex-A17 ARM processors",
239 [FeatureVMLxForwarding,
240 FeatureT2XtPk, FeatureVFP4,
241 FeatureHWDiv, FeatureHWDivARM,
242 FeatureAvoidPartialCPSR,
243 FeatureVirtualization,
246 def ProcA53 : SubtargetFeature<"a53", "ARMProcFamily", "CortexA53",
247 "Cortex-A53 ARM processors",
248 [FeatureHWDiv, FeatureHWDivARM,
249 FeatureTrustZone, FeatureT2XtPk,
250 FeatureCrypto, FeatureCRC]>;
252 def ProcA57 : SubtargetFeature<"a57", "ARMProcFamily", "CortexA57",
253 "Cortex-A57 ARM processors",
254 [FeatureHWDiv, FeatureHWDivARM,
255 FeatureTrustZone, FeatureT2XtPk,
256 FeatureCrypto, FeatureCRC]>;
258 def ProcR4 : SubtargetFeature<"r4", "ARMProcFamily", "CortexR4",
259 "Cortex-R4 ARM processors",
261 FeatureAvoidPartialCPSR,
262 FeatureDSPThumb2, FeatureT2XtPk,
263 HasV7Ops, FeatureDB, FeatureHasRAS,
266 def ProcR5 : SubtargetFeature<"r5", "ARMProcFamily", "CortexR5",
267 "Cortex-R5 ARM processors",
269 FeatureHWDiv, FeatureHWDivARM,
270 FeatureHasSlowFPVMLx,
271 FeatureAvoidPartialCPSR,
274 // FIXME: krait has currently the same features as A9
275 // plus VFP4 and hardware division features.
276 def ProcKrait : SubtargetFeature<"krait", "ARMProcFamily", "Krait",
277 "Qualcomm ARM processors",
278 [FeatureVMLxForwarding,
279 FeatureT2XtPk, FeatureFP16,
280 FeatureAvoidPartialCPSR,
287 class ProcNoItin<string Name, list<SubtargetFeature> Features>
288 : Processor<Name, NoItineraries, Features>;
291 def : ProcNoItin<"generic", []>;
292 def : ProcNoItin<"arm8", []>;
293 def : ProcNoItin<"arm810", []>;
294 def : ProcNoItin<"strongarm", []>;
295 def : ProcNoItin<"strongarm110", []>;
296 def : ProcNoItin<"strongarm1100", []>;
297 def : ProcNoItin<"strongarm1110", []>;
300 def : ProcNoItin<"arm7tdmi", [HasV4TOps]>;
301 def : ProcNoItin<"arm7tdmi-s", [HasV4TOps]>;
302 def : ProcNoItin<"arm710t", [HasV4TOps]>;
303 def : ProcNoItin<"arm720t", [HasV4TOps]>;
304 def : ProcNoItin<"arm9", [HasV4TOps]>;
305 def : ProcNoItin<"arm9tdmi", [HasV4TOps]>;
306 def : ProcNoItin<"arm920", [HasV4TOps]>;
307 def : ProcNoItin<"arm920t", [HasV4TOps]>;
308 def : ProcNoItin<"arm922t", [HasV4TOps]>;
309 def : ProcNoItin<"arm940t", [HasV4TOps]>;
310 def : ProcNoItin<"ep9312", [HasV4TOps]>;
313 def : ProcNoItin<"arm10tdmi", [HasV5TOps]>;
314 def : ProcNoItin<"arm1020t", [HasV5TOps]>;
317 def : ProcNoItin<"arm9e", [HasV5TEOps]>;
318 def : ProcNoItin<"arm926ej-s", [HasV5TEOps]>;
319 def : ProcNoItin<"arm946e-s", [HasV5TEOps]>;
320 def : ProcNoItin<"arm966e-s", [HasV5TEOps]>;
321 def : ProcNoItin<"arm968e-s", [HasV5TEOps]>;
322 def : ProcNoItin<"arm10e", [HasV5TEOps]>;
323 def : ProcNoItin<"arm1020e", [HasV5TEOps]>;
324 def : ProcNoItin<"arm1022e", [HasV5TEOps]>;
325 def : ProcNoItin<"xscale", [HasV5TEOps]>;
326 def : ProcNoItin<"iwmmxt", [HasV5TEOps]>;
329 def : Processor<"arm1136j-s", ARMV6Itineraries, [HasV6Ops]>;
330 def : Processor<"arm1136jf-s", ARMV6Itineraries, [HasV6Ops, FeatureVFP2,
331 FeatureHasSlowFPVMLx]>;
334 def : Processor<"cortex-m0", ARMV6Itineraries, [HasV6MOps, FeatureNoARM,
335 FeatureDB, FeatureMClass]>;
336 def : Processor<"cortex-m0plus", ARMV6Itineraries, [HasV6MOps, FeatureNoARM,
337 FeatureDB, FeatureMClass]>;
338 def : Processor<"cortex-m1", ARMV6Itineraries, [HasV6MOps, FeatureNoARM,
339 FeatureDB, FeatureMClass]>;
340 def : Processor<"sc000", ARMV6Itineraries, [HasV6MOps, FeatureNoARM,
341 FeatureDB, FeatureMClass]>;
344 def : Processor<"arm1176jz-s", ARMV6Itineraries, [HasV6KOps]>;
345 def : Processor<"arm1176jzf-s", ARMV6Itineraries, [HasV6KOps, FeatureVFP2,
346 FeatureHasSlowFPVMLx]>;
347 def : Processor<"mpcorenovfp", ARMV6Itineraries, [HasV6KOps]>;
348 def : Processor<"mpcore", ARMV6Itineraries, [HasV6KOps, FeatureVFP2,
349 FeatureHasSlowFPVMLx]>;
352 def : Processor<"arm1156t2-s", ARMV6Itineraries, [HasV6T2Ops,
354 def : Processor<"arm1156t2f-s", ARMV6Itineraries, [HasV6T2Ops, FeatureVFP2,
355 FeatureHasSlowFPVMLx,
359 // FIXME: A5 has currently the same Schedule model as A8
360 def : ProcessorModel<"cortex-a5", CortexA8Model,
361 [ProcA5, HasV7Ops, FeatureNEON, FeatureDB,
362 FeatureVFP4, FeatureDSPThumb2,
363 FeatureHasRAS, FeatureAClass]>;
364 def : ProcessorModel<"cortex-a7", CortexA8Model,
365 [ProcA7, HasV7Ops, FeatureNEON, FeatureDB,
366 FeatureDSPThumb2, FeatureHasRAS,
368 def : ProcessorModel<"cortex-a8", CortexA8Model,
369 [ProcA8, HasV7Ops, FeatureNEON, FeatureDB,
370 FeatureDSPThumb2, FeatureHasRAS,
372 def : ProcessorModel<"cortex-a9", CortexA9Model,
373 [ProcA9, HasV7Ops, FeatureNEON, FeatureDB,
374 FeatureDSPThumb2, FeatureHasRAS, FeatureMP,
377 // FIXME: A12 has currently the same Schedule model as A9
378 def : ProcessorModel<"cortex-a12", CortexA9Model,
379 [ProcA12, HasV7Ops, FeatureNEON, FeatureDB,
380 FeatureDSPThumb2, FeatureMP,
381 FeatureHasRAS, FeatureAClass]>;
383 // FIXME: A15 has currently the same ProcessorModel as A9.
384 def : ProcessorModel<"cortex-a15", CortexA9Model,
385 [ProcA15, HasV7Ops, FeatureNEON, FeatureDB,
386 FeatureDSPThumb2, FeatureHasRAS,
389 // FIXME: A17 has currently the same Schedule model as A9
390 def : ProcessorModel<"cortex-a17", CortexA9Model,
391 [ProcA17, HasV7Ops, FeatureNEON, FeatureDB,
392 FeatureDSPThumb2, FeatureMP,
393 FeatureHasRAS, FeatureAClass]>;
395 // FIXME: krait has currently the same Schedule model as A9
396 def : ProcessorModel<"krait", CortexA9Model,
397 [ProcKrait, HasV7Ops,
398 FeatureNEON, FeatureDB,
399 FeatureDSPThumb2, FeatureHasRAS,
402 // FIXME: R4 has currently the same ProcessorModel as A8.
403 def : ProcessorModel<"cortex-r4", CortexA8Model,
406 // FIXME: R4F has currently the same ProcessorModel as A8.
407 def : ProcessorModel<"cortex-r4f", CortexA8Model,
409 FeatureSlowFPBrcc, FeatureHasSlowFPVMLx,
410 FeatureVFP3, FeatureVFPOnlySP, FeatureD16]>;
412 // FIXME: R5 has currently the same ProcessorModel as A8.
413 def : ProcessorModel<"cortex-r5", CortexA8Model,
414 [ProcR5, HasV7Ops, FeatureDB,
415 FeatureVFP3, FeatureDSPThumb2,
416 FeatureHasRAS, FeatureVFPOnlySP,
417 FeatureD16, FeatureRClass]>;
419 // FIXME: R7 has currently the same ProcessorModel as A8 and is modelled as R5.
420 def : ProcessorModel<"cortex-r7", CortexA8Model,
421 [ProcR5, HasV7Ops, FeatureDB,
422 FeatureVFP3, FeatureDSPThumb2,
423 FeatureHasRAS, FeatureVFPOnlySP,
424 FeatureD16, FeatureMP, FeatureRClass]>;
427 def : ProcNoItin<"cortex-m3", [HasV7Ops,
428 FeatureThumb2, FeatureNoARM, FeatureDB,
429 FeatureHWDiv, FeatureMClass]>;
430 def : ProcNoItin<"sc300", [HasV7Ops,
431 FeatureThumb2, FeatureNoARM, FeatureDB,
432 FeatureHWDiv, FeatureMClass]>;
435 def : ProcNoItin<"cortex-m4", [HasV7Ops,
436 FeatureThumb2, FeatureNoARM, FeatureDB,
437 FeatureHWDiv, FeatureDSPThumb2,
438 FeatureT2XtPk, FeatureVFP4,
439 FeatureVFPOnlySP, FeatureD16,
441 def : ProcNoItin<"cortex-m7", [HasV7Ops,
442 FeatureThumb2, FeatureNoARM, FeatureDB,
443 FeatureHWDiv, FeatureDSPThumb2,
444 FeatureT2XtPk, FeatureFPARMv8,
445 FeatureD16, FeatureMClass]>;
448 // Swift uArch Processors.
449 def : ProcessorModel<"swift", SwiftModel,
450 [ProcSwift, HasV7Ops, FeatureNEON,
451 FeatureDB, FeatureDSPThumb2,
452 FeatureHasRAS, FeatureAClass]>;
455 def : ProcNoItin<"cortex-a53", [ProcA53, HasV8Ops, FeatureAClass,
456 FeatureDB, FeatureFPARMv8,
457 FeatureNEON, FeatureDSPThumb2]>;
458 def : ProcNoItin<"cortex-a57", [ProcA57, HasV8Ops, FeatureAClass,
459 FeatureDB, FeatureFPARMv8,
460 FeatureNEON, FeatureDSPThumb2]>;
461 // FIXME: Cortex-A72 is currently modelled as an Cortex-A57.
462 def : ProcNoItin<"cortex-a72", [ProcA57, HasV8Ops, FeatureAClass,
463 FeatureDB, FeatureFPARMv8,
464 FeatureNEON, FeatureDSPThumb2]>;
466 // Cyclone is very similar to swift
467 def : ProcessorModel<"cyclone", SwiftModel,
468 [ProcSwift, HasV8Ops, HasV7Ops,
469 FeatureCrypto, FeatureFPARMv8,
470 FeatureDB,FeatureDSPThumb2,
471 FeatureHasRAS, FeatureZCZeroing]>;
473 //===----------------------------------------------------------------------===//
474 // Register File Description
475 //===----------------------------------------------------------------------===//
477 include "ARMRegisterInfo.td"
479 include "ARMCallingConv.td"
481 //===----------------------------------------------------------------------===//
482 // Instruction Descriptions
483 //===----------------------------------------------------------------------===//
485 include "ARMInstrInfo.td"
487 def ARMInstrInfo : InstrInfo;
489 //===----------------------------------------------------------------------===//
490 // Declare the target which we are implementing
491 //===----------------------------------------------------------------------===//
493 def ARMAsmWriter : AsmWriter {
494 string AsmWriterClassName = "InstPrinter";
495 int PassSubtarget = 1;
497 bit isMCAsmWriter = 1;
501 // Pull in Instruction Info:
502 let InstructionSet = ARMInstrInfo;
503 let AssemblyWriters = [ARMAsmWriter];