lib/Target/ARM/ARM.td

   1 //===- ARM.td - Describe the ARM Target Machine ------------*- tablegen -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 //
  11 //===----------------------------------------------------------------------===//
  12
  13 //===----------------------------------------------------------------------===//
  14 // Target-independent interfaces which we are implementing
  15 //===----------------------------------------------------------------------===//
  16
  17 include "llvm/Target/Target.td"
  18
  19 //===----------------------------------------------------------------------===//
  20 // ARM Subtarget state.
  21 //
  22
  23 def ModeThumb  : SubtargetFeature<"thumb-mode", "InThumbMode", "true",
  24                                   "Thumb mode">;
  25
  26 //===----------------------------------------------------------------------===//
  27 // ARM Subtarget features.
  28 //
  29
  30 def FeatureVFP2 : SubtargetFeature<"vfp2", "HasVFPv2", "true",
  31                                    "Enable VFP2 instructions">;
  32 def FeatureVFP3 : SubtargetFeature<"vfp3", "HasVFPv3", "true",
  33                                    "Enable VFP3 instructions",
  34                                    [FeatureVFP2]>;
  35 def FeatureNEON : SubtargetFeature<"neon", "HasNEON", "true",
  36                                    "Enable NEON instructions",
  37                                    [FeatureVFP3]>;
  38 def FeatureThumb2 : SubtargetFeature<"thumb2", "HasThumb2", "true",
  39                                      "Enable Thumb2 instructions">;
  40 def FeatureNoARM  : SubtargetFeature<"noarm", "NoARM", "true",
  41                                      "Does not support ARM mode execution">;
  42 def FeatureFP16   : SubtargetFeature<"fp16", "HasFP16", "true",
  43                                      "Enable half-precision floating point">;
  44 def FeatureD16    : SubtargetFeature<"d16", "HasD16", "true",
  45                                      "Restrict VFP3 to 16 double registers">;
  46 def FeatureHWDiv  : SubtargetFeature<"hwdiv", "HasHardwareDivide", "true",
  47                                      "Enable divide instructions">;
  48 def FeatureT2XtPk : SubtargetFeature<"t2xtpk", "HasT2ExtractPack", "true",
  49                                  "Enable Thumb2 extract and pack instructions">;
  50 def FeatureDB     : SubtargetFeature<"db", "HasDataBarrier", "true",
  51                                    "Has data barrier (dmb / dsb) instructions">;
  52 def FeatureSlowFPBrcc : SubtargetFeature<"slow-fp-brcc", "SlowFPBrcc", "true",
  53                                          "FP compare + branch is slow">;
  54 def FeatureVFPOnlySP : SubtargetFeature<"fp-only-sp", "FPOnlySP", "true",
  55                           "Floating point unit supports single precision only">;
  56
  57 // Some processors have FP multiply-accumulate instructions that don't
  58 // play nicely with other VFP / NEON instructions, and it's generally better
  59 // to just not use them.
  60 def FeatureHasSlowFPVMLx : SubtargetFeature<"slowfpvmlx", "SlowFPVMLx", "true",
  61                                          "Disable VFP / NEON MAC instructions">;
  62
  63 // Cortex-A8 / A9 Advanced SIMD has multiplier accumulator forwarding.
  64 def FeatureVMLxForwarding : SubtargetFeature<"vmlx-forwarding",
  65                                        "HasVMLxForwarding", "true",
  66                                        "Has multiplier accumulator forwarding">;
  67
  68 // Some processors benefit from using NEON instructions for scalar
  69 // single-precision FP operations.
  70 def FeatureNEONForFP : SubtargetFeature<"neonfp", "UseNEONForSinglePrecisionFP",
  71                                         "true",
  72                                         "Use NEON for single precision FP">;
  73
  74 // Disable 32-bit to 16-bit narrowing for experimentation.
  75 def FeaturePref32BitThumb : SubtargetFeature<"32bit", "Pref32BitThumb", "true",
  76                                              "Prefer 32-bit Thumb instrs">;
  77
  78 /// Some instructions update CPSR partially, which can add false dependency for
  79 /// out-of-order implementation, e.g. Cortex-A9, unless each individual bit is
  80 /// mapped to a separate physical register. Avoid partial CPSR update for these
  81 /// processors.
  82 def FeatureAvoidPartialCPSR : SubtargetFeature<"avoid-partial-cpsr",
  83                                                "AvoidCPSRPartialUpdate", "true",
  84                                  "Avoid CPSR partial update for OOO execution">;
  85
  86 /// Some M architectures don't have the DSP extension (v7E-M vs. v7M)
  87 def FeatureDSPThumb2 : SubtargetFeature<"t2dsp", "Thumb2DSP", "true",
  88                                  "Supports v7 DSP instructions in Thumb2">;
  89
  90 // Multiprocessing extension.
  91 def FeatureMP : SubtargetFeature<"mp", "HasMPExtension", "true",
  92                                  "Supports Multiprocessing extension">;
  93
  94 // M-series ISA?
  95 def FeatureMClass : SubtargetFeature<"mclass", "IsMClass", "true",
  96                                      "Is microcontroller profile ('M' series)">;
  97
  98 // ARM ISAs.
  99 def HasV4TOps   : SubtargetFeature<"v4t", "HasV4TOps", "true",
 100                                    "Support ARM v4T instructions">;
 101 def HasV5TOps   : SubtargetFeature<"v5t", "HasV5TOps", "true",
 102                                    "Support ARM v5T instructions",
 103                                    [HasV4TOps]>;
 104 def HasV5TEOps  : SubtargetFeature<"v5te", "HasV5TEOps", "true",
 105                              "Support ARM v5TE, v5TEj, and v5TExp instructions",
 106                                    [HasV5TOps]>;
 107 def HasV6Ops    : SubtargetFeature<"v6", "HasV6Ops", "true",
 108                                    "Support ARM v6 instructions",
 109                                    [HasV5TEOps]>;
 110 def HasV6T2Ops  : SubtargetFeature<"v6t2", "HasV6T2Ops", "true",
 111                                    "Support ARM v6t2 instructions",
 112                                    [HasV6Ops, FeatureThumb2]>;
 113 def HasV7Ops    : SubtargetFeature<"v7", "HasV7Ops", "true",
 114                                    "Support ARM v7 instructions",
 115                                    [HasV6T2Ops]>;
 116
 117 //===----------------------------------------------------------------------===//
 118 // ARM Processors supported.
 119 //
 120
 121 include "ARMSchedule.td"
 122
 123 // ARM processor families.
 124 def ProcA8      : SubtargetFeature<"a8", "ARMProcFamily", "CortexA8",
 125                                    "Cortex-A8 ARM processors",
 126                                    [FeatureSlowFPBrcc, FeatureNEONForFP,
 127                                     FeatureHasSlowFPVMLx, FeatureVMLxForwarding,
 128                                     FeatureT2XtPk]>;
 129 def ProcA9      : SubtargetFeature<"a9", "ARMProcFamily", "CortexA9",
 130                                    "Cortex-A9 ARM processors",
 131                                    [FeatureVMLxForwarding,
 132                                     FeatureT2XtPk, FeatureFP16,
 133                                     FeatureAvoidPartialCPSR]>;
 134
 135 class ProcNoItin<string Name, list<SubtargetFeature> Features>
 136  : Processor<Name, GenericItineraries, Features>;
 137
 138 // V4 Processors.
 139 def : ProcNoItin<"generic",         []>;
 140 def : ProcNoItin<"arm8",            []>;
 141 def : ProcNoItin<"arm810",          []>;
 142 def : ProcNoItin<"strongarm",       []>;
 143 def : ProcNoItin<"strongarm110",    []>;
 144 def : ProcNoItin<"strongarm1100",   []>;
 145 def : ProcNoItin<"strongarm1110",   []>;
 146
 147 // V4T Processors.
 148 def : ProcNoItin<"arm7tdmi",        [HasV4TOps]>;
 149 def : ProcNoItin<"arm7tdmi-s",      [HasV4TOps]>;
 150 def : ProcNoItin<"arm710t",         [HasV4TOps]>;
 151 def : ProcNoItin<"arm720t",         [HasV4TOps]>;
 152 def : ProcNoItin<"arm9",            [HasV4TOps]>;
 153 def : ProcNoItin<"arm9tdmi",        [HasV4TOps]>;
 154 def : ProcNoItin<"arm920",          [HasV4TOps]>;
 155 def : ProcNoItin<"arm920t",         [HasV4TOps]>;
 156 def : ProcNoItin<"arm922t",         [HasV4TOps]>;
 157 def : ProcNoItin<"arm940t",         [HasV4TOps]>;
 158 def : ProcNoItin<"ep9312",          [HasV4TOps]>;
 159
 160 // V5T Processors.
 161 def : ProcNoItin<"arm10tdmi",       [HasV5TOps]>;
 162 def : ProcNoItin<"arm1020t",        [HasV5TOps]>;
 163
 164 // V5TE Processors.
 165 def : ProcNoItin<"arm9e",           [HasV5TEOps]>;
 166 def : ProcNoItin<"arm926ej-s",      [HasV5TEOps]>;
 167 def : ProcNoItin<"arm946e-s",       [HasV5TEOps]>;
 168 def : ProcNoItin<"arm966e-s",       [HasV5TEOps]>;
 169 def : ProcNoItin<"arm968e-s",       [HasV5TEOps]>;
 170 def : ProcNoItin<"arm10e",          [HasV5TEOps]>;
 171 def : ProcNoItin<"arm1020e",        [HasV5TEOps]>;
 172 def : ProcNoItin<"arm1022e",        [HasV5TEOps]>;
 173 def : ProcNoItin<"xscale",          [HasV5TEOps]>;
 174 def : ProcNoItin<"iwmmxt",          [HasV5TEOps]>;
 175
 176 // V6 Processors.
 177 def : Processor<"arm1136j-s",       ARMV6Itineraries, [HasV6Ops]>;
 178 def : Processor<"arm1136jf-s",      ARMV6Itineraries, [HasV6Ops, FeatureVFP2,
 179                                                        FeatureHasSlowFPVMLx]>;
 180 def : Processor<"arm1176jz-s",      ARMV6Itineraries, [HasV6Ops]>;
 181 def : Processor<"arm1176jzf-s",     ARMV6Itineraries, [HasV6Ops, FeatureVFP2,
 182                                                        FeatureHasSlowFPVMLx]>;
 183 def : Processor<"mpcorenovfp",      ARMV6Itineraries, [HasV6Ops]>;
 184 def : Processor<"mpcore",           ARMV6Itineraries, [HasV6Ops, FeatureVFP2,
 185                                                        FeatureHasSlowFPVMLx]>;
 186
 187 // V6M Processors.
 188 def : Processor<"cortex-m0",        ARMV6Itineraries, [HasV6Ops, FeatureNoARM,
 189                                                        FeatureDB, FeatureMClass]>;
 190
 191 // V6T2 Processors.
 192 def : Processor<"arm1156t2-s",      ARMV6Itineraries, [HasV6T2Ops,
 193                                                        FeatureDSPThumb2]>;
 194 def : Processor<"arm1156t2f-s",     ARMV6Itineraries, [HasV6T2Ops, FeatureVFP2,
 195                                                        FeatureHasSlowFPVMLx,
 196                                                        FeatureDSPThumb2]>;
 197
 198 // V7a Processors.
 199 def : Processor<"cortex-a8",        CortexA8Itineraries,
 200                                     [ProcA8, HasV7Ops, FeatureNEON, FeatureDB,
 201                                      FeatureDSPThumb2]>;
 202 def : Processor<"cortex-a9",        CortexA9Itineraries,
 203                                     [ProcA9, HasV7Ops, FeatureNEON, FeatureDB,
 204                                      FeatureDSPThumb2]>;
 205 def : Processor<"cortex-a9-mp",     CortexA9Itineraries,
 206                                     [ProcA9, HasV7Ops, FeatureNEON, FeatureDB,
 207                                      FeatureDSPThumb2, FeatureMP]>;
 208
 209 // V7M Processors.
 210 def : ProcNoItin<"cortex-m3",       [HasV7Ops,
 211                                      FeatureThumb2, FeatureNoARM, FeatureDB,
 212                                      FeatureHWDiv, FeatureMClass]>;
 213
 214 // V7EM Processors.
 215 def : ProcNoItin<"cortex-m4",       [HasV7Ops,
 216                                      FeatureThumb2, FeatureNoARM, FeatureDB,
 217                                      FeatureHWDiv, FeatureDSPThumb2,
 218                                      FeatureT2XtPk, FeatureVFP2,
 219                                      FeatureVFPOnlySP, FeatureMClass]>;
 220
 221 //===----------------------------------------------------------------------===//
 222 // Register File Description
 223 //===----------------------------------------------------------------------===//
 224
 225 include "ARMRegisterInfo.td"
 226
 227 include "ARMCallingConv.td"
 228
 229 //===----------------------------------------------------------------------===//
 230 // Instruction Descriptions
 231 //===----------------------------------------------------------------------===//
 232
 233 include "ARMInstrInfo.td"
 234
 235 def ARMInstrInfo : InstrInfo;
 236
 237
 238 //===----------------------------------------------------------------------===//
 239 // Assembly printer
 240 //===----------------------------------------------------------------------===//
 241 // ARM Uses the MC printer for asm output, so make sure the TableGen
 242 // AsmWriter bits get associated with the correct class.
 243 def ARMAsmWriter : AsmWriter {
 244   string AsmWriterClassName  = "InstPrinter";
 245   bit isMCAsmWriter = 1;
 246 }
 247
 248 //===----------------------------------------------------------------------===//
 249 // Declare the target which we are implementing
 250 //===----------------------------------------------------------------------===//
 251
 252 def ARM : Target {
 253   // Pull in Instruction Info:
 254   let InstructionSet = ARMInstrInfo;
 255
 256   let AssemblyWriters = [ARMAsmWriter];
 257 }