1 //===-- ARM.td - Describe the ARM Target Machine -----------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
13 //===----------------------------------------------------------------------===//
14 // Target-independent interfaces which we are implementing
15 //===----------------------------------------------------------------------===//
17 include "llvm/Target/Target.td"
19 //===----------------------------------------------------------------------===//
20 // ARM Subtarget state.
23 def ModeThumb : SubtargetFeature<"thumb-mode", "InThumbMode", "true",
26 //===----------------------------------------------------------------------===//
27 // ARM Subtarget features.
30 def FeatureVFP2 : SubtargetFeature<"vfp2", "HasVFPv2", "true",
31 "Enable VFP2 instructions">;
32 def FeatureVFP3 : SubtargetFeature<"vfp3", "HasVFPv3", "true",
33 "Enable VFP3 instructions",
35 def FeatureNEON : SubtargetFeature<"neon", "HasNEON", "true",
36 "Enable NEON instructions",
38 def FeatureThumb2 : SubtargetFeature<"thumb2", "HasThumb2", "true",
39 "Enable Thumb2 instructions">;
40 def FeatureNoARM : SubtargetFeature<"noarm", "NoARM", "true",
41 "Does not support ARM mode execution">;
42 def FeatureFP16 : SubtargetFeature<"fp16", "HasFP16", "true",
43 "Enable half-precision floating point">;
44 def FeatureVFP4 : SubtargetFeature<"vfp4", "HasVFPv4", "true",
45 "Enable VFP4 instructions",
46 [FeatureVFP3, FeatureFP16]>;
47 def FeatureD16 : SubtargetFeature<"d16", "HasD16", "true",
48 "Restrict VFP3 to 16 double registers">;
49 def FeatureHWDiv : SubtargetFeature<"hwdiv", "HasHardwareDivide", "true",
50 "Enable divide instructions">;
51 def FeatureHWDivARM : SubtargetFeature<"hwdiv-arm",
52 "HasHardwareDivideInARM", "true",
53 "Enable divide instructions in ARM mode">;
54 def FeatureT2XtPk : SubtargetFeature<"t2xtpk", "HasT2ExtractPack", "true",
55 "Enable Thumb2 extract and pack instructions">;
56 def FeatureDB : SubtargetFeature<"db", "HasDataBarrier", "true",
57 "Has data barrier (dmb / dsb) instructions">;
58 def FeatureSlowFPBrcc : SubtargetFeature<"slow-fp-brcc", "SlowFPBrcc", "true",
59 "FP compare + branch is slow">;
60 def FeatureVFPOnlySP : SubtargetFeature<"fp-only-sp", "FPOnlySP", "true",
61 "Floating point unit supports single precision only">;
63 // Some processors have FP multiply-accumulate instructions that don't
64 // play nicely with other VFP / NEON instructions, and it's generally better
65 // to just not use them.
66 def FeatureHasSlowFPVMLx : SubtargetFeature<"slowfpvmlx", "SlowFPVMLx", "true",
67 "Disable VFP / NEON MAC instructions">;
69 // Cortex-A8 / A9 Advanced SIMD has multiplier accumulator forwarding.
70 def FeatureVMLxForwarding : SubtargetFeature<"vmlx-forwarding",
71 "HasVMLxForwarding", "true",
72 "Has multiplier accumulator forwarding">;
74 // Some processors benefit from using NEON instructions for scalar
75 // single-precision FP operations.
76 def FeatureNEONForFP : SubtargetFeature<"neonfp", "UseNEONForSinglePrecisionFP",
78 "Use NEON for single precision FP">;
80 // Disable 32-bit to 16-bit narrowing for experimentation.
81 def FeaturePref32BitThumb : SubtargetFeature<"32bit", "Pref32BitThumb", "true",
82 "Prefer 32-bit Thumb instrs">;
84 /// Some instructions update CPSR partially, which can add false dependency for
85 /// out-of-order implementation, e.g. Cortex-A9, unless each individual bit is
86 /// mapped to a separate physical register. Avoid partial CPSR update for these
88 def FeatureAvoidPartialCPSR : SubtargetFeature<"avoid-partial-cpsr",
89 "AvoidCPSRPartialUpdate", "true",
90 "Avoid CPSR partial update for OOO execution">;
92 def FeatureAvoidMOVsShOp : SubtargetFeature<"avoid-movs-shop",
93 "AvoidMOVsShifterOperand", "true",
94 "Avoid movs instructions with shifter operand">;
96 // Some processors perform return stack prediction. CodeGen should avoid issue
97 // "normal" call instructions to callees which do not return.
98 def FeatureHasRAS : SubtargetFeature<"ras", "HasRAS", "true",
99 "Has return address stack">;
101 /// Some M architectures don't have the DSP extension (v7E-M vs. v7M)
102 def FeatureDSPThumb2 : SubtargetFeature<"t2dsp", "Thumb2DSP", "true",
103 "Supports v7 DSP instructions in Thumb2">;
105 // Multiprocessing extension.
106 def FeatureMP : SubtargetFeature<"mp", "HasMPExtension", "true",
107 "Supports Multiprocessing extension">;
110 def FeatureMClass : SubtargetFeature<"mclass", "IsMClass", "true",
111 "Is microcontroller profile ('M' series)">;
113 // Special TRAP encoding for NaCl, which looks like a TRAP in Thumb too.
114 // See ARMInstrInfo.td for details.
115 def FeatureNaClTrap : SubtargetFeature<"nacl-trap", "UseNaClTrap", "true",
119 def HasV4TOps : SubtargetFeature<"v4t", "HasV4TOps", "true",
120 "Support ARM v4T instructions">;
121 def HasV5TOps : SubtargetFeature<"v5t", "HasV5TOps", "true",
122 "Support ARM v5T instructions",
124 def HasV5TEOps : SubtargetFeature<"v5te", "HasV5TEOps", "true",
125 "Support ARM v5TE, v5TEj, and v5TExp instructions",
127 def HasV6Ops : SubtargetFeature<"v6", "HasV6Ops", "true",
128 "Support ARM v6 instructions",
130 def HasV6T2Ops : SubtargetFeature<"v6t2", "HasV6T2Ops", "true",
131 "Support ARM v6t2 instructions",
132 [HasV6Ops, FeatureThumb2]>;
133 def HasV7Ops : SubtargetFeature<"v7", "HasV7Ops", "true",
134 "Support ARM v7 instructions",
137 //===----------------------------------------------------------------------===//
138 // ARM Processors supported.
141 include "ARMSchedule.td"
143 // ARM processor families.
144 def ProcA5 : SubtargetFeature<"a5", "ARMProcFamily", "CortexA5",
145 "Cortex-A5 ARM processors",
146 [FeatureSlowFPBrcc, FeatureNEONForFP,
147 FeatureHasSlowFPVMLx, FeatureVMLxForwarding,
149 def ProcA8 : SubtargetFeature<"a8", "ARMProcFamily", "CortexA8",
150 "Cortex-A8 ARM processors",
151 [FeatureSlowFPBrcc, FeatureNEONForFP,
152 FeatureHasSlowFPVMLx, FeatureVMLxForwarding,
154 def ProcA9 : SubtargetFeature<"a9", "ARMProcFamily", "CortexA9",
155 "Cortex-A9 ARM processors",
156 [FeatureVMLxForwarding,
157 FeatureT2XtPk, FeatureFP16,
158 FeatureAvoidPartialCPSR]>;
159 def ProcSwift : SubtargetFeature<"swift", "ARMProcFamily", "Swift",
160 "Swift ARM processors",
161 [FeatureNEONForFP, FeatureT2XtPk,
162 FeatureVFP4, FeatureMP, FeatureHWDiv,
163 FeatureHWDivARM, FeatureAvoidPartialCPSR,
164 FeatureAvoidMOVsShOp,
165 FeatureHasSlowFPVMLx]>;
167 // FIXME: It has not been determined if A15 has these features.
168 def ProcA15 : SubtargetFeature<"a15", "ARMProcFamily", "CortexA15",
169 "Cortex-A15 ARM processors",
170 [FeatureT2XtPk, FeatureFP16,
171 FeatureAvoidPartialCPSR]>;
172 def ProcR5 : SubtargetFeature<"r5", "ARMProcFamily", "CortexR5",
173 "Cortex-R5 ARM processors",
174 [FeatureSlowFPBrcc, FeatureHWDivARM,
175 FeatureHasSlowFPVMLx,
176 FeatureAvoidPartialCPSR,
179 class ProcNoItin<string Name, list<SubtargetFeature> Features>
180 : Processor<Name, NoItineraries, Features>;
183 def : ProcNoItin<"generic", []>;
184 def : ProcNoItin<"arm8", []>;
185 def : ProcNoItin<"arm810", []>;
186 def : ProcNoItin<"strongarm", []>;
187 def : ProcNoItin<"strongarm110", []>;
188 def : ProcNoItin<"strongarm1100", []>;
189 def : ProcNoItin<"strongarm1110", []>;
192 def : ProcNoItin<"arm7tdmi", [HasV4TOps]>;
193 def : ProcNoItin<"arm7tdmi-s", [HasV4TOps]>;
194 def : ProcNoItin<"arm710t", [HasV4TOps]>;
195 def : ProcNoItin<"arm720t", [HasV4TOps]>;
196 def : ProcNoItin<"arm9", [HasV4TOps]>;
197 def : ProcNoItin<"arm9tdmi", [HasV4TOps]>;
198 def : ProcNoItin<"arm920", [HasV4TOps]>;
199 def : ProcNoItin<"arm920t", [HasV4TOps]>;
200 def : ProcNoItin<"arm922t", [HasV4TOps]>;
201 def : ProcNoItin<"arm940t", [HasV4TOps]>;
202 def : ProcNoItin<"ep9312", [HasV4TOps]>;
205 def : ProcNoItin<"arm10tdmi", [HasV5TOps]>;
206 def : ProcNoItin<"arm1020t", [HasV5TOps]>;
209 def : ProcNoItin<"arm9e", [HasV5TEOps]>;
210 def : ProcNoItin<"arm926ej-s", [HasV5TEOps]>;
211 def : ProcNoItin<"arm946e-s", [HasV5TEOps]>;
212 def : ProcNoItin<"arm966e-s", [HasV5TEOps]>;
213 def : ProcNoItin<"arm968e-s", [HasV5TEOps]>;
214 def : ProcNoItin<"arm10e", [HasV5TEOps]>;
215 def : ProcNoItin<"arm1020e", [HasV5TEOps]>;
216 def : ProcNoItin<"arm1022e", [HasV5TEOps]>;
217 def : ProcNoItin<"xscale", [HasV5TEOps]>;
218 def : ProcNoItin<"iwmmxt", [HasV5TEOps]>;
221 def : Processor<"arm1136j-s", ARMV6Itineraries, [HasV6Ops]>;
222 def : Processor<"arm1136jf-s", ARMV6Itineraries, [HasV6Ops, FeatureVFP2,
223 FeatureHasSlowFPVMLx]>;
224 def : Processor<"arm1176jz-s", ARMV6Itineraries, [HasV6Ops]>;
225 def : Processor<"arm1176jzf-s", ARMV6Itineraries, [HasV6Ops, FeatureVFP2,
226 FeatureHasSlowFPVMLx]>;
227 def : Processor<"mpcorenovfp", ARMV6Itineraries, [HasV6Ops]>;
228 def : Processor<"mpcore", ARMV6Itineraries, [HasV6Ops, FeatureVFP2,
229 FeatureHasSlowFPVMLx]>;
232 def : Processor<"cortex-m0", ARMV6Itineraries, [HasV6Ops, FeatureNoARM,
233 FeatureDB, FeatureMClass]>;
236 def : Processor<"arm1156t2-s", ARMV6Itineraries, [HasV6T2Ops,
238 def : Processor<"arm1156t2f-s", ARMV6Itineraries, [HasV6T2Ops, FeatureVFP2,
239 FeatureHasSlowFPVMLx,
243 // FIXME: A5 has currently the same Schedule model as A8
244 def : ProcessorModel<"cortex-a5", CortexA8Model,
245 [ProcA5, HasV7Ops, FeatureNEON, FeatureDB,
246 FeatureVFP4, FeatureDSPThumb2,
248 def : ProcessorModel<"cortex-a8", CortexA8Model,
249 [ProcA8, HasV7Ops, FeatureNEON, FeatureDB,
250 FeatureDSPThumb2, FeatureHasRAS]>;
251 def : ProcessorModel<"cortex-a9", CortexA9Model,
252 [ProcA9, HasV7Ops, FeatureNEON, FeatureDB,
253 FeatureDSPThumb2, FeatureHasRAS]>;
254 def : ProcessorModel<"cortex-a9-mp", CortexA9Model,
255 [ProcA9, HasV7Ops, FeatureNEON, FeatureDB,
256 FeatureDSPThumb2, FeatureMP,
258 // FIXME: A15 has currently the same ProcessorModel as A9.
259 def : ProcessorModel<"cortex-a15", CortexA9Model,
260 [ProcA15, HasV7Ops, FeatureNEON, FeatureDB,
261 FeatureDSPThumb2, FeatureHasRAS]>;
262 // FIXME: R5 has currently the same ProcessorModel as A8.
263 def : ProcessorModel<"cortex-r5", CortexA8Model,
264 [ProcR5, HasV7Ops, FeatureDB,
265 FeatureVFP3, FeatureDSPThumb2,
269 def : ProcNoItin<"cortex-m3", [HasV7Ops,
270 FeatureThumb2, FeatureNoARM, FeatureDB,
271 FeatureHWDiv, FeatureMClass]>;
274 def : ProcNoItin<"cortex-m4", [HasV7Ops,
275 FeatureThumb2, FeatureNoARM, FeatureDB,
276 FeatureHWDiv, FeatureDSPThumb2,
277 FeatureT2XtPk, FeatureVFP4,
278 FeatureVFPOnlySP, FeatureMClass]>;
280 // Swift uArch Processors.
281 def : ProcessorModel<"swift", SwiftModel,
282 [ProcSwift, HasV7Ops, FeatureNEON,
283 FeatureDB, FeatureDSPThumb2,
286 //===----------------------------------------------------------------------===//
287 // Register File Description
288 //===----------------------------------------------------------------------===//
290 include "ARMRegisterInfo.td"
292 include "ARMCallingConv.td"
294 //===----------------------------------------------------------------------===//
295 // Instruction Descriptions
296 //===----------------------------------------------------------------------===//
298 include "ARMInstrInfo.td"
300 def ARMInstrInfo : InstrInfo;
303 //===----------------------------------------------------------------------===//
305 //===----------------------------------------------------------------------===//
306 // ARM Uses the MC printer for asm output, so make sure the TableGen
307 // AsmWriter bits get associated with the correct class.
308 def ARMAsmWriter : AsmWriter {
309 string AsmWriterClassName = "InstPrinter";
310 bit isMCAsmWriter = 1;
313 //===----------------------------------------------------------------------===//
314 // Declare the target which we are implementing
315 //===----------------------------------------------------------------------===//
318 // Pull in Instruction Info:
319 let InstructionSet = ARMInstrInfo;
321 let AssemblyWriters = [ARMAsmWriter];