1 //===-- SIRegisterInfo.td - SI Register defs ---------------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 //===----------------------------------------------------------------------===//
11 // Declarations that describe the SI registers
12 //===----------------------------------------------------------------------===//
13 class SIReg <string n, bits<16> regIdx = 0> : Register<n>,
14 DwarfRegNum<[!cast<int>(HWEncoding)]> {
15 let Namespace = "AMDGPU";
17 // This is the not yet the complete register encoding. An additional
18 // bit is set for VGPRs.
19 let HWEncoding = regIdx;
23 def VCC_LO : SIReg<"vcc_lo", 106>;
24 def VCC_HI : SIReg<"vcc_hi", 107>;
26 // VCC for 64-bit instructions
27 def VCC : RegisterWithSubRegs<"vcc", [VCC_LO, VCC_HI]>,
28 DwarfRegAlias<VCC_LO> {
29 let Namespace = "AMDGPU";
30 let SubRegIndices = [sub0, sub1];
34 def EXEC_LO : SIReg<"exec_lo", 126>;
35 def EXEC_HI : SIReg<"exec_hi", 127>;
37 def EXEC : RegisterWithSubRegs<"EXEC", [EXEC_LO, EXEC_HI]>,
38 DwarfRegAlias<EXEC_LO> {
39 let Namespace = "AMDGPU";
40 let SubRegIndices = [sub0, sub1];
44 def SCC : SIReg<"scc", 253>;
45 def M0 : SIReg <"m0", 124>;
47 multiclass FLAT_SCR_LOHI_m <string n, bits<16> ci_e, bits<16> vi_e> {
48 def _ci : SIReg<n, ci_e>;
49 def _vi : SIReg<n, vi_e>;
50 def "" : SIReg<"", 0>;
53 class FlatReg <Register lo, Register hi, bits<16> encoding> :
54 RegisterWithSubRegs<"flat_scratch", [lo, hi]>,
56 let Namespace = "AMDGPU";
57 let SubRegIndices = [sub0, sub1];
58 let HWEncoding = encoding;
61 defm FLAT_SCR_LO : FLAT_SCR_LOHI_m<"flat_scratch_lo", 104, 102>; // Offset in units of 256-bytes.
62 defm FLAT_SCR_HI : FLAT_SCR_LOHI_m<"flat_scratch_hi", 105, 103>; // Size is the per-thread scratch size, in bytes.
64 def FLAT_SCR_ci : FlatReg<FLAT_SCR_LO_ci, FLAT_SCR_HI_ci, 104>;
65 def FLAT_SCR_vi : FlatReg<FLAT_SCR_LO_vi, FLAT_SCR_HI_vi, 102>;
66 def FLAT_SCR : FlatReg<FLAT_SCR_LO, FLAT_SCR_HI, 0>;
69 foreach Index = 0-103 in {
70 def SGPR#Index : SIReg <"SGPR"#Index, Index>;
74 foreach Index = 0-255 in {
75 def VGPR#Index : SIReg <"VGPR"#Index, Index> {
76 let HWEncoding{8} = 1;
80 //===----------------------------------------------------------------------===//
81 // Groupings using register classes and tuples
82 //===----------------------------------------------------------------------===//
84 // TODO: Do we need to set DwarfRegAlias on register tuples?
86 // SGPR 32-bit registers
87 def SGPR_32 : RegisterClass<"AMDGPU", [i32, f32], 32,
88 (add (sequence "SGPR%u", 0, 103))>;
90 // SGPR 64-bit registers
91 def SGPR_64Regs : RegisterTuples<[sub0, sub1],
92 [(add (decimate SGPR_32, 2)),
93 (add (decimate (shl SGPR_32, 1), 2))]>;
95 // SGPR 128-bit registers
96 def SGPR_128 : RegisterTuples<[sub0, sub1, sub2, sub3],
97 [(add (decimate SGPR_32, 4)),
98 (add (decimate (shl SGPR_32, 1), 4)),
99 (add (decimate (shl SGPR_32, 2), 4)),
100 (add (decimate (shl SGPR_32, 3), 4))]>;
102 // SGPR 256-bit registers
103 def SGPR_256 : RegisterTuples<[sub0, sub1, sub2, sub3, sub4, sub5, sub6, sub7],
104 [(add (decimate SGPR_32, 4)),
105 (add (decimate (shl SGPR_32, 1), 4)),
106 (add (decimate (shl SGPR_32, 2), 4)),
107 (add (decimate (shl SGPR_32, 3), 4)),
108 (add (decimate (shl SGPR_32, 4), 4)),
109 (add (decimate (shl SGPR_32, 5), 4)),
110 (add (decimate (shl SGPR_32, 6), 4)),
111 (add (decimate (shl SGPR_32, 7), 4))]>;
113 // SGPR 512-bit registers
114 def SGPR_512 : RegisterTuples<[sub0, sub1, sub2, sub3, sub4, sub5, sub6, sub7,
115 sub8, sub9, sub10, sub11, sub12, sub13, sub14, sub15],
116 [(add (decimate SGPR_32, 4)),
117 (add (decimate (shl SGPR_32, 1), 4)),
118 (add (decimate (shl SGPR_32, 2), 4)),
119 (add (decimate (shl SGPR_32, 3), 4)),
120 (add (decimate (shl SGPR_32, 4), 4)),
121 (add (decimate (shl SGPR_32, 5), 4)),
122 (add (decimate (shl SGPR_32, 6), 4)),
123 (add (decimate (shl SGPR_32, 7), 4)),
124 (add (decimate (shl SGPR_32, 8), 4)),
125 (add (decimate (shl SGPR_32, 9), 4)),
126 (add (decimate (shl SGPR_32, 10), 4)),
127 (add (decimate (shl SGPR_32, 11), 4)),
128 (add (decimate (shl SGPR_32, 12), 4)),
129 (add (decimate (shl SGPR_32, 13), 4)),
130 (add (decimate (shl SGPR_32, 14), 4)),
131 (add (decimate (shl SGPR_32, 15), 4))]>;
133 // VGPR 32-bit registers
134 def VGPR_32 : RegisterClass<"AMDGPU", [i32, f32], 32,
135 (add (sequence "VGPR%u", 0, 255))>;
137 // VGPR 64-bit registers
138 def VGPR_64 : RegisterTuples<[sub0, sub1],
139 [(add (trunc VGPR_32, 255)),
140 (add (shl VGPR_32, 1))]>;
142 // VGPR 96-bit registers
143 def VGPR_96 : RegisterTuples<[sub0, sub1, sub2],
144 [(add (trunc VGPR_32, 254)),
145 (add (shl VGPR_32, 1)),
146 (add (shl VGPR_32, 2))]>;
148 // VGPR 128-bit registers
149 def VGPR_128 : RegisterTuples<[sub0, sub1, sub2, sub3],
150 [(add (trunc VGPR_32, 253)),
151 (add (shl VGPR_32, 1)),
152 (add (shl VGPR_32, 2)),
153 (add (shl VGPR_32, 3))]>;
155 // VGPR 256-bit registers
156 def VGPR_256 : RegisterTuples<[sub0, sub1, sub2, sub3, sub4, sub5, sub6, sub7],
157 [(add (trunc VGPR_32, 249)),
158 (add (shl VGPR_32, 1)),
159 (add (shl VGPR_32, 2)),
160 (add (shl VGPR_32, 3)),
161 (add (shl VGPR_32, 4)),
162 (add (shl VGPR_32, 5)),
163 (add (shl VGPR_32, 6)),
164 (add (shl VGPR_32, 7))]>;
166 // VGPR 512-bit registers
167 def VGPR_512 : RegisterTuples<[sub0, sub1, sub2, sub3, sub4, sub5, sub6, sub7,
168 sub8, sub9, sub10, sub11, sub12, sub13, sub14, sub15],
169 [(add (trunc VGPR_32, 241)),
170 (add (shl VGPR_32, 1)),
171 (add (shl VGPR_32, 2)),
172 (add (shl VGPR_32, 3)),
173 (add (shl VGPR_32, 4)),
174 (add (shl VGPR_32, 5)),
175 (add (shl VGPR_32, 6)),
176 (add (shl VGPR_32, 7)),
177 (add (shl VGPR_32, 8)),
178 (add (shl VGPR_32, 9)),
179 (add (shl VGPR_32, 10)),
180 (add (shl VGPR_32, 11)),
181 (add (shl VGPR_32, 12)),
182 (add (shl VGPR_32, 13)),
183 (add (shl VGPR_32, 14)),
184 (add (shl VGPR_32, 15))]>;
186 //===----------------------------------------------------------------------===//
187 // Register classes used as source and destination
188 //===----------------------------------------------------------------------===//
190 class RegImmMatcher<string name> : AsmOperandClass {
192 let RenderMethod = "addRegOrImmOperands";
195 // Register class for all scalar registers (SGPRs + Special Registers)
196 def SReg_32 : RegisterClass<"AMDGPU", [i32, f32], 32,
197 (add SGPR_32, M0, VCC_LO, VCC_HI, EXEC_LO, EXEC_HI, FLAT_SCR_LO, FLAT_SCR_HI)
200 def SGPR_64 : RegisterClass<"AMDGPU", [v2i32, i64, f64], 32, (add SGPR_64Regs)>;
202 def SReg_64 : RegisterClass<"AMDGPU", [v2i32, i64, f64, i1], 32,
203 (add SGPR_64, VCC, EXEC, FLAT_SCR)
206 def SReg_128 : RegisterClass<"AMDGPU", [v4i32, v16i8, v2i64], 32, (add SGPR_128)> {
207 // Requires 2 s_mov_b64 to copy
211 def SReg_256 : RegisterClass<"AMDGPU", [v32i8, v8i32, v8f32], 32, (add SGPR_256)> {
212 // Requires 4 s_mov_b64 to copy
216 def SReg_512 : RegisterClass<"AMDGPU", [v64i8, v16i32], 32, (add SGPR_512)> {
217 // Requires 8 s_mov_b64 to copy
221 // Register class for all vector registers (VGPRs + Interploation Registers)
222 def VReg_64 : RegisterClass<"AMDGPU", [i64, f64, v2i32, v2f32], 32, (add VGPR_64)> {
223 // Requires 2 v_mov_b32 to copy
227 def VReg_96 : RegisterClass<"AMDGPU", [untyped], 32, (add VGPR_96)> {
230 // Requires 3 v_mov_b32 to copy
234 def VReg_128 : RegisterClass<"AMDGPU", [v4i32, v4f32, v2i64, v2f64], 32, (add VGPR_128)> {
235 // Requires 4 v_mov_b32 to copy
239 def VReg_256 : RegisterClass<"AMDGPU", [v32i8, v8i32, v8f32], 32, (add VGPR_256)> {
243 def VReg_512 : RegisterClass<"AMDGPU", [v16i32, v16f32], 32, (add VGPR_512)> {
247 def VReg_1 : RegisterClass<"AMDGPU", [i1], 32, (add VGPR_32)> {
251 class RegImmOperand <RegisterClass rc> : RegisterOperand<rc> {
252 let OperandNamespace = "AMDGPU";
253 let OperandType = "OPERAND_REG_IMM32";
256 class RegInlineOperand <RegisterClass rc> : RegisterOperand<rc> {
257 let OperandNamespace = "AMDGPU";
258 let OperandType = "OPERAND_REG_INLINE_C";
261 //===----------------------------------------------------------------------===//
262 // SSrc_* Operands with an SGPR or a 32-bit immediate
263 //===----------------------------------------------------------------------===//
265 def SSrc_32 : RegImmOperand<SReg_32> {
266 let ParserMatchClass = RegImmMatcher<"SSrc32">;
269 def SSrc_64 : RegImmOperand<SReg_64> {
270 let ParserMatchClass = RegImmMatcher<"SSrc64">;
273 //===----------------------------------------------------------------------===//
274 // SCSrc_* Operands with an SGPR or a inline constant
275 //===----------------------------------------------------------------------===//
277 def SCSrc_32 : RegInlineOperand<SReg_32> {
278 let ParserMatchClass = RegImmMatcher<"SCSrc32">;
281 //===----------------------------------------------------------------------===//
282 // VSrc_* Operands with an SGPR, VGPR or a 32-bit immediate
283 //===----------------------------------------------------------------------===//
285 def VS_32 : RegisterClass<"AMDGPU", [i32, f32], 32, (add VGPR_32, SReg_32)>;
287 def VS_64 : RegisterClass<"AMDGPU", [i64, f64], 32, (add VReg_64, SReg_64)> {
291 def VSrc_32 : RegisterOperand<VS_32> {
292 let OperandNamespace = "AMDGPU";
293 let OperandType = "OPERAND_REG_IMM32";
294 let ParserMatchClass = RegImmMatcher<"VSrc32">;
297 def VSrc_64 : RegisterOperand<VS_64> {
298 let OperandNamespace = "AMDGPU";
299 let OperandType = "OPERAND_REG_IMM32";
300 let ParserMatchClass = RegImmMatcher<"VSrc64">;
303 //===----------------------------------------------------------------------===//
304 // VCSrc_* Operands with an SGPR, VGPR or an inline constant
305 //===----------------------------------------------------------------------===//
307 def VCSrc_32 : RegisterOperand<VS_32> {
308 let OperandNamespace = "AMDGPU";
309 let OperandType = "OPERAND_REG_INLINE_C";
310 let ParserMatchClass = RegImmMatcher<"VCSrc32">;
313 def VCSrc_64 : RegisterOperand<VS_64> {
314 let OperandNamespace = "AMDGPU";
315 let OperandType = "OPERAND_REG_INLINE_C";
316 let ParserMatchClass = RegImmMatcher<"VCSrc64">;
319 //===----------------------------------------------------------------------===//
320 // SCSrc_* Operands with an SGPR or an inline constant
321 //===----------------------------------------------------------------------===//
323 def SCSrc_64 : RegisterOperand<SReg_64> {
324 let OperandNamespace = "AMDGPU";
325 let OperandType = "OPERAND_REG_INLINE_C";
326 let ParserMatchClass = RegImmMatcher<"SCSrc64">;