1 //===-- SIRegisterInfo.h - SI Register Info Interface ----------*- C++ -*--===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// \brief Interface definition for SIRegisterInfo
13 //===----------------------------------------------------------------------===//
16 #ifndef LLVM_LIB_TARGET_R600_SIREGISTERINFO_H
17 #define LLVM_LIB_TARGET_R600_SIREGISTERINFO_H
19 #include "AMDGPURegisterInfo.h"
20 #include "AMDGPUSubtarget.h"
21 #include "llvm/Support/Debug.h"
25 struct SIRegisterInfo : public AMDGPURegisterInfo {
27 void reserveRegisterTuples(BitVector &, unsigned Reg) const;
32 /// Return the end register initially reserved for the scratch buffer in case
33 /// spilling is needed.
34 unsigned reservedPrivateSegmentBufferReg(const MachineFunction &MF) const;
36 /// Return the end register initially reserved for the scratch wave offset in
37 /// case spilling is needed.
38 unsigned reservedPrivateSegmentWaveByteOffsetReg(
39 const MachineFunction &MF) const;
41 BitVector getReservedRegs(const MachineFunction &MF) const override;
43 unsigned getRegPressureSetLimit(const MachineFunction &MF,
44 unsigned Idx) const override;
46 bool requiresRegisterScavenging(const MachineFunction &Fn) const override;
48 void eliminateFrameIndex(MachineBasicBlock::iterator MI, int SPAdj,
49 unsigned FIOperandNum,
50 RegScavenger *RS) const override;
52 unsigned getHWRegIndex(unsigned Reg) const override;
54 /// \brief Return the 'base' register class for this register.
55 /// e.g. SGPR0 => SReg_32, VGPR => VGPR_32 SGPR0_SGPR1 -> SReg_32, etc.
56 const TargetRegisterClass *getPhysRegClass(unsigned Reg) const;
58 /// \returns true if this class contains only SGPR registers
59 bool isSGPRClass(const TargetRegisterClass *RC) const {
63 /// \returns true if this class ID contains only SGPR registers
64 bool isSGPRClassID(unsigned RCID) const {
65 return isSGPRClass(getRegClass(RCID));
68 /// \returns true if this class contains VGPR registers.
69 bool hasVGPRs(const TargetRegisterClass *RC) const;
71 /// returns true if this is a pseudoregister class combination of VGPRs and
72 /// SGPRs for operand modeling. FIXME: We should set isAllocatable = 0 on
74 static bool isPseudoRegClass(const TargetRegisterClass *RC) {
75 return RC == &AMDGPU::VS_32RegClass || RC == &AMDGPU::VS_64RegClass;
78 /// \returns A VGPR reg class with the same width as \p SRC
79 const TargetRegisterClass *getEquivalentVGPRClass(
80 const TargetRegisterClass *SRC) const;
82 /// \returns The register class that is used for a sub-register of \p RC for
83 /// the given \p SubIdx. If \p SubIdx equals NoSubRegister, \p RC will
85 const TargetRegisterClass *getSubRegClass(const TargetRegisterClass *RC,
86 unsigned SubIdx) const;
88 bool shouldRewriteCopySrc(const TargetRegisterClass *DefRC,
90 const TargetRegisterClass *SrcRC,
91 unsigned SrcSubReg) const override;
93 /// \p Channel This is the register channel (e.g. a value from 0-16), not the
95 /// \returns The sub-register of Reg that is in Channel.
96 unsigned getPhysRegSubReg(unsigned Reg, const TargetRegisterClass *SubRC,
97 unsigned Channel) const;
99 /// \returns True if operands defined with this operand type can accept
100 /// a literal constant (i.e. any 32-bit immediate).
101 bool opCanUseLiteralConstant(unsigned OpType) const;
103 /// \returns True if operands defined with this operand type can accept
104 /// an inline constant. i.e. An integer value in the range (-16, 64) or
105 /// -4.0f, -2.0f, -1.0f, -0.5f, 0.0f, 0.5f, 1.0f, 2.0f, 4.0f.
106 bool opCanUseInlineConstant(unsigned OpType) const;
108 enum PreloadedValue {
110 PRIVATE_SEGMENT_BUFFER = 0,
113 KERNARG_SEGMENT_PTR = 3,
117 PRIVATE_SEGMENT_WAVE_BYTE_OFFSET = 14,
120 FIRST_VGPR_VALUE = 15,
121 WORKITEM_ID_X = FIRST_VGPR_VALUE,
126 /// \brief Returns the physical register that \p Value is stored in.
127 unsigned getPreloadedValue(const MachineFunction &MF,
128 enum PreloadedValue Value) const;
130 /// \brief Give the maximum number of VGPRs that can be used by \p WaveCount
131 /// concurrent waves.
132 unsigned getNumVGPRsAllowed(unsigned WaveCount) const;
134 /// \brief Give the maximum number of SGPRs that can be used by \p WaveCount
135 /// concurrent waves.
136 unsigned getNumSGPRsAllowed(AMDGPUSubtarget::Generation gen,
137 unsigned WaveCount) const;
139 unsigned findUnusedRegister(const MachineRegisterInfo &MRI,
140 const TargetRegisterClass *RC) const;
143 void buildScratchLoadStore(MachineBasicBlock::iterator MI,
144 unsigned LoadStoreOp, unsigned Value,
145 unsigned ScratchRsrcReg, unsigned ScratchOffset,
146 int64_t Offset, RegScavenger *RS) const;
149 } // End namespace llvm