1 //===- SIMachineFunctionInfo.h - SIMachineFunctionInfo interface -*- C++ -*-==//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
12 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_LIB_TARGET_R600_SIMACHINEFUNCTIONINFO_H
16 #define LLVM_LIB_TARGET_R600_SIMACHINEFUNCTIONINFO_H
18 #include "AMDGPUMachineFunction.h"
19 #include "SIRegisterInfo.h"
24 class MachineRegisterInfo;
26 /// This class keeps track of the SPI_SP_INPUT_ADDR config register, which
27 /// tells the hardware which interpolation parameters to load.
28 class SIMachineFunctionInfo : public AMDGPUMachineFunction {
29 // FIXME: This should be removed and getPreloadedValue moved here.
30 friend struct SIRegisterInfo;
31 void anchor() override;
35 // Registers that may be reserved for spilling purposes. These may be the same
36 // as the input registers.
37 unsigned ScratchRSrcReg;
38 unsigned ScratchWaveOffsetReg;
40 // Input registers setup for the HSA ABI.
41 // User SGPRs in allocation order.
42 unsigned PrivateSegmentBufferUserSGPR;
43 unsigned DispatchPtrUserSGPR;
44 unsigned QueuePtrUserSGPR;
45 unsigned KernargSegmentPtrUserSGPR;
46 unsigned DispatchIDUserSGPR;
47 unsigned FlatScratchInitUserSGPR;
48 unsigned PrivateSegmentSizeUserSGPR;
49 unsigned GridWorkGroupCountXUserSGPR;
50 unsigned GridWorkGroupCountYUserSGPR;
51 unsigned GridWorkGroupCountZUserSGPR;
53 // System SGPRs in allocation order.
54 unsigned WorkGroupIDXSystemSGPR;
55 unsigned WorkGroupIDYSystemSGPR;
56 unsigned WorkGroupIDZSystemSGPR;
57 unsigned WorkGroupInfoSystemSGPR;
58 unsigned PrivateSegmentWaveByteOffsetSystemSGPR;
61 // FIXME: Make private
62 unsigned LDSWaveSpillSize;
64 std::map<unsigned, unsigned> LaneVGPRs;
65 unsigned ScratchOffsetReg;
66 unsigned NumUserSGPRs;
67 unsigned NumSystemSGPRs;
73 // Feature bits required for inputs passed in user SGPRs.
74 bool PrivateSegmentBuffer : 1;
78 bool KernargSegmentPtr : 1;
79 bool FlatScratchInit : 1;
80 bool GridWorkgroupCountX : 1;
81 bool GridWorkgroupCountY : 1;
82 bool GridWorkgroupCountZ : 1;
84 // Feature bits required for inputs passed in system SGPRs.
85 bool WorkGroupIDX : 1; // Always initialized.
86 bool WorkGroupIDY : 1;
87 bool WorkGroupIDZ : 1;
88 bool WorkGroupInfo : 1;
89 bool PrivateSegmentWaveByteOffset : 1;
91 bool WorkItemIDX : 1; // Always initialized.
96 MCPhysReg getNextUserSGPR() const {
97 assert(NumSystemSGPRs == 0 && "System SGPRs must be added after user SGPRs");
98 return AMDGPU::SGPR0 + NumUserSGPRs;
101 MCPhysReg getNextSystemSGPR() const {
102 return AMDGPU::SGPR0 + NumUserSGPRs + NumSystemSGPRs;
109 SpilledReg(unsigned R, int L) : VGPR (R), Lane (L) { }
110 SpilledReg() : VGPR(0), Lane(-1) { }
111 bool hasLane() { return Lane != -1;}
114 // SIMachineFunctionInfo definition
116 SIMachineFunctionInfo(const MachineFunction &MF);
117 SpilledReg getSpilledReg(MachineFunction *MF, unsigned FrameIndex,
119 bool hasCalculatedTID() const { return TIDReg != AMDGPU::NoRegister; };
120 unsigned getTIDReg() const { return TIDReg; };
121 void setTIDReg(unsigned Reg) { TIDReg = Reg; }
124 unsigned addPrivateSegmentBuffer(const SIRegisterInfo &TRI);
125 unsigned addDispatchPtr(const SIRegisterInfo &TRI);
126 unsigned addQueuePtr(const SIRegisterInfo &TRI);
127 unsigned addKernargSegmentPtr(const SIRegisterInfo &TRI);
130 unsigned addWorkGroupIDX() {
131 WorkGroupIDXSystemSGPR = getNextSystemSGPR();
133 return WorkGroupIDXSystemSGPR;
136 unsigned addWorkGroupIDY() {
137 WorkGroupIDYSystemSGPR = getNextSystemSGPR();
139 return WorkGroupIDYSystemSGPR;
142 unsigned addWorkGroupIDZ() {
143 WorkGroupIDZSystemSGPR = getNextSystemSGPR();
145 return WorkGroupIDZSystemSGPR;
148 unsigned addWorkGroupInfo() {
149 WorkGroupInfoSystemSGPR = getNextSystemSGPR();
151 return WorkGroupInfoSystemSGPR;
154 unsigned addPrivateSegmentWaveByteOffset() {
155 PrivateSegmentWaveByteOffsetSystemSGPR = getNextSystemSGPR();
157 return PrivateSegmentWaveByteOffsetSystemSGPR;
160 bool hasPrivateSegmentBuffer() const {
161 return PrivateSegmentBuffer;
164 bool hasDispatchPtr() const {
168 bool hasQueuePtr() const {
172 bool hasDispatchID() const {
176 bool hasKernargSegmentPtr() const {
177 return KernargSegmentPtr;
180 bool hasFlatScratchInit() const {
181 return FlatScratchInit;
184 bool hasGridWorkgroupCountX() const {
185 return GridWorkgroupCountX;
188 bool hasGridWorkgroupCountY() const {
189 return GridWorkgroupCountY;
192 bool hasGridWorkgroupCountZ() const {
193 return GridWorkgroupCountZ;
196 bool hasWorkGroupIDX() const {
200 bool hasWorkGroupIDY() const {
204 bool hasWorkGroupIDZ() const {
208 bool hasWorkGroupInfo() const {
209 return WorkGroupInfo;
212 bool hasPrivateSegmentWaveByteOffset() const {
213 return PrivateSegmentWaveByteOffset;
216 bool hasWorkItemIDX() const {
220 bool hasWorkItemIDY() const {
224 bool hasWorkItemIDZ() const {
228 unsigned getNumUserSGPRs() const {
232 unsigned getNumPreloadedSGPRs() const {
233 return NumUserSGPRs + NumSystemSGPRs;
236 unsigned getPrivateSegmentWaveByteOffsetSystemSGPR() const {
237 return PrivateSegmentWaveByteOffsetSystemSGPR;
240 /// \brief Returns the physical register reserved for use as the resource
241 /// descriptor for scratch accesses.
242 unsigned getScratchRSrcReg() const {
243 return ScratchRSrcReg;
246 void setScratchRSrcReg(unsigned Reg) {
247 assert(Reg != AMDGPU::NoRegister && "Should never be unset");
248 ScratchRSrcReg = Reg;
251 unsigned getScratchWaveOffsetReg() const {
252 return ScratchWaveOffsetReg;
255 void setScratchWaveOffsetReg(unsigned Reg) {
256 assert(Reg != AMDGPU::NoRegister && "Should never be unset");
257 ScratchWaveOffsetReg = Reg;
260 bool hasSpilledSGPRs() const {
261 return HasSpilledSGPRs;
264 void setHasSpilledSGPRs(bool Spill = true) {
265 HasSpilledSGPRs = Spill;
268 bool hasSpilledVGPRs() const {
269 return HasSpilledVGPRs;
272 void setHasSpilledVGPRs(bool Spill = true) {
273 HasSpilledVGPRs = Spill;
276 unsigned getMaximumWorkGroupSize(const MachineFunction &MF) const;
279 } // End namespace llvm