1 //===-- SIMachineFunctionInfo.cpp - SI Machine Function Info -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
9 //===----------------------------------------------------------------------===//
12 #include "SIMachineFunctionInfo.h"
13 #include "AMDGPUSubtarget.h"
14 #include "SIInstrInfo.h"
15 #include "llvm/CodeGen/MachineInstrBuilder.h"
16 #include "llvm/CodeGen/MachineFrameInfo.h"
17 #include "llvm/CodeGen/MachineRegisterInfo.h"
18 #include "llvm/IR/Function.h"
19 #include "llvm/IR/LLVMContext.h"
26 // Pin the vtable to this file.
27 void SIMachineFunctionInfo::anchor() {}
29 SIMachineFunctionInfo::SIMachineFunctionInfo(const MachineFunction &MF)
30 : AMDGPUMachineFunction(MF),
31 TIDReg(AMDGPU::NoRegister),
32 ScratchRSrcReg(AMDGPU::NoRegister),
36 HasSpilledSGPRs(false),
37 HasSpilledVGPRs(false),
41 KernargSegmentPtr(true),
42 FlatScratchInit(false),
43 GridWorkgroupCountX(false),
44 GridWorkgroupCountY(false),
45 GridWorkgroupCountZ(false),
53 const Function *F = MF.getFunction();
55 if (F->hasFnAttribute("amdgpu-dispatch-ptr"))
58 if (F->hasFnAttribute("amdgpu-work-group-id-y"))
61 if (F->hasFnAttribute("amdgpu-work-group-id-z"))
64 if (F->hasFnAttribute("amdgpu-work-item-id-y"))
67 if (F->hasFnAttribute("amdgpu-work-item-id-z"))
71 SIMachineFunctionInfo::SpilledReg SIMachineFunctionInfo::getSpilledReg(
75 const MachineFrameInfo *FrameInfo = MF->getFrameInfo();
76 const SIRegisterInfo *TRI = static_cast<const SIRegisterInfo *>(
77 MF->getSubtarget<AMDGPUSubtarget>().getRegisterInfo());
78 MachineRegisterInfo &MRI = MF->getRegInfo();
79 int64_t Offset = FrameInfo->getObjectOffset(FrameIndex);
82 unsigned LaneVGPRIdx = Offset / (64 * 4);
83 unsigned Lane = (Offset / 4) % 64;
85 struct SpilledReg Spill;
87 if (!LaneVGPRs.count(LaneVGPRIdx)) {
88 unsigned LaneVGPR = TRI->findUnusedRegister(MRI, &AMDGPU::VGPR_32RegClass);
89 LaneVGPRs[LaneVGPRIdx] = LaneVGPR;
91 // Add this register as live-in to all blocks to avoid machine verifer
92 // complaining about use of an undefined physical register.
93 for (MachineFunction::iterator BI = MF->begin(), BE = MF->end();
95 BI->addLiveIn(LaneVGPR);
99 Spill.VGPR = LaneVGPRs[LaneVGPRIdx];
104 unsigned SIMachineFunctionInfo::getMaximumWorkGroupSize(
105 const MachineFunction &MF) const {
106 const AMDGPUSubtarget &ST = MF.getSubtarget<AMDGPUSubtarget>();
107 // FIXME: We should get this information from kernel attributes if it
109 return getShaderType() == ShaderType::COMPUTE ? 256 : ST.getWavefrontSize();