1 //===-- SIInstrInfo.td - SI Instruction Infos -------------*- tablegen -*--===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
9 def isCI : Predicate<"Subtarget->getGeneration() "
10 ">= AMDGPUSubtarget::SEA_ISLANDS">;
11 def isCIOnly : Predicate<"Subtarget->getGeneration() =="
12 "AMDGPUSubtarget::SEA_ISLANDS">,
13 AssemblerPredicate <"FeatureSeaIslands">;
15 def DisableInst : Predicate <"false">, AssemblerPredicate<"FeatureDisable">;
22 class vopc <bits<8> si, bits<8> vi = !add(0x40, si)> : vop {
23 field bits<8> SI = si;
24 field bits<8> VI = vi;
26 field bits<9> SI3 = {0, si{7-0}};
27 field bits<10> VI3 = {0, 0, vi{7-0}};
30 class vop1 <bits<8> si, bits<8> vi = si> : vop {
31 field bits<8> SI = si;
32 field bits<8> VI = vi;
34 field bits<9> SI3 = {1, 1, si{6-0}};
35 field bits<10> VI3 = !add(0x140, vi);
38 class vop2 <bits<6> si, bits<6> vi = si> : vop {
39 field bits<6> SI = si;
40 field bits<6> VI = vi;
42 field bits<9> SI3 = {1, 0, 0, si{5-0}};
43 field bits<10> VI3 = {0, 1, 0, 0, vi{5-0}};
46 // Specify a VOP2 opcode for SI and VOP3 opcode for VI
47 // that doesn't have VOP2 encoding on VI
48 class vop23 <bits<6> si, bits<10> vi> : vop2 <si> {
52 class vop3 <bits<9> si, bits<10> vi = {0, si}> : vop {
57 class sop1 <bits<8> si, bits<8> vi = si> {
58 field bits<8> SI = si;
59 field bits<8> VI = vi;
62 class sop2 <bits<7> si, bits<7> vi = si> {
63 field bits<7> SI = si;
64 field bits<7> VI = vi;
67 class sopk <bits<5> si, bits<5> vi = si> {
68 field bits<5> SI = si;
69 field bits<5> VI = vi;
72 // Specify an SMRD opcode for SI and SMEM opcode for VI
74 // FIXME: This should really be bits<5> si, Tablegen crashes if
75 // parameter default value is other parameter with different bit size
76 class smrd<bits<8> si, bits<8> vi = si> {
77 field bits<5> SI = si{4-0};
78 field bits<8> VI = vi;
81 // Execpt for the NONE field, this must be kept in sync with the SISubtarget enum
82 // in AMDGPUInstrInfo.cpp
89 //===----------------------------------------------------------------------===//
91 //===----------------------------------------------------------------------===//
93 def SIload_constant : SDNode<"AMDGPUISD::LOAD_CONSTANT",
94 SDTypeProfile<1, 2, [SDTCisVT<0, f32>, SDTCisVT<1, v4i32>, SDTCisVT<2, i32>]>,
95 [SDNPMayLoad, SDNPMemOperand]
98 def SItbuffer_store : SDNode<"AMDGPUISD::TBUFFER_STORE_FORMAT",
100 [SDTCisVT<0, v4i32>, // rsrc(SGPR)
101 SDTCisVT<1, iAny>, // vdata(VGPR)
102 SDTCisVT<2, i32>, // num_channels(imm)
103 SDTCisVT<3, i32>, // vaddr(VGPR)
104 SDTCisVT<4, i32>, // soffset(SGPR)
105 SDTCisVT<5, i32>, // inst_offset(imm)
106 SDTCisVT<6, i32>, // dfmt(imm)
107 SDTCisVT<7, i32>, // nfmt(imm)
108 SDTCisVT<8, i32>, // offen(imm)
109 SDTCisVT<9, i32>, // idxen(imm)
110 SDTCisVT<10, i32>, // glc(imm)
111 SDTCisVT<11, i32>, // slc(imm)
112 SDTCisVT<12, i32> // tfe(imm)
114 [SDNPMayStore, SDNPMemOperand, SDNPHasChain]
117 def SIload_input : SDNode<"AMDGPUISD::LOAD_INPUT",
118 SDTypeProfile<1, 3, [SDTCisVT<0, v4f32>, SDTCisVT<1, v4i32>, SDTCisVT<2, i16>,
122 class SDSample<string opcode> : SDNode <opcode,
123 SDTypeProfile<1, 4, [SDTCisVT<0, v4f32>, SDTCisVT<2, v32i8>,
124 SDTCisVT<3, v4i32>, SDTCisVT<4, i32>]>
127 def SIsample : SDSample<"AMDGPUISD::SAMPLE">;
128 def SIsampleb : SDSample<"AMDGPUISD::SAMPLEB">;
129 def SIsampled : SDSample<"AMDGPUISD::SAMPLED">;
130 def SIsamplel : SDSample<"AMDGPUISD::SAMPLEL">;
132 def SIconstdata_ptr : SDNode<
133 "AMDGPUISD::CONST_DATA_PTR", SDTypeProfile <1, 1, [SDTCisVT<0, i64>,
137 //===----------------------------------------------------------------------===//
138 // PatFrags for FLAT instructions
139 //===----------------------------------------------------------------------===//
141 class flat_ld <SDPatternOperator ld> : PatFrag<(ops node:$ptr),
143 return isFlatLoad(dyn_cast<LoadSDNode>(N)) ||
144 isGlobalLoad(dyn_cast<LoadSDNode>(N)) ||
145 isConstantLoad(cast<LoadSDNode>(N), -1);
148 def flat_load : flat_ld <load>;
149 def flat_az_extloadi8 : flat_ld <az_extloadi8>;
150 def flat_sextloadi8 : flat_ld <sextloadi8>;
151 def flat_az_extloadi16 : flat_ld <az_extloadi16>;
152 def flat_sextloadi16 : flat_ld <sextloadi16>;
154 class flat_st <SDPatternOperator st> : PatFrag<(ops node:$val, node:$ptr),
155 (st node:$val, node:$ptr), [{
156 return isFlatStore(dyn_cast<StoreSDNode>(N)) ||
157 isGlobalStore(dyn_cast<StoreSDNode>(N));
160 def flat_store: flat_st <store>;
161 def flat_truncstorei8 : flat_st <truncstorei8>;
162 def flat_truncstorei16 : flat_st <truncstorei16>;
165 def mubuf_load : PatFrag <(ops node:$ptr), (load node:$ptr), [{
166 return isGlobalLoad(cast<LoadSDNode>(N)) ||
167 isConstantLoad(cast<LoadSDNode>(N), -1);
170 def smrd_load : PatFrag <(ops node:$ptr), (load node:$ptr), [{
171 return isConstantLoad(cast<LoadSDNode>(N), -1) &&
172 static_cast<const SITargetLowering *>(getTargetLowering())->isMemOpUniform(N);
175 //===----------------------------------------------------------------------===//
176 // SDNodes and PatFrag for local loads and stores to enable s_mov_b32 m0, -1
177 // to be glued to the memory instructions.
178 //===----------------------------------------------------------------------===//
180 def SIld_local : SDNode <"ISD::LOAD", SDTLoad,
181 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand, SDNPInGlue]
184 def si_ld_local : PatFrag <(ops node:$ptr), (SIld_local node:$ptr), [{
185 return isLocalLoad(cast<LoadSDNode>(N));
188 def si_load_local : PatFrag <(ops node:$ptr), (si_ld_local node:$ptr), [{
189 return cast<LoadSDNode>(N)->getAddressingMode() == ISD::UNINDEXED &&
190 cast<LoadSDNode>(N)->getExtensionType() == ISD::NON_EXTLOAD;
193 def si_load_local_align8 : Aligned8Bytes <
194 (ops node:$ptr), (si_load_local node:$ptr)
197 def si_sextload_local : PatFrag <(ops node:$ptr), (si_ld_local node:$ptr), [{
198 return cast<LoadSDNode>(N)->getExtensionType() == ISD::SEXTLOAD;
200 def si_az_extload_local : AZExtLoadBase <si_ld_local>;
202 multiclass SIExtLoadLocal <PatFrag ld_node> {
204 def _i8 : PatFrag <(ops node:$ptr), (ld_node node:$ptr),
205 [{return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i8;}]
208 def _i16 : PatFrag <(ops node:$ptr), (ld_node node:$ptr),
209 [{return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i16;}]
213 defm si_sextload_local : SIExtLoadLocal <si_sextload_local>;
214 defm si_az_extload_local : SIExtLoadLocal <si_az_extload_local>;
216 def SIst_local : SDNode <"ISD::STORE", SDTStore,
217 [SDNPHasChain, SDNPMayStore, SDNPMemOperand, SDNPInGlue]
220 def si_st_local : PatFrag <
221 (ops node:$val, node:$ptr), (SIst_local node:$val, node:$ptr), [{
222 return isLocalStore(cast<StoreSDNode>(N));
225 def si_store_local : PatFrag <
226 (ops node:$val, node:$ptr), (si_st_local node:$val, node:$ptr), [{
227 return cast<StoreSDNode>(N)->getAddressingMode() == ISD::UNINDEXED &&
228 !cast<StoreSDNode>(N)->isTruncatingStore();
231 def si_store_local_align8 : Aligned8Bytes <
232 (ops node:$val, node:$ptr), (si_store_local node:$val, node:$ptr)
235 def si_truncstore_local : PatFrag <
236 (ops node:$val, node:$ptr), (si_st_local node:$val, node:$ptr), [{
237 return cast<StoreSDNode>(N)->isTruncatingStore();
240 def si_truncstore_local_i8 : PatFrag <
241 (ops node:$val, node:$ptr), (si_truncstore_local node:$val, node:$ptr), [{
242 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i8;
245 def si_truncstore_local_i16 : PatFrag <
246 (ops node:$val, node:$ptr), (si_truncstore_local node:$val, node:$ptr), [{
247 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i16;
250 multiclass SIAtomicM0Glue2 <string op_name> {
252 def _glue : SDNode <"ISD::ATOMIC_"#op_name, SDTAtomic2,
253 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand, SDNPInGlue]
256 def _local : local_binary_atomic_op <!cast<SDNode>(NAME#"_glue")>;
259 defm si_atomic_load_add : SIAtomicM0Glue2 <"LOAD_ADD">;
260 defm si_atomic_load_and : SIAtomicM0Glue2 <"LOAD_AND">;
261 defm si_atomic_load_min : SIAtomicM0Glue2 <"LOAD_MIN">;
262 defm si_atomic_load_max : SIAtomicM0Glue2 <"LOAD_MAX">;
263 defm si_atomic_load_or : SIAtomicM0Glue2 <"LOAD_OR">;
264 defm si_atomic_load_sub : SIAtomicM0Glue2 <"LOAD_SUB">;
265 defm si_atomic_load_xor : SIAtomicM0Glue2 <"LOAD_XOR">;
266 defm si_atomic_load_umin : SIAtomicM0Glue2 <"LOAD_UMIN">;
267 defm si_atomic_load_umax : SIAtomicM0Glue2 <"LOAD_UMAX">;
268 defm si_atomic_swap : SIAtomicM0Glue2 <"SWAP">;
270 def si_atomic_cmp_swap_glue : SDNode <"ISD::ATOMIC_CMP_SWAP", SDTAtomic3,
271 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand, SDNPInGlue]
274 defm si_atomic_cmp_swap : AtomicCmpSwapLocal <si_atomic_cmp_swap_glue>;
276 // Transformation function, extract the lower 32bit of a 64bit immediate
277 def LO32 : SDNodeXForm<imm, [{
278 return CurDAG->getTargetConstant(N->getZExtValue() & 0xffffffff, SDLoc(N),
282 def LO32f : SDNodeXForm<fpimm, [{
283 APInt V = N->getValueAPF().bitcastToAPInt().trunc(32);
284 return CurDAG->getTargetConstantFP(APFloat(APFloat::IEEEsingle, V), MVT::f32);
287 // Transformation function, extract the upper 32bit of a 64bit immediate
288 def HI32 : SDNodeXForm<imm, [{
289 return CurDAG->getTargetConstant(N->getZExtValue() >> 32, SDLoc(N), MVT::i32);
292 def HI32f : SDNodeXForm<fpimm, [{
293 APInt V = N->getValueAPF().bitcastToAPInt().lshr(32).trunc(32);
294 return CurDAG->getTargetConstantFP(APFloat(APFloat::IEEEsingle, V), SDLoc(N),
298 def IMM8bitDWORD : PatLeaf <(imm),
299 [{return (N->getZExtValue() & ~0x3FC) == 0;}]
302 def as_dword_i32imm : SDNodeXForm<imm, [{
303 return CurDAG->getTargetConstant(N->getZExtValue() >> 2, SDLoc(N), MVT::i32);
306 def as_i1imm : SDNodeXForm<imm, [{
307 return CurDAG->getTargetConstant(N->getZExtValue(), SDLoc(N), MVT::i1);
310 def as_i8imm : SDNodeXForm<imm, [{
311 return CurDAG->getTargetConstant(N->getZExtValue(), SDLoc(N), MVT::i8);
314 def as_i16imm : SDNodeXForm<imm, [{
315 return CurDAG->getTargetConstant(N->getSExtValue(), SDLoc(N), MVT::i16);
318 def as_i32imm: SDNodeXForm<imm, [{
319 return CurDAG->getTargetConstant(N->getSExtValue(), SDLoc(N), MVT::i32);
322 def as_i64imm: SDNodeXForm<imm, [{
323 return CurDAG->getTargetConstant(N->getSExtValue(), SDLoc(N), MVT::i64);
326 // Copied from the AArch64 backend:
327 def bitcast_fpimm_to_i32 : SDNodeXForm<fpimm, [{
328 return CurDAG->getTargetConstant(
329 N->getValueAPF().bitcastToAPInt().getZExtValue(), SDLoc(N), MVT::i32);
332 // Copied from the AArch64 backend:
333 def bitcast_fpimm_to_i64 : SDNodeXForm<fpimm, [{
334 return CurDAG->getTargetConstant(
335 N->getValueAPF().bitcastToAPInt().getZExtValue(), SDLoc(N), MVT::i64);
338 def IMM8bit : PatLeaf <(imm),
339 [{return isUInt<8>(N->getZExtValue());}]
342 def IMM12bit : PatLeaf <(imm),
343 [{return isUInt<12>(N->getZExtValue());}]
346 def IMM16bit : PatLeaf <(imm),
347 [{return isUInt<16>(N->getZExtValue());}]
350 def IMM20bit : PatLeaf <(imm),
351 [{return isUInt<20>(N->getZExtValue());}]
354 def IMM32bit : PatLeaf <(imm),
355 [{return isUInt<32>(N->getZExtValue());}]
358 def mubuf_vaddr_offset : PatFrag<
359 (ops node:$ptr, node:$offset, node:$imm_offset),
360 (add (add node:$ptr, node:$offset), node:$imm_offset)
363 class InlineImm <ValueType vt> : PatLeaf <(vt imm), [{
364 return isInlineImmediate(N);
367 class InlineFPImm <ValueType vt> : PatLeaf <(vt fpimm), [{
368 return isInlineImmediate(N);
371 class SGPRImm <dag frag> : PatLeaf<frag, [{
372 if (Subtarget->getGeneration() < AMDGPUSubtarget::SOUTHERN_ISLANDS) {
375 const SIRegisterInfo *SIRI =
376 static_cast<const SIRegisterInfo *>(Subtarget->getRegisterInfo());
377 for (SDNode::use_iterator U = N->use_begin(), E = SDNode::use_end();
379 const TargetRegisterClass *RC = getOperandRegClass(*U, U.getOperandNo());
380 if (RC && SIRI->isSGPRClass(RC))
386 //===----------------------------------------------------------------------===//
388 //===----------------------------------------------------------------------===//
390 def FRAMEri32 : Operand<iPTR> {
391 let MIOperandInfo = (ops i32:$ptr, i32imm:$index);
394 def SoppBrTarget : AsmOperandClass {
395 let Name = "SoppBrTarget";
396 let ParserMethod = "parseSOppBrTarget";
399 def sopp_brtarget : Operand<OtherVT> {
400 let EncoderMethod = "getSOPPBrEncoding";
401 let OperandType = "OPERAND_PCREL";
402 let ParserMatchClass = SoppBrTarget;
405 def const_ga : Operand<iPTR>;
407 include "SIInstrFormats.td"
408 include "VIInstrFormats.td"
410 def MubufOffsetMatchClass : AsmOperandClass {
411 let Name = "MubufOffset";
412 let ParserMethod = "parseMubufOptionalOps";
413 let RenderMethod = "addImmOperands";
416 class DSOffsetBaseMatchClass <string parser> : AsmOperandClass {
417 let Name = "DSOffset"#parser;
418 let ParserMethod = parser;
419 let RenderMethod = "addImmOperands";
420 let PredicateMethod = "isDSOffset";
423 def DSOffsetMatchClass : DSOffsetBaseMatchClass <"parseDSOptionalOps">;
424 def DSOffsetGDSMatchClass : DSOffsetBaseMatchClass <"parseDSOffsetOptional">;
426 def DSOffset01MatchClass : AsmOperandClass {
427 let Name = "DSOffset1";
428 let ParserMethod = "parseDSOff01OptionalOps";
429 let RenderMethod = "addImmOperands";
430 let PredicateMethod = "isDSOffset01";
433 class GDSBaseMatchClass <string parser> : AsmOperandClass {
434 let Name = "GDS"#parser;
435 let PredicateMethod = "isImm";
436 let ParserMethod = parser;
437 let RenderMethod = "addImmOperands";
440 def GDSMatchClass : GDSBaseMatchClass <"parseDSOptionalOps">;
441 def GDS01MatchClass : GDSBaseMatchClass <"parseDSOff01OptionalOps">;
443 class GLCBaseMatchClass <string parser> : AsmOperandClass {
444 let Name = "GLC"#parser;
445 let PredicateMethod = "isImm";
446 let ParserMethod = parser;
447 let RenderMethod = "addImmOperands";
450 def GLCMubufMatchClass : GLCBaseMatchClass <"parseMubufOptionalOps">;
451 def GLCFlatMatchClass : GLCBaseMatchClass <"parseFlatOptionalOps">;
453 class SLCBaseMatchClass <string parser> : AsmOperandClass {
454 let Name = "SLC"#parser;
455 let PredicateMethod = "isImm";
456 let ParserMethod = parser;
457 let RenderMethod = "addImmOperands";
460 def SLCMubufMatchClass : SLCBaseMatchClass <"parseMubufOptionalOps">;
461 def SLCFlatMatchClass : SLCBaseMatchClass <"parseFlatOptionalOps">;
462 def SLCFlatAtomicMatchClass : SLCBaseMatchClass <"parseFlatAtomicOptionalOps">;
464 class TFEBaseMatchClass <string parser> : AsmOperandClass {
465 let Name = "TFE"#parser;
466 let PredicateMethod = "isImm";
467 let ParserMethod = parser;
468 let RenderMethod = "addImmOperands";
471 def TFEMubufMatchClass : TFEBaseMatchClass <"parseMubufOptionalOps">;
472 def TFEFlatMatchClass : TFEBaseMatchClass <"parseFlatOptionalOps">;
473 def TFEFlatAtomicMatchClass : TFEBaseMatchClass <"parseFlatAtomicOptionalOps">;
475 def OModMatchClass : AsmOperandClass {
477 let PredicateMethod = "isImm";
478 let ParserMethod = "parseVOP3OptionalOps";
479 let RenderMethod = "addImmOperands";
482 def ClampMatchClass : AsmOperandClass {
484 let PredicateMethod = "isImm";
485 let ParserMethod = "parseVOP3OptionalOps";
486 let RenderMethod = "addImmOperands";
489 class SMRDOffsetBaseMatchClass <string predicate> : AsmOperandClass {
490 let Name = "SMRDOffset"#predicate;
491 let PredicateMethod = predicate;
492 let RenderMethod = "addImmOperands";
495 def SMRDOffsetMatchClass : SMRDOffsetBaseMatchClass <"isSMRDOffset">;
496 def SMRDLiteralOffsetMatchClass : SMRDOffsetBaseMatchClass <
497 "isSMRDLiteralOffset"
500 let OperandType = "OPERAND_IMMEDIATE" in {
502 def offen : Operand<i1> {
503 let PrintMethod = "printOffen";
505 def idxen : Operand<i1> {
506 let PrintMethod = "printIdxen";
508 def addr64 : Operand<i1> {
509 let PrintMethod = "printAddr64";
511 def mbuf_offset : Operand<i16> {
512 let PrintMethod = "printMBUFOffset";
513 let ParserMatchClass = MubufOffsetMatchClass;
515 class ds_offset_base <AsmOperandClass mc> : Operand<i16> {
516 let PrintMethod = "printDSOffset";
517 let ParserMatchClass = mc;
519 def ds_offset : ds_offset_base <DSOffsetMatchClass>;
520 def ds_offset_gds : ds_offset_base <DSOffsetGDSMatchClass>;
522 def ds_offset0 : Operand<i8> {
523 let PrintMethod = "printDSOffset0";
524 let ParserMatchClass = DSOffset01MatchClass;
526 def ds_offset1 : Operand<i8> {
527 let PrintMethod = "printDSOffset1";
528 let ParserMatchClass = DSOffset01MatchClass;
530 class gds_base <AsmOperandClass mc> : Operand <i1> {
531 let PrintMethod = "printGDS";
532 let ParserMatchClass = mc;
534 def gds : gds_base <GDSMatchClass>;
536 def gds01 : gds_base <GDS01MatchClass>;
538 class glc_base <AsmOperandClass mc> : Operand <i1> {
539 let PrintMethod = "printGLC";
540 let ParserMatchClass = mc;
543 def glc : glc_base <GLCMubufMatchClass>;
544 def glc_flat : glc_base <GLCFlatMatchClass>;
546 class slc_base <AsmOperandClass mc> : Operand <i1> {
547 let PrintMethod = "printSLC";
548 let ParserMatchClass = mc;
551 def slc : slc_base <SLCMubufMatchClass>;
552 def slc_flat : slc_base <SLCFlatMatchClass>;
553 def slc_flat_atomic : slc_base <SLCFlatAtomicMatchClass>;
555 class tfe_base <AsmOperandClass mc> : Operand <i1> {
556 let PrintMethod = "printTFE";
557 let ParserMatchClass = mc;
560 def tfe : tfe_base <TFEMubufMatchClass>;
561 def tfe_flat : tfe_base <TFEFlatMatchClass>;
562 def tfe_flat_atomic : tfe_base <TFEFlatAtomicMatchClass>;
564 def omod : Operand <i32> {
565 let PrintMethod = "printOModSI";
566 let ParserMatchClass = OModMatchClass;
569 def ClampMod : Operand <i1> {
570 let PrintMethod = "printClampSI";
571 let ParserMatchClass = ClampMatchClass;
574 def smrd_offset : Operand <i32> {
575 let PrintMethod = "printU32ImmOperand";
576 let ParserMatchClass = SMRDOffsetMatchClass;
579 def smrd_literal_offset : Operand <i32> {
580 let PrintMethod = "printU32ImmOperand";
581 let ParserMatchClass = SMRDLiteralOffsetMatchClass;
584 } // End OperandType = "OPERAND_IMMEDIATE"
586 def VOPDstS64 : VOPDstOperand <SReg_64>;
588 //===----------------------------------------------------------------------===//
590 //===----------------------------------------------------------------------===//
592 def DS1Addr1Offset : ComplexPattern<i32, 2, "SelectDS1Addr1Offset">;
593 def DS64Bit4ByteAligned : ComplexPattern<i32, 3, "SelectDS64Bit4ByteAligned">;
595 def MUBUFAddr32 : ComplexPattern<i64, 9, "SelectMUBUFAddr32">;
596 def MUBUFAddr64 : ComplexPattern<i64, 7, "SelectMUBUFAddr64">;
597 def MUBUFAddr64Atomic : ComplexPattern<i64, 5, "SelectMUBUFAddr64">;
598 def MUBUFScratch : ComplexPattern<i64, 4, "SelectMUBUFScratch">;
599 def MUBUFOffset : ComplexPattern<i64, 6, "SelectMUBUFOffset">;
600 def MUBUFOffsetAtomic : ComplexPattern<i64, 4, "SelectMUBUFOffset">;
602 def SMRDImm : ComplexPattern<i64, 2, "SelectSMRDImm">;
603 def SMRDImm32 : ComplexPattern<i64, 2, "SelectSMRDImm32">;
604 def SMRDSgpr : ComplexPattern<i64, 2, "SelectSMRDSgpr">;
605 def SMRDBufferImm : ComplexPattern<i32, 1, "SelectSMRDBufferImm">;
606 def SMRDBufferImm32 : ComplexPattern<i32, 1, "SelectSMRDBufferImm32">;
607 def SMRDBufferSgpr : ComplexPattern<i32, 1, "SelectSMRDBufferSgpr">;
609 def VOP3Mods0 : ComplexPattern<untyped, 4, "SelectVOP3Mods0">;
610 def VOP3NoMods0 : ComplexPattern<untyped, 4, "SelectVOP3NoMods0">;
611 def VOP3Mods0Clamp : ComplexPattern<untyped, 3, "SelectVOP3Mods0Clamp">;
612 def VOP3Mods0Clamp0OMod : ComplexPattern<untyped, 4, "SelectVOP3Mods0Clamp0OMod">;
613 def VOP3Mods : ComplexPattern<untyped, 2, "SelectVOP3Mods">;
614 def VOP3NoMods : ComplexPattern<untyped, 2, "SelectVOP3NoMods">;
616 //===----------------------------------------------------------------------===//
617 // SI assembler operands
618 //===----------------------------------------------------------------------===//
639 //===----------------------------------------------------------------------===//
641 // SI Instruction multiclass helpers.
643 // Instructions with _32 take 32-bit operands.
644 // Instructions with _64 take 64-bit operands.
646 // VOP_* instructions can use either a 32-bit or 64-bit encoding. The 32-bit
647 // encoding is the standard encoding, but instruction that make use of
648 // any of the instruction modifiers must use the 64-bit encoding.
650 // Instructions with _e32 use the 32-bit encoding.
651 // Instructions with _e64 use the 64-bit encoding.
653 //===----------------------------------------------------------------------===//
655 class SIMCInstr <string pseudo, int subtarget> {
656 string PseudoInstr = pseudo;
657 int Subtarget = subtarget;
660 //===----------------------------------------------------------------------===//
662 //===----------------------------------------------------------------------===//
664 class EXPCommon : InstSI<
666 (ins i32imm:$en, i32imm:$tgt, i32imm:$compr, i32imm:$done, i32imm:$vm,
667 VGPR_32:$src0, VGPR_32:$src1, VGPR_32:$src2, VGPR_32:$src3),
668 "exp $en, $tgt, $compr, $done, $vm, $src0, $src1, $src2, $src3",
677 let isPseudo = 1, isCodeGenOnly = 1 in {
678 def "" : EXPCommon, SIMCInstr <"exp", SISubtarget.NONE> ;
681 def _si : EXPCommon, SIMCInstr <"exp", SISubtarget.SI>, EXPe;
683 def _vi : EXPCommon, SIMCInstr <"exp", SISubtarget.VI>, EXPe_vi;
686 //===----------------------------------------------------------------------===//
688 //===----------------------------------------------------------------------===//
690 class SOP1_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> :
691 SOP1 <outs, ins, "", pattern>,
692 SIMCInstr<opName, SISubtarget.NONE> {
694 let isCodeGenOnly = 1;
697 class SOP1_Real_si <sop1 op, string opName, dag outs, dag ins, string asm> :
698 SOP1 <outs, ins, asm, []>,
700 SIMCInstr<opName, SISubtarget.SI> {
701 let isCodeGenOnly = 0;
702 let AssemblerPredicates = [isSICI];
705 class SOP1_Real_vi <sop1 op, string opName, dag outs, dag ins, string asm> :
706 SOP1 <outs, ins, asm, []>,
708 SIMCInstr<opName, SISubtarget.VI> {
709 let isCodeGenOnly = 0;
710 let AssemblerPredicates = [isVI];
713 multiclass SOP1_m <sop1 op, string opName, dag outs, dag ins, string asm,
716 def "" : SOP1_Pseudo <opName, outs, ins, pattern>;
718 def _si : SOP1_Real_si <op, opName, outs, ins, asm>;
720 def _vi : SOP1_Real_vi <op, opName, outs, ins, asm>;
724 multiclass SOP1_32 <sop1 op, string opName, list<dag> pattern> : SOP1_m <
725 op, opName, (outs SReg_32:$dst), (ins SSrc_32:$src0),
726 opName#" $dst, $src0", pattern
729 multiclass SOP1_64 <sop1 op, string opName, list<dag> pattern> : SOP1_m <
730 op, opName, (outs SReg_64:$dst), (ins SSrc_64:$src0),
731 opName#" $dst, $src0", pattern
734 // no input, 64-bit output.
735 multiclass SOP1_64_0 <sop1 op, string opName, list<dag> pattern> {
736 def "" : SOP1_Pseudo <opName, (outs SReg_64:$dst), (ins), pattern>;
738 def _si : SOP1_Real_si <op, opName, (outs SReg_64:$dst), (ins),
743 def _vi : SOP1_Real_vi <op, opName, (outs SReg_64:$dst), (ins),
749 // 64-bit input, no output
750 multiclass SOP1_1 <sop1 op, string opName, list<dag> pattern> {
751 def "" : SOP1_Pseudo <opName, (outs), (ins SReg_64:$src0), pattern>;
753 def _si : SOP1_Real_si <op, opName, (outs), (ins SReg_64:$src0),
758 def _vi : SOP1_Real_vi <op, opName, (outs), (ins SReg_64:$src0),
764 // 64-bit input, 32-bit output.
765 multiclass SOP1_32_64 <sop1 op, string opName, list<dag> pattern> : SOP1_m <
766 op, opName, (outs SReg_32:$dst), (ins SSrc_64:$src0),
767 opName#" $dst, $src0", pattern
770 class SOP2_Pseudo<string opName, dag outs, dag ins, list<dag> pattern> :
771 SOP2<outs, ins, "", pattern>,
772 SIMCInstr<opName, SISubtarget.NONE> {
774 let isCodeGenOnly = 1;
777 // Pseudo instructions have no encodings, but adding this field here allows
779 // let sdst = xxx in {
780 // for multiclasses that include both real and pseudo instructions.
781 field bits<7> sdst = 0;
784 class SOP2_Real_si<sop2 op, string opName, dag outs, dag ins, string asm> :
785 SOP2<outs, ins, asm, []>,
787 SIMCInstr<opName, SISubtarget.SI> {
788 let AssemblerPredicates = [isSICI];
791 class SOP2_Real_vi<sop2 op, string opName, dag outs, dag ins, string asm> :
792 SOP2<outs, ins, asm, []>,
794 SIMCInstr<opName, SISubtarget.VI> {
795 let AssemblerPredicates = [isVI];
798 multiclass SOP2_m <sop2 op, string opName, dag outs, dag ins, string asm,
801 def "" : SOP2_Pseudo <opName, outs, ins, pattern>;
803 def _si : SOP2_Real_si <op, opName, outs, ins, asm>;
805 def _vi : SOP2_Real_vi <op, opName, outs, ins, asm>;
809 multiclass SOP2_32 <sop2 op, string opName, list<dag> pattern> : SOP2_m <
810 op, opName, (outs SReg_32:$dst), (ins SSrc_32:$src0, SSrc_32:$src1),
811 opName#" $dst, $src0, $src1", pattern
814 multiclass SOP2_64 <sop2 op, string opName, list<dag> pattern> : SOP2_m <
815 op, opName, (outs SReg_64:$dst), (ins SSrc_64:$src0, SSrc_64:$src1),
816 opName#" $dst, $src0, $src1", pattern
819 multiclass SOP2_64_32 <sop2 op, string opName, list<dag> pattern> : SOP2_m <
820 op, opName, (outs SReg_64:$dst), (ins SSrc_64:$src0, SSrc_32:$src1),
821 opName#" $dst, $src0, $src1", pattern
824 class SOPC_Helper <bits<7> op, RegisterOperand rc, ValueType vt,
825 string opName, PatLeaf cond> : SOPC <
826 op, (outs), (ins rc:$src0, rc:$src1),
827 opName#" $src0, $src1", []> {
831 class SOPC_32<bits<7> op, string opName, PatLeaf cond = COND_NULL>
832 : SOPC_Helper<op, SSrc_32, i32, opName, cond>;
834 class SOPC_64<bits<7> op, string opName, PatLeaf cond = COND_NULL>
835 : SOPC_Helper<op, SSrc_64, i64, opName, cond>;
837 class SOPK_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> :
838 SOPK <outs, ins, "", pattern>,
839 SIMCInstr<opName, SISubtarget.NONE> {
841 let isCodeGenOnly = 1;
844 class SOPK_Real_si <sopk op, string opName, dag outs, dag ins, string asm> :
845 SOPK <outs, ins, asm, []>,
847 SIMCInstr<opName, SISubtarget.SI> {
848 let AssemblerPredicates = [isSICI];
849 let isCodeGenOnly = 0;
852 class SOPK_Real_vi <sopk op, string opName, dag outs, dag ins, string asm> :
853 SOPK <outs, ins, asm, []>,
855 SIMCInstr<opName, SISubtarget.VI> {
856 let AssemblerPredicates = [isVI];
857 let isCodeGenOnly = 0;
860 multiclass SOPK_m <sopk op, string opName, dag outs, dag ins, string opAsm,
861 string asm = opName#opAsm> {
862 def "" : SOPK_Pseudo <opName, outs, ins, []>;
864 def _si : SOPK_Real_si <op, opName, outs, ins, asm>;
866 def _vi : SOPK_Real_vi <op, opName, outs, ins, asm>;
870 multiclass SOPK_32 <sopk op, string opName, list<dag> pattern> {
871 def "" : SOPK_Pseudo <opName, (outs SReg_32:$dst), (ins u16imm:$src0),
874 def _si : SOPK_Real_si <op, opName, (outs SReg_32:$dst), (ins u16imm:$src0),
875 opName#" $dst, $src0">;
877 def _vi : SOPK_Real_vi <op, opName, (outs SReg_32:$dst), (ins u16imm:$src0),
878 opName#" $dst, $src0">;
881 multiclass SOPK_SCC <sopk op, string opName, list<dag> pattern> {
882 def "" : SOPK_Pseudo <opName, (outs),
883 (ins SReg_32:$src0, u16imm:$src1), pattern> {
888 def _si : SOPK_Real_si <op, opName, (outs),
889 (ins SReg_32:$sdst, u16imm:$simm16), opName#" $sdst, $simm16"> {
893 def _vi : SOPK_Real_vi <op, opName, (outs),
894 (ins SReg_32:$sdst, u16imm:$simm16), opName#" $sdst, $simm16"> {
899 multiclass SOPK_32TIE <sopk op, string opName, list<dag> pattern> : SOPK_m <
900 op, opName, (outs SReg_32:$sdst), (ins SReg_32:$src0, u16imm:$simm16),
904 multiclass SOPK_IMM32 <sopk op, string opName, dag outs, dag ins,
905 string argAsm, string asm = opName#argAsm> {
907 def "" : SOPK_Pseudo <opName, outs, ins, []>;
909 def _si : SOPK <outs, ins, asm, []>,
911 SIMCInstr<opName, SISubtarget.SI> {
912 let AssemblerPredicates = [isSICI];
913 let isCodeGenOnly = 0;
916 def _vi : SOPK <outs, ins, asm, []>,
918 SIMCInstr<opName, SISubtarget.VI> {
919 let AssemblerPredicates = [isVI];
920 let isCodeGenOnly = 0;
923 //===----------------------------------------------------------------------===//
925 //===----------------------------------------------------------------------===//
927 class SMRD_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> :
928 SMRD <outs, ins, "", pattern>,
929 SIMCInstr<opName, SISubtarget.NONE> {
931 let isCodeGenOnly = 1;
934 class SMRD_Real_si <bits<5> op, string opName, bit imm, dag outs, dag ins,
936 SMRD <outs, ins, asm, []>,
938 SIMCInstr<opName, SISubtarget.SI> {
939 let AssemblerPredicates = [isSICI];
942 class SMRD_Real_vi <bits<8> op, string opName, bit imm, dag outs, dag ins,
943 string asm, list<dag> pattern = []> :
944 SMRD <outs, ins, asm, pattern>,
946 SIMCInstr<opName, SISubtarget.VI> {
947 let AssemblerPredicates = [isVI];
950 multiclass SMRD_m <smrd op, string opName, bit imm, dag outs, dag ins,
951 string asm, list<dag> pattern> {
953 def "" : SMRD_Pseudo <opName, outs, ins, pattern>;
955 def _si : SMRD_Real_si <op.SI, opName, imm, outs, ins, asm>;
957 // glc is only applicable to scalar stores, which are not yet
960 def _vi : SMRD_Real_vi <op.VI, opName, imm, outs, ins, asm>;
964 multiclass SMRD_Inval <smrd op, string opName,
965 SDPatternOperator node> {
966 let hasSideEffects = 1, mayStore = 1 in {
967 def "" : SMRD_Pseudo <opName, (outs), (ins), [(node)]>;
969 let sbase = 0, offset = 0 in {
971 def _si : SMRD_Real_si <op.SI, opName, 0, (outs), (ins), opName>;
974 let glc = 0, sdata = 0 in {
975 def _vi : SMRD_Real_vi <op.VI, opName, 0, (outs), (ins), opName>;
981 class SMEM_Inval <bits<8> op, string opName, SDPatternOperator node> :
982 SMRD_Real_vi<op, opName, 0, (outs), (ins), opName, [(node)]> {
983 let hasSideEffects = 1;
991 multiclass SMRD_Helper <smrd op, string opName, RegisterClass baseClass,
992 RegisterClass dstClass> {
994 op, opName#"_IMM", 1, (outs dstClass:$dst),
995 (ins baseClass:$sbase, smrd_offset:$offset),
996 opName#" $dst, $sbase, $offset", []
1000 (outs dstClass:$dst), (ins baseClass:$sbase, smrd_literal_offset:$offset),
1001 opName#" $dst, $sbase, $offset", []>, SMRD_IMMe_ci <op.SI> {
1002 let AssemblerPredicates = [isCIOnly];
1005 defm _SGPR : SMRD_m <
1006 op, opName#"_SGPR", 0, (outs dstClass:$dst),
1007 (ins baseClass:$sbase, SReg_32:$soff),
1008 opName#" $dst, $sbase, $soff", []
1012 //===----------------------------------------------------------------------===//
1013 // Vector ALU classes
1014 //===----------------------------------------------------------------------===//
1016 // This must always be right before the operand being input modified.
1017 def InputMods : OperandWithDefaultOps <i32, (ops (i32 0))> {
1018 let PrintMethod = "printOperandAndMods";
1021 def InputModsMatchClass : AsmOperandClass {
1022 let Name = "RegWithInputMods";
1025 def InputModsNoDefault : Operand <i32> {
1026 let PrintMethod = "printOperandAndMods";
1027 let ParserMatchClass = InputModsMatchClass;
1030 class getNumSrcArgs<ValueType Src0, ValueType Src1, ValueType Src2> {
1032 !if (!eq(Src0.Value, untyped.Value), 0,
1033 !if (!eq(Src1.Value, untyped.Value), 1, // VOP1
1034 !if (!eq(Src2.Value, untyped.Value), 2, // VOP2
1038 // Returns the register class to use for the destination of VOP[123C]
1039 // instructions for the given VT.
1040 class getVALUDstForVT<ValueType VT> {
1041 RegisterOperand ret = !if(!eq(VT.Size, 32), VOPDstOperand<VGPR_32>,
1042 !if(!eq(VT.Size, 64), VOPDstOperand<VReg_64>,
1043 !if(!eq(VT.Size, 16), VOPDstOperand<VGPR_32>,
1044 VOPDstOperand<SReg_64>))); // else VT == i1
1047 // Returns the register class to use for source 0 of VOP[12C]
1048 // instructions for the given VT.
1049 class getVOPSrc0ForVT<ValueType VT> {
1050 RegisterOperand ret = !if(!eq(VT.Size, 64), VSrc_64, VSrc_32);
1053 // Returns the register class to use for source 1 of VOP[12C] for the
1055 class getVOPSrc1ForVT<ValueType VT> {
1056 RegisterClass ret = !if(!eq(VT.Size, 64), VReg_64, VGPR_32);
1059 // Returns the register class to use for sources of VOP3 instructions for the
1061 class getVOP3SrcForVT<ValueType VT> {
1062 RegisterOperand ret =
1063 !if(!eq(VT.Size, 64),
1065 !if(!eq(VT.Value, i1.Value),
1072 // Returns 1 if the source arguments have modifiers, 0 if they do not.
1073 // XXX - do f16 instructions?
1074 class hasModifiers<ValueType SrcVT> {
1075 bit ret = !if(!eq(SrcVT.Value, f32.Value), 1,
1076 !if(!eq(SrcVT.Value, f64.Value), 1, 0));
1079 // Returns the input arguments for VOP[12C] instructions for the given SrcVT.
1080 class getIns32 <RegisterOperand Src0RC, RegisterClass Src1RC, int NumSrcArgs> {
1081 dag ret = !if(!eq(NumSrcArgs, 1), (ins Src0RC:$src0), // VOP1
1082 !if(!eq(NumSrcArgs, 2), (ins Src0RC:$src0, Src1RC:$src1), // VOP2
1086 // Returns the input arguments for VOP3 instructions for the given SrcVT.
1087 class getIns64 <RegisterOperand Src0RC, RegisterOperand Src1RC,
1088 RegisterOperand Src2RC, int NumSrcArgs,
1092 !if (!eq(NumSrcArgs, 1),
1093 !if (!eq(HasModifiers, 1),
1094 // VOP1 with modifiers
1095 (ins InputModsNoDefault:$src0_modifiers, Src0RC:$src0,
1096 ClampMod:$clamp, omod:$omod)
1098 // VOP1 without modifiers
1101 !if (!eq(NumSrcArgs, 2),
1102 !if (!eq(HasModifiers, 1),
1103 // VOP 2 with modifiers
1104 (ins InputModsNoDefault:$src0_modifiers, Src0RC:$src0,
1105 InputModsNoDefault:$src1_modifiers, Src1RC:$src1,
1106 ClampMod:$clamp, omod:$omod)
1108 // VOP2 without modifiers
1109 (ins Src0RC:$src0, Src1RC:$src1)
1111 /* NumSrcArgs == 3 */,
1112 !if (!eq(HasModifiers, 1),
1113 // VOP3 with modifiers
1114 (ins InputModsNoDefault:$src0_modifiers, Src0RC:$src0,
1115 InputModsNoDefault:$src1_modifiers, Src1RC:$src1,
1116 InputModsNoDefault:$src2_modifiers, Src2RC:$src2,
1117 ClampMod:$clamp, omod:$omod)
1119 // VOP3 without modifiers
1120 (ins Src0RC:$src0, Src1RC:$src1, Src2RC:$src2)
1124 // Returns the assembly string for the inputs and outputs of a VOP[12C]
1125 // instruction. This does not add the _e32 suffix, so it can be reused
1127 class getAsm32 <bit HasDst, int NumSrcArgs> {
1128 string dst = "$dst";
1129 string src0 = ", $src0";
1130 string src1 = ", $src1";
1131 string src2 = ", $src2";
1132 string ret = !if(HasDst, dst, "") #
1133 !if(!eq(NumSrcArgs, 1), src0, "") #
1134 !if(!eq(NumSrcArgs, 2), src0#src1, "") #
1135 !if(!eq(NumSrcArgs, 3), src0#src1#src2, "");
1138 // Returns the assembly string for the inputs and outputs of a VOP3
1140 class getAsm64 <bit HasDst, int NumSrcArgs, bit HasModifiers> {
1141 string src0 = !if(!eq(NumSrcArgs, 1), "$src0_modifiers", "$src0_modifiers,");
1142 string src1 = !if(!eq(NumSrcArgs, 1), "",
1143 !if(!eq(NumSrcArgs, 2), " $src1_modifiers",
1144 " $src1_modifiers,"));
1145 string src2 = !if(!eq(NumSrcArgs, 3), " $src2_modifiers", "");
1147 !if(!eq(HasModifiers, 0),
1148 getAsm32<HasDst, NumSrcArgs>.ret,
1149 "$dst, "#src0#src1#src2#"$clamp"#"$omod");
1152 class VOPProfile <list<ValueType> _ArgVT> {
1154 field list<ValueType> ArgVT = _ArgVT;
1156 field ValueType DstVT = ArgVT[0];
1157 field ValueType Src0VT = ArgVT[1];
1158 field ValueType Src1VT = ArgVT[2];
1159 field ValueType Src2VT = ArgVT[3];
1160 field RegisterOperand DstRC = getVALUDstForVT<DstVT>.ret;
1161 field RegisterOperand Src0RC32 = getVOPSrc0ForVT<Src0VT>.ret;
1162 field RegisterClass Src1RC32 = getVOPSrc1ForVT<Src1VT>.ret;
1163 field RegisterOperand Src0RC64 = getVOP3SrcForVT<Src0VT>.ret;
1164 field RegisterOperand Src1RC64 = getVOP3SrcForVT<Src1VT>.ret;
1165 field RegisterOperand Src2RC64 = getVOP3SrcForVT<Src2VT>.ret;
1167 field bit HasDst = !if(!eq(DstVT.Value, untyped.Value), 0, 1);
1168 field bit HasDst32 = HasDst;
1169 field int NumSrcArgs = getNumSrcArgs<Src0VT, Src1VT, Src2VT>.ret;
1170 field bit HasModifiers = hasModifiers<Src0VT>.ret;
1172 field dag Outs = !if(HasDst,(outs DstRC:$dst),(outs));
1174 // VOP3b instructions are a special case with a second explicit
1175 // output. This is manually overridden for them.
1176 field dag Outs32 = Outs;
1177 field dag Outs64 = Outs;
1179 field dag Ins32 = getIns32<Src0RC32, Src1RC32, NumSrcArgs>.ret;
1180 field dag Ins64 = getIns64<Src0RC64, Src1RC64, Src2RC64, NumSrcArgs,
1183 field string Asm32 = getAsm32<HasDst, NumSrcArgs>.ret;
1184 field string Asm64 = getAsm64<HasDst, NumSrcArgs, HasModifiers>.ret;
1187 // FIXME: I think these F16/I16 profiles will need to use f16/i16 types in order
1188 // for the instruction patterns to work.
1189 def VOP_F16_F16 : VOPProfile <[f16, f16, untyped, untyped]>;
1190 def VOP_F16_I16 : VOPProfile <[f16, i32, untyped, untyped]>;
1191 def VOP_I16_F16 : VOPProfile <[i32, f16, untyped, untyped]>;
1193 def VOP_F16_F16_F16 : VOPProfile <[f16, f16, f16, untyped]>;
1194 def VOP_F16_F16_I16 : VOPProfile <[f16, f16, i32, untyped]>;
1195 def VOP_I16_I16_I16 : VOPProfile <[i32, i32, i32, untyped]>;
1197 def VOP_NONE : VOPProfile <[untyped, untyped, untyped, untyped]>;
1199 def VOP_F32_F32 : VOPProfile <[f32, f32, untyped, untyped]>;
1200 def VOP_F32_F64 : VOPProfile <[f32, f64, untyped, untyped]>;
1201 def VOP_F32_I32 : VOPProfile <[f32, i32, untyped, untyped]>;
1202 def VOP_F64_F32 : VOPProfile <[f64, f32, untyped, untyped]>;
1203 def VOP_F64_F64 : VOPProfile <[f64, f64, untyped, untyped]>;
1204 def VOP_F64_I32 : VOPProfile <[f64, i32, untyped, untyped]>;
1205 def VOP_I32_F32 : VOPProfile <[i32, f32, untyped, untyped]>;
1206 def VOP_I32_F64 : VOPProfile <[i32, f64, untyped, untyped]>;
1207 def VOP_I32_I32 : VOPProfile <[i32, i32, untyped, untyped]>;
1209 def VOP_F32_F32_F32 : VOPProfile <[f32, f32, f32, untyped]>;
1210 def VOP_F32_F32_I32 : VOPProfile <[f32, f32, i32, untyped]>;
1211 def VOP_F64_F64_F64 : VOPProfile <[f64, f64, f64, untyped]>;
1212 def VOP_F64_F64_I32 : VOPProfile <[f64, f64, i32, untyped]>;
1213 def VOP_I32_F32_F32 : VOPProfile <[i32, f32, f32, untyped]>;
1214 def VOP_I32_F32_I32 : VOPProfile <[i32, f32, i32, untyped]>;
1215 def VOP_I32_I32_I32 : VOPProfile <[i32, i32, i32, untyped]>;
1217 // Write out to vcc or arbitrary SGPR.
1218 def VOP2b_I32_I1_I32_I32 : VOPProfile<[i32, i32, i32, untyped]> {
1219 let Asm32 = "$dst, vcc, $src0, $src1";
1220 let Asm64 = "$dst, $sdst, $src0, $src1";
1221 let Outs32 = (outs DstRC:$dst);
1222 let Outs64 = (outs DstRC:$dst, SReg_64:$sdst);
1225 // Write out to vcc or arbitrary SGPR and read in from vcc or
1227 def VOP2b_I32_I1_I32_I32_I1 : VOPProfile<[i32, i32, i32, i1]> {
1228 // We use VCSrc_32 to exclude literal constants, even though the
1229 // encoding normally allows them since the implicit VCC use means
1230 // using one would always violate the constant bus
1231 // restriction. SGPRs are still allowed because it should
1232 // technically be possible to use VCC again as src0.
1233 let Src0RC32 = VCSrc_32;
1234 let Asm32 = "$dst, vcc, $src0, $src1, vcc";
1235 let Asm64 = "$dst, $sdst, $src0, $src1, $src2";
1236 let Outs32 = (outs DstRC:$dst);
1237 let Outs64 = (outs DstRC:$dst, SReg_64:$sdst);
1239 // Suppress src2 implied by type since the 32-bit encoding uses an
1240 // implicit VCC use.
1241 let Ins32 = (ins Src0RC32:$src0, Src1RC32:$src1);
1244 class VOP3b_Profile<ValueType vt> : VOPProfile<[vt, vt, vt, vt]> {
1245 let Outs64 = (outs DstRC:$vdst, SReg_64:$sdst);
1246 let Asm64 = "$vdst, $sdst, $src0_modifiers, $src1_modifiers, $src2_modifiers"#"$clamp"#"$omod";
1249 def VOP3b_F32_I1_F32_F32_F32 : VOP3b_Profile<f32> {
1250 // FIXME: Hack to stop printing _e64
1251 let DstRC = RegisterOperand<VGPR_32>;
1254 def VOP3b_F64_I1_F64_F64_F64 : VOP3b_Profile<f64> {
1255 // FIXME: Hack to stop printing _e64
1256 let DstRC = RegisterOperand<VReg_64>;
1259 // VOPC instructions are a special case because for the 32-bit
1260 // encoding, we want to display the implicit vcc write as if it were
1261 // an explicit $dst.
1262 class VOPC_Profile<ValueType vt0, ValueType vt1 = vt0> : VOPProfile <[i1, vt0, vt1, untyped]> {
1263 let Asm32 = "vcc, $src0, $src1";
1264 // The destination for 32-bit encoding is implicit.
1268 class VOPC_Class_Profile<ValueType vt> : VOPC_Profile<vt, i32> {
1269 let Ins64 = (ins InputModsNoDefault:$src0_modifiers, Src0RC64:$src0, Src1RC64:$src1);
1270 let Asm64 = "$dst, $src0_modifiers, $src1";
1273 def VOPC_I1_F32_F32 : VOPC_Profile<f32>;
1274 def VOPC_I1_F64_F64 : VOPC_Profile<f64>;
1275 def VOPC_I1_I32_I32 : VOPC_Profile<i32>;
1276 def VOPC_I1_I64_I64 : VOPC_Profile<i64>;
1278 def VOPC_I1_F32_I32 : VOPC_Class_Profile<f32>;
1279 def VOPC_I1_F64_I32 : VOPC_Class_Profile<f64>;
1281 def VOP_I64_I64_I32 : VOPProfile <[i64, i64, i32, untyped]>;
1282 def VOP_I64_I32_I64 : VOPProfile <[i64, i32, i64, untyped]>;
1283 def VOP_I64_I64_I64 : VOPProfile <[i64, i64, i64, untyped]>;
1284 def VOP_CNDMASK : VOPProfile <[i32, i32, i32, untyped]> {
1285 let Ins32 = (ins Src0RC32:$src0, Src1RC32:$src1);
1286 let Ins64 = (ins Src0RC64:$src0, Src1RC64:$src1, SSrc_64:$src2);
1287 let Asm64 = "$dst, $src0, $src1, $src2";
1290 def VOP_F32_F32_F32_F32 : VOPProfile <[f32, f32, f32, f32]>;
1291 def VOP_MADK : VOPProfile <[f32, f32, f32, f32]> {
1292 field dag Ins = (ins VCSrc_32:$src0, VGPR_32:$vsrc1, u32imm:$src2);
1293 field string Asm = "$dst, $src0, $vsrc1, $src2";
1295 def VOP_MAC : VOPProfile <[f32, f32, f32, f32]> {
1296 let Ins32 = (ins Src0RC32:$src0, Src1RC32:$src1, VGPR_32:$src2);
1297 let Ins64 = getIns64<Src0RC64, Src1RC64, RegisterOperand<VGPR_32>, 3,
1299 let Asm32 = getAsm32<1, 2>.ret;
1300 let Asm64 = getAsm64<1, 2, HasModifiers>.ret;
1302 def VOP_F64_F64_F64_F64 : VOPProfile <[f64, f64, f64, f64]>;
1303 def VOP_I32_I32_I32_I32 : VOPProfile <[i32, i32, i32, i32]>;
1304 def VOP_I64_I32_I32_I64 : VOPProfile <[i64, i32, i32, i64]>;
1306 class SIInstAlias <string asm, Instruction inst, VOPProfile p> :
1307 InstAlias <asm, (inst)>, PredicateControl {
1309 field bit isCompare;
1310 field bit isCommutable;
1314 !if (!eq(p.NumSrcArgs, 0),
1316 (inst p.DstRC:$dst),
1317 !if (!eq(p.NumSrcArgs, 1),
1319 (inst p.DstRC:$dst, p.Src0RC32:$src0),
1320 !if (!eq(p.NumSrcArgs, 2),
1322 (inst p.DstRC:$dst, p.Src0RC32:$src0, p.Src1RC32:$src1),
1323 // else - unreachable
1326 !if (!eq(p.NumSrcArgs, 2),
1328 (inst p.Src0RC32:$src0, p.Src1RC32:$src1),
1329 !if (!eq(p.NumSrcArgs, 1),
1331 (inst p.Src0RC32:$src1),
1337 class SIInstAliasSI <string asm, string op_name, VOPProfile p> :
1338 SIInstAlias <asm, !cast<Instruction>(op_name#"_e32_si"), p> {
1339 let AssemblerPredicate = SIAssemblerPredicate;
1342 class SIInstAliasVI <string asm, string op_name, VOPProfile p> :
1343 SIInstAlias <asm, !cast<Instruction>(op_name#"_e32_vi"), p> {
1344 let AssemblerPredicates = [isVI];
1347 multiclass SIInstAliasBuilder <string asm, VOPProfile p> {
1349 def : SIInstAliasSI <asm, NAME, p>;
1351 def : SIInstAliasVI <asm, NAME, p>;
1354 class VOP <string opName> {
1355 string OpName = opName;
1358 class VOP2_REV <string revOp, bit isOrig> {
1359 string RevOp = revOp;
1360 bit IsOrig = isOrig;
1363 class AtomicNoRet <string noRetOp, bit isRet> {
1364 string NoRetOp = noRetOp;
1368 class VOP1_Pseudo <dag outs, dag ins, list<dag> pattern, string opName> :
1369 VOP1Common <outs, ins, "", pattern>,
1371 SIMCInstr <opName#"_e32", SISubtarget.NONE>,
1372 MnemonicAlias<opName#"_e32", opName> {
1374 let isCodeGenOnly = 1;
1380 class VOP1_Real_si <string opName, vop1 op, dag outs, dag ins, string asm> :
1381 VOP1<op.SI, outs, ins, asm, []>,
1382 SIMCInstr <opName#"_e32", SISubtarget.SI> {
1383 let AssemblerPredicate = SIAssemblerPredicate;
1386 class VOP1_Real_vi <string opName, vop1 op, dag outs, dag ins, string asm> :
1387 VOP1<op.VI, outs, ins, asm, []>,
1388 SIMCInstr <opName#"_e32", SISubtarget.VI> {
1389 let AssemblerPredicates = [isVI];
1392 multiclass VOP1_m <vop1 op, string opName, VOPProfile p, list<dag> pattern,
1393 string asm = opName#p.Asm32> {
1394 def "" : VOP1_Pseudo <p.Outs, p.Ins32, pattern, opName>;
1396 def _si : VOP1_Real_si <opName, op, p.Outs, p.Ins32, asm>;
1398 def _vi : VOP1_Real_vi <opName, op, p.Outs, p.Ins32, asm>;
1402 multiclass VOP1SI_m <vop1 op, string opName, VOPProfile p, list<dag> pattern,
1403 string asm = opName#p.Asm32> {
1405 def "" : VOP1_Pseudo <p.Outs, p.Ins32, pattern, opName>;
1407 def _si : VOP1_Real_si <opName, op, p.Outs, p.Ins32, asm>;
1410 class VOP2_Pseudo <dag outs, dag ins, list<dag> pattern, string opName> :
1411 VOP2Common <outs, ins, "", pattern>,
1413 SIMCInstr<opName#"_e32", SISubtarget.NONE>,
1414 MnemonicAlias<opName#"_e32", opName> {
1416 let isCodeGenOnly = 1;
1419 class VOP2_Real_si <string opName, vop2 op, dag outs, dag ins, string asm> :
1420 VOP2 <op.SI, outs, ins, opName#asm, []>,
1421 SIMCInstr <opName#"_e32", SISubtarget.SI> {
1422 let AssemblerPredicates = [isSICI];
1425 class VOP2_Real_vi <string opName, vop2 op, dag outs, dag ins, string asm> :
1426 VOP2 <op.VI, outs, ins, opName#asm, []>,
1427 SIMCInstr <opName#"_e32", SISubtarget.VI> {
1428 let AssemblerPredicates = [isVI];
1431 multiclass VOP2SI_m <vop2 op, string opName, VOPProfile p, list<dag> pattern,
1434 def "" : VOP2_Pseudo <p.Outs32, p.Ins32, pattern, opName>,
1435 VOP2_REV<revOp#"_e32", !eq(revOp, opName)>;
1437 def _si : VOP2_Real_si <opName, op, p.Outs32, p.Ins32, p.Asm32>;
1440 multiclass VOP2_m <vop2 op, string opName, VOPProfile p, list <dag> pattern,
1443 def "" : VOP2_Pseudo <p.Outs32, p.Ins32, pattern, opName>,
1444 VOP2_REV<revOp#"_e32", !eq(revOp, opName)>;
1446 def _si : VOP2_Real_si <opName, op, p.Outs32, p.Ins32, p.Asm32>;
1448 def _vi : VOP2_Real_vi <opName, op, p.Outs32, p.Ins32, p.Asm32>;
1452 class VOP3DisableFields <bit HasSrc1, bit HasSrc2, bit HasModifiers> {
1454 bits<2> src0_modifiers = !if(HasModifiers, ?, 0);
1455 bits<2> src1_modifiers = !if(HasModifiers, !if(HasSrc1, ?, 0), 0);
1456 bits<2> src2_modifiers = !if(HasModifiers, !if(HasSrc2, ?, 0), 0);
1457 bits<2> omod = !if(HasModifiers, ?, 0);
1458 bits<1> clamp = !if(HasModifiers, ?, 0);
1459 bits<9> src1 = !if(HasSrc1, ?, 0);
1460 bits<9> src2 = !if(HasSrc2, ?, 0);
1463 class VOP3DisableModFields <bit HasSrc0Mods,
1464 bit HasSrc1Mods = 0,
1465 bit HasSrc2Mods = 0,
1466 bit HasOutputMods = 0> {
1467 bits<2> src0_modifiers = !if(HasSrc0Mods, ?, 0);
1468 bits<2> src1_modifiers = !if(HasSrc1Mods, ?, 0);
1469 bits<2> src2_modifiers = !if(HasSrc2Mods, ?, 0);
1470 bits<2> omod = !if(HasOutputMods, ?, 0);
1471 bits<1> clamp = !if(HasOutputMods, ?, 0);
1474 class VOP3_Pseudo <dag outs, dag ins, list<dag> pattern, string opName> :
1475 VOP3Common <outs, ins, "", pattern>,
1477 SIMCInstr<opName#"_e64", SISubtarget.NONE>,
1478 MnemonicAlias<opName#"_e64", opName> {
1480 let isCodeGenOnly = 1;
1486 class VOP3_Real_si <bits<9> op, dag outs, dag ins, string asm, string opName> :
1487 VOP3Common <outs, ins, asm, []>,
1489 SIMCInstr<opName#"_e64", SISubtarget.SI> {
1490 let AssemblerPredicates = [isSICI];
1493 class VOP3_Real_vi <bits<10> op, dag outs, dag ins, string asm, string opName> :
1494 VOP3Common <outs, ins, asm, []>,
1496 SIMCInstr <opName#"_e64", SISubtarget.VI> {
1497 let AssemblerPredicates = [isVI];
1500 class VOP3b_Real_si <bits<9> op, dag outs, dag ins, string asm, string opName> :
1501 VOP3Common <outs, ins, asm, []>,
1503 SIMCInstr<opName#"_e64", SISubtarget.SI> {
1504 let AssemblerPredicates = [isSICI];
1507 class VOP3b_Real_vi <bits<10> op, dag outs, dag ins, string asm, string opName> :
1508 VOP3Common <outs, ins, asm, []>,
1510 SIMCInstr <opName#"_e64", SISubtarget.VI> {
1511 let AssemblerPredicates = [isVI];
1514 multiclass VOP3_m <vop op, dag outs, dag ins, string asm, list<dag> pattern,
1515 string opName, int NumSrcArgs, bit HasMods = 1> {
1517 def "" : VOP3_Pseudo <outs, ins, pattern, opName>;
1519 def _si : VOP3_Real_si <op.SI3, outs, ins, asm, opName>,
1520 VOP3DisableFields<!if(!eq(NumSrcArgs, 1), 0, 1),
1521 !if(!eq(NumSrcArgs, 2), 0, 1),
1523 def _vi : VOP3_Real_vi <op.VI3, outs, ins, asm, opName>,
1524 VOP3DisableFields<!if(!eq(NumSrcArgs, 1), 0, 1),
1525 !if(!eq(NumSrcArgs, 2), 0, 1),
1529 multiclass VOP3_1_m <vop op, dag outs, dag ins, string asm,
1530 list<dag> pattern, string opName, bit HasMods = 1> {
1532 def "" : VOP3_Pseudo <outs, ins, pattern, opName>;
1534 def _si : VOP3_Real_si <op.SI3, outs, ins, asm, opName>,
1535 VOP3DisableFields<0, 0, HasMods>;
1537 def _vi : VOP3_Real_vi <op.VI3, outs, ins, asm, opName>,
1538 VOP3DisableFields<0, 0, HasMods>;
1541 multiclass VOP3SI_1_m <vop op, dag outs, dag ins, string asm,
1542 list<dag> pattern, string opName, bit HasMods = 1> {
1544 def "" : VOP3_Pseudo <outs, ins, pattern, opName>;
1546 def _si : VOP3_Real_si <op.SI3, outs, ins, asm, opName>,
1547 VOP3DisableFields<0, 0, HasMods>;
1548 // No VI instruction. This class is for SI only.
1551 multiclass VOP3_2_m <vop op, dag outs, dag ins, string asm,
1552 list<dag> pattern, string opName, string revOp,
1555 def "" : VOP3_Pseudo <outs, ins, pattern, opName>,
1556 VOP2_REV<revOp#"_e64", !eq(revOp, opName)>;
1558 def _si : VOP3_Real_si <op.SI3, outs, ins, asm, opName>,
1559 VOP3DisableFields<1, 0, HasMods>;
1561 def _vi : VOP3_Real_vi <op.VI3, outs, ins, asm, opName>,
1562 VOP3DisableFields<1, 0, HasMods>;
1565 multiclass VOP3SI_2_m <vop op, dag outs, dag ins, string asm,
1566 list<dag> pattern, string opName, string revOp,
1569 def "" : VOP3_Pseudo <outs, ins, pattern, opName>,
1570 VOP2_REV<revOp#"_e64", !eq(revOp, opName)>;
1572 def _si : VOP3_Real_si <op.SI3, outs, ins, asm, opName>,
1573 VOP3DisableFields<1, 0, HasMods>;
1575 // No VI instruction. This class is for SI only.
1578 // Two operand VOP3b instruction that may have a 3rd SGPR bool operand
1579 // instead of an implicit VCC as in the VOP2b format.
1580 multiclass VOP3b_2_3_m <vop op, dag outs, dag ins, string asm,
1581 list<dag> pattern, string opName, string revOp,
1582 bit HasMods = 1, bit useSrc2Input = 0> {
1583 def "" : VOP3_Pseudo <outs, ins, pattern, opName>;
1585 def _si : VOP3b_Real_si <op.SI3, outs, ins, asm, opName>,
1586 VOP3DisableFields<1, useSrc2Input, HasMods>;
1588 def _vi : VOP3b_Real_vi <op.VI3, outs, ins, asm, opName>,
1589 VOP3DisableFields<1, useSrc2Input, HasMods>;
1592 multiclass VOP3_C_m <vop op, dag outs, dag ins, string asm,
1593 list<dag> pattern, string opName,
1594 bit HasMods, bit defExec,
1595 string revOp, list<SchedReadWrite> sched> {
1597 def "" : VOP3_Pseudo <outs, ins, pattern, opName>,
1598 VOP2_REV<revOp#"_e64", !eq(revOp, opName)> {
1599 let Defs = !if(defExec, [EXEC], []);
1600 let SchedRW = sched;
1603 def _si : VOP3_Real_si <op.SI3, outs, ins, asm, opName>,
1604 VOP3DisableFields<1, 0, HasMods> {
1605 let Defs = !if(defExec, [EXEC], []);
1606 let SchedRW = sched;
1609 def _vi : VOP3_Real_vi <op.VI3, outs, ins, asm, opName>,
1610 VOP3DisableFields<1, 0, HasMods> {
1611 let Defs = !if(defExec, [EXEC], []);
1612 let SchedRW = sched;
1616 // An instruction that is VOP2 on SI and VOP3 on VI, no modifiers.
1617 multiclass VOP2SI_3VI_m <vop3 op, string opName, dag outs, dag ins,
1618 string asm, list<dag> pattern = []> {
1619 let isPseudo = 1, isCodeGenOnly = 1 in {
1620 def "" : VOPAnyCommon <outs, ins, "", pattern>,
1621 SIMCInstr<opName, SISubtarget.NONE>;
1624 def _si : VOP2 <op.SI3{5-0}, outs, ins, asm, []>,
1625 SIMCInstr <opName, SISubtarget.SI> {
1626 let AssemblerPredicates = [isSICI];
1629 def _vi : VOP3Common <outs, ins, asm, []>,
1631 VOP3DisableFields <1, 0, 0>,
1632 SIMCInstr <opName, SISubtarget.VI> {
1633 let AssemblerPredicates = [isVI];
1637 multiclass VOP1_Helper <vop1 op, string opName, VOPProfile p, list<dag> pat32,
1640 defm _e32 : VOP1_m <op, opName, p, pat32>;
1642 defm _e64 : VOP3_1_m <op, p.Outs, p.Ins64, opName#p.Asm64, pat64, opName,
1646 multiclass VOP1Inst <vop1 op, string opName, VOPProfile P,
1647 SDPatternOperator node = null_frag> : VOP1_Helper <
1650 [(set P.DstVT:$dst, (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0,
1651 i32:$src0_modifiers, i1:$clamp, i32:$omod))))],
1652 [(set P.DstVT:$dst, (node P.Src0VT:$src0))])
1655 multiclass VOP1InstSI <vop1 op, string opName, VOPProfile P,
1656 SDPatternOperator node = null_frag> {
1658 defm _e32 : VOP1SI_m <op, opName, P, []>;
1660 defm _e64 : VOP3SI_1_m <op, P.Outs, P.Ins64, opName#P.Asm64,
1662 [(set P.DstVT:$dst, (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0,
1663 i32:$src0_modifiers, i1:$clamp, i32:$omod))))],
1664 [(set P.DstVT:$dst, (node P.Src0VT:$src0))]),
1665 opName, P.HasModifiers>;
1668 multiclass VOP2_Helper <vop2 op, string opName, VOPProfile p, list<dag> pat32,
1669 list<dag> pat64, string revOp> {
1671 defm _e32 : VOP2_m <op, opName, p, pat32, revOp>;
1673 defm _e64 : VOP3_2_m <op, p.Outs, p.Ins64, opName#p.Asm64, pat64, opName,
1674 revOp, p.HasModifiers>;
1677 multiclass VOP2Inst <vop2 op, string opName, VOPProfile P,
1678 SDPatternOperator node = null_frag,
1679 string revOp = opName> : VOP2_Helper <
1683 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1684 i1:$clamp, i32:$omod)),
1685 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))],
1686 [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1))]),
1690 multiclass VOP2InstSI <vop2 op, string opName, VOPProfile P,
1691 SDPatternOperator node = null_frag,
1692 string revOp = opName> {
1694 defm _e32 : VOP2SI_m <op, opName, P, [], revOp>;
1696 defm _e64 : VOP3SI_2_m <op, P.Outs, P.Ins64, opName#P.Asm64,
1699 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1700 i1:$clamp, i32:$omod)),
1701 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))],
1702 [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1))]),
1703 opName, revOp, P.HasModifiers>;
1706 multiclass VOP2b_Helper <vop2 op, string opName, VOPProfile p,
1707 list<dag> pat32, list<dag> pat64,
1708 string revOp, bit useSGPRInput> {
1710 let SchedRW = [Write32Bit, WriteSALU] in {
1711 let Uses = !if(useSGPRInput, [VCC, EXEC], [EXEC]), Defs = [VCC] in {
1712 defm _e32 : VOP2_m <op, opName, p, pat32, revOp>;
1715 defm _e64 : VOP3b_2_3_m <op, p.Outs64, p.Ins64, opName#p.Asm64, pat64,
1716 opName, revOp, p.HasModifiers, useSGPRInput>;
1720 multiclass VOP2bInst <vop2 op, string opName, VOPProfile P,
1721 SDPatternOperator node = null_frag,
1722 string revOp = opName> : VOP2b_Helper <
1726 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1727 i1:$clamp, i32:$omod)),
1728 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))],
1729 [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1))]),
1730 revOp, !eq(P.NumSrcArgs, 3)
1733 // A VOP2 instruction that is VOP3-only on VI.
1734 multiclass VOP2_VI3_Helper <vop23 op, string opName, VOPProfile p,
1735 list<dag> pat32, list<dag> pat64, string revOp> {
1737 defm _e32 : VOP2SI_m <op, opName, p, pat32, revOp>;
1739 defm _e64 : VOP3_2_m <op, p.Outs, p.Ins64, opName#p.Asm64, pat64, opName,
1740 revOp, p.HasModifiers>;
1743 multiclass VOP2_VI3_Inst <vop23 op, string opName, VOPProfile P,
1744 SDPatternOperator node = null_frag,
1745 string revOp = opName>
1750 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1751 i1:$clamp, i32:$omod)),
1752 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))],
1753 [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1))]),
1757 multiclass VOP2MADK <vop2 op, string opName, list<dag> pattern = []> {
1759 def "" : VOP2_Pseudo <VOP_MADK.Outs, VOP_MADK.Ins, pattern, opName>;
1761 let isCodeGenOnly = 0 in {
1762 def _si : VOP2Common <VOP_MADK.Outs, VOP_MADK.Ins,
1763 !strconcat(opName, VOP_MADK.Asm), []>,
1764 SIMCInstr <opName#"_e32", SISubtarget.SI>,
1765 VOP2_MADKe <op.SI> {
1766 let AssemblerPredicates = [isSICI];
1769 def _vi : VOP2Common <VOP_MADK.Outs, VOP_MADK.Ins,
1770 !strconcat(opName, VOP_MADK.Asm), []>,
1771 SIMCInstr <opName#"_e32", SISubtarget.VI>,
1772 VOP2_MADKe <op.VI> {
1773 let AssemblerPredicates = [isVI];
1775 } // End isCodeGenOnly = 0
1778 class VOPC_Pseudo <dag ins, list<dag> pattern, string opName> :
1779 VOPCCommon <ins, "", pattern>,
1781 SIMCInstr<opName#"_e32", SISubtarget.NONE> {
1783 let isCodeGenOnly = 1;
1786 multiclass VOPC_m <vopc op, dag ins, string op_asm, list<dag> pattern,
1787 string opName, bit DefExec, VOPProfile p,
1788 list<SchedReadWrite> sched,
1789 string revOpName = "", string asm = opName#"_e32 "#op_asm,
1790 string alias_asm = opName#" "#op_asm> {
1791 def "" : VOPC_Pseudo <ins, pattern, opName> {
1792 let Defs = !if(DefExec, [VCC, EXEC], [VCC]);
1793 let SchedRW = sched;
1796 let AssemblerPredicates = [isSICI] in {
1797 def _si : VOPC<op.SI, ins, asm, []>,
1798 SIMCInstr <opName#"_e32", SISubtarget.SI> {
1799 let Defs = !if(DefExec, [VCC, EXEC], [VCC]);
1800 let hasSideEffects = DefExec;
1801 let SchedRW = sched;
1804 } // End AssemblerPredicates = [isSICI]
1806 let AssemblerPredicates = [isVI] in {
1807 def _vi : VOPC<op.VI, ins, asm, []>,
1808 SIMCInstr <opName#"_e32", SISubtarget.VI> {
1809 let Defs = !if(DefExec, [VCC, EXEC], [VCC]);
1810 let hasSideEffects = DefExec;
1811 let SchedRW = sched;
1814 } // End AssemblerPredicates = [isVI]
1816 defm : SIInstAliasBuilder<alias_asm, p>;
1819 multiclass VOPC_Helper <vopc op, string opName, list<dag> pat32,
1820 list<dag> pat64, bit DefExec, string revOp,
1821 VOPProfile p, list<SchedReadWrite> sched> {
1822 defm _e32 : VOPC_m <op, p.Ins32, p.Asm32, pat32, opName, DefExec, p, sched>;
1824 defm _e64 : VOP3_C_m <op, (outs VOPDstS64:$dst), p.Ins64, opName#p.Asm64, pat64,
1825 opName, p.HasModifiers, DefExec, revOp, sched>;
1828 // Special case for class instructions which only have modifiers on
1829 // the 1st source operand.
1830 multiclass VOPC_Class_Helper <vopc op, string opName, list<dag> pat32,
1831 list<dag> pat64, bit DefExec, string revOp,
1832 VOPProfile p, list<SchedReadWrite> sched> {
1833 defm _e32 : VOPC_m <op, p.Ins32, p.Asm32, pat32, opName, DefExec, p, sched>;
1835 defm _e64 : VOP3_C_m <op, (outs VOPDstS64:$dst), p.Ins64, opName#p.Asm64, pat64,
1836 opName, p.HasModifiers, DefExec, revOp, sched>,
1837 VOP3DisableModFields<1, 0, 0>;
1840 multiclass VOPCInst <vopc op, string opName,
1841 VOPProfile P, PatLeaf cond = COND_NULL,
1842 string revOp = opName,
1844 list<SchedReadWrite> sched = [Write32Bit]> :
1849 (setcc (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1850 i1:$clamp, i32:$omod)),
1851 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers)),
1853 [(set i1:$dst, (setcc P.Src0VT:$src0, P.Src1VT:$src1, cond))]),
1854 DefExec, revOp, P, sched
1857 multiclass VOPCClassInst <vopc op, string opName, VOPProfile P,
1859 list<SchedReadWrite> sched> : VOPC_Class_Helper <
1863 (AMDGPUfp_class (P.Src0VT (VOP3Mods0Clamp0OMod P.Src0VT:$src0, i32:$src0_modifiers)), P.Src1VT:$src1))],
1864 [(set i1:$dst, (AMDGPUfp_class P.Src0VT:$src0, P.Src1VT:$src1))]),
1865 DefExec, opName, P, sched
1869 multiclass VOPC_F32 <vopc op, string opName, PatLeaf cond = COND_NULL, string revOp = opName> :
1870 VOPCInst <op, opName, VOPC_I1_F32_F32, cond, revOp>;
1872 multiclass VOPC_F64 <vopc op, string opName, PatLeaf cond = COND_NULL, string revOp = opName> :
1873 VOPCInst <op, opName, VOPC_I1_F64_F64, cond, revOp, 0, [WriteDoubleAdd]>;
1875 multiclass VOPC_I32 <vopc op, string opName, PatLeaf cond = COND_NULL, string revOp = opName> :
1876 VOPCInst <op, opName, VOPC_I1_I32_I32, cond, revOp>;
1878 multiclass VOPC_I64 <vopc op, string opName, PatLeaf cond = COND_NULL, string revOp = opName> :
1879 VOPCInst <op, opName, VOPC_I1_I64_I64, cond, revOp, 0, [Write64Bit]>;
1882 multiclass VOPCX <vopc op, string opName, VOPProfile P,
1883 PatLeaf cond = COND_NULL,
1884 list<SchedReadWrite> sched,
1886 : VOPCInst <op, opName, P, cond, revOp, 1, sched>;
1888 multiclass VOPCX_F32 <vopc op, string opName, string revOp = opName> :
1889 VOPCX <op, opName, VOPC_I1_F32_F32, COND_NULL, [Write32Bit], revOp>;
1891 multiclass VOPCX_F64 <vopc op, string opName, string revOp = opName> :
1892 VOPCX <op, opName, VOPC_I1_F64_F64, COND_NULL, [WriteDoubleAdd], revOp>;
1894 multiclass VOPCX_I32 <vopc op, string opName, string revOp = opName> :
1895 VOPCX <op, opName, VOPC_I1_I32_I32, COND_NULL, [Write32Bit], revOp>;
1897 multiclass VOPCX_I64 <vopc op, string opName, string revOp = opName> :
1898 VOPCX <op, opName, VOPC_I1_I64_I64, COND_NULL, [Write64Bit], revOp>;
1900 multiclass VOP3_Helper <vop3 op, string opName, dag outs, dag ins, string asm,
1901 list<dag> pat, int NumSrcArgs, bit HasMods> : VOP3_m <
1902 op, outs, ins, opName#" "#asm, pat, opName, NumSrcArgs, HasMods
1905 multiclass VOPC_CLASS_F32 <vopc op, string opName> :
1906 VOPCClassInst <op, opName, VOPC_I1_F32_I32, 0, [Write32Bit]>;
1908 multiclass VOPCX_CLASS_F32 <vopc op, string opName> :
1909 VOPCClassInst <op, opName, VOPC_I1_F32_I32, 1, [Write32Bit]>;
1911 multiclass VOPC_CLASS_F64 <vopc op, string opName> :
1912 VOPCClassInst <op, opName, VOPC_I1_F64_I32, 0, [WriteDoubleAdd]>;
1914 multiclass VOPCX_CLASS_F64 <vopc op, string opName> :
1915 VOPCClassInst <op, opName, VOPC_I1_F64_I32, 1, [WriteDoubleAdd]>;
1917 multiclass VOP3Inst <vop3 op, string opName, VOPProfile P,
1918 SDPatternOperator node = null_frag> : VOP3_Helper <
1919 op, opName, (outs P.DstRC.RegClass:$dst), P.Ins64, P.Asm64,
1920 !if(!eq(P.NumSrcArgs, 3),
1923 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1924 i1:$clamp, i32:$omod)),
1925 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers)),
1926 (P.Src2VT (VOP3Mods P.Src2VT:$src2, i32:$src2_modifiers))))],
1927 [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1,
1929 !if(!eq(P.NumSrcArgs, 2),
1932 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1933 i1:$clamp, i32:$omod)),
1934 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))],
1935 [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1))])
1936 /* P.NumSrcArgs == 1 */,
1939 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1940 i1:$clamp, i32:$omod))))],
1941 [(set P.DstVT:$dst, (node P.Src0VT:$src0))]))),
1942 P.NumSrcArgs, P.HasModifiers
1945 // Special case for v_div_fmas_{f32|f64}, since it seems to be the
1946 // only VOP instruction that implicitly reads VCC.
1947 multiclass VOP3_VCC_Inst <vop3 op, string opName,
1949 SDPatternOperator node = null_frag> : VOP3_Helper <
1951 (outs P.DstRC.RegClass:$dst),
1952 (ins InputModsNoDefault:$src0_modifiers, P.Src0RC64:$src0,
1953 InputModsNoDefault:$src1_modifiers, P.Src1RC64:$src1,
1954 InputModsNoDefault:$src2_modifiers, P.Src2RC64:$src2,
1957 "$dst, $src0_modifiers, $src1_modifiers, $src2_modifiers"#"$clamp"#"$omod",
1959 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1960 i1:$clamp, i32:$omod)),
1961 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers)),
1962 (P.Src2VT (VOP3Mods P.Src2VT:$src2, i32:$src2_modifiers)),
1967 multiclass VOP3bInst <vop op, string opName, VOPProfile P, list<dag> pattern = []> :
1969 op, P.Outs64, P.Ins64,
1970 opName#" "#P.Asm64, pattern,
1974 class Vop3ModPat<Instruction Inst, VOPProfile P, SDPatternOperator node> : Pat<
1975 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp, i32:$omod)),
1976 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers)),
1977 (P.Src2VT (VOP3Mods P.Src2VT:$src2, i32:$src2_modifiers))),
1978 (Inst i32:$src0_modifiers, P.Src0VT:$src0,
1979 i32:$src1_modifiers, P.Src1VT:$src1,
1980 i32:$src2_modifiers, P.Src2VT:$src2,
1984 //===----------------------------------------------------------------------===//
1985 // Interpolation opcodes
1986 //===----------------------------------------------------------------------===//
1988 class VINTRP_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> :
1989 VINTRPCommon <outs, ins, "", pattern>,
1990 SIMCInstr<opName, SISubtarget.NONE> {
1992 let isCodeGenOnly = 1;
1995 class VINTRP_Real_si <bits <2> op, string opName, dag outs, dag ins,
1997 VINTRPCommon <outs, ins, asm, []>,
1999 SIMCInstr<opName, SISubtarget.SI>;
2001 class VINTRP_Real_vi <bits <2> op, string opName, dag outs, dag ins,
2003 VINTRPCommon <outs, ins, asm, []>,
2005 SIMCInstr<opName, SISubtarget.VI>;
2007 multiclass VINTRP_m <bits <2> op, dag outs, dag ins, string asm,
2008 list<dag> pattern = []> {
2009 def "" : VINTRP_Pseudo <NAME, outs, ins, pattern>;
2011 def _si : VINTRP_Real_si <op, NAME, outs, ins, asm>;
2013 def _vi : VINTRP_Real_vi <op, NAME, outs, ins, asm>;
2016 //===----------------------------------------------------------------------===//
2017 // Vector I/O classes
2018 //===----------------------------------------------------------------------===//
2020 class DS_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> :
2021 DS <outs, ins, "", pattern>,
2022 SIMCInstr <opName, SISubtarget.NONE> {
2024 let isCodeGenOnly = 1;
2027 class DS_Real_si <bits<8> op, string opName, dag outs, dag ins, string asm> :
2028 DS <outs, ins, asm, []>,
2030 SIMCInstr <opName, SISubtarget.SI> {
2031 let isCodeGenOnly = 0;
2034 class DS_Real_vi <bits<8> op, string opName, dag outs, dag ins, string asm> :
2035 DS <outs, ins, asm, []>,
2037 SIMCInstr <opName, SISubtarget.VI>;
2039 class DS_Off16_Real_si <bits<8> op, string opName, dag outs, dag ins, string asm> :
2040 DS_Real_si <op,opName, outs, ins, asm> {
2042 // Single load interpret the 2 i8imm operands as a single i16 offset.
2044 let offset0 = offset{7-0};
2045 let offset1 = offset{15-8};
2046 let isCodeGenOnly = 0;
2049 class DS_Off16_Real_vi <bits<8> op, string opName, dag outs, dag ins, string asm> :
2050 DS_Real_vi <op, opName, outs, ins, asm> {
2052 // Single load interpret the 2 i8imm operands as a single i16 offset.
2054 let offset0 = offset{7-0};
2055 let offset1 = offset{15-8};
2058 multiclass DS_1A_RET <bits<8> op, string opName, RegisterClass rc,
2059 dag outs = (outs rc:$vdst),
2060 dag ins = (ins VGPR_32:$addr, ds_offset:$offset, gds:$gds),
2061 string asm = opName#" $vdst, $addr"#"$offset$gds"> {
2063 def "" : DS_Pseudo <opName, outs, ins, []>;
2065 let data0 = 0, data1 = 0 in {
2066 def _si : DS_Off16_Real_si <op, opName, outs, ins, asm>;
2067 def _vi : DS_Off16_Real_vi <op, opName, outs, ins, asm>;
2071 multiclass DS_1A_Off8_RET <bits<8> op, string opName, RegisterClass rc,
2072 dag outs = (outs rc:$vdst),
2073 dag ins = (ins VGPR_32:$addr, ds_offset0:$offset0, ds_offset1:$offset1,
2075 string asm = opName#" $vdst, $addr"#"$offset0"#"$offset1$gds"> {
2077 def "" : DS_Pseudo <opName, outs, ins, []>;
2079 let data0 = 0, data1 = 0, AsmMatchConverter = "cvtDSOffset01" in {
2080 def _si : DS_Real_si <op, opName, outs, ins, asm>;
2081 def _vi : DS_Real_vi <op, opName, outs, ins, asm>;
2085 multiclass DS_1A1D_NORET <bits<8> op, string opName, RegisterClass rc,
2087 dag ins = (ins VGPR_32:$addr, rc:$data0, ds_offset:$offset, gds:$gds),
2088 string asm = opName#" $addr, $data0"#"$offset$gds"> {
2090 def "" : DS_Pseudo <opName, outs, ins, []>,
2091 AtomicNoRet<opName, 0>;
2093 let data1 = 0, vdst = 0 in {
2094 def _si : DS_Off16_Real_si <op, opName, outs, ins, asm>;
2095 def _vi : DS_Off16_Real_vi <op, opName, outs, ins, asm>;
2099 multiclass DS_1A1D_Off8_NORET <bits<8> op, string opName, RegisterClass rc,
2101 dag ins = (ins VGPR_32:$addr, rc:$data0, rc:$data1,
2102 ds_offset0:$offset0, ds_offset1:$offset1, gds01:$gds),
2103 string asm = opName#" $addr, $data0, $data1"#"$offset0"#"$offset1"#"$gds"> {
2105 def "" : DS_Pseudo <opName, outs, ins, []>;
2107 let vdst = 0, AsmMatchConverter = "cvtDSOffset01" in {
2108 def _si : DS_Real_si <op, opName, outs, ins, asm>;
2109 def _vi : DS_Real_vi <op, opName, outs, ins, asm>;
2113 multiclass DS_1A1D_RET <bits<8> op, string opName, RegisterClass rc,
2114 string noRetOp = "",
2115 dag outs = (outs rc:$vdst),
2116 dag ins = (ins VGPR_32:$addr, rc:$data0, ds_offset:$offset, gds:$gds),
2117 string asm = opName#" $vdst, $addr, $data0"#"$offset$gds"> {
2119 let hasPostISelHook = 1 in {
2120 def "" : DS_Pseudo <opName, outs, ins, []>,
2121 AtomicNoRet<noRetOp, 1>;
2124 def _si : DS_Off16_Real_si <op, opName, outs, ins, asm>;
2125 def _vi : DS_Off16_Real_vi <op, opName, outs, ins, asm>;
2130 multiclass DS_1A2D_RET_m <bits<8> op, string opName, RegisterClass rc,
2131 string noRetOp = "", dag ins,
2132 dag outs = (outs rc:$vdst),
2133 string asm = opName#" $vdst, $addr, $data0, $data1"#"$offset"#"$gds"> {
2135 let hasPostISelHook = 1 in {
2136 def "" : DS_Pseudo <opName, outs, ins, []>,
2137 AtomicNoRet<noRetOp, 1>;
2139 def _si : DS_Off16_Real_si <op, opName, outs, ins, asm>;
2140 def _vi : DS_Off16_Real_vi <op, opName, outs, ins, asm>;
2144 multiclass DS_1A2D_RET <bits<8> op, string asm, RegisterClass rc,
2145 string noRetOp = "", RegisterClass src = rc> :
2146 DS_1A2D_RET_m <op, asm, rc, noRetOp,
2147 (ins VGPR_32:$addr, src:$data0, src:$data1,
2148 ds_offset:$offset, gds:$gds)
2151 multiclass DS_1A2D_NORET <bits<8> op, string opName, RegisterClass rc,
2152 string noRetOp = opName,
2154 dag ins = (ins VGPR_32:$addr, rc:$data0, rc:$data1,
2155 ds_offset:$offset, gds:$gds),
2156 string asm = opName#" $addr, $data0, $data1"#"$offset"#"$gds"> {
2158 def "" : DS_Pseudo <opName, outs, ins, []>,
2159 AtomicNoRet<noRetOp, 0>;
2162 def _si : DS_Off16_Real_si <op, opName, outs, ins, asm>;
2163 def _vi : DS_Off16_Real_vi <op, opName, outs, ins, asm>;
2167 multiclass DS_0A_RET <bits<8> op, string opName,
2168 dag outs = (outs VGPR_32:$vdst),
2169 dag ins = (ins ds_offset:$offset, gds:$gds),
2170 string asm = opName#" $vdst"#"$offset"#"$gds"> {
2172 let mayLoad = 1, mayStore = 1 in {
2173 def "" : DS_Pseudo <opName, outs, ins, []>;
2175 let addr = 0, data0 = 0, data1 = 0 in {
2176 def _si : DS_Off16_Real_si <op, opName, outs, ins, asm>;
2177 def _vi : DS_Off16_Real_vi <op, opName, outs, ins, asm>;
2178 } // end addr = 0, data0 = 0, data1 = 0
2179 } // end mayLoad = 1, mayStore = 1
2182 multiclass DS_1A_RET_GDS <bits<8> op, string opName,
2183 dag outs = (outs VGPR_32:$vdst),
2184 dag ins = (ins VGPR_32:$addr, ds_offset_gds:$offset),
2185 string asm = opName#" $vdst, $addr"#"$offset gds"> {
2187 def "" : DS_Pseudo <opName, outs, ins, []>;
2189 let data0 = 0, data1 = 0, gds = 1 in {
2190 def _si : DS_Off16_Real_si <op, opName, outs, ins, asm>;
2191 def _vi : DS_Off16_Real_vi <op, opName, outs, ins, asm>;
2192 } // end data0 = 0, data1 = 0, gds = 1
2195 multiclass DS_1A_GDS <bits<8> op, string opName,
2197 dag ins = (ins VGPR_32:$addr),
2198 string asm = opName#" $addr gds"> {
2200 def "" : DS_Pseudo <opName, outs, ins, []>;
2202 let vdst = 0, data0 = 0, data1 = 0, offset0 = 0, offset1 = 0, gds = 1 in {
2203 def _si : DS_Real_si <op, opName, outs, ins, asm>;
2204 def _vi : DS_Real_vi <op, opName, outs, ins, asm>;
2205 } // end vdst = 0, data = 0, data1 = 0, gds = 1
2208 multiclass DS_1A <bits<8> op, string opName,
2210 dag ins = (ins VGPR_32:$addr, ds_offset:$offset, gds:$gds),
2211 string asm = opName#" $addr"#"$offset"#"$gds"> {
2213 let mayLoad = 1, mayStore = 1 in {
2214 def "" : DS_Pseudo <opName, outs, ins, []>;
2216 let vdst = 0, data0 = 0, data1 = 0 in {
2217 def _si : DS_Off16_Real_si <op, opName, outs, ins, asm>;
2218 def _vi : DS_Off16_Real_vi <op, opName, outs, ins, asm>;
2219 } // let vdst = 0, data0 = 0, data1 = 0
2220 } // end mayLoad = 1, mayStore = 1
2223 //===----------------------------------------------------------------------===//
2225 //===----------------------------------------------------------------------===//
2227 class MTBUF_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> :
2228 MTBUF <outs, ins, "", pattern>,
2229 SIMCInstr<opName, SISubtarget.NONE> {
2231 let isCodeGenOnly = 1;
2234 class MTBUF_Real_si <bits<3> op, string opName, dag outs, dag ins,
2236 MTBUF <outs, ins, asm, []>,
2238 SIMCInstr<opName, SISubtarget.SI>;
2240 class MTBUF_Real_vi <bits<4> op, string opName, dag outs, dag ins, string asm> :
2241 MTBUF <outs, ins, asm, []>,
2243 SIMCInstr <opName, SISubtarget.VI>;
2245 multiclass MTBUF_m <bits<3> op, string opName, dag outs, dag ins, string asm,
2246 list<dag> pattern> {
2248 def "" : MTBUF_Pseudo <opName, outs, ins, pattern>;
2250 def _si : MTBUF_Real_si <op, opName, outs, ins, asm>;
2252 def _vi : MTBUF_Real_vi <{0, op{2}, op{1}, op{0}}, opName, outs, ins, asm>;
2256 let mayStore = 1, mayLoad = 0 in {
2258 multiclass MTBUF_Store_Helper <bits<3> op, string opName,
2259 RegisterClass regClass> : MTBUF_m <
2261 (ins regClass:$vdata, u16imm:$offset, i1imm:$offen, i1imm:$idxen, i1imm:$glc,
2262 i1imm:$addr64, i8imm:$dfmt, i8imm:$nfmt, VGPR_32:$vaddr,
2263 SReg_128:$srsrc, i1imm:$slc, i1imm:$tfe, SCSrc_32:$soffset),
2264 opName#" $vdata, $offset, $offen, $idxen, $glc, $addr64, $dfmt,"
2265 #" $nfmt, $vaddr, $srsrc, $slc, $tfe, $soffset", []
2268 } // mayStore = 1, mayLoad = 0
2270 let mayLoad = 1, mayStore = 0 in {
2272 multiclass MTBUF_Load_Helper <bits<3> op, string opName,
2273 RegisterClass regClass> : MTBUF_m <
2274 op, opName, (outs regClass:$dst),
2275 (ins u16imm:$offset, i1imm:$offen, i1imm:$idxen, i1imm:$glc, i1imm:$addr64,
2276 i8imm:$dfmt, i8imm:$nfmt, VGPR_32:$vaddr, SReg_128:$srsrc,
2277 i1imm:$slc, i1imm:$tfe, SCSrc_32:$soffset),
2278 opName#" $dst, $offset, $offen, $idxen, $glc, $addr64, $dfmt,"
2279 #" $nfmt, $vaddr, $srsrc, $slc, $tfe, $soffset", []
2282 } // mayLoad = 1, mayStore = 0
2284 //===----------------------------------------------------------------------===//
2286 //===----------------------------------------------------------------------===//
2288 class mubuf <bits<7> si, bits<7> vi = si> {
2289 field bits<7> SI = si;
2290 field bits<7> VI = vi;
2293 let isCodeGenOnly = 0 in {
2295 class MUBUF_si <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern> :
2296 MUBUF <outs, ins, asm, pattern>, MUBUFe <op> {
2300 } // End let isCodeGenOnly = 0
2302 class MUBUF_vi <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern> :
2303 MUBUF <outs, ins, asm, pattern>, MUBUFe_vi <op> {
2307 class MUBUFAddr64Table <bit is_addr64, string suffix = ""> {
2308 bit IsAddr64 = is_addr64;
2309 string OpName = NAME # suffix;
2312 class MUBUF_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> :
2313 MUBUF <outs, ins, "", pattern>,
2314 SIMCInstr<opName, SISubtarget.NONE> {
2316 let isCodeGenOnly = 1;
2318 // dummy fields, so that we can use let statements around multiclasses
2328 class MUBUF_Real_si <mubuf op, string opName, dag outs, dag ins,
2330 MUBUF <outs, ins, asm, []>,
2332 SIMCInstr<opName, SISubtarget.SI> {
2336 class MUBUF_Real_vi <mubuf op, string opName, dag outs, dag ins,
2338 MUBUF <outs, ins, asm, []>,
2340 SIMCInstr<opName, SISubtarget.VI> {
2344 multiclass MUBUF_m <mubuf op, string opName, dag outs, dag ins, string asm,
2345 list<dag> pattern> {
2347 def "" : MUBUF_Pseudo <opName, outs, ins, pattern>,
2348 MUBUFAddr64Table <0>;
2350 let addr64 = 0, isCodeGenOnly = 0 in {
2351 def _si : MUBUF_Real_si <op, opName, outs, ins, asm>;
2354 def _vi : MUBUF_Real_vi <op, opName, outs, ins, asm>;
2357 multiclass MUBUFAddr64_m <mubuf op, string opName, dag outs,
2358 dag ins, string asm, list<dag> pattern> {
2360 def "" : MUBUF_Pseudo <opName, outs, ins, pattern>,
2361 MUBUFAddr64Table <1>;
2363 let addr64 = 1, isCodeGenOnly = 0 in {
2364 def _si : MUBUF_Real_si <op, opName, outs, ins, asm>;
2367 // There is no VI version. If the pseudo is selected, it should be lowered
2368 // for VI appropriately.
2371 multiclass MUBUFAtomicOffset_m <mubuf op, string opName, dag outs, dag ins,
2372 string asm, list<dag> pattern, bit is_return> {
2374 def "" : MUBUF_Pseudo <opName, outs, ins, pattern>,
2375 MUBUFAddr64Table <0, !if(is_return, "_RTN", "")>,
2376 AtomicNoRet<NAME#"_OFFSET", is_return>;
2378 let offen = 0, idxen = 0, tfe = 0, vaddr = 0 in {
2380 def _si : MUBUF_Real_si <op, opName, outs, ins, asm>;
2383 def _vi : MUBUF_Real_vi <op, opName, outs, ins, asm>;
2387 multiclass MUBUFAtomicAddr64_m <mubuf op, string opName, dag outs, dag ins,
2388 string asm, list<dag> pattern, bit is_return> {
2390 def "" : MUBUF_Pseudo <opName, outs, ins, pattern>,
2391 MUBUFAddr64Table <1, !if(is_return, "_RTN", "")>,
2392 AtomicNoRet<NAME#"_ADDR64", is_return>;
2394 let offen = 0, idxen = 0, addr64 = 1, tfe = 0 in {
2395 def _si : MUBUF_Real_si <op, opName, outs, ins, asm>;
2398 // There is no VI version. If the pseudo is selected, it should be lowered
2399 // for VI appropriately.
2402 multiclass MUBUF_Atomic <mubuf op, string name, RegisterClass rc,
2403 ValueType vt, SDPatternOperator atomic> {
2405 let mayStore = 1, mayLoad = 1, hasPostISelHook = 1 in {
2407 // No return variants
2410 defm _ADDR64 : MUBUFAtomicAddr64_m <
2411 op, name#"_addr64", (outs),
2412 (ins rc:$vdata, VReg_64:$vaddr, SReg_128:$srsrc,
2413 SCSrc_32:$soffset, mbuf_offset:$offset, slc:$slc),
2414 name#" $vdata, $vaddr, $srsrc, $soffset addr64"#"$offset"#"$slc", [], 0
2417 defm _OFFSET : MUBUFAtomicOffset_m <
2418 op, name#"_offset", (outs),
2419 (ins rc:$vdata, SReg_128:$srsrc, SCSrc_32:$soffset, mbuf_offset:$offset,
2421 name#" $vdata, $srsrc, $soffset"#"$offset"#"$slc", [], 0
2425 // Variant that return values
2426 let glc = 1, Constraints = "$vdata = $vdata_in",
2427 DisableEncoding = "$vdata_in" in {
2429 defm _RTN_ADDR64 : MUBUFAtomicAddr64_m <
2430 op, name#"_rtn_addr64", (outs rc:$vdata),
2431 (ins rc:$vdata_in, VReg_64:$vaddr, SReg_128:$srsrc,
2432 SCSrc_32:$soffset, mbuf_offset:$offset, slc:$slc),
2433 name#" $vdata, $vaddr, $srsrc, $soffset addr64"#"$offset"#" glc"#"$slc",
2435 (atomic (MUBUFAddr64Atomic v4i32:$srsrc, i64:$vaddr, i32:$soffset,
2436 i16:$offset, i1:$slc), vt:$vdata_in))], 1
2439 defm _RTN_OFFSET : MUBUFAtomicOffset_m <
2440 op, name#"_rtn_offset", (outs rc:$vdata),
2441 (ins rc:$vdata_in, SReg_128:$srsrc, SCSrc_32:$soffset,
2442 mbuf_offset:$offset, slc:$slc),
2443 name#" $vdata, $srsrc, $soffset"#"$offset"#" glc$slc",
2445 (atomic (MUBUFOffsetAtomic v4i32:$srsrc, i32:$soffset, i16:$offset,
2446 i1:$slc), vt:$vdata_in))], 1
2451 } // mayStore = 1, mayLoad = 1, hasPostISelHook = 1
2454 // FIXME: tfe can't be an operand because it requires a separate
2455 // opcode because it needs an N+1 register class dest register.
2456 multiclass MUBUF_Load_Helper <mubuf op, string name, RegisterClass regClass,
2457 ValueType load_vt = i32,
2458 SDPatternOperator ld = null_frag> {
2460 let mayLoad = 1, mayStore = 0 in {
2461 let offen = 0, idxen = 0, vaddr = 0 in {
2462 defm _OFFSET : MUBUF_m <op, name#"_offset", (outs regClass:$vdata),
2463 (ins SReg_128:$srsrc, SCSrc_32:$soffset,
2464 mbuf_offset:$offset, glc:$glc, slc:$slc, tfe:$tfe),
2465 name#" $vdata, $srsrc, $soffset"#"$offset"#"$glc"#"$slc"#"$tfe",
2466 [(set load_vt:$vdata, (ld (MUBUFOffset v4i32:$srsrc,
2467 i32:$soffset, i16:$offset,
2468 i1:$glc, i1:$slc, i1:$tfe)))]>;
2471 let offen = 1, idxen = 0 in {
2472 defm _OFFEN : MUBUF_m <op, name#"_offen", (outs regClass:$vdata),
2473 (ins VGPR_32:$vaddr, SReg_128:$srsrc,
2474 SCSrc_32:$soffset, mbuf_offset:$offset, glc:$glc, slc:$slc,
2476 name#" $vdata, $vaddr, $srsrc, $soffset offen"#"$offset"#"$glc"#"$slc"#"$tfe", []>;
2479 let offen = 0, idxen = 1 in {
2480 defm _IDXEN : MUBUF_m <op, name#"_idxen", (outs regClass:$vdata),
2481 (ins VGPR_32:$vaddr, SReg_128:$srsrc,
2482 SCSrc_32:$soffset, mbuf_offset:$offset, glc:$glc,
2483 slc:$slc, tfe:$tfe),
2484 name#" $vdata, $vaddr, $srsrc, $soffset idxen"#"$offset"#"$glc"#"$slc"#"$tfe", []>;
2487 let offen = 1, idxen = 1 in {
2488 defm _BOTHEN : MUBUF_m <op, name#"_bothen", (outs regClass:$vdata),
2489 (ins VReg_64:$vaddr, SReg_128:$srsrc, SCSrc_32:$soffset,
2490 mbuf_offset:$offset, glc:$glc, slc:$slc, tfe:$tfe),
2491 name#" $vdata, $vaddr, $srsrc, $soffset idxen offen"#"$offset"#"$glc"#"$slc"#"$tfe", []>;
2494 let offen = 0, idxen = 0 in {
2495 defm _ADDR64 : MUBUFAddr64_m <op, name#"_addr64", (outs regClass:$vdata),
2496 (ins VReg_64:$vaddr, SReg_128:$srsrc,
2497 SCSrc_32:$soffset, mbuf_offset:$offset,
2498 glc:$glc, slc:$slc, tfe:$tfe),
2499 name#" $vdata, $vaddr, $srsrc, $soffset addr64"#"$offset"#
2500 "$glc"#"$slc"#"$tfe",
2501 [(set load_vt:$vdata, (ld (MUBUFAddr64 v4i32:$srsrc,
2502 i64:$vaddr, i32:$soffset,
2503 i16:$offset, i1:$glc, i1:$slc,
2509 multiclass MUBUF_Store_Helper <mubuf op, string name, RegisterClass vdataClass,
2510 ValueType store_vt = i32, SDPatternOperator st = null_frag> {
2511 let mayLoad = 0, mayStore = 1 in {
2512 defm : MUBUF_m <op, name, (outs),
2513 (ins vdataClass:$vdata, VGPR_32:$vaddr, SReg_128:$srsrc, SCSrc_32:$soffset,
2514 mbuf_offset:$offset, offen:$offen, idxen:$idxen, glc:$glc, slc:$slc,
2516 name#" $vdata, $vaddr, $srsrc, $soffset"#"$offen"#"$idxen"#"$offset"#
2517 "$glc"#"$slc"#"$tfe", []>;
2519 let offen = 0, idxen = 0, vaddr = 0 in {
2520 defm _OFFSET : MUBUF_m <op, name#"_offset",(outs),
2521 (ins vdataClass:$vdata, SReg_128:$srsrc, SCSrc_32:$soffset,
2522 mbuf_offset:$offset, glc:$glc, slc:$slc, tfe:$tfe),
2523 name#" $vdata, $srsrc, $soffset"#"$offset"#"$glc"#"$slc"#"$tfe",
2524 [(st store_vt:$vdata, (MUBUFOffset v4i32:$srsrc, i32:$soffset,
2525 i16:$offset, i1:$glc, i1:$slc, i1:$tfe))]>;
2526 } // offen = 0, idxen = 0, vaddr = 0
2528 let offen = 1, idxen = 0 in {
2529 defm _OFFEN : MUBUF_m <op, name#"_offen", (outs),
2530 (ins vdataClass:$vdata, VGPR_32:$vaddr, SReg_128:$srsrc,
2531 SCSrc_32:$soffset, mbuf_offset:$offset, glc:$glc,
2532 slc:$slc, tfe:$tfe),
2533 name#" $vdata, $vaddr, $srsrc, $soffset offen"#"$offset"#
2534 "$glc"#"$slc"#"$tfe", []>;
2535 } // end offen = 1, idxen = 0
2537 let offen = 0, idxen = 1 in {
2538 defm _IDXEN : MUBUF_m <op, name#"_idxen", (outs),
2539 (ins vdataClass:$vdata, VGPR_32:$vaddr, SReg_128:$srsrc,
2540 SCSrc_32:$soffset, mbuf_offset:$offset, glc:$glc,
2541 slc:$slc, tfe:$tfe),
2542 name#" $vdata, $vaddr, $srsrc, $soffset idxen"#"$offset"#"$glc"#"$slc"#"$tfe", []>;
2545 let offen = 1, idxen = 1 in {
2546 defm _BOTHEN : MUBUF_m <op, name#"_bothen", (outs),
2547 (ins vdataClass:$vdata, VReg_64:$vaddr, SReg_128:$srsrc, SCSrc_32:$soffset,
2548 mbuf_offset:$offset, glc:$glc, slc:$slc, tfe:$tfe),
2549 name#" $vdata, $vaddr, $srsrc, $soffset idxen offen"#"$offset"#"$glc"#"$slc"#"$tfe", []>;
2552 let offen = 0, idxen = 0 in {
2553 defm _ADDR64 : MUBUFAddr64_m <op, name#"_addr64", (outs),
2554 (ins vdataClass:$vdata, VReg_64:$vaddr, SReg_128:$srsrc,
2556 mbuf_offset:$offset, glc:$glc, slc:$slc,
2558 name#" $vdata, $vaddr, $srsrc, $soffset addr64"#
2559 "$offset"#"$glc"#"$slc"#"$tfe",
2560 [(st store_vt:$vdata,
2561 (MUBUFAddr64 v4i32:$srsrc, i64:$vaddr,
2562 i32:$soffset, i16:$offset,
2563 i1:$glc, i1:$slc, i1:$tfe))]>;
2565 } // End mayLoad = 0, mayStore = 1
2568 // For cache invalidation instructions.
2569 multiclass MUBUF_Invalidate <mubuf op, string opName, SDPatternOperator node> {
2570 let hasSideEffects = 1, mayStore = 1, AsmMatchConverter = "" in {
2571 def "" : MUBUF_Pseudo <opName, (outs), (ins), [(node)]>;
2573 // Set everything to 0.
2574 let offset = 0, offen = 0, idxen = 0, glc = 0, vaddr = 0,
2575 vdata = 0, srsrc = 0, slc = 0, tfe = 0, soffset = 0 in {
2577 def _si : MUBUF_Real_si <op, opName, (outs), (ins), opName>;
2580 def _vi : MUBUF_Real_vi <op, opName, (outs), (ins), opName>;
2582 } // End hasSideEffects = 1, mayStore = 1, AsmMatchConverter = ""
2585 //===----------------------------------------------------------------------===//
2587 //===----------------------------------------------------------------------===//
2589 class flat <bits<7> ci, bits<7> vi = ci> {
2590 field bits<7> CI = ci;
2591 field bits<7> VI = vi;
2594 class FLAT_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> :
2595 FLAT <0, outs, ins, "", pattern>,
2596 SIMCInstr<opName, SISubtarget.NONE> {
2598 let isCodeGenOnly = 1;
2601 class FLAT_Real_ci <bits<7> op, string opName, dag outs, dag ins, string asm> :
2602 FLAT <op, outs, ins, asm, []>,
2603 SIMCInstr<opName, SISubtarget.SI> {
2604 let AssemblerPredicate = isCIOnly;
2607 class FLAT_Real_vi <bits<7> op, string opName, dag outs, dag ins, string asm> :
2608 FLAT <op, outs, ins, asm, []>,
2609 SIMCInstr<opName, SISubtarget.VI> {
2610 let AssemblerPredicate = VIAssemblerPredicate;
2613 multiclass FLAT_AtomicRet_m <flat op, dag outs, dag ins, string asm,
2614 list<dag> pattern> {
2615 def "" : FLAT_Pseudo <NAME#"_RTN", outs, ins, pattern>,
2616 AtomicNoRet <NAME, 1>;
2618 def _ci : FLAT_Real_ci <op.CI, NAME#"_RTN", outs, ins, asm>;
2620 def _vi : FLAT_Real_vi <op.VI, NAME#"_RTN", outs, ins, asm>;
2623 multiclass FLAT_Load_Helper <flat op, string asm_name,
2624 RegisterClass regClass,
2625 dag outs = (outs regClass:$vdst),
2626 dag ins = (ins VReg_64:$addr, glc_flat:$glc, slc_flat:$slc, tfe_flat:$tfe),
2627 string asm = asm_name#" $vdst, $addr"#"$glc"#"$slc"#"$tfe"> {
2629 let data = 0, mayLoad = 1 in {
2631 def "" : FLAT_Pseudo <NAME, outs, ins, []>;
2633 def _ci : FLAT_Real_ci <op.CI, NAME, outs, ins, asm>;
2635 def _vi : FLAT_Real_vi <op.VI, NAME, outs, ins, asm>;
2639 multiclass FLAT_Store_Helper <flat op, string asm_name,
2640 RegisterClass vdataClass,
2642 dag ins = (ins vdataClass:$data, VReg_64:$addr, glc_flat:$glc,
2643 slc_flat:$slc, tfe_flat:$tfe),
2644 string asm = asm_name#" $data, $addr"#"$glc"#"$slc"#"$tfe"> {
2646 let mayLoad = 0, mayStore = 1, vdst = 0 in {
2648 def "" : FLAT_Pseudo <NAME, outs, ins, []>;
2650 def _ci : FLAT_Real_ci <op.CI, NAME, outs, ins, asm>;
2652 def _vi : FLAT_Real_vi <op.VI, NAME, outs, ins, asm>;
2656 multiclass FLAT_ATOMIC <flat op, string asm_name, RegisterClass vdst_rc,
2657 RegisterClass data_rc = vdst_rc,
2658 dag outs_noret = (outs),
2659 string asm_noret = asm_name#" $addr, $data"#"$slc"#"$tfe"> {
2661 let mayLoad = 1, mayStore = 1, glc = 0, vdst = 0 in {
2662 def "" : FLAT_Pseudo <NAME, outs_noret,
2663 (ins VReg_64:$addr, data_rc:$data,
2664 slc_flat_atomic:$slc, tfe_flat_atomic:$tfe), []>,
2665 AtomicNoRet <NAME, 0>;
2667 def _ci : FLAT_Real_ci <op.CI, NAME, outs_noret,
2668 (ins VReg_64:$addr, data_rc:$data,
2669 slc_flat_atomic:$slc, tfe_flat_atomic:$tfe),
2672 def _vi : FLAT_Real_vi <op.VI, NAME, outs_noret,
2673 (ins VReg_64:$addr, data_rc:$data,
2674 slc_flat_atomic:$slc, tfe_flat_atomic:$tfe),
2678 let glc = 1, hasPostISelHook = 1 in {
2679 defm _RTN : FLAT_AtomicRet_m <op, (outs vdst_rc:$vdst),
2680 (ins VReg_64:$addr, data_rc:$data, slc_flat_atomic:$slc,
2681 tfe_flat_atomic:$tfe),
2682 asm_name#" $vdst, $addr, $data glc"#"$slc"#"$tfe", []>;
2686 class MIMG_Mask <string op, int channels> {
2688 int Channels = channels;
2691 class MIMG_NoSampler_Helper <bits<7> op, string asm,
2692 RegisterClass dst_rc,
2693 RegisterClass src_rc> : MIMG <
2695 (outs dst_rc:$vdata),
2696 (ins i32imm:$dmask, i1imm:$unorm, i1imm:$glc, i1imm:$da, i1imm:$r128,
2697 i1imm:$tfe, i1imm:$lwe, i1imm:$slc, src_rc:$vaddr,
2699 asm#" $vdata, $dmask, $unorm, $glc, $da, $r128,"
2700 #" $tfe, $lwe, $slc, $vaddr, $srsrc",
2705 let hasPostISelHook = 1;
2708 multiclass MIMG_NoSampler_Src_Helper <bits<7> op, string asm,
2709 RegisterClass dst_rc,
2711 def _V1 : MIMG_NoSampler_Helper <op, asm, dst_rc, VGPR_32>,
2712 MIMG_Mask<asm#"_V1", channels>;
2713 def _V2 : MIMG_NoSampler_Helper <op, asm, dst_rc, VReg_64>,
2714 MIMG_Mask<asm#"_V2", channels>;
2715 def _V4 : MIMG_NoSampler_Helper <op, asm, dst_rc, VReg_128>,
2716 MIMG_Mask<asm#"_V4", channels>;
2719 multiclass MIMG_NoSampler <bits<7> op, string asm> {
2720 defm _V1 : MIMG_NoSampler_Src_Helper <op, asm, VGPR_32, 1>;
2721 defm _V2 : MIMG_NoSampler_Src_Helper <op, asm, VReg_64, 2>;
2722 defm _V3 : MIMG_NoSampler_Src_Helper <op, asm, VReg_96, 3>;
2723 defm _V4 : MIMG_NoSampler_Src_Helper <op, asm, VReg_128, 4>;
2726 class MIMG_Sampler_Helper <bits<7> op, string asm,
2727 RegisterClass dst_rc,
2728 RegisterClass src_rc, int wqm> : MIMG <
2730 (outs dst_rc:$vdata),
2731 (ins i32imm:$dmask, i1imm:$unorm, i1imm:$glc, i1imm:$da, i1imm:$r128,
2732 i1imm:$tfe, i1imm:$lwe, i1imm:$slc, src_rc:$vaddr,
2733 SReg_256:$srsrc, SReg_128:$ssamp),
2734 asm#" $vdata, $dmask, $unorm, $glc, $da, $r128,"
2735 #" $tfe, $lwe, $slc, $vaddr, $srsrc, $ssamp",
2739 let hasPostISelHook = 1;
2743 multiclass MIMG_Sampler_Src_Helper <bits<7> op, string asm,
2744 RegisterClass dst_rc,
2745 int channels, int wqm> {
2746 def _V1 : MIMG_Sampler_Helper <op, asm, dst_rc, VGPR_32, wqm>,
2747 MIMG_Mask<asm#"_V1", channels>;
2748 def _V2 : MIMG_Sampler_Helper <op, asm, dst_rc, VReg_64, wqm>,
2749 MIMG_Mask<asm#"_V2", channels>;
2750 def _V4 : MIMG_Sampler_Helper <op, asm, dst_rc, VReg_128, wqm>,
2751 MIMG_Mask<asm#"_V4", channels>;
2752 def _V8 : MIMG_Sampler_Helper <op, asm, dst_rc, VReg_256, wqm>,
2753 MIMG_Mask<asm#"_V8", channels>;
2754 def _V16 : MIMG_Sampler_Helper <op, asm, dst_rc, VReg_512, wqm>,
2755 MIMG_Mask<asm#"_V16", channels>;
2758 multiclass MIMG_Sampler <bits<7> op, string asm> {
2759 defm _V1 : MIMG_Sampler_Src_Helper<op, asm, VGPR_32, 1, 0>;
2760 defm _V2 : MIMG_Sampler_Src_Helper<op, asm, VReg_64, 2, 0>;
2761 defm _V3 : MIMG_Sampler_Src_Helper<op, asm, VReg_96, 3, 0>;
2762 defm _V4 : MIMG_Sampler_Src_Helper<op, asm, VReg_128, 4, 0>;
2765 multiclass MIMG_Sampler_WQM <bits<7> op, string asm> {
2766 defm _V1 : MIMG_Sampler_Src_Helper<op, asm, VGPR_32, 1, 1>;
2767 defm _V2 : MIMG_Sampler_Src_Helper<op, asm, VReg_64, 2, 1>;
2768 defm _V3 : MIMG_Sampler_Src_Helper<op, asm, VReg_96, 3, 1>;
2769 defm _V4 : MIMG_Sampler_Src_Helper<op, asm, VReg_128, 4, 1>;
2772 class MIMG_Gather_Helper <bits<7> op, string asm,
2773 RegisterClass dst_rc,
2774 RegisterClass src_rc, int wqm> : MIMG <
2776 (outs dst_rc:$vdata),
2777 (ins i32imm:$dmask, i1imm:$unorm, i1imm:$glc, i1imm:$da, i1imm:$r128,
2778 i1imm:$tfe, i1imm:$lwe, i1imm:$slc, src_rc:$vaddr,
2779 SReg_256:$srsrc, SReg_128:$ssamp),
2780 asm#" $vdata, $dmask, $unorm, $glc, $da, $r128,"
2781 #" $tfe, $lwe, $slc, $vaddr, $srsrc, $ssamp",
2786 // DMASK was repurposed for GATHER4. 4 components are always
2787 // returned and DMASK works like a swizzle - it selects
2788 // the component to fetch. The only useful DMASK values are
2789 // 1=red, 2=green, 4=blue, 8=alpha. (e.g. 1 returns
2790 // (red,red,red,red) etc.) The ISA document doesn't mention
2792 // Therefore, disable all code which updates DMASK by setting these two:
2794 let hasPostISelHook = 0;
2798 multiclass MIMG_Gather_Src_Helper <bits<7> op, string asm,
2799 RegisterClass dst_rc,
2800 int channels, int wqm> {
2801 def _V1 : MIMG_Gather_Helper <op, asm, dst_rc, VGPR_32, wqm>,
2802 MIMG_Mask<asm#"_V1", channels>;
2803 def _V2 : MIMG_Gather_Helper <op, asm, dst_rc, VReg_64, wqm>,
2804 MIMG_Mask<asm#"_V2", channels>;
2805 def _V4 : MIMG_Gather_Helper <op, asm, dst_rc, VReg_128, wqm>,
2806 MIMG_Mask<asm#"_V4", channels>;
2807 def _V8 : MIMG_Gather_Helper <op, asm, dst_rc, VReg_256, wqm>,
2808 MIMG_Mask<asm#"_V8", channels>;
2809 def _V16 : MIMG_Gather_Helper <op, asm, dst_rc, VReg_512, wqm>,
2810 MIMG_Mask<asm#"_V16", channels>;
2813 multiclass MIMG_Gather <bits<7> op, string asm> {
2814 defm _V1 : MIMG_Gather_Src_Helper<op, asm, VGPR_32, 1, 0>;
2815 defm _V2 : MIMG_Gather_Src_Helper<op, asm, VReg_64, 2, 0>;
2816 defm _V3 : MIMG_Gather_Src_Helper<op, asm, VReg_96, 3, 0>;
2817 defm _V4 : MIMG_Gather_Src_Helper<op, asm, VReg_128, 4, 0>;
2820 multiclass MIMG_Gather_WQM <bits<7> op, string asm> {
2821 defm _V1 : MIMG_Gather_Src_Helper<op, asm, VGPR_32, 1, 1>;
2822 defm _V2 : MIMG_Gather_Src_Helper<op, asm, VReg_64, 2, 1>;
2823 defm _V3 : MIMG_Gather_Src_Helper<op, asm, VReg_96, 3, 1>;
2824 defm _V4 : MIMG_Gather_Src_Helper<op, asm, VReg_128, 4, 1>;
2827 //===----------------------------------------------------------------------===//
2828 // Vector instruction mappings
2829 //===----------------------------------------------------------------------===//
2831 // Maps an opcode in e32 form to its e64 equivalent
2832 def getVOPe64 : InstrMapping {
2833 let FilterClass = "VOP";
2834 let RowFields = ["OpName"];
2835 let ColFields = ["Size"];
2837 let ValueCols = [["8"]];
2840 // Maps an opcode in e64 form to its e32 equivalent
2841 def getVOPe32 : InstrMapping {
2842 let FilterClass = "VOP";
2843 let RowFields = ["OpName"];
2844 let ColFields = ["Size"];
2846 let ValueCols = [["4"]];
2849 def getMaskedMIMGOp : InstrMapping {
2850 let FilterClass = "MIMG_Mask";
2851 let RowFields = ["Op"];
2852 let ColFields = ["Channels"];
2854 let ValueCols = [["1"], ["2"], ["3"] ];
2857 // Maps an commuted opcode to its original version
2858 def getCommuteOrig : InstrMapping {
2859 let FilterClass = "VOP2_REV";
2860 let RowFields = ["RevOp"];
2861 let ColFields = ["IsOrig"];
2863 let ValueCols = [["1"]];
2866 // Maps an original opcode to its commuted version
2867 def getCommuteRev : InstrMapping {
2868 let FilterClass = "VOP2_REV";
2869 let RowFields = ["RevOp"];
2870 let ColFields = ["IsOrig"];
2872 let ValueCols = [["0"]];
2875 def getCommuteCmpOrig : InstrMapping {
2876 let FilterClass = "VOP2_REV";
2877 let RowFields = ["RevOp"];
2878 let ColFields = ["IsOrig"];
2880 let ValueCols = [["1"]];
2883 // Maps an original opcode to its commuted version
2884 def getCommuteCmpRev : InstrMapping {
2885 let FilterClass = "VOP2_REV";
2886 let RowFields = ["RevOp"];
2887 let ColFields = ["IsOrig"];
2889 let ValueCols = [["0"]];
2893 def getMCOpcodeGen : InstrMapping {
2894 let FilterClass = "SIMCInstr";
2895 let RowFields = ["PseudoInstr"];
2896 let ColFields = ["Subtarget"];
2897 let KeyCol = [!cast<string>(SISubtarget.NONE)];
2898 let ValueCols = [[!cast<string>(SISubtarget.SI)],[!cast<string>(SISubtarget.VI)]];
2901 def getAddr64Inst : InstrMapping {
2902 let FilterClass = "MUBUFAddr64Table";
2903 let RowFields = ["OpName"];
2904 let ColFields = ["IsAddr64"];
2906 let ValueCols = [["1"]];
2909 // Maps an atomic opcode to its version with a return value.
2910 def getAtomicRetOp : InstrMapping {
2911 let FilterClass = "AtomicNoRet";
2912 let RowFields = ["NoRetOp"];
2913 let ColFields = ["IsRet"];
2915 let ValueCols = [["1"]];
2918 // Maps an atomic opcode to its returnless version.
2919 def getAtomicNoRetOp : InstrMapping {
2920 let FilterClass = "AtomicNoRet";
2921 let RowFields = ["NoRetOp"];
2922 let ColFields = ["IsRet"];
2924 let ValueCols = [["0"]];
2927 include "SIInstructions.td"
2928 include "CIInstructions.td"
2929 include "VIInstructions.td"