1 //===-- SIInstrInfo.td - SI Instruction Infos -------------*- tablegen -*--===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
9 def isCI : Predicate<"Subtarget->getGeneration() "
10 ">= AMDGPUSubtarget::SEA_ISLANDS">;
11 def isCIOnly : Predicate<"Subtarget->getGeneration() =="
12 "AMDGPUSubtarget::SEA_ISLANDS">,
13 AssemblerPredicate <"FeatureSeaIslands">;
14 def isVI : Predicate <
15 "Subtarget->getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS">,
16 AssemblerPredicate<"FeatureGCN3Encoding">;
18 def DisableInst : Predicate <"false">, AssemblerPredicate<"FeatureDisable">;
25 class vopc <bits<8> si, bits<8> vi = !add(0x40, si)> : vop {
26 field bits<8> SI = si;
27 field bits<8> VI = vi;
29 field bits<9> SI3 = {0, si{7-0}};
30 field bits<10> VI3 = {0, 0, vi{7-0}};
33 class vop1 <bits<8> si, bits<8> vi = si> : vop {
34 field bits<8> SI = si;
35 field bits<8> VI = vi;
37 field bits<9> SI3 = {1, 1, si{6-0}};
38 field bits<10> VI3 = !add(0x140, vi);
41 class vop2 <bits<6> si, bits<6> vi = si> : vop {
42 field bits<6> SI = si;
43 field bits<6> VI = vi;
45 field bits<9> SI3 = {1, 0, 0, si{5-0}};
46 field bits<10> VI3 = {0, 1, 0, 0, vi{5-0}};
49 // Specify a VOP2 opcode for SI and VOP3 opcode for VI
50 // that doesn't have VOP2 encoding on VI
51 class vop23 <bits<6> si, bits<10> vi> : vop2 <si> {
55 class vop3 <bits<9> si, bits<10> vi = {0, si}> : vop {
60 class sop1 <bits<8> si, bits<8> vi = si> {
61 field bits<8> SI = si;
62 field bits<8> VI = vi;
65 class sop2 <bits<7> si, bits<7> vi = si> {
66 field bits<7> SI = si;
67 field bits<7> VI = vi;
70 class sopk <bits<5> si, bits<5> vi = si> {
71 field bits<5> SI = si;
72 field bits<5> VI = vi;
75 // Execpt for the NONE field, this must be kept in sync with the SISubtarget enum
76 // in AMDGPUInstrInfo.cpp
83 //===----------------------------------------------------------------------===//
85 //===----------------------------------------------------------------------===//
87 def SIload_constant : SDNode<"AMDGPUISD::LOAD_CONSTANT",
88 SDTypeProfile<1, 2, [SDTCisVT<0, f32>, SDTCisVT<1, v4i32>, SDTCisVT<2, i32>]>,
89 [SDNPMayLoad, SDNPMemOperand]
92 def SItbuffer_store : SDNode<"AMDGPUISD::TBUFFER_STORE_FORMAT",
94 [SDTCisVT<0, v4i32>, // rsrc(SGPR)
95 SDTCisVT<1, iAny>, // vdata(VGPR)
96 SDTCisVT<2, i32>, // num_channels(imm)
97 SDTCisVT<3, i32>, // vaddr(VGPR)
98 SDTCisVT<4, i32>, // soffset(SGPR)
99 SDTCisVT<5, i32>, // inst_offset(imm)
100 SDTCisVT<6, i32>, // dfmt(imm)
101 SDTCisVT<7, i32>, // nfmt(imm)
102 SDTCisVT<8, i32>, // offen(imm)
103 SDTCisVT<9, i32>, // idxen(imm)
104 SDTCisVT<10, i32>, // glc(imm)
105 SDTCisVT<11, i32>, // slc(imm)
106 SDTCisVT<12, i32> // tfe(imm)
108 [SDNPMayStore, SDNPMemOperand, SDNPHasChain]
111 def SIload_input : SDNode<"AMDGPUISD::LOAD_INPUT",
112 SDTypeProfile<1, 3, [SDTCisVT<0, v4f32>, SDTCisVT<1, v4i32>, SDTCisVT<2, i16>,
116 class SDSample<string opcode> : SDNode <opcode,
117 SDTypeProfile<1, 4, [SDTCisVT<0, v4f32>, SDTCisVT<2, v32i8>,
118 SDTCisVT<3, v4i32>, SDTCisVT<4, i32>]>
121 def SIsample : SDSample<"AMDGPUISD::SAMPLE">;
122 def SIsampleb : SDSample<"AMDGPUISD::SAMPLEB">;
123 def SIsampled : SDSample<"AMDGPUISD::SAMPLED">;
124 def SIsamplel : SDSample<"AMDGPUISD::SAMPLEL">;
126 def SIconstdata_ptr : SDNode<
127 "AMDGPUISD::CONST_DATA_PTR", SDTypeProfile <1, 0, [SDTCisVT<0, i64>]>
130 //===----------------------------------------------------------------------===//
131 // SDNodes and PatFrag for local loads and stores to enable s_mov_b32 m0, -1
132 // to be glued to the memory instructions.
133 //===----------------------------------------------------------------------===//
135 def SIld_local : SDNode <"ISD::LOAD", SDTLoad,
136 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand, SDNPInGlue]
139 def si_ld_local : PatFrag <(ops node:$ptr), (SIld_local node:$ptr), [{
140 return isLocalLoad(cast<LoadSDNode>(N));
143 def si_load_local : PatFrag <(ops node:$ptr), (si_ld_local node:$ptr), [{
144 return cast<LoadSDNode>(N)->getAddressingMode() == ISD::UNINDEXED &&
145 cast<LoadSDNode>(N)->getExtensionType() == ISD::NON_EXTLOAD;
148 def si_load_local_align8 : Aligned8Bytes <
149 (ops node:$ptr), (si_load_local node:$ptr)
152 def si_sextload_local : PatFrag <(ops node:$ptr), (si_ld_local node:$ptr), [{
153 return cast<LoadSDNode>(N)->getExtensionType() == ISD::SEXTLOAD;
155 def si_az_extload_local : AZExtLoadBase <si_ld_local>;
157 multiclass SIExtLoadLocal <PatFrag ld_node> {
159 def _i8 : PatFrag <(ops node:$ptr), (ld_node node:$ptr),
160 [{return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i8;}]
163 def _i16 : PatFrag <(ops node:$ptr), (ld_node node:$ptr),
164 [{return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i16;}]
168 defm si_sextload_local : SIExtLoadLocal <si_sextload_local>;
169 defm si_az_extload_local : SIExtLoadLocal <si_az_extload_local>;
171 def SIst_local : SDNode <"ISD::STORE", SDTStore,
172 [SDNPHasChain, SDNPMayStore, SDNPMemOperand, SDNPInGlue]
175 def si_st_local : PatFrag <
176 (ops node:$val, node:$ptr), (SIst_local node:$val, node:$ptr), [{
177 return isLocalStore(cast<StoreSDNode>(N));
180 def si_store_local : PatFrag <
181 (ops node:$val, node:$ptr), (si_st_local node:$val, node:$ptr), [{
182 return cast<StoreSDNode>(N)->getAddressingMode() == ISD::UNINDEXED &&
183 !cast<StoreSDNode>(N)->isTruncatingStore();
186 def si_store_local_align8 : Aligned8Bytes <
187 (ops node:$val, node:$ptr), (si_store_local node:$val, node:$ptr)
190 def si_truncstore_local : PatFrag <
191 (ops node:$val, node:$ptr), (si_st_local node:$val, node:$ptr), [{
192 return cast<StoreSDNode>(N)->isTruncatingStore();
195 def si_truncstore_local_i8 : PatFrag <
196 (ops node:$val, node:$ptr), (si_truncstore_local node:$val, node:$ptr), [{
197 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i8;
200 def si_truncstore_local_i16 : PatFrag <
201 (ops node:$val, node:$ptr), (si_truncstore_local node:$val, node:$ptr), [{
202 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i16;
205 multiclass SIAtomicM0Glue2 <string op_name> {
207 def _glue : SDNode <"ISD::ATOMIC_"#op_name, SDTAtomic2,
208 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand, SDNPInGlue]
211 def _local : local_binary_atomic_op <!cast<SDNode>(NAME#"_glue")>;
214 defm si_atomic_load_add : SIAtomicM0Glue2 <"LOAD_ADD">;
215 defm si_atomic_load_and : SIAtomicM0Glue2 <"LOAD_AND">;
216 defm si_atomic_load_min : SIAtomicM0Glue2 <"LOAD_MIN">;
217 defm si_atomic_load_max : SIAtomicM0Glue2 <"LOAD_MAX">;
218 defm si_atomic_load_or : SIAtomicM0Glue2 <"LOAD_OR">;
219 defm si_atomic_load_sub : SIAtomicM0Glue2 <"LOAD_SUB">;
220 defm si_atomic_load_xor : SIAtomicM0Glue2 <"LOAD_XOR">;
221 defm si_atomic_load_umin : SIAtomicM0Glue2 <"LOAD_UMIN">;
222 defm si_atomic_load_umax : SIAtomicM0Glue2 <"LOAD_UMAX">;
223 defm si_atomic_swap : SIAtomicM0Glue2 <"SWAP">;
225 def si_atomic_cmp_swap_glue : SDNode <"ISD::ATOMIC_CMP_SWAP", SDTAtomic3,
226 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand, SDNPInGlue]
229 defm si_atomic_cmp_swap : AtomicCmpSwapLocal <si_atomic_cmp_swap_glue>;
231 // Transformation function, extract the lower 32bit of a 64bit immediate
232 def LO32 : SDNodeXForm<imm, [{
233 return CurDAG->getTargetConstant(N->getZExtValue() & 0xffffffff, SDLoc(N),
237 def LO32f : SDNodeXForm<fpimm, [{
238 APInt V = N->getValueAPF().bitcastToAPInt().trunc(32);
239 return CurDAG->getTargetConstantFP(APFloat(APFloat::IEEEsingle, V), MVT::f32);
242 // Transformation function, extract the upper 32bit of a 64bit immediate
243 def HI32 : SDNodeXForm<imm, [{
244 return CurDAG->getTargetConstant(N->getZExtValue() >> 32, SDLoc(N), MVT::i32);
247 def HI32f : SDNodeXForm<fpimm, [{
248 APInt V = N->getValueAPF().bitcastToAPInt().lshr(32).trunc(32);
249 return CurDAG->getTargetConstantFP(APFloat(APFloat::IEEEsingle, V), SDLoc(N),
253 def IMM8bitDWORD : PatLeaf <(imm),
254 [{return (N->getZExtValue() & ~0x3FC) == 0;}]
257 def as_dword_i32imm : SDNodeXForm<imm, [{
258 return CurDAG->getTargetConstant(N->getZExtValue() >> 2, SDLoc(N), MVT::i32);
261 def as_i1imm : SDNodeXForm<imm, [{
262 return CurDAG->getTargetConstant(N->getZExtValue(), SDLoc(N), MVT::i1);
265 def as_i8imm : SDNodeXForm<imm, [{
266 return CurDAG->getTargetConstant(N->getZExtValue(), SDLoc(N), MVT::i8);
269 def as_i16imm : SDNodeXForm<imm, [{
270 return CurDAG->getTargetConstant(N->getSExtValue(), SDLoc(N), MVT::i16);
273 def as_i32imm: SDNodeXForm<imm, [{
274 return CurDAG->getTargetConstant(N->getSExtValue(), SDLoc(N), MVT::i32);
277 def as_i64imm: SDNodeXForm<imm, [{
278 return CurDAG->getTargetConstant(N->getSExtValue(), SDLoc(N), MVT::i64);
281 // Copied from the AArch64 backend:
282 def bitcast_fpimm_to_i32 : SDNodeXForm<fpimm, [{
283 return CurDAG->getTargetConstant(
284 N->getValueAPF().bitcastToAPInt().getZExtValue(), SDLoc(N), MVT::i32);
287 // Copied from the AArch64 backend:
288 def bitcast_fpimm_to_i64 : SDNodeXForm<fpimm, [{
289 return CurDAG->getTargetConstant(
290 N->getValueAPF().bitcastToAPInt().getZExtValue(), SDLoc(N), MVT::i64);
293 def IMM8bit : PatLeaf <(imm),
294 [{return isUInt<8>(N->getZExtValue());}]
297 def IMM12bit : PatLeaf <(imm),
298 [{return isUInt<12>(N->getZExtValue());}]
301 def IMM16bit : PatLeaf <(imm),
302 [{return isUInt<16>(N->getZExtValue());}]
305 def IMM20bit : PatLeaf <(imm),
306 [{return isUInt<20>(N->getZExtValue());}]
309 def IMM32bit : PatLeaf <(imm),
310 [{return isUInt<32>(N->getZExtValue());}]
313 def mubuf_vaddr_offset : PatFrag<
314 (ops node:$ptr, node:$offset, node:$imm_offset),
315 (add (add node:$ptr, node:$offset), node:$imm_offset)
318 class InlineImm <ValueType vt> : PatLeaf <(vt imm), [{
319 return isInlineImmediate(N);
322 class InlineFPImm <ValueType vt> : PatLeaf <(vt fpimm), [{
323 return isInlineImmediate(N);
326 class SGPRImm <dag frag> : PatLeaf<frag, [{
327 if (Subtarget->getGeneration() < AMDGPUSubtarget::SOUTHERN_ISLANDS) {
330 const SIRegisterInfo *SIRI =
331 static_cast<const SIRegisterInfo *>(Subtarget->getRegisterInfo());
332 for (SDNode::use_iterator U = N->use_begin(), E = SDNode::use_end();
334 if (SIRI->isSGPRClass(getOperandRegClass(*U, U.getOperandNo()))) {
341 //===----------------------------------------------------------------------===//
343 //===----------------------------------------------------------------------===//
345 def FRAMEri32 : Operand<iPTR> {
346 let MIOperandInfo = (ops i32:$ptr, i32imm:$index);
349 def SoppBrTarget : AsmOperandClass {
350 let Name = "SoppBrTarget";
351 let ParserMethod = "parseSOppBrTarget";
354 def sopp_brtarget : Operand<OtherVT> {
355 let EncoderMethod = "getSOPPBrEncoding";
356 let OperandType = "OPERAND_PCREL";
357 let ParserMatchClass = SoppBrTarget;
360 include "SIInstrFormats.td"
361 include "VIInstrFormats.td"
363 def MubufOffsetMatchClass : AsmOperandClass {
364 let Name = "MubufOffset";
365 let ParserMethod = "parseMubufOptionalOps";
366 let RenderMethod = "addImmOperands";
369 class DSOffsetBaseMatchClass <string parser> : AsmOperandClass {
370 let Name = "DSOffset"#parser;
371 let ParserMethod = parser;
372 let RenderMethod = "addImmOperands";
373 let PredicateMethod = "isDSOffset";
376 def DSOffsetMatchClass : DSOffsetBaseMatchClass <"parseDSOptionalOps">;
377 def DSOffsetGDSMatchClass : DSOffsetBaseMatchClass <"parseDSOffsetOptional">;
379 def DSOffset01MatchClass : AsmOperandClass {
380 let Name = "DSOffset1";
381 let ParserMethod = "parseDSOff01OptionalOps";
382 let RenderMethod = "addImmOperands";
383 let PredicateMethod = "isDSOffset01";
386 class GDSBaseMatchClass <string parser> : AsmOperandClass {
387 let Name = "GDS"#parser;
388 let PredicateMethod = "isImm";
389 let ParserMethod = parser;
390 let RenderMethod = "addImmOperands";
393 def GDSMatchClass : GDSBaseMatchClass <"parseDSOptionalOps">;
394 def GDS01MatchClass : GDSBaseMatchClass <"parseDSOff01OptionalOps">;
396 class GLCBaseMatchClass <string parser> : AsmOperandClass {
397 let Name = "GLC"#parser;
398 let PredicateMethod = "isImm";
399 let ParserMethod = parser;
400 let RenderMethod = "addImmOperands";
403 def GLCMubufMatchClass : GLCBaseMatchClass <"parseMubufOptionalOps">;
404 def GLCFlatMatchClass : GLCBaseMatchClass <"parseFlatOptionalOps">;
406 class SLCBaseMatchClass <string parser> : AsmOperandClass {
407 let Name = "SLC"#parser;
408 let PredicateMethod = "isImm";
409 let ParserMethod = parser;
410 let RenderMethod = "addImmOperands";
413 def SLCMubufMatchClass : SLCBaseMatchClass <"parseMubufOptionalOps">;
414 def SLCFlatMatchClass : SLCBaseMatchClass <"parseFlatOptionalOps">;
415 def SLCFlatAtomicMatchClass : SLCBaseMatchClass <"parseFlatAtomicOptionalOps">;
417 class TFEBaseMatchClass <string parser> : AsmOperandClass {
418 let Name = "TFE"#parser;
419 let PredicateMethod = "isImm";
420 let ParserMethod = parser;
421 let RenderMethod = "addImmOperands";
424 def TFEMubufMatchClass : TFEBaseMatchClass <"parseMubufOptionalOps">;
425 def TFEFlatMatchClass : TFEBaseMatchClass <"parseFlatOptionalOps">;
426 def TFEFlatAtomicMatchClass : TFEBaseMatchClass <"parseFlatAtomicOptionalOps">;
428 def OModMatchClass : AsmOperandClass {
430 let PredicateMethod = "isImm";
431 let ParserMethod = "parseVOP3OptionalOps";
432 let RenderMethod = "addImmOperands";
435 def ClampMatchClass : AsmOperandClass {
437 let PredicateMethod = "isImm";
438 let ParserMethod = "parseVOP3OptionalOps";
439 let RenderMethod = "addImmOperands";
442 class SMRDOffsetBaseMatchClass <string predicate> : AsmOperandClass {
443 let Name = "SMRDOffset"#predicate;
444 let PredicateMethod = predicate;
445 let RenderMethod = "addImmOperands";
448 def SMRDOffsetMatchClass : SMRDOffsetBaseMatchClass <"isSMRDOffset">;
449 def SMRDLiteralOffsetMatchClass : SMRDOffsetBaseMatchClass <
450 "isSMRDLiteralOffset"
453 let OperandType = "OPERAND_IMMEDIATE" in {
455 def offen : Operand<i1> {
456 let PrintMethod = "printOffen";
458 def idxen : Operand<i1> {
459 let PrintMethod = "printIdxen";
461 def addr64 : Operand<i1> {
462 let PrintMethod = "printAddr64";
464 def mbuf_offset : Operand<i16> {
465 let PrintMethod = "printMBUFOffset";
466 let ParserMatchClass = MubufOffsetMatchClass;
468 class ds_offset_base <AsmOperandClass mc> : Operand<i16> {
469 let PrintMethod = "printDSOffset";
470 let ParserMatchClass = mc;
472 def ds_offset : ds_offset_base <DSOffsetMatchClass>;
473 def ds_offset_gds : ds_offset_base <DSOffsetGDSMatchClass>;
475 def ds_offset0 : Operand<i8> {
476 let PrintMethod = "printDSOffset0";
477 let ParserMatchClass = DSOffset01MatchClass;
479 def ds_offset1 : Operand<i8> {
480 let PrintMethod = "printDSOffset1";
481 let ParserMatchClass = DSOffset01MatchClass;
483 class gds_base <AsmOperandClass mc> : Operand <i1> {
484 let PrintMethod = "printGDS";
485 let ParserMatchClass = mc;
487 def gds : gds_base <GDSMatchClass>;
489 def gds01 : gds_base <GDS01MatchClass>;
491 class glc_base <AsmOperandClass mc> : Operand <i1> {
492 let PrintMethod = "printGLC";
493 let ParserMatchClass = mc;
496 def glc : glc_base <GLCMubufMatchClass>;
497 def glc_flat : glc_base <GLCFlatMatchClass>;
499 class slc_base <AsmOperandClass mc> : Operand <i1> {
500 let PrintMethod = "printSLC";
501 let ParserMatchClass = mc;
504 def slc : slc_base <SLCMubufMatchClass>;
505 def slc_flat : slc_base <SLCFlatMatchClass>;
506 def slc_flat_atomic : slc_base <SLCFlatAtomicMatchClass>;
508 class tfe_base <AsmOperandClass mc> : Operand <i1> {
509 let PrintMethod = "printTFE";
510 let ParserMatchClass = mc;
513 def tfe : tfe_base <TFEMubufMatchClass>;
514 def tfe_flat : tfe_base <TFEFlatMatchClass>;
515 def tfe_flat_atomic : tfe_base <TFEFlatAtomicMatchClass>;
517 def omod : Operand <i32> {
518 let PrintMethod = "printOModSI";
519 let ParserMatchClass = OModMatchClass;
522 def ClampMod : Operand <i1> {
523 let PrintMethod = "printClampSI";
524 let ParserMatchClass = ClampMatchClass;
527 def smrd_offset : Operand <i32> {
528 let PrintMethod = "printU32ImmOperand";
529 let ParserMatchClass = SMRDOffsetMatchClass;
532 def smrd_literal_offset : Operand <i32> {
533 let PrintMethod = "printU32ImmOperand";
534 let ParserMatchClass = SMRDLiteralOffsetMatchClass;
537 } // End OperandType = "OPERAND_IMMEDIATE"
539 def VOPDstS64 : VOPDstOperand <SReg_64>;
541 //===----------------------------------------------------------------------===//
543 //===----------------------------------------------------------------------===//
545 def DS1Addr1Offset : ComplexPattern<i32, 2, "SelectDS1Addr1Offset">;
546 def DS64Bit4ByteAligned : ComplexPattern<i32, 3, "SelectDS64Bit4ByteAligned">;
548 def MUBUFAddr32 : ComplexPattern<i64, 9, "SelectMUBUFAddr32">;
549 def MUBUFAddr64 : ComplexPattern<i64, 7, "SelectMUBUFAddr64">;
550 def MUBUFAddr64Atomic : ComplexPattern<i64, 5, "SelectMUBUFAddr64">;
551 def MUBUFScratch : ComplexPattern<i64, 4, "SelectMUBUFScratch">;
552 def MUBUFOffset : ComplexPattern<i64, 6, "SelectMUBUFOffset">;
553 def MUBUFOffsetAtomic : ComplexPattern<i64, 4, "SelectMUBUFOffset">;
555 def SMRDImm : ComplexPattern<i64, 2, "SelectSMRDImm">;
556 def SMRDImm32 : ComplexPattern<i64, 2, "SelectSMRDImm32">;
557 def SMRDSgpr : ComplexPattern<i64, 2, "SelectSMRDSgpr">;
558 def SMRDBufferImm : ComplexPattern<i32, 1, "SelectSMRDBufferImm">;
559 def SMRDBufferImm32 : ComplexPattern<i32, 1, "SelectSMRDBufferImm32">;
560 def SMRDBufferSgpr : ComplexPattern<i32, 1, "SelectSMRDBufferSgpr">;
562 def VOP3Mods0 : ComplexPattern<untyped, 4, "SelectVOP3Mods0">;
563 def VOP3NoMods0 : ComplexPattern<untyped, 4, "SelectVOP3NoMods0">;
564 def VOP3Mods0Clamp : ComplexPattern<untyped, 3, "SelectVOP3Mods0Clamp">;
565 def VOP3Mods0Clamp0OMod : ComplexPattern<untyped, 4, "SelectVOP3Mods0Clamp0OMod">;
566 def VOP3Mods : ComplexPattern<untyped, 2, "SelectVOP3Mods">;
567 def VOP3NoMods : ComplexPattern<untyped, 2, "SelectVOP3NoMods">;
569 //===----------------------------------------------------------------------===//
570 // SI assembler operands
571 //===----------------------------------------------------------------------===//
592 //===----------------------------------------------------------------------===//
594 // SI Instruction multiclass helpers.
596 // Instructions with _32 take 32-bit operands.
597 // Instructions with _64 take 64-bit operands.
599 // VOP_* instructions can use either a 32-bit or 64-bit encoding. The 32-bit
600 // encoding is the standard encoding, but instruction that make use of
601 // any of the instruction modifiers must use the 64-bit encoding.
603 // Instructions with _e32 use the 32-bit encoding.
604 // Instructions with _e64 use the 64-bit encoding.
606 //===----------------------------------------------------------------------===//
608 class SIMCInstr <string pseudo, int subtarget> {
609 string PseudoInstr = pseudo;
610 int Subtarget = subtarget;
613 //===----------------------------------------------------------------------===//
615 //===----------------------------------------------------------------------===//
617 class EXPCommon : InstSI<
619 (ins i32imm:$en, i32imm:$tgt, i32imm:$compr, i32imm:$done, i32imm:$vm,
620 VGPR_32:$src0, VGPR_32:$src1, VGPR_32:$src2, VGPR_32:$src3),
621 "exp $en, $tgt, $compr, $done, $vm, $src0, $src1, $src2, $src3",
630 let isPseudo = 1, isCodeGenOnly = 1 in {
631 def "" : EXPCommon, SIMCInstr <"exp", SISubtarget.NONE> ;
634 def _si : EXPCommon, SIMCInstr <"exp", SISubtarget.SI>, EXPe;
636 def _vi : EXPCommon, SIMCInstr <"exp", SISubtarget.VI>, EXPe_vi;
639 //===----------------------------------------------------------------------===//
641 //===----------------------------------------------------------------------===//
643 class SOP1_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> :
644 SOP1 <outs, ins, "", pattern>,
645 SIMCInstr<opName, SISubtarget.NONE> {
647 let isCodeGenOnly = 1;
650 class SOP1_Real_si <sop1 op, string opName, dag outs, dag ins, string asm> :
651 SOP1 <outs, ins, asm, []>,
653 SIMCInstr<opName, SISubtarget.SI> {
654 let isCodeGenOnly = 0;
655 let AssemblerPredicates = [isSICI];
658 class SOP1_Real_vi <sop1 op, string opName, dag outs, dag ins, string asm> :
659 SOP1 <outs, ins, asm, []>,
661 SIMCInstr<opName, SISubtarget.VI> {
662 let isCodeGenOnly = 0;
663 let AssemblerPredicates = [isVI];
666 multiclass SOP1_m <sop1 op, string opName, dag outs, dag ins, string asm,
669 def "" : SOP1_Pseudo <opName, outs, ins, pattern>;
671 def _si : SOP1_Real_si <op, opName, outs, ins, asm>;
673 def _vi : SOP1_Real_vi <op, opName, outs, ins, asm>;
677 multiclass SOP1_32 <sop1 op, string opName, list<dag> pattern> : SOP1_m <
678 op, opName, (outs SReg_32:$dst), (ins SSrc_32:$src0),
679 opName#" $dst, $src0", pattern
682 multiclass SOP1_64 <sop1 op, string opName, list<dag> pattern> : SOP1_m <
683 op, opName, (outs SReg_64:$dst), (ins SSrc_64:$src0),
684 opName#" $dst, $src0", pattern
687 // no input, 64-bit output.
688 multiclass SOP1_64_0 <sop1 op, string opName, list<dag> pattern> {
689 def "" : SOP1_Pseudo <opName, (outs SReg_64:$dst), (ins), pattern>;
691 def _si : SOP1_Real_si <op, opName, (outs SReg_64:$dst), (ins),
696 def _vi : SOP1_Real_vi <op, opName, (outs SReg_64:$dst), (ins),
702 // 64-bit input, no output
703 multiclass SOP1_1 <sop1 op, string opName, list<dag> pattern> {
704 def "" : SOP1_Pseudo <opName, (outs), (ins SReg_64:$src0), pattern>;
706 def _si : SOP1_Real_si <op, opName, (outs), (ins SReg_64:$src0),
711 def _vi : SOP1_Real_vi <op, opName, (outs), (ins SReg_64:$src0),
717 // 64-bit input, 32-bit output.
718 multiclass SOP1_32_64 <sop1 op, string opName, list<dag> pattern> : SOP1_m <
719 op, opName, (outs SReg_32:$dst), (ins SSrc_64:$src0),
720 opName#" $dst, $src0", pattern
723 class SOP2_Pseudo<string opName, dag outs, dag ins, list<dag> pattern> :
724 SOP2<outs, ins, "", pattern>,
725 SIMCInstr<opName, SISubtarget.NONE> {
727 let isCodeGenOnly = 1;
730 // Pseudo instructions have no encodings, but adding this field here allows
732 // let sdst = xxx in {
733 // for multiclasses that include both real and pseudo instructions.
734 field bits<7> sdst = 0;
737 class SOP2_Real_si<sop2 op, string opName, dag outs, dag ins, string asm> :
738 SOP2<outs, ins, asm, []>,
740 SIMCInstr<opName, SISubtarget.SI> {
741 let AssemblerPredicates = [isSICI];
744 class SOP2_Real_vi<sop2 op, string opName, dag outs, dag ins, string asm> :
745 SOP2<outs, ins, asm, []>,
747 SIMCInstr<opName, SISubtarget.VI> {
748 let AssemblerPredicates = [isVI];
751 multiclass SOP2_m <sop2 op, string opName, dag outs, dag ins, string asm,
754 def "" : SOP2_Pseudo <opName, outs, ins, pattern>;
756 def _si : SOP2_Real_si <op, opName, outs, ins, asm>;
758 def _vi : SOP2_Real_vi <op, opName, outs, ins, asm>;
762 multiclass SOP2_32 <sop2 op, string opName, list<dag> pattern> : SOP2_m <
763 op, opName, (outs SReg_32:$dst), (ins SSrc_32:$src0, SSrc_32:$src1),
764 opName#" $dst, $src0, $src1", pattern
767 multiclass SOP2_64 <sop2 op, string opName, list<dag> pattern> : SOP2_m <
768 op, opName, (outs SReg_64:$dst), (ins SSrc_64:$src0, SSrc_64:$src1),
769 opName#" $dst, $src0, $src1", pattern
772 multiclass SOP2_64_32 <sop2 op, string opName, list<dag> pattern> : SOP2_m <
773 op, opName, (outs SReg_64:$dst), (ins SSrc_64:$src0, SSrc_32:$src1),
774 opName#" $dst, $src0, $src1", pattern
777 class SOPC_Helper <bits<7> op, RegisterOperand rc, ValueType vt,
778 string opName, PatLeaf cond> : SOPC <
779 op, (outs), (ins rc:$src0, rc:$src1),
780 opName#" $src0, $src1", []> {
784 class SOPC_32<bits<7> op, string opName, PatLeaf cond = COND_NULL>
785 : SOPC_Helper<op, SSrc_32, i32, opName, cond>;
787 class SOPC_64<bits<7> op, string opName, PatLeaf cond = COND_NULL>
788 : SOPC_Helper<op, SSrc_64, i64, opName, cond>;
790 class SOPK_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> :
791 SOPK <outs, ins, "", pattern>,
792 SIMCInstr<opName, SISubtarget.NONE> {
794 let isCodeGenOnly = 1;
797 class SOPK_Real_si <sopk op, string opName, dag outs, dag ins, string asm> :
798 SOPK <outs, ins, asm, []>,
800 SIMCInstr<opName, SISubtarget.SI> {
801 let AssemblerPredicates = [isSICI];
802 let isCodeGenOnly = 0;
805 class SOPK_Real_vi <sopk op, string opName, dag outs, dag ins, string asm> :
806 SOPK <outs, ins, asm, []>,
808 SIMCInstr<opName, SISubtarget.VI> {
809 let AssemblerPredicates = [isVI];
810 let isCodeGenOnly = 0;
813 multiclass SOPK_m <sopk op, string opName, dag outs, dag ins, string opAsm,
814 string asm = opName#opAsm> {
815 def "" : SOPK_Pseudo <opName, outs, ins, []>;
817 def _si : SOPK_Real_si <op, opName, outs, ins, asm>;
819 def _vi : SOPK_Real_vi <op, opName, outs, ins, asm>;
823 multiclass SOPK_32 <sopk op, string opName, list<dag> pattern> {
824 def "" : SOPK_Pseudo <opName, (outs SReg_32:$dst), (ins u16imm:$src0),
827 def _si : SOPK_Real_si <op, opName, (outs SReg_32:$dst), (ins u16imm:$src0),
828 opName#" $dst, $src0">;
830 def _vi : SOPK_Real_vi <op, opName, (outs SReg_32:$dst), (ins u16imm:$src0),
831 opName#" $dst, $src0">;
834 multiclass SOPK_SCC <sopk op, string opName, list<dag> pattern> {
835 def "" : SOPK_Pseudo <opName, (outs),
836 (ins SReg_32:$src0, u16imm:$src1), pattern> {
841 def _si : SOPK_Real_si <op, opName, (outs),
842 (ins SReg_32:$sdst, u16imm:$simm16), opName#" $sdst, $simm16"> {
846 def _vi : SOPK_Real_vi <op, opName, (outs),
847 (ins SReg_32:$sdst, u16imm:$simm16), opName#" $sdst, $simm16"> {
852 multiclass SOPK_32TIE <sopk op, string opName, list<dag> pattern> : SOPK_m <
853 op, opName, (outs SReg_32:$sdst), (ins SReg_32:$src0, u16imm:$simm16),
857 multiclass SOPK_IMM32 <sopk op, string opName, dag outs, dag ins,
858 string argAsm, string asm = opName#argAsm> {
860 def "" : SOPK_Pseudo <opName, outs, ins, []>;
862 def _si : SOPK <outs, ins, asm, []>,
864 SIMCInstr<opName, SISubtarget.SI> {
865 let AssemblerPredicates = [isSICI];
866 let isCodeGenOnly = 0;
869 def _vi : SOPK <outs, ins, asm, []>,
871 SIMCInstr<opName, SISubtarget.VI> {
872 let AssemblerPredicates = [isVI];
873 let isCodeGenOnly = 0;
876 //===----------------------------------------------------------------------===//
878 //===----------------------------------------------------------------------===//
880 class SMRD_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> :
881 SMRD <outs, ins, "", pattern>,
882 SIMCInstr<opName, SISubtarget.NONE> {
884 let isCodeGenOnly = 1;
887 class SMRD_Real_si <bits<5> op, string opName, bit imm, dag outs, dag ins,
889 SMRD <outs, ins, asm, []>,
891 SIMCInstr<opName, SISubtarget.SI> {
892 let AssemblerPredicates = [isSICI];
895 class SMRD_Real_vi <bits<8> op, string opName, bit imm, dag outs, dag ins,
897 SMRD <outs, ins, asm, []>,
899 SIMCInstr<opName, SISubtarget.VI> {
900 let AssemblerPredicates = [isVI];
903 multiclass SMRD_m <bits<5> op, string opName, bit imm, dag outs, dag ins,
904 string asm, list<dag> pattern> {
906 def "" : SMRD_Pseudo <opName, outs, ins, pattern>;
908 def _si : SMRD_Real_si <op, opName, imm, outs, ins, asm>;
910 // glc is only applicable to scalar stores, which are not yet
913 def _vi : SMRD_Real_vi <{0, 0, 0, op}, opName, imm, outs, ins, asm>;
917 multiclass SMRD_Helper <bits<5> op, string opName, RegisterClass baseClass,
918 RegisterClass dstClass> {
920 op, opName#"_IMM", 1, (outs dstClass:$dst),
921 (ins baseClass:$sbase, smrd_offset:$offset),
922 opName#" $dst, $sbase, $offset", []
926 (outs dstClass:$dst), (ins baseClass:$sbase, smrd_literal_offset:$offset),
927 opName#" $dst, $sbase, $offset", []>, SMRD_IMMe_ci <op> {
928 let AssemblerPredicates = [isCIOnly];
931 defm _SGPR : SMRD_m <
932 op, opName#"_SGPR", 0, (outs dstClass:$dst),
933 (ins baseClass:$sbase, SReg_32:$soff),
934 opName#" $dst, $sbase, $soff", []
938 //===----------------------------------------------------------------------===//
939 // Vector ALU classes
940 //===----------------------------------------------------------------------===//
942 // This must always be right before the operand being input modified.
943 def InputMods : OperandWithDefaultOps <i32, (ops (i32 0))> {
944 let PrintMethod = "printOperandAndMods";
947 def InputModsMatchClass : AsmOperandClass {
948 let Name = "RegWithInputMods";
951 def InputModsNoDefault : Operand <i32> {
952 let PrintMethod = "printOperandAndMods";
953 let ParserMatchClass = InputModsMatchClass;
956 class getNumSrcArgs<ValueType Src1, ValueType Src2> {
958 !if (!eq(Src1.Value, untyped.Value), 1, // VOP1
959 !if (!eq(Src2.Value, untyped.Value), 2, // VOP2
963 // Returns the register class to use for the destination of VOP[123C]
964 // instructions for the given VT.
965 class getVALUDstForVT<ValueType VT> {
966 RegisterOperand ret = !if(!eq(VT.Size, 32), VOPDstOperand<VGPR_32>,
967 !if(!eq(VT.Size, 64), VOPDstOperand<VReg_64>,
968 !if(!eq(VT.Size, 16), VOPDstOperand<VGPR_32>,
969 VOPDstOperand<SReg_64>))); // else VT == i1
972 // Returns the register class to use for source 0 of VOP[12C]
973 // instructions for the given VT.
974 class getVOPSrc0ForVT<ValueType VT> {
975 RegisterOperand ret = !if(!eq(VT.Size, 64), VSrc_64, VSrc_32);
978 // Returns the register class to use for source 1 of VOP[12C] for the
980 class getVOPSrc1ForVT<ValueType VT> {
981 RegisterClass ret = !if(!eq(VT.Size, 64), VReg_64, VGPR_32);
984 // Returns the register class to use for sources of VOP3 instructions for the
986 class getVOP3SrcForVT<ValueType VT> {
987 RegisterOperand ret = !if(!eq(VT.Size, 64), VCSrc_64, VCSrc_32);
990 // Returns 1 if the source arguments have modifiers, 0 if they do not.
991 // XXX - do f16 instructions?
992 class hasModifiers<ValueType SrcVT> {
993 bit ret = !if(!eq(SrcVT.Value, f32.Value), 1,
994 !if(!eq(SrcVT.Value, f64.Value), 1, 0));
997 // Returns the input arguments for VOP[12C] instructions for the given SrcVT.
998 class getIns32 <RegisterOperand Src0RC, RegisterClass Src1RC, int NumSrcArgs> {
999 dag ret = !if(!eq(NumSrcArgs, 1), (ins Src0RC:$src0), // VOP1
1000 !if(!eq(NumSrcArgs, 2), (ins Src0RC:$src0, Src1RC:$src1), // VOP2
1004 // Returns the input arguments for VOP3 instructions for the given SrcVT.
1005 class getIns64 <RegisterOperand Src0RC, RegisterOperand Src1RC,
1006 RegisterOperand Src2RC, int NumSrcArgs,
1010 !if (!eq(NumSrcArgs, 1),
1011 !if (!eq(HasModifiers, 1),
1012 // VOP1 with modifiers
1013 (ins InputModsNoDefault:$src0_modifiers, Src0RC:$src0,
1014 ClampMod:$clamp, omod:$omod)
1016 // VOP1 without modifiers
1019 !if (!eq(NumSrcArgs, 2),
1020 !if (!eq(HasModifiers, 1),
1021 // VOP 2 with modifiers
1022 (ins InputModsNoDefault:$src0_modifiers, Src0RC:$src0,
1023 InputModsNoDefault:$src1_modifiers, Src1RC:$src1,
1024 ClampMod:$clamp, omod:$omod)
1026 // VOP2 without modifiers
1027 (ins Src0RC:$src0, Src1RC:$src1)
1029 /* NumSrcArgs == 3 */,
1030 !if (!eq(HasModifiers, 1),
1031 // VOP3 with modifiers
1032 (ins InputModsNoDefault:$src0_modifiers, Src0RC:$src0,
1033 InputModsNoDefault:$src1_modifiers, Src1RC:$src1,
1034 InputModsNoDefault:$src2_modifiers, Src2RC:$src2,
1035 ClampMod:$clamp, omod:$omod)
1037 // VOP3 without modifiers
1038 (ins Src0RC:$src0, Src1RC:$src1, Src2RC:$src2)
1042 // Returns the assembly string for the inputs and outputs of a VOP[12C]
1043 // instruction. This does not add the _e32 suffix, so it can be reused
1045 class getAsm32 <int NumSrcArgs> {
1046 string src1 = ", $src1";
1047 string src2 = ", $src2";
1048 string ret = "$dst, $src0"#
1049 !if(!eq(NumSrcArgs, 1), "", src1)#
1050 !if(!eq(NumSrcArgs, 3), src2, "");
1053 // Returns the assembly string for the inputs and outputs of a VOP3
1055 class getAsm64 <int NumSrcArgs, bit HasModifiers> {
1056 string src0 = !if(!eq(NumSrcArgs, 1), "$src0_modifiers", "$src0_modifiers,");
1057 string src1 = !if(!eq(NumSrcArgs, 1), "",
1058 !if(!eq(NumSrcArgs, 2), " $src1_modifiers",
1059 " $src1_modifiers,"));
1060 string src2 = !if(!eq(NumSrcArgs, 3), " $src2_modifiers", "");
1062 !if(!eq(HasModifiers, 0),
1063 getAsm32<NumSrcArgs>.ret,
1064 "$dst, "#src0#src1#src2#"$clamp"#"$omod");
1068 class VOPProfile <list<ValueType> _ArgVT> {
1070 field list<ValueType> ArgVT = _ArgVT;
1072 field ValueType DstVT = ArgVT[0];
1073 field ValueType Src0VT = ArgVT[1];
1074 field ValueType Src1VT = ArgVT[2];
1075 field ValueType Src2VT = ArgVT[3];
1076 field RegisterOperand DstRC = getVALUDstForVT<DstVT>.ret;
1077 field RegisterOperand Src0RC32 = getVOPSrc0ForVT<Src0VT>.ret;
1078 field RegisterClass Src1RC32 = getVOPSrc1ForVT<Src1VT>.ret;
1079 field RegisterOperand Src0RC64 = getVOP3SrcForVT<Src0VT>.ret;
1080 field RegisterOperand Src1RC64 = getVOP3SrcForVT<Src1VT>.ret;
1081 field RegisterOperand Src2RC64 = getVOP3SrcForVT<Src2VT>.ret;
1083 field int NumSrcArgs = getNumSrcArgs<Src1VT, Src2VT>.ret;
1084 field bit HasModifiers = hasModifiers<Src0VT>.ret;
1086 field dag Outs = (outs DstRC:$dst);
1088 field dag Ins32 = getIns32<Src0RC32, Src1RC32, NumSrcArgs>.ret;
1089 field dag Ins64 = getIns64<Src0RC64, Src1RC64, Src2RC64, NumSrcArgs,
1092 field string Asm32 = getAsm32<NumSrcArgs>.ret;
1093 field string Asm64 = getAsm64<NumSrcArgs, HasModifiers>.ret;
1096 // FIXME: I think these F16/I16 profiles will need to use f16/i16 types in order
1097 // for the instruction patterns to work.
1098 def VOP_F16_F16 : VOPProfile <[f16, f16, untyped, untyped]>;
1099 def VOP_F16_I16 : VOPProfile <[f16, i32, untyped, untyped]>;
1100 def VOP_I16_F16 : VOPProfile <[i32, f16, untyped, untyped]>;
1102 def VOP_F16_F16_F16 : VOPProfile <[f16, f16, f16, untyped]>;
1103 def VOP_F16_F16_I16 : VOPProfile <[f16, f16, i32, untyped]>;
1104 def VOP_I16_I16_I16 : VOPProfile <[i32, i32, i32, untyped]>;
1106 def VOP_F32_F32 : VOPProfile <[f32, f32, untyped, untyped]>;
1107 def VOP_F32_F64 : VOPProfile <[f32, f64, untyped, untyped]>;
1108 def VOP_F32_I32 : VOPProfile <[f32, i32, untyped, untyped]>;
1109 def VOP_F64_F32 : VOPProfile <[f64, f32, untyped, untyped]>;
1110 def VOP_F64_F64 : VOPProfile <[f64, f64, untyped, untyped]>;
1111 def VOP_F64_I32 : VOPProfile <[f64, i32, untyped, untyped]>;
1112 def VOP_I32_F32 : VOPProfile <[i32, f32, untyped, untyped]>;
1113 def VOP_I32_F64 : VOPProfile <[i32, f64, untyped, untyped]>;
1114 def VOP_I32_I32 : VOPProfile <[i32, i32, untyped, untyped]>;
1116 def VOP_F32_F32_F32 : VOPProfile <[f32, f32, f32, untyped]>;
1117 def VOP_F32_F32_I32 : VOPProfile <[f32, f32, i32, untyped]>;
1118 def VOP_F64_F64_F64 : VOPProfile <[f64, f64, f64, untyped]>;
1119 def VOP_F64_F64_I32 : VOPProfile <[f64, f64, i32, untyped]>;
1120 def VOP_I32_F32_F32 : VOPProfile <[i32, f32, f32, untyped]>;
1121 def VOP_I32_F32_I32 : VOPProfile <[i32, f32, i32, untyped]>;
1122 def VOP_I32_I32_I32 : VOPProfile <[i32, i32, i32, untyped]>;
1123 def VOP_I32_I32_I32_VCC : VOPProfile <[i32, i32, i32, untyped]> {
1124 let Src0RC32 = VCSrc_32;
1127 // VOPC instructions are a special case because for the 32-bit
1128 // encoding, we want to display the implicit vcc write as if it were
1129 // an explicit $dst.
1130 class VOPC_Profile<ValueType vt0, ValueType vt1 = vt0> : VOPProfile <[i1, vt0, vt1, untyped]> {
1131 let Asm32 = "vcc, $src0, $src1";
1134 class VOPC_Class_Profile<ValueType vt> : VOPC_Profile<vt, i32> {
1135 let Ins64 = (ins InputModsNoDefault:$src0_modifiers, Src0RC64:$src0, Src1RC64:$src1);
1136 let Asm64 = "$dst, $src0_modifiers, $src1";
1139 def VOPC_I1_F32_F32 : VOPC_Profile<f32>;
1140 def VOPC_I1_F64_F64 : VOPC_Profile<f64>;
1141 def VOPC_I1_I32_I32 : VOPC_Profile<i32>;
1142 def VOPC_I1_I64_I64 : VOPC_Profile<i64>;
1144 def VOPC_I1_F32_I32 : VOPC_Class_Profile<f32>;
1145 def VOPC_I1_F64_I32 : VOPC_Class_Profile<f64>;
1147 def VOP_I64_I64_I32 : VOPProfile <[i64, i64, i32, untyped]>;
1148 def VOP_I64_I32_I64 : VOPProfile <[i64, i32, i64, untyped]>;
1149 def VOP_I64_I64_I64 : VOPProfile <[i64, i64, i64, untyped]>;
1150 def VOP_CNDMASK : VOPProfile <[i32, i32, i32, untyped]> {
1151 let Ins32 = (ins Src0RC32:$src0, Src1RC32:$src1);
1152 let Ins64 = (ins Src0RC64:$src0, Src1RC64:$src1, SSrc_64:$src2);
1153 let Asm64 = "$dst, $src0, $src1, $src2";
1156 def VOP_F32_F32_F32_F32 : VOPProfile <[f32, f32, f32, f32]>;
1157 def VOP_MADK : VOPProfile <[f32, f32, f32, f32]> {
1158 field dag Ins = (ins VCSrc_32:$src0, VGPR_32:$vsrc1, u32imm:$src2);
1159 field string Asm = "$dst, $src0, $vsrc1, $src2";
1161 def VOP_MAC : VOPProfile <[f32, f32, f32, f32]> {
1162 let Ins32 = (ins Src0RC32:$src0, Src1RC32:$src1, VGPR_32:$src2);
1163 let Ins64 = getIns64<Src0RC64, Src1RC64, RegisterOperand<VGPR_32>, 3,
1165 let Asm32 = getAsm32<2>.ret;
1166 let Asm64 = getAsm64<2, HasModifiers>.ret;
1168 def VOP_F64_F64_F64_F64 : VOPProfile <[f64, f64, f64, f64]>;
1169 def VOP_I32_I32_I32_I32 : VOPProfile <[i32, i32, i32, i32]>;
1170 def VOP_I64_I32_I32_I64 : VOPProfile <[i64, i32, i32, i64]>;
1172 class SIInstAlias <string asm, dag result> : InstAlias <asm, result>,
1174 field bit isCompare;
1175 field bit isCommutable;
1178 class VOP <string opName> {
1179 string OpName = opName;
1182 class VOP2_REV <string revOp, bit isOrig> {
1183 string RevOp = revOp;
1184 bit IsOrig = isOrig;
1187 class AtomicNoRet <string noRetOp, bit isRet> {
1188 string NoRetOp = noRetOp;
1192 class VOP1_Pseudo <dag outs, dag ins, list<dag> pattern, string opName> :
1193 VOP1Common <outs, ins, "", pattern>,
1195 SIMCInstr <opName#"_e32", SISubtarget.NONE>,
1196 MnemonicAlias<opName#"_e32", opName> {
1198 let isCodeGenOnly = 1;
1204 class VOP1_Real_si <string opName, vop1 op, dag outs, dag ins, string asm> :
1205 VOP1<op.SI, outs, ins, asm, []>,
1206 SIMCInstr <opName#"_e32", SISubtarget.SI> {
1207 let AssemblerPredicate = SIAssemblerPredicate;
1210 class VOP1_Real_vi <string opName, vop1 op, dag outs, dag ins, string asm> :
1211 VOP1<op.VI, outs, ins, asm, []>,
1212 SIMCInstr <opName#"_e32", SISubtarget.VI> {
1213 let AssemblerPredicates = [isVI];
1216 multiclass VOP1_m <vop1 op, dag outs, dag ins, string asm, list<dag> pattern,
1218 def "" : VOP1_Pseudo <outs, ins, pattern, opName>;
1220 def _si : VOP1_Real_si <opName, op, outs, ins, asm>;
1222 def _vi : VOP1_Real_vi <opName, op, outs, ins, asm>;
1225 multiclass VOP1SI_m <vop1 op, dag outs, dag ins, string asm, list<dag> pattern,
1227 def "" : VOP1_Pseudo <outs, ins, pattern, opName>;
1229 def _si : VOP1_Real_si <opName, op, outs, ins, asm>;
1232 class VOP2_Pseudo <dag outs, dag ins, list<dag> pattern, string opName> :
1233 VOP2Common <outs, ins, "", pattern>,
1235 SIMCInstr<opName#"_e32", SISubtarget.NONE>,
1236 MnemonicAlias<opName#"_e32", opName> {
1238 let isCodeGenOnly = 1;
1241 class VOP2_Real_si <string opName, vop2 op, dag outs, dag ins, string asm> :
1242 VOP2 <op.SI, outs, ins, opName#asm, []>,
1243 SIMCInstr <opName#"_e32", SISubtarget.SI> {
1244 let AssemblerPredicates = [isSICI];
1247 class VOP2_Real_vi <string opName, vop2 op, dag outs, dag ins, string asm> :
1248 VOP2 <op.VI, outs, ins, opName#asm, []>,
1249 SIMCInstr <opName#"_e32", SISubtarget.VI> {
1250 let AssemblerPredicates = [isVI];
1253 multiclass VOP2SI_m <vop2 op, dag outs, dag ins, string asm, list<dag> pattern,
1254 string opName, string revOp> {
1255 def "" : VOP2_Pseudo <outs, ins, pattern, opName>,
1256 VOP2_REV<revOp#"_e32", !eq(revOp, opName)>;
1258 def _si : VOP2_Real_si <opName, op, outs, ins, asm>;
1261 multiclass VOP2_m <vop2 op, dag outs, dag ins, string asm, list<dag> pattern,
1262 string opName, string revOp> {
1263 def "" : VOP2_Pseudo <outs, ins, pattern, opName>,
1264 VOP2_REV<revOp#"_e32", !eq(revOp, opName)>;
1266 def _si : VOP2_Real_si <opName, op, outs, ins, asm>;
1268 def _vi : VOP2_Real_vi <opName, op, outs, ins, asm>;
1272 class VOP3DisableFields <bit HasSrc1, bit HasSrc2, bit HasModifiers> {
1274 bits<2> src0_modifiers = !if(HasModifiers, ?, 0);
1275 bits<2> src1_modifiers = !if(HasModifiers, !if(HasSrc1, ?, 0), 0);
1276 bits<2> src2_modifiers = !if(HasModifiers, !if(HasSrc2, ?, 0), 0);
1277 bits<2> omod = !if(HasModifiers, ?, 0);
1278 bits<1> clamp = !if(HasModifiers, ?, 0);
1279 bits<9> src1 = !if(HasSrc1, ?, 0);
1280 bits<9> src2 = !if(HasSrc2, ?, 0);
1283 class VOP3DisableModFields <bit HasSrc0Mods,
1284 bit HasSrc1Mods = 0,
1285 bit HasSrc2Mods = 0,
1286 bit HasOutputMods = 0> {
1287 bits<2> src0_modifiers = !if(HasSrc0Mods, ?, 0);
1288 bits<2> src1_modifiers = !if(HasSrc1Mods, ?, 0);
1289 bits<2> src2_modifiers = !if(HasSrc2Mods, ?, 0);
1290 bits<2> omod = !if(HasOutputMods, ?, 0);
1291 bits<1> clamp = !if(HasOutputMods, ?, 0);
1294 class VOP3_Pseudo <dag outs, dag ins, list<dag> pattern, string opName> :
1295 VOP3Common <outs, ins, "", pattern>,
1297 SIMCInstr<opName#"_e64", SISubtarget.NONE>,
1298 MnemonicAlias<opName#"_e64", opName> {
1300 let isCodeGenOnly = 1;
1303 class VOP3_Real_si <bits<9> op, dag outs, dag ins, string asm, string opName> :
1304 VOP3Common <outs, ins, asm, []>,
1306 SIMCInstr<opName#"_e64", SISubtarget.SI> {
1307 let AssemblerPredicates = [isSICI];
1310 class VOP3_Real_vi <bits<10> op, dag outs, dag ins, string asm, string opName> :
1311 VOP3Common <outs, ins, asm, []>,
1313 SIMCInstr <opName#"_e64", SISubtarget.VI> {
1314 let AssemblerPredicates = [isVI];
1317 class VOP3b_Real_si <bits<9> op, dag outs, dag ins, string asm, string opName> :
1318 VOP3Common <outs, ins, asm, []>,
1320 SIMCInstr<opName#"_e64", SISubtarget.SI> {
1321 let AssemblerPredicates = [isSICI];
1324 class VOP3b_Real_vi <bits<10> op, dag outs, dag ins, string asm, string opName> :
1325 VOP3Common <outs, ins, asm, []>,
1327 SIMCInstr <opName#"_e64", SISubtarget.VI> {
1328 let AssemblerPredicates = [isVI];
1331 multiclass VOP3_m <vop op, dag outs, dag ins, string asm, list<dag> pattern,
1332 string opName, int NumSrcArgs, bit HasMods = 1> {
1334 def "" : VOP3_Pseudo <outs, ins, pattern, opName>;
1336 def _si : VOP3_Real_si <op.SI3, outs, ins, asm, opName>,
1337 VOP3DisableFields<!if(!eq(NumSrcArgs, 1), 0, 1),
1338 !if(!eq(NumSrcArgs, 2), 0, 1),
1340 def _vi : VOP3_Real_vi <op.VI3, outs, ins, asm, opName>,
1341 VOP3DisableFields<!if(!eq(NumSrcArgs, 1), 0, 1),
1342 !if(!eq(NumSrcArgs, 2), 0, 1),
1346 // VOP3_m without source modifiers
1347 multiclass VOP3_m_nomods <vop op, dag outs, dag ins, string asm, list<dag> pattern,
1348 string opName, int NumSrcArgs, bit HasMods = 1> {
1350 def "" : VOP3_Pseudo <outs, ins, pattern, opName>;
1352 let src0_modifiers = 0,
1357 def _si : VOP3_Real_si <op.SI3, outs, ins, asm, opName>;
1358 def _vi : VOP3_Real_vi <op.VI3, outs, ins, asm, opName>;
1362 multiclass VOP3_1_m <vop op, dag outs, dag ins, string asm,
1363 list<dag> pattern, string opName, bit HasMods = 1> {
1365 def "" : VOP3_Pseudo <outs, ins, pattern, opName>;
1367 def _si : VOP3_Real_si <op.SI3, outs, ins, asm, opName>,
1368 VOP3DisableFields<0, 0, HasMods>;
1370 def _vi : VOP3_Real_vi <op.VI3, outs, ins, asm, opName>,
1371 VOP3DisableFields<0, 0, HasMods>;
1374 multiclass VOP3SI_1_m <vop op, dag outs, dag ins, string asm,
1375 list<dag> pattern, string opName, bit HasMods = 1> {
1377 def "" : VOP3_Pseudo <outs, ins, pattern, opName>;
1379 def _si : VOP3_Real_si <op.SI3, outs, ins, asm, opName>,
1380 VOP3DisableFields<0, 0, HasMods>;
1381 // No VI instruction. This class is for SI only.
1384 multiclass VOP3_2_m <vop op, dag outs, dag ins, string asm,
1385 list<dag> pattern, string opName, string revOp,
1386 bit HasMods = 1, bit UseFullOp = 0> {
1388 def "" : VOP3_Pseudo <outs, ins, pattern, opName>,
1389 VOP2_REV<revOp#"_e64", !eq(revOp, opName)>;
1391 def _si : VOP3_Real_si <op.SI3, outs, ins, asm, opName>,
1392 VOP3DisableFields<1, 0, HasMods>;
1394 def _vi : VOP3_Real_vi <op.VI3, outs, ins, asm, opName>,
1395 VOP3DisableFields<1, 0, HasMods>;
1398 multiclass VOP3SI_2_m <vop op, dag outs, dag ins, string asm,
1399 list<dag> pattern, string opName, string revOp,
1400 bit HasMods = 1, bit UseFullOp = 0> {
1402 def "" : VOP3_Pseudo <outs, ins, pattern, opName>,
1403 VOP2_REV<revOp#"_e64", !eq(revOp, opName)>;
1405 def _si : VOP3_Real_si <op.SI3, outs, ins, asm, opName>,
1406 VOP3DisableFields<1, 0, HasMods>;
1408 // No VI instruction. This class is for SI only.
1411 // XXX - Is v_div_scale_{f32|f64} only available in vop3b without
1412 // option of implicit vcc use?
1413 multiclass VOP3b_2_m <vop op, dag outs, dag ins, string asm,
1414 list<dag> pattern, string opName, string revOp,
1415 bit HasMods = 1, bit UseFullOp = 0> {
1416 def "" : VOP3_Pseudo <outs, ins, pattern, opName>,
1417 VOP2_REV<revOp#"_e64", !eq(revOp, opName)>;
1419 // The VOP2 variant puts the carry out into VCC, the VOP3 variant
1420 // can write it into any SGPR. We currently don't use the carry out,
1421 // so for now hardcode it to VCC as well.
1422 let sdst = SIOperand.VCC, Defs = [VCC] in {
1423 def _si : VOP3b_Real_si <op.SI3, outs, ins, asm, opName>,
1424 VOP3DisableFields<1, 0, HasMods>;
1426 def _vi : VOP3b_Real_vi <op.VI3, outs, ins, asm, opName>,
1427 VOP3DisableFields<1, 0, HasMods>;
1428 } // End sdst = SIOperand.VCC, Defs = [VCC]
1431 multiclass VOP3b_3_m <vop op, dag outs, dag ins, string asm,
1432 list<dag> pattern, string opName, string revOp,
1433 bit HasMods = 1, bit UseFullOp = 0> {
1434 def "" : VOP3_Pseudo <outs, ins, pattern, opName>;
1437 def _si : VOP3b_Real_si <op.SI3, outs, ins, asm, opName>,
1438 VOP3DisableFields<1, 1, HasMods>;
1440 def _vi : VOP3b_Real_vi <op.VI3, outs, ins, asm, opName>,
1441 VOP3DisableFields<1, 1, HasMods>;
1444 multiclass VOP3_C_m <vop op, dag outs, dag ins, string asm,
1445 list<dag> pattern, string opName,
1446 bit HasMods, bit defExec, string revOp> {
1448 def "" : VOP3_Pseudo <outs, ins, pattern, opName>,
1449 VOP2_REV<revOp#"_e64", !eq(revOp, opName)>;
1451 def _si : VOP3_Real_si <op.SI3, outs, ins, asm, opName>,
1452 VOP3DisableFields<1, 0, HasMods> {
1453 let Defs = !if(defExec, [EXEC], []);
1456 def _vi : VOP3_Real_vi <op.VI3, outs, ins, asm, opName>,
1457 VOP3DisableFields<1, 0, HasMods> {
1458 let Defs = !if(defExec, [EXEC], []);
1462 // An instruction that is VOP2 on SI and VOP3 on VI, no modifiers.
1463 multiclass VOP2SI_3VI_m <vop3 op, string opName, dag outs, dag ins,
1464 string asm, list<dag> pattern = []> {
1465 let isPseudo = 1, isCodeGenOnly = 1 in {
1466 def "" : VOPAnyCommon <outs, ins, "", pattern>,
1467 SIMCInstr<opName, SISubtarget.NONE>;
1470 def _si : VOP2 <op.SI3{5-0}, outs, ins, asm, []>,
1471 SIMCInstr <opName, SISubtarget.SI> {
1472 let AssemblerPredicates = [isSICI];
1475 def _vi : VOP3Common <outs, ins, asm, []>,
1477 VOP3DisableFields <1, 0, 0>,
1478 SIMCInstr <opName, SISubtarget.VI> {
1479 let AssemblerPredicates = [isVI];
1483 multiclass VOP1_Helper <vop1 op, string opName, dag outs,
1484 dag ins32, string asm32, list<dag> pat32,
1485 dag ins64, string asm64, list<dag> pat64,
1488 defm _e32 : VOP1_m <op, outs, ins32, opName#asm32, pat32, opName>;
1490 defm _e64 : VOP3_1_m <op, outs, ins64, opName#asm64, pat64, opName, HasMods>;
1493 multiclass VOP1Inst <vop1 op, string opName, VOPProfile P,
1494 SDPatternOperator node = null_frag> : VOP1_Helper <
1496 P.Ins32, P.Asm32, [],
1499 [(set P.DstVT:$dst, (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0,
1500 i32:$src0_modifiers, i1:$clamp, i32:$omod))))],
1501 [(set P.DstVT:$dst, (node P.Src0VT:$src0))]),
1505 multiclass VOP1InstSI <vop1 op, string opName, VOPProfile P,
1506 SDPatternOperator node = null_frag> {
1508 defm _e32 : VOP1SI_m <op, P.Outs, P.Ins32, opName#P.Asm32, [], opName>;
1510 defm _e64 : VOP3SI_1_m <op, P.Outs, P.Ins64, opName#P.Asm64,
1512 [(set P.DstVT:$dst, (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0,
1513 i32:$src0_modifiers, i1:$clamp, i32:$omod))))],
1514 [(set P.DstVT:$dst, (node P.Src0VT:$src0))]),
1515 opName, P.HasModifiers>;
1518 multiclass VOP2_Helper <vop2 op, string opName, dag outs,
1519 dag ins32, string asm32, list<dag> pat32,
1520 dag ins64, string asm64, list<dag> pat64,
1521 string revOp, bit HasMods> {
1522 defm _e32 : VOP2_m <op, outs, ins32, asm32, pat32, opName, revOp>;
1524 defm _e64 : VOP3_2_m <op,
1525 outs, ins64, opName#asm64, pat64, opName, revOp, HasMods
1529 multiclass VOP2Inst <vop2 op, string opName, VOPProfile P,
1530 SDPatternOperator node = null_frag,
1531 string revOp = opName> : VOP2_Helper <
1533 P.Ins32, P.Asm32, [],
1537 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1538 i1:$clamp, i32:$omod)),
1539 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))],
1540 [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1))]),
1541 revOp, P.HasModifiers
1544 multiclass VOP2InstSI <vop2 op, string opName, VOPProfile P,
1545 SDPatternOperator node = null_frag,
1546 string revOp = opName> {
1547 defm _e32 : VOP2SI_m <op, P.Outs, P.Ins32, P.Asm32, [], opName, revOp>;
1549 defm _e64 : VOP3SI_2_m <op, P.Outs, P.Ins64, opName#P.Asm64,
1552 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1553 i1:$clamp, i32:$omod)),
1554 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))],
1555 [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1))]),
1556 opName, revOp, P.HasModifiers>;
1559 multiclass VOP2b_Helper <vop2 op, string opName, dag outs,
1560 dag ins32, string asm32, list<dag> pat32,
1561 dag ins64, string asm64, list<dag> pat64,
1562 string revOp, bit HasMods> {
1564 defm _e32 : VOP2_m <op, outs, ins32, asm32, pat32, opName, revOp>;
1566 defm _e64 : VOP3b_2_m <op,
1567 outs, ins64, opName#asm64, pat64, opName, revOp, HasMods
1571 multiclass VOP2bInst <vop2 op, string opName, VOPProfile P,
1572 SDPatternOperator node = null_frag,
1573 string revOp = opName> : VOP2b_Helper <
1575 P.Ins32, P.Asm32, [],
1579 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1580 i1:$clamp, i32:$omod)),
1581 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))],
1582 [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1))]),
1583 revOp, P.HasModifiers
1586 // A VOP2 instruction that is VOP3-only on VI.
1587 multiclass VOP2_VI3_Helper <vop23 op, string opName, dag outs,
1588 dag ins32, string asm32, list<dag> pat32,
1589 dag ins64, string asm64, list<dag> pat64,
1590 string revOp, bit HasMods> {
1591 defm _e32 : VOP2SI_m <op, outs, ins32, asm32, pat32, opName, revOp>;
1593 defm _e64 : VOP3_2_m <op, outs, ins64, opName#asm64, pat64, opName,
1597 multiclass VOP2_VI3_Inst <vop23 op, string opName, VOPProfile P,
1598 SDPatternOperator node = null_frag,
1599 string revOp = opName>
1602 P.Ins32, P.Asm32, [],
1606 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1607 i1:$clamp, i32:$omod)),
1608 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))],
1609 [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1))]),
1610 revOp, P.HasModifiers
1613 multiclass VOP2MADK <vop2 op, string opName, list<dag> pattern = []> {
1615 def "" : VOP2_Pseudo <VOP_MADK.Outs, VOP_MADK.Ins, pattern, opName>;
1617 let isCodeGenOnly = 0 in {
1618 def _si : VOP2Common <VOP_MADK.Outs, VOP_MADK.Ins,
1619 !strconcat(opName, VOP_MADK.Asm), []>,
1620 SIMCInstr <opName#"_e32", SISubtarget.SI>,
1621 VOP2_MADKe <op.SI> {
1622 let AssemblerPredicates = [isSICI];
1625 def _vi : VOP2Common <VOP_MADK.Outs, VOP_MADK.Ins,
1626 !strconcat(opName, VOP_MADK.Asm), []>,
1627 SIMCInstr <opName#"_e32", SISubtarget.VI>,
1628 VOP2_MADKe <op.VI> {
1629 let AssemblerPredicates = [isVI];
1631 } // End isCodeGenOnly = 0
1634 class VOPC_Pseudo <dag ins, list<dag> pattern, string opName> :
1635 VOPCCommon <ins, "", pattern>,
1637 SIMCInstr<opName#"_e32", SISubtarget.NONE> {
1639 let isCodeGenOnly = 1;
1642 multiclass VOPC_m <vopc op, dag ins, string op_asm, list<dag> pattern,
1643 string opName, bit DefExec, VOPProfile p,
1644 string revOpName = "", string asm = opName#"_e32 "#op_asm,
1645 string alias_asm = opName#" "#op_asm> {
1646 def "" : VOPC_Pseudo <ins, pattern, opName>;
1648 let AssemblerPredicates = [isSICI] in {
1650 def _si : VOPC<op.SI, ins, asm, []>,
1651 SIMCInstr <opName#"_e32", SISubtarget.SI> {
1652 let Defs = !if(DefExec, [VCC, EXEC], [VCC]);
1653 let hasSideEffects = DefExec;
1658 (!cast<Instruction>(NAME#"_e32_si") p.Src0RC32:$src0, p.Src1RC32:$src1)
1661 } // End AssemblerPredicates = [isSICI]
1664 let AssemblerPredicates = [isVI] in {
1666 def _vi : VOPC<op.VI, ins, asm, []>,
1667 SIMCInstr <opName#"_e32", SISubtarget.VI> {
1668 let Defs = !if(DefExec, [VCC, EXEC], [VCC]);
1669 let hasSideEffects = DefExec;
1674 (!cast<Instruction>(NAME#"_e32_vi") p.Src0RC32:$src0, p.Src1RC32:$src1)
1677 } // End AssemblerPredicates = [isVI]
1680 multiclass VOPC_Helper <vopc op, string opName,
1681 dag ins32, string asm32, list<dag> pat32,
1682 dag out64, dag ins64, string asm64, list<dag> pat64,
1683 bit HasMods, bit DefExec, string revOp,
1685 defm _e32 : VOPC_m <op, ins32, asm32, pat32, opName, DefExec, p>;
1687 defm _e64 : VOP3_C_m <op, out64, ins64, opName#asm64, pat64,
1688 opName, HasMods, DefExec, revOp>;
1691 // Special case for class instructions which only have modifiers on
1692 // the 1st source operand.
1693 multiclass VOPC_Class_Helper <vopc op, string opName,
1694 dag ins32, string asm32, list<dag> pat32,
1695 dag out64, dag ins64, string asm64, list<dag> pat64,
1696 bit HasMods, bit DefExec, string revOp,
1698 defm _e32 : VOPC_m <op, ins32, asm32, pat32, opName, DefExec, p>;
1700 defm _e64 : VOP3_C_m <op, out64, ins64, opName#asm64, pat64,
1701 opName, HasMods, DefExec, revOp>,
1702 VOP3DisableModFields<1, 0, 0>;
1705 multiclass VOPCInst <vopc op, string opName,
1706 VOPProfile P, PatLeaf cond = COND_NULL,
1707 string revOp = opName,
1708 bit DefExec = 0> : VOPC_Helper <
1710 P.Ins32, P.Asm32, [],
1711 (outs VOPDstS64:$dst), P.Ins64, P.Asm64,
1714 (setcc (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1715 i1:$clamp, i32:$omod)),
1716 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers)),
1718 [(set i1:$dst, (setcc P.Src0VT:$src0, P.Src1VT:$src1, cond))]),
1719 P.HasModifiers, DefExec, revOp, P
1722 multiclass VOPCClassInst <vopc op, string opName, VOPProfile P,
1723 bit DefExec = 0> : VOPC_Class_Helper <
1725 P.Ins32, P.Asm32, [],
1726 (outs VOPDstS64:$dst), P.Ins64, P.Asm64,
1729 (AMDGPUfp_class (P.Src0VT (VOP3Mods0Clamp0OMod P.Src0VT:$src0, i32:$src0_modifiers)), P.Src1VT:$src1))],
1730 [(set i1:$dst, (AMDGPUfp_class P.Src0VT:$src0, P.Src1VT:$src1))]),
1731 P.HasModifiers, DefExec, opName, P
1735 multiclass VOPC_F32 <vopc op, string opName, PatLeaf cond = COND_NULL, string revOp = opName> :
1736 VOPCInst <op, opName, VOPC_I1_F32_F32, cond, revOp>;
1738 multiclass VOPC_F64 <vopc op, string opName, PatLeaf cond = COND_NULL, string revOp = opName> :
1739 VOPCInst <op, opName, VOPC_I1_F64_F64, cond, revOp>;
1741 multiclass VOPC_I32 <vopc op, string opName, PatLeaf cond = COND_NULL, string revOp = opName> :
1742 VOPCInst <op, opName, VOPC_I1_I32_I32, cond, revOp>;
1744 multiclass VOPC_I64 <vopc op, string opName, PatLeaf cond = COND_NULL, string revOp = opName> :
1745 VOPCInst <op, opName, VOPC_I1_I64_I64, cond, revOp>;
1748 multiclass VOPCX <vopc op, string opName, VOPProfile P,
1749 PatLeaf cond = COND_NULL,
1751 : VOPCInst <op, opName, P, cond, revOp, 1>;
1753 multiclass VOPCX_F32 <vopc op, string opName, string revOp = opName> :
1754 VOPCX <op, opName, VOPC_I1_F32_F32, COND_NULL, revOp>;
1756 multiclass VOPCX_F64 <vopc op, string opName, string revOp = opName> :
1757 VOPCX <op, opName, VOPC_I1_F64_F64, COND_NULL, revOp>;
1759 multiclass VOPCX_I32 <vopc op, string opName, string revOp = opName> :
1760 VOPCX <op, opName, VOPC_I1_I32_I32, COND_NULL, revOp>;
1762 multiclass VOPCX_I64 <vopc op, string opName, string revOp = opName> :
1763 VOPCX <op, opName, VOPC_I1_I64_I64, COND_NULL, revOp>;
1765 multiclass VOP3_Helper <vop3 op, string opName, dag outs, dag ins, string asm,
1766 list<dag> pat, int NumSrcArgs, bit HasMods> : VOP3_m <
1767 op, outs, ins, opName#" "#asm, pat, opName, NumSrcArgs, HasMods
1770 multiclass VOPC_CLASS_F32 <vopc op, string opName> :
1771 VOPCClassInst <op, opName, VOPC_I1_F32_I32, 0>;
1773 multiclass VOPCX_CLASS_F32 <vopc op, string opName> :
1774 VOPCClassInst <op, opName, VOPC_I1_F32_I32, 1>;
1776 multiclass VOPC_CLASS_F64 <vopc op, string opName> :
1777 VOPCClassInst <op, opName, VOPC_I1_F64_I32, 0>;
1779 multiclass VOPCX_CLASS_F64 <vopc op, string opName> :
1780 VOPCClassInst <op, opName, VOPC_I1_F64_I32, 1>;
1782 multiclass VOP3Inst <vop3 op, string opName, VOPProfile P,
1783 SDPatternOperator node = null_frag> : VOP3_Helper <
1784 op, opName, (outs P.DstRC.RegClass:$dst), P.Ins64, P.Asm64,
1785 !if(!eq(P.NumSrcArgs, 3),
1788 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1789 i1:$clamp, i32:$omod)),
1790 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers)),
1791 (P.Src2VT (VOP3Mods P.Src2VT:$src2, i32:$src2_modifiers))))],
1792 [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1,
1794 !if(!eq(P.NumSrcArgs, 2),
1797 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1798 i1:$clamp, i32:$omod)),
1799 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))],
1800 [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1))])
1801 /* P.NumSrcArgs == 1 */,
1804 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1805 i1:$clamp, i32:$omod))))],
1806 [(set P.DstVT:$dst, (node P.Src0VT:$src0))]))),
1807 P.NumSrcArgs, P.HasModifiers
1810 // Special case for v_div_fmas_{f32|f64}, since it seems to be the
1811 // only VOP instruction that implicitly reads VCC.
1812 multiclass VOP3_VCC_Inst <vop3 op, string opName,
1814 SDPatternOperator node = null_frag> : VOP3_Helper <
1816 (outs P.DstRC.RegClass:$dst),
1817 (ins InputModsNoDefault:$src0_modifiers, P.Src0RC64:$src0,
1818 InputModsNoDefault:$src1_modifiers, P.Src1RC64:$src1,
1819 InputModsNoDefault:$src2_modifiers, P.Src2RC64:$src2,
1822 "$dst, $src0_modifiers, $src1_modifiers, $src2_modifiers"#"$clamp"#"$omod",
1824 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1825 i1:$clamp, i32:$omod)),
1826 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers)),
1827 (P.Src2VT (VOP3Mods P.Src2VT:$src2, i32:$src2_modifiers)),
1832 multiclass VOP3b_Helper <vop op, RegisterClass vrc, RegisterOperand arc,
1833 string opName, list<dag> pattern> :
1835 op, (outs vrc:$vdst, SReg_64:$sdst),
1836 (ins InputModsNoDefault:$src0_modifiers, arc:$src0,
1837 InputModsNoDefault:$src1_modifiers, arc:$src1,
1838 InputModsNoDefault:$src2_modifiers, arc:$src2,
1839 ClampMod:$clamp, omod:$omod),
1840 opName#" $vdst, $sdst, $src0_modifiers, $src1_modifiers, $src2_modifiers"#"$clamp"#"$omod", pattern,
1841 opName, opName, 1, 1
1844 multiclass VOP3b_64 <vop3 op, string opName, list<dag> pattern> :
1845 VOP3b_Helper <op, VReg_64, VSrc_64, opName, pattern>;
1847 multiclass VOP3b_32 <vop3 op, string opName, list<dag> pattern> :
1848 VOP3b_Helper <op, VGPR_32, VSrc_32, opName, pattern>;
1851 class Vop3ModPat<Instruction Inst, VOPProfile P, SDPatternOperator node> : Pat<
1852 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp, i32:$omod)),
1853 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers)),
1854 (P.Src2VT (VOP3Mods P.Src2VT:$src2, i32:$src2_modifiers))),
1855 (Inst i32:$src0_modifiers, P.Src0VT:$src0,
1856 i32:$src1_modifiers, P.Src1VT:$src1,
1857 i32:$src2_modifiers, P.Src2VT:$src2,
1861 //===----------------------------------------------------------------------===//
1862 // Interpolation opcodes
1863 //===----------------------------------------------------------------------===//
1865 class VINTRP_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> :
1866 VINTRPCommon <outs, ins, "", pattern>,
1867 SIMCInstr<opName, SISubtarget.NONE> {
1869 let isCodeGenOnly = 1;
1872 class VINTRP_Real_si <bits <2> op, string opName, dag outs, dag ins,
1874 VINTRPCommon <outs, ins, asm, []>,
1876 SIMCInstr<opName, SISubtarget.SI>;
1878 class VINTRP_Real_vi <bits <2> op, string opName, dag outs, dag ins,
1880 VINTRPCommon <outs, ins, asm, []>,
1882 SIMCInstr<opName, SISubtarget.VI>;
1884 multiclass VINTRP_m <bits <2> op, dag outs, dag ins, string asm,
1885 list<dag> pattern = []> {
1886 def "" : VINTRP_Pseudo <NAME, outs, ins, pattern>;
1888 def _si : VINTRP_Real_si <op, NAME, outs, ins, asm>;
1890 def _vi : VINTRP_Real_vi <op, NAME, outs, ins, asm>;
1893 //===----------------------------------------------------------------------===//
1894 // Vector I/O classes
1895 //===----------------------------------------------------------------------===//
1897 class DS_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> :
1898 DS <outs, ins, "", pattern>,
1899 SIMCInstr <opName, SISubtarget.NONE> {
1901 let isCodeGenOnly = 1;
1904 class DS_Real_si <bits<8> op, string opName, dag outs, dag ins, string asm> :
1905 DS <outs, ins, asm, []>,
1907 SIMCInstr <opName, SISubtarget.SI> {
1908 let isCodeGenOnly = 0;
1911 class DS_Real_vi <bits<8> op, string opName, dag outs, dag ins, string asm> :
1912 DS <outs, ins, asm, []>,
1914 SIMCInstr <opName, SISubtarget.VI>;
1916 class DS_Off16_Real_si <bits<8> op, string opName, dag outs, dag ins, string asm> :
1917 DS_Real_si <op,opName, outs, ins, asm> {
1919 // Single load interpret the 2 i8imm operands as a single i16 offset.
1921 let offset0 = offset{7-0};
1922 let offset1 = offset{15-8};
1923 let isCodeGenOnly = 0;
1926 class DS_Off16_Real_vi <bits<8> op, string opName, dag outs, dag ins, string asm> :
1927 DS_Real_vi <op, opName, outs, ins, asm> {
1929 // Single load interpret the 2 i8imm operands as a single i16 offset.
1931 let offset0 = offset{7-0};
1932 let offset1 = offset{15-8};
1935 multiclass DS_1A_RET <bits<8> op, string opName, RegisterClass rc,
1936 dag outs = (outs rc:$vdst),
1937 dag ins = (ins VGPR_32:$addr, ds_offset:$offset, gds:$gds),
1938 string asm = opName#" $vdst, $addr"#"$offset$gds"> {
1940 def "" : DS_Pseudo <opName, outs, ins, []>;
1942 let data0 = 0, data1 = 0 in {
1943 def _si : DS_Off16_Real_si <op, opName, outs, ins, asm>;
1944 def _vi : DS_Off16_Real_vi <op, opName, outs, ins, asm>;
1948 multiclass DS_1A_Off8_RET <bits<8> op, string opName, RegisterClass rc,
1949 dag outs = (outs rc:$vdst),
1950 dag ins = (ins VGPR_32:$addr, ds_offset0:$offset0, ds_offset1:$offset1,
1952 string asm = opName#" $vdst, $addr"#"$offset0"#"$offset1$gds"> {
1954 def "" : DS_Pseudo <opName, outs, ins, []>;
1956 let data0 = 0, data1 = 0, AsmMatchConverter = "cvtDSOffset01" in {
1957 def _si : DS_Real_si <op, opName, outs, ins, asm>;
1958 def _vi : DS_Real_vi <op, opName, outs, ins, asm>;
1962 multiclass DS_1A1D_NORET <bits<8> op, string opName, RegisterClass rc,
1964 dag ins = (ins VGPR_32:$addr, rc:$data0, ds_offset:$offset, gds:$gds),
1965 string asm = opName#" $addr, $data0"#"$offset$gds"> {
1967 def "" : DS_Pseudo <opName, outs, ins, []>,
1968 AtomicNoRet<opName, 0>;
1970 let data1 = 0, vdst = 0 in {
1971 def _si : DS_Off16_Real_si <op, opName, outs, ins, asm>;
1972 def _vi : DS_Off16_Real_vi <op, opName, outs, ins, asm>;
1976 multiclass DS_1A1D_Off8_NORET <bits<8> op, string opName, RegisterClass rc,
1978 dag ins = (ins VGPR_32:$addr, rc:$data0, rc:$data1,
1979 ds_offset0:$offset0, ds_offset1:$offset1, gds01:$gds),
1980 string asm = opName#" $addr, $data0, $data1"#"$offset0"#"$offset1"#"$gds"> {
1982 def "" : DS_Pseudo <opName, outs, ins, []>;
1984 let vdst = 0, AsmMatchConverter = "cvtDSOffset01" in {
1985 def _si : DS_Real_si <op, opName, outs, ins, asm>;
1986 def _vi : DS_Real_vi <op, opName, outs, ins, asm>;
1990 multiclass DS_1A1D_RET <bits<8> op, string opName, RegisterClass rc,
1991 string noRetOp = "",
1992 dag outs = (outs rc:$vdst),
1993 dag ins = (ins VGPR_32:$addr, rc:$data0, ds_offset:$offset, gds:$gds),
1994 string asm = opName#" $vdst, $addr, $data0"#"$offset$gds"> {
1996 def "" : DS_Pseudo <opName, outs, ins, []>,
1997 AtomicNoRet<noRetOp, 1>;
2000 def _si : DS_Off16_Real_si <op, opName, outs, ins, asm>;
2001 def _vi : DS_Off16_Real_vi <op, opName, outs, ins, asm>;
2005 multiclass DS_1A2D_RET_m <bits<8> op, string opName, RegisterClass rc,
2006 string noRetOp = "", dag ins,
2007 dag outs = (outs rc:$vdst),
2008 string asm = opName#" $vdst, $addr, $data0, $data1"#"$offset"#"$gds"> {
2010 def "" : DS_Pseudo <opName, outs, ins, []>,
2011 AtomicNoRet<noRetOp, 1>;
2013 def _si : DS_Off16_Real_si <op, opName, outs, ins, asm>;
2014 def _vi : DS_Off16_Real_vi <op, opName, outs, ins, asm>;
2017 multiclass DS_1A2D_RET <bits<8> op, string asm, RegisterClass rc,
2018 string noRetOp = "", RegisterClass src = rc> :
2019 DS_1A2D_RET_m <op, asm, rc, noRetOp,
2020 (ins VGPR_32:$addr, src:$data0, src:$data1,
2021 ds_offset:$offset, gds:$gds)
2024 multiclass DS_1A2D_NORET <bits<8> op, string opName, RegisterClass rc,
2025 string noRetOp = opName,
2027 dag ins = (ins VGPR_32:$addr, rc:$data0, rc:$data1,
2028 ds_offset:$offset, gds:$gds),
2029 string asm = opName#" $addr, $data0, $data1"#"$offset"#"$gds"> {
2031 def "" : DS_Pseudo <opName, outs, ins, []>,
2032 AtomicNoRet<noRetOp, 0>;
2035 def _si : DS_Off16_Real_si <op, opName, outs, ins, asm>;
2036 def _vi : DS_Off16_Real_vi <op, opName, outs, ins, asm>;
2040 multiclass DS_0A_RET <bits<8> op, string opName,
2041 dag outs = (outs VGPR_32:$vdst),
2042 dag ins = (ins ds_offset:$offset, gds:$gds),
2043 string asm = opName#" $vdst"#"$offset"#"$gds"> {
2045 let mayLoad = 1, mayStore = 1 in {
2046 def "" : DS_Pseudo <opName, outs, ins, []>;
2048 let addr = 0, data0 = 0, data1 = 0 in {
2049 def _si : DS_Off16_Real_si <op, opName, outs, ins, asm>;
2050 def _vi : DS_Off16_Real_vi <op, opName, outs, ins, asm>;
2051 } // end addr = 0, data0 = 0, data1 = 0
2052 } // end mayLoad = 1, mayStore = 1
2055 multiclass DS_1A_RET_GDS <bits<8> op, string opName,
2056 dag outs = (outs VGPR_32:$vdst),
2057 dag ins = (ins VGPR_32:$addr, ds_offset_gds:$offset),
2058 string asm = opName#" $vdst, $addr"#"$offset gds"> {
2060 def "" : DS_Pseudo <opName, outs, ins, []>;
2062 let data0 = 0, data1 = 0, gds = 1 in {
2063 def _si : DS_Off16_Real_si <op, opName, outs, ins, asm>;
2064 def _vi : DS_Off16_Real_vi <op, opName, outs, ins, asm>;
2065 } // end data0 = 0, data1 = 0, gds = 1
2068 multiclass DS_1A_GDS <bits<8> op, string opName,
2070 dag ins = (ins VGPR_32:$addr),
2071 string asm = opName#" $addr gds"> {
2073 def "" : DS_Pseudo <opName, outs, ins, []>;
2075 let vdst = 0, data0 = 0, data1 = 0, offset0 = 0, offset1 = 0, gds = 1 in {
2076 def _si : DS_Real_si <op, opName, outs, ins, asm>;
2077 def _vi : DS_Real_vi <op, opName, outs, ins, asm>;
2078 } // end vdst = 0, data = 0, data1 = 0, gds = 1
2081 multiclass DS_1A <bits<8> op, string opName,
2083 dag ins = (ins VGPR_32:$addr, ds_offset:$offset, gds:$gds),
2084 string asm = opName#" $addr"#"$offset"#"$gds"> {
2086 let mayLoad = 1, mayStore = 1 in {
2087 def "" : DS_Pseudo <opName, outs, ins, []>;
2089 let vdst = 0, data0 = 0, data1 = 0 in {
2090 def _si : DS_Off16_Real_si <op, opName, outs, ins, asm>;
2091 def _vi : DS_Off16_Real_vi <op, opName, outs, ins, asm>;
2092 } // let vdst = 0, data0 = 0, data1 = 0
2093 } // end mayLoad = 1, mayStore = 1
2096 //===----------------------------------------------------------------------===//
2098 //===----------------------------------------------------------------------===//
2100 class MTBUF_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> :
2101 MTBUF <outs, ins, "", pattern>,
2102 SIMCInstr<opName, SISubtarget.NONE> {
2104 let isCodeGenOnly = 1;
2107 class MTBUF_Real_si <bits<3> op, string opName, dag outs, dag ins,
2109 MTBUF <outs, ins, asm, []>,
2111 SIMCInstr<opName, SISubtarget.SI>;
2113 class MTBUF_Real_vi <bits<4> op, string opName, dag outs, dag ins, string asm> :
2114 MTBUF <outs, ins, asm, []>,
2116 SIMCInstr <opName, SISubtarget.VI>;
2118 multiclass MTBUF_m <bits<3> op, string opName, dag outs, dag ins, string asm,
2119 list<dag> pattern> {
2121 def "" : MTBUF_Pseudo <opName, outs, ins, pattern>;
2123 def _si : MTBUF_Real_si <op, opName, outs, ins, asm>;
2125 def _vi : MTBUF_Real_vi <{0, op{2}, op{1}, op{0}}, opName, outs, ins, asm>;
2129 let mayStore = 1, mayLoad = 0 in {
2131 multiclass MTBUF_Store_Helper <bits<3> op, string opName,
2132 RegisterClass regClass> : MTBUF_m <
2134 (ins regClass:$vdata, u16imm:$offset, i1imm:$offen, i1imm:$idxen, i1imm:$glc,
2135 i1imm:$addr64, i8imm:$dfmt, i8imm:$nfmt, VGPR_32:$vaddr,
2136 SReg_128:$srsrc, i1imm:$slc, i1imm:$tfe, SCSrc_32:$soffset),
2137 opName#" $vdata, $offset, $offen, $idxen, $glc, $addr64, $dfmt,"
2138 #" $nfmt, $vaddr, $srsrc, $slc, $tfe, $soffset", []
2141 } // mayStore = 1, mayLoad = 0
2143 let mayLoad = 1, mayStore = 0 in {
2145 multiclass MTBUF_Load_Helper <bits<3> op, string opName,
2146 RegisterClass regClass> : MTBUF_m <
2147 op, opName, (outs regClass:$dst),
2148 (ins u16imm:$offset, i1imm:$offen, i1imm:$idxen, i1imm:$glc, i1imm:$addr64,
2149 i8imm:$dfmt, i8imm:$nfmt, VGPR_32:$vaddr, SReg_128:$srsrc,
2150 i1imm:$slc, i1imm:$tfe, SCSrc_32:$soffset),
2151 opName#" $dst, $offset, $offen, $idxen, $glc, $addr64, $dfmt,"
2152 #" $nfmt, $vaddr, $srsrc, $slc, $tfe, $soffset", []
2155 } // mayLoad = 1, mayStore = 0
2157 //===----------------------------------------------------------------------===//
2159 //===----------------------------------------------------------------------===//
2161 class mubuf <bits<7> si, bits<7> vi = si> {
2162 field bits<7> SI = si;
2163 field bits<7> VI = vi;
2166 let isCodeGenOnly = 0 in {
2168 class MUBUF_si <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern> :
2169 MUBUF <outs, ins, asm, pattern>, MUBUFe <op> {
2173 } // End let isCodeGenOnly = 0
2175 class MUBUF_vi <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern> :
2176 MUBUF <outs, ins, asm, pattern>, MUBUFe_vi <op> {
2180 class MUBUFAddr64Table <bit is_addr64, string suffix = ""> {
2181 bit IsAddr64 = is_addr64;
2182 string OpName = NAME # suffix;
2185 class MUBUF_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> :
2186 MUBUF <outs, ins, "", pattern>,
2187 SIMCInstr<opName, SISubtarget.NONE> {
2189 let isCodeGenOnly = 1;
2191 // dummy fields, so that we can use let statements around multiclasses
2201 class MUBUF_Real_si <mubuf op, string opName, dag outs, dag ins,
2203 MUBUF <outs, ins, asm, []>,
2205 SIMCInstr<opName, SISubtarget.SI> {
2209 class MUBUF_Real_vi <mubuf op, string opName, dag outs, dag ins,
2211 MUBUF <outs, ins, asm, []>,
2213 SIMCInstr<opName, SISubtarget.VI> {
2217 multiclass MUBUF_m <mubuf op, string opName, dag outs, dag ins, string asm,
2218 list<dag> pattern> {
2220 def "" : MUBUF_Pseudo <opName, outs, ins, pattern>,
2221 MUBUFAddr64Table <0>;
2223 let addr64 = 0, isCodeGenOnly = 0 in {
2224 def _si : MUBUF_Real_si <op, opName, outs, ins, asm>;
2227 def _vi : MUBUF_Real_vi <op, opName, outs, ins, asm>;
2230 multiclass MUBUFAddr64_m <mubuf op, string opName, dag outs,
2231 dag ins, string asm, list<dag> pattern> {
2233 def "" : MUBUF_Pseudo <opName, outs, ins, pattern>,
2234 MUBUFAddr64Table <1>;
2236 let addr64 = 1, isCodeGenOnly = 0 in {
2237 def _si : MUBUF_Real_si <op, opName, outs, ins, asm>;
2240 // There is no VI version. If the pseudo is selected, it should be lowered
2241 // for VI appropriately.
2244 multiclass MUBUFAtomicOffset_m <mubuf op, string opName, dag outs, dag ins,
2245 string asm, list<dag> pattern, bit is_return> {
2247 def "" : MUBUF_Pseudo <opName, outs, ins, pattern>,
2248 MUBUFAddr64Table <0, !if(is_return, "_RTN", "")>,
2249 AtomicNoRet<NAME#"_OFFSET", is_return>;
2251 let offen = 0, idxen = 0, tfe = 0, vaddr = 0 in {
2253 def _si : MUBUF_Real_si <op, opName, outs, ins, asm>;
2256 def _vi : MUBUF_Real_vi <op, opName, outs, ins, asm>;
2260 multiclass MUBUFAtomicAddr64_m <mubuf op, string opName, dag outs, dag ins,
2261 string asm, list<dag> pattern, bit is_return> {
2263 def "" : MUBUF_Pseudo <opName, outs, ins, pattern>,
2264 MUBUFAddr64Table <1, !if(is_return, "_RTN", "")>,
2265 AtomicNoRet<NAME#"_ADDR64", is_return>;
2267 let offen = 0, idxen = 0, addr64 = 1, tfe = 0 in {
2268 def _si : MUBUF_Real_si <op, opName, outs, ins, asm>;
2271 // There is no VI version. If the pseudo is selected, it should be lowered
2272 // for VI appropriately.
2275 multiclass MUBUF_Atomic <mubuf op, string name, RegisterClass rc,
2276 ValueType vt, SDPatternOperator atomic> {
2278 let mayStore = 1, mayLoad = 1, hasPostISelHook = 1 in {
2280 // No return variants
2283 defm _ADDR64 : MUBUFAtomicAddr64_m <
2284 op, name#"_addr64", (outs),
2285 (ins rc:$vdata, SReg_128:$srsrc, VReg_64:$vaddr,
2286 SCSrc_32:$soffset, mbuf_offset:$offset, slc:$slc),
2287 name#" $vdata, $vaddr, $srsrc, $soffset addr64"#"$offset"#"$slc", [], 0
2290 defm _OFFSET : MUBUFAtomicOffset_m <
2291 op, name#"_offset", (outs),
2292 (ins rc:$vdata, SReg_128:$srsrc, SCSrc_32:$soffset, mbuf_offset:$offset,
2294 name#" $vdata, $srsrc, $soffset"#"$offset"#"$slc", [], 0
2298 // Variant that return values
2299 let glc = 1, Constraints = "$vdata = $vdata_in",
2300 DisableEncoding = "$vdata_in" in {
2302 defm _RTN_ADDR64 : MUBUFAtomicAddr64_m <
2303 op, name#"_rtn_addr64", (outs rc:$vdata),
2304 (ins rc:$vdata_in, SReg_128:$srsrc, VReg_64:$vaddr,
2305 SCSrc_32:$soffset, mbuf_offset:$offset, slc:$slc),
2306 name#" $vdata, $vaddr, $srsrc, $soffset addr64"#"$offset"#" glc"#"$slc",
2308 (atomic (MUBUFAddr64Atomic v4i32:$srsrc, i64:$vaddr, i32:$soffset,
2309 i16:$offset, i1:$slc), vt:$vdata_in))], 1
2312 defm _RTN_OFFSET : MUBUFAtomicOffset_m <
2313 op, name#"_rtn_offset", (outs rc:$vdata),
2314 (ins rc:$vdata_in, SReg_128:$srsrc, SCSrc_32:$soffset,
2315 mbuf_offset:$offset, slc:$slc),
2316 name#" $vdata, $srsrc, $soffset"#"$offset"#" glc $slc",
2318 (atomic (MUBUFOffsetAtomic v4i32:$srsrc, i32:$soffset, i16:$offset,
2319 i1:$slc), vt:$vdata_in))], 1
2324 } // mayStore = 1, mayLoad = 1, hasPostISelHook = 1
2327 multiclass MUBUF_Load_Helper <mubuf op, string name, RegisterClass regClass,
2328 ValueType load_vt = i32,
2329 SDPatternOperator ld = null_frag> {
2331 let mayLoad = 1, mayStore = 0 in {
2332 let offen = 0, idxen = 0, vaddr = 0 in {
2333 defm _OFFSET : MUBUF_m <op, name#"_offset", (outs regClass:$vdata),
2334 (ins SReg_128:$srsrc, SCSrc_32:$soffset,
2335 mbuf_offset:$offset, glc:$glc, slc:$slc, tfe:$tfe),
2336 name#" $vdata, $srsrc, $soffset"#"$offset"#"$glc"#"$slc"#"$tfe",
2337 [(set load_vt:$vdata, (ld (MUBUFOffset v4i32:$srsrc,
2338 i32:$soffset, i16:$offset,
2339 i1:$glc, i1:$slc, i1:$tfe)))]>;
2342 let offen = 1, idxen = 0 in {
2343 defm _OFFEN : MUBUF_m <op, name#"_offen", (outs regClass:$vdata),
2344 (ins VGPR_32:$vaddr, SReg_128:$srsrc,
2345 SCSrc_32:$soffset, mbuf_offset:$offset, glc:$glc, slc:$slc,
2347 name#" $vdata, $vaddr, $srsrc, $soffset offen"#"$offset"#"$glc"#"$slc"#"$tfe", []>;
2350 let offen = 0, idxen = 1 in {
2351 defm _IDXEN : MUBUF_m <op, name#"_idxen", (outs regClass:$vdata),
2352 (ins VGPR_32:$vaddr, SReg_128:$srsrc,
2353 SCSrc_32:$soffset, mbuf_offset:$offset, glc:$glc,
2354 slc:$slc, tfe:$tfe),
2355 name#" $vdata, $vaddr, $srsrc, $soffset idxen"#"$offset"#"$glc"#"$slc"#"$tfe", []>;
2358 let offen = 1, idxen = 1 in {
2359 defm _BOTHEN : MUBUF_m <op, name#"_bothen", (outs regClass:$vdata),
2360 (ins VReg_64:$vaddr, SReg_128:$srsrc, SCSrc_32:$soffset,
2361 mbuf_offset:$offset, glc:$glc, slc:$slc, tfe:$tfe),
2362 name#" $vdata, $vaddr, $srsrc, $soffset idxen offen"#"$offset"#"$glc"#"$slc"#"$tfe", []>;
2365 let offen = 0, idxen = 0 in {
2366 defm _ADDR64 : MUBUFAddr64_m <op, name#"_addr64", (outs regClass:$vdata),
2367 (ins VReg_64:$vaddr, SReg_128:$srsrc,
2368 SCSrc_32:$soffset, mbuf_offset:$offset,
2369 glc:$glc, slc:$slc, tfe:$tfe),
2370 name#" $vdata, $vaddr, $srsrc, $soffset addr64"#"$offset"#
2371 "$glc"#"$slc"#"$tfe",
2372 [(set load_vt:$vdata, (ld (MUBUFAddr64 v4i32:$srsrc,
2373 i64:$vaddr, i32:$soffset,
2374 i16:$offset, i1:$glc, i1:$slc,
2380 multiclass MUBUF_Store_Helper <mubuf op, string name, RegisterClass vdataClass,
2381 ValueType store_vt = i32, SDPatternOperator st = null_frag> {
2382 let mayLoad = 0, mayStore = 1 in {
2383 defm : MUBUF_m <op, name, (outs),
2384 (ins vdataClass:$vdata, VGPR_32:$vaddr, SReg_128:$srsrc, SCSrc_32:$soffset,
2385 mbuf_offset:$offset, offen:$offen, idxen:$idxen, glc:$glc, slc:$slc,
2387 name#" $vdata, $vaddr, $srsrc, $soffset"#"$offen"#"$idxen"#"$offset"#
2388 "$glc"#"$slc"#"$tfe", []>;
2390 let offen = 0, idxen = 0, vaddr = 0 in {
2391 defm _OFFSET : MUBUF_m <op, name#"_offset",(outs),
2392 (ins vdataClass:$vdata, SReg_128:$srsrc, SCSrc_32:$soffset,
2393 mbuf_offset:$offset, glc:$glc, slc:$slc, tfe:$tfe),
2394 name#" $vdata, $srsrc, $soffset"#"$offset"#"$glc"#"$slc"#"$tfe",
2395 [(st store_vt:$vdata, (MUBUFOffset v4i32:$srsrc, i32:$soffset,
2396 i16:$offset, i1:$glc, i1:$slc, i1:$tfe))]>;
2397 } // offen = 0, idxen = 0, vaddr = 0
2399 let offen = 1, idxen = 0 in {
2400 defm _OFFEN : MUBUF_m <op, name#"_offen", (outs),
2401 (ins vdataClass:$vdata, VGPR_32:$vaddr, SReg_128:$srsrc,
2402 SCSrc_32:$soffset, mbuf_offset:$offset, glc:$glc,
2403 slc:$slc, tfe:$tfe),
2404 name#" $vdata, $vaddr, $srsrc, $soffset offen"#"$offset"#
2405 "$glc"#"$slc"#"$tfe", []>;
2406 } // end offen = 1, idxen = 0
2408 let offen = 0, idxen = 1 in {
2409 defm _IDXEN : MUBUF_m <op, name#"_idxen", (outs),
2410 (ins vdataClass:$vdata, VGPR_32:$vaddr, SReg_128:$srsrc,
2411 SCSrc_32:$soffset, mbuf_offset:$offset, glc:$glc,
2412 slc:$slc, tfe:$tfe),
2413 name#" $vdata, $vaddr, $srsrc, $soffset idxen"#"$offset"#"$glc"#"$slc"#"$tfe", []>;
2416 let offen = 1, idxen = 1 in {
2417 defm _BOTHEN : MUBUF_m <op, name#"_bothen", (outs),
2418 (ins vdataClass:$vdata, VReg_64:$vaddr, SReg_128:$srsrc, SCSrc_32:$soffset,
2419 mbuf_offset:$offset, glc:$glc, slc:$slc, tfe:$tfe),
2420 name#" $vdata, $vaddr, $srsrc, $soffset idxen offen"#"$offset"#"$glc"#"$slc"#"$tfe", []>;
2423 let offen = 0, idxen = 0 in {
2424 defm _ADDR64 : MUBUFAddr64_m <op, name#"_addr64", (outs),
2425 (ins vdataClass:$vdata, VReg_64:$vaddr, SReg_128:$srsrc,
2427 mbuf_offset:$offset, glc:$glc, slc:$slc,
2429 name#" $vdata, $vaddr, $srsrc, $soffset addr64"#
2430 "$offset"#"$glc"#"$slc"#"$tfe",
2431 [(st store_vt:$vdata,
2432 (MUBUFAddr64 v4i32:$srsrc, i64:$vaddr,
2433 i32:$soffset, i16:$offset,
2434 i1:$glc, i1:$slc, i1:$tfe))]>;
2436 } // End mayLoad = 0, mayStore = 1
2439 class FLAT_Load_Helper <bits<7> op, string asm, RegisterClass regClass> :
2440 FLAT <op, (outs regClass:$vdst),
2441 (ins VReg_64:$addr, glc_flat:$glc, slc_flat:$slc, tfe_flat:$tfe),
2442 asm#" $vdst, $addr"#"$glc"#"$slc"#"$tfe", []> {
2447 class FLAT_Store_Helper <bits<7> op, string name, RegisterClass vdataClass> :
2448 FLAT <op, (outs), (ins vdataClass:$data, VReg_64:$addr,
2449 glc_flat:$glc, slc_flat:$slc, tfe_flat:$tfe),
2450 name#" $data, $addr"#"$glc"#"$slc"#"$tfe",
2460 multiclass FLAT_ATOMIC <bits<7> op, string name, RegisterClass vdst_rc,
2461 RegisterClass data_rc = vdst_rc> {
2463 let mayLoad = 1, mayStore = 1 in {
2464 def "" : FLAT <op, (outs),
2465 (ins VReg_64:$addr, data_rc:$data, slc_flat_atomic:$slc,
2466 tfe_flat_atomic:$tfe),
2467 name#" $addr, $data"#"$slc"#"$tfe", []>,
2468 AtomicNoRet <NAME, 0> {
2473 def _RTN : FLAT <op, (outs vdst_rc:$vdst),
2474 (ins VReg_64:$addr, data_rc:$data, slc_flat_atomic:$slc,
2475 tfe_flat_atomic:$tfe),
2476 name#" $vdst, $addr, $data glc"#"$slc"#"$tfe", []>,
2477 AtomicNoRet <NAME, 1> {
2483 class MIMG_Mask <string op, int channels> {
2485 int Channels = channels;
2488 class MIMG_NoSampler_Helper <bits<7> op, string asm,
2489 RegisterClass dst_rc,
2490 RegisterClass src_rc> : MIMG <
2492 (outs dst_rc:$vdata),
2493 (ins i32imm:$dmask, i1imm:$unorm, i1imm:$glc, i1imm:$da, i1imm:$r128,
2494 i1imm:$tfe, i1imm:$lwe, i1imm:$slc, src_rc:$vaddr,
2496 asm#" $vdata, $dmask, $unorm, $glc, $da, $r128,"
2497 #" $tfe, $lwe, $slc, $vaddr, $srsrc",
2502 let hasPostISelHook = 1;
2505 multiclass MIMG_NoSampler_Src_Helper <bits<7> op, string asm,
2506 RegisterClass dst_rc,
2508 def _V1 : MIMG_NoSampler_Helper <op, asm, dst_rc, VGPR_32>,
2509 MIMG_Mask<asm#"_V1", channels>;
2510 def _V2 : MIMG_NoSampler_Helper <op, asm, dst_rc, VReg_64>,
2511 MIMG_Mask<asm#"_V2", channels>;
2512 def _V4 : MIMG_NoSampler_Helper <op, asm, dst_rc, VReg_128>,
2513 MIMG_Mask<asm#"_V4", channels>;
2516 multiclass MIMG_NoSampler <bits<7> op, string asm> {
2517 defm _V1 : MIMG_NoSampler_Src_Helper <op, asm, VGPR_32, 1>;
2518 defm _V2 : MIMG_NoSampler_Src_Helper <op, asm, VReg_64, 2>;
2519 defm _V3 : MIMG_NoSampler_Src_Helper <op, asm, VReg_96, 3>;
2520 defm _V4 : MIMG_NoSampler_Src_Helper <op, asm, VReg_128, 4>;
2523 class MIMG_Sampler_Helper <bits<7> op, string asm,
2524 RegisterClass dst_rc,
2525 RegisterClass src_rc, int wqm> : MIMG <
2527 (outs dst_rc:$vdata),
2528 (ins i32imm:$dmask, i1imm:$unorm, i1imm:$glc, i1imm:$da, i1imm:$r128,
2529 i1imm:$tfe, i1imm:$lwe, i1imm:$slc, src_rc:$vaddr,
2530 SReg_256:$srsrc, SReg_128:$ssamp),
2531 asm#" $vdata, $dmask, $unorm, $glc, $da, $r128,"
2532 #" $tfe, $lwe, $slc, $vaddr, $srsrc, $ssamp",
2536 let hasPostISelHook = 1;
2540 multiclass MIMG_Sampler_Src_Helper <bits<7> op, string asm,
2541 RegisterClass dst_rc,
2542 int channels, int wqm> {
2543 def _V1 : MIMG_Sampler_Helper <op, asm, dst_rc, VGPR_32, wqm>,
2544 MIMG_Mask<asm#"_V1", channels>;
2545 def _V2 : MIMG_Sampler_Helper <op, asm, dst_rc, VReg_64, wqm>,
2546 MIMG_Mask<asm#"_V2", channels>;
2547 def _V4 : MIMG_Sampler_Helper <op, asm, dst_rc, VReg_128, wqm>,
2548 MIMG_Mask<asm#"_V4", channels>;
2549 def _V8 : MIMG_Sampler_Helper <op, asm, dst_rc, VReg_256, wqm>,
2550 MIMG_Mask<asm#"_V8", channels>;
2551 def _V16 : MIMG_Sampler_Helper <op, asm, dst_rc, VReg_512, wqm>,
2552 MIMG_Mask<asm#"_V16", channels>;
2555 multiclass MIMG_Sampler <bits<7> op, string asm> {
2556 defm _V1 : MIMG_Sampler_Src_Helper<op, asm, VGPR_32, 1, 0>;
2557 defm _V2 : MIMG_Sampler_Src_Helper<op, asm, VReg_64, 2, 0>;
2558 defm _V3 : MIMG_Sampler_Src_Helper<op, asm, VReg_96, 3, 0>;
2559 defm _V4 : MIMG_Sampler_Src_Helper<op, asm, VReg_128, 4, 0>;
2562 multiclass MIMG_Sampler_WQM <bits<7> op, string asm> {
2563 defm _V1 : MIMG_Sampler_Src_Helper<op, asm, VGPR_32, 1, 1>;
2564 defm _V2 : MIMG_Sampler_Src_Helper<op, asm, VReg_64, 2, 1>;
2565 defm _V3 : MIMG_Sampler_Src_Helper<op, asm, VReg_96, 3, 1>;
2566 defm _V4 : MIMG_Sampler_Src_Helper<op, asm, VReg_128, 4, 1>;
2569 class MIMG_Gather_Helper <bits<7> op, string asm,
2570 RegisterClass dst_rc,
2571 RegisterClass src_rc, int wqm> : MIMG <
2573 (outs dst_rc:$vdata),
2574 (ins i32imm:$dmask, i1imm:$unorm, i1imm:$glc, i1imm:$da, i1imm:$r128,
2575 i1imm:$tfe, i1imm:$lwe, i1imm:$slc, src_rc:$vaddr,
2576 SReg_256:$srsrc, SReg_128:$ssamp),
2577 asm#" $vdata, $dmask, $unorm, $glc, $da, $r128,"
2578 #" $tfe, $lwe, $slc, $vaddr, $srsrc, $ssamp",
2583 // DMASK was repurposed for GATHER4. 4 components are always
2584 // returned and DMASK works like a swizzle - it selects
2585 // the component to fetch. The only useful DMASK values are
2586 // 1=red, 2=green, 4=blue, 8=alpha. (e.g. 1 returns
2587 // (red,red,red,red) etc.) The ISA document doesn't mention
2589 // Therefore, disable all code which updates DMASK by setting these two:
2591 let hasPostISelHook = 0;
2595 multiclass MIMG_Gather_Src_Helper <bits<7> op, string asm,
2596 RegisterClass dst_rc,
2597 int channels, int wqm> {
2598 def _V1 : MIMG_Gather_Helper <op, asm, dst_rc, VGPR_32, wqm>,
2599 MIMG_Mask<asm#"_V1", channels>;
2600 def _V2 : MIMG_Gather_Helper <op, asm, dst_rc, VReg_64, wqm>,
2601 MIMG_Mask<asm#"_V2", channels>;
2602 def _V4 : MIMG_Gather_Helper <op, asm, dst_rc, VReg_128, wqm>,
2603 MIMG_Mask<asm#"_V4", channels>;
2604 def _V8 : MIMG_Gather_Helper <op, asm, dst_rc, VReg_256, wqm>,
2605 MIMG_Mask<asm#"_V8", channels>;
2606 def _V16 : MIMG_Gather_Helper <op, asm, dst_rc, VReg_512, wqm>,
2607 MIMG_Mask<asm#"_V16", channels>;
2610 multiclass MIMG_Gather <bits<7> op, string asm> {
2611 defm _V1 : MIMG_Gather_Src_Helper<op, asm, VGPR_32, 1, 0>;
2612 defm _V2 : MIMG_Gather_Src_Helper<op, asm, VReg_64, 2, 0>;
2613 defm _V3 : MIMG_Gather_Src_Helper<op, asm, VReg_96, 3, 0>;
2614 defm _V4 : MIMG_Gather_Src_Helper<op, asm, VReg_128, 4, 0>;
2617 multiclass MIMG_Gather_WQM <bits<7> op, string asm> {
2618 defm _V1 : MIMG_Gather_Src_Helper<op, asm, VGPR_32, 1, 1>;
2619 defm _V2 : MIMG_Gather_Src_Helper<op, asm, VReg_64, 2, 1>;
2620 defm _V3 : MIMG_Gather_Src_Helper<op, asm, VReg_96, 3, 1>;
2621 defm _V4 : MIMG_Gather_Src_Helper<op, asm, VReg_128, 4, 1>;
2624 //===----------------------------------------------------------------------===//
2625 // Vector instruction mappings
2626 //===----------------------------------------------------------------------===//
2628 // Maps an opcode in e32 form to its e64 equivalent
2629 def getVOPe64 : InstrMapping {
2630 let FilterClass = "VOP";
2631 let RowFields = ["OpName"];
2632 let ColFields = ["Size"];
2634 let ValueCols = [["8"]];
2637 // Maps an opcode in e64 form to its e32 equivalent
2638 def getVOPe32 : InstrMapping {
2639 let FilterClass = "VOP";
2640 let RowFields = ["OpName"];
2641 let ColFields = ["Size"];
2643 let ValueCols = [["4"]];
2646 def getMaskedMIMGOp : InstrMapping {
2647 let FilterClass = "MIMG_Mask";
2648 let RowFields = ["Op"];
2649 let ColFields = ["Channels"];
2651 let ValueCols = [["1"], ["2"], ["3"] ];
2654 // Maps an commuted opcode to its original version
2655 def getCommuteOrig : InstrMapping {
2656 let FilterClass = "VOP2_REV";
2657 let RowFields = ["RevOp"];
2658 let ColFields = ["IsOrig"];
2660 let ValueCols = [["1"]];
2663 // Maps an original opcode to its commuted version
2664 def getCommuteRev : InstrMapping {
2665 let FilterClass = "VOP2_REV";
2666 let RowFields = ["RevOp"];
2667 let ColFields = ["IsOrig"];
2669 let ValueCols = [["0"]];
2672 def getCommuteCmpOrig : InstrMapping {
2673 let FilterClass = "VOP2_REV";
2674 let RowFields = ["RevOp"];
2675 let ColFields = ["IsOrig"];
2677 let ValueCols = [["1"]];
2680 // Maps an original opcode to its commuted version
2681 def getCommuteCmpRev : InstrMapping {
2682 let FilterClass = "VOP2_REV";
2683 let RowFields = ["RevOp"];
2684 let ColFields = ["IsOrig"];
2686 let ValueCols = [["0"]];
2690 def getMCOpcodeGen : InstrMapping {
2691 let FilterClass = "SIMCInstr";
2692 let RowFields = ["PseudoInstr"];
2693 let ColFields = ["Subtarget"];
2694 let KeyCol = [!cast<string>(SISubtarget.NONE)];
2695 let ValueCols = [[!cast<string>(SISubtarget.SI)],[!cast<string>(SISubtarget.VI)]];
2698 def getAddr64Inst : InstrMapping {
2699 let FilterClass = "MUBUFAddr64Table";
2700 let RowFields = ["OpName"];
2701 let ColFields = ["IsAddr64"];
2703 let ValueCols = [["1"]];
2706 // Maps an atomic opcode to its version with a return value.
2707 def getAtomicRetOp : InstrMapping {
2708 let FilterClass = "AtomicNoRet";
2709 let RowFields = ["NoRetOp"];
2710 let ColFields = ["IsRet"];
2712 let ValueCols = [["1"]];
2715 // Maps an atomic opcode to its returnless version.
2716 def getAtomicNoRetOp : InstrMapping {
2717 let FilterClass = "AtomicNoRet";
2718 let RowFields = ["NoRetOp"];
2719 let ColFields = ["IsRet"];
2721 let ValueCols = [["0"]];
2724 include "SIInstructions.td"
2725 include "CIInstructions.td"
2726 include "VIInstructions.td"