1 //===-- SIInstrInfo.h - SI Instruction Info Interface -----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// \brief Interface definition for SIInstrInfo.
13 //===----------------------------------------------------------------------===//
16 #ifndef LLVM_LIB_TARGET_R600_SIINSTRINFO_H
17 #define LLVM_LIB_TARGET_R600_SIINSTRINFO_H
19 #include "AMDGPUInstrInfo.h"
20 #include "SIDefines.h"
21 #include "SIRegisterInfo.h"
25 class SIInstrInfo : public AMDGPUInstrInfo {
27 const SIRegisterInfo RI;
29 unsigned buildExtractSubReg(MachineBasicBlock::iterator MI,
30 MachineRegisterInfo &MRI,
31 MachineOperand &SuperReg,
32 const TargetRegisterClass *SuperRC,
34 const TargetRegisterClass *SubRC) const;
35 MachineOperand buildExtractSubRegOrImm(MachineBasicBlock::iterator MI,
36 MachineRegisterInfo &MRI,
37 MachineOperand &SuperReg,
38 const TargetRegisterClass *SuperRC,
40 const TargetRegisterClass *SubRC) const;
42 void swapOperands(MachineBasicBlock::iterator Inst) const;
44 void splitScalar64BitUnaryOp(SmallVectorImpl<MachineInstr *> &Worklist,
45 MachineInstr *Inst, unsigned Opcode) const;
47 void splitScalar64BitBinaryOp(SmallVectorImpl<MachineInstr *> &Worklist,
48 MachineInstr *Inst, unsigned Opcode) const;
50 void splitScalar64BitBCNT(SmallVectorImpl<MachineInstr *> &Worklist,
51 MachineInstr *Inst) const;
52 void splitScalar64BitBFE(SmallVectorImpl<MachineInstr *> &Worklist,
53 MachineInstr *Inst) const;
55 void addUsersToMoveToVALUWorklist(
56 unsigned Reg, MachineRegisterInfo &MRI,
57 SmallVectorImpl<MachineInstr *> &Worklist) const;
59 const TargetRegisterClass *
60 getDestEquivalentVGPRClass(const MachineInstr &Inst) const;
62 bool checkInstOffsetsDoNotOverlap(MachineInstr *MIa,
63 MachineInstr *MIb) const;
65 unsigned findUsedSGPR(const MachineInstr *MI, int OpIndices[3]) const;
68 MachineInstr *commuteInstructionImpl(MachineInstr *MI,
71 unsigned OpIdx1) const override;
74 explicit SIInstrInfo(const AMDGPUSubtarget &st);
76 const SIRegisterInfo &getRegisterInfo() const override {
80 bool isReallyTriviallyReMaterializable(const MachineInstr *MI,
81 AliasAnalysis *AA) const override;
83 bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2,
85 int64_t &Offset2) const override;
87 bool getMemOpBaseRegImmOfs(MachineInstr *LdSt, unsigned &BaseReg,
89 const TargetRegisterInfo *TRI) const final;
91 bool shouldClusterLoads(MachineInstr *FirstLdSt,
92 MachineInstr *SecondLdSt,
93 unsigned NumLoads) const final;
95 void copyPhysReg(MachineBasicBlock &MBB,
96 MachineBasicBlock::iterator MI, DebugLoc DL,
97 unsigned DestReg, unsigned SrcReg,
98 bool KillSrc) const override;
100 unsigned calculateLDSSpillAddress(MachineBasicBlock &MBB,
101 MachineBasicBlock::iterator MI,
105 unsigned Size) const;
107 void storeRegToStackSlot(MachineBasicBlock &MBB,
108 MachineBasicBlock::iterator MI,
109 unsigned SrcReg, bool isKill, int FrameIndex,
110 const TargetRegisterClass *RC,
111 const TargetRegisterInfo *TRI) const override;
113 void loadRegFromStackSlot(MachineBasicBlock &MBB,
114 MachineBasicBlock::iterator MI,
115 unsigned DestReg, int FrameIndex,
116 const TargetRegisterClass *RC,
117 const TargetRegisterInfo *TRI) const override;
119 bool expandPostRAPseudo(MachineBasicBlock::iterator MI) const override;
121 // \brief Returns an opcode that can be used to move a value to a \p DstRC
122 // register. If there is no hardware instruction that can store to \p
123 // DstRC, then AMDGPU::COPY is returned.
124 unsigned getMovOpcode(const TargetRegisterClass *DstRC) const;
127 int commuteOpcode(const MachineInstr &MI) const;
129 bool findCommutedOpIndices(MachineInstr *MI,
131 unsigned &SrcOpIdx2) const override;
133 bool areMemAccessesTriviallyDisjoint(
134 MachineInstr *MIa, MachineInstr *MIb,
135 AliasAnalysis *AA = nullptr) const override;
137 MachineInstr *buildMovInstr(MachineBasicBlock *MBB,
138 MachineBasicBlock::iterator I,
139 unsigned DstReg, unsigned SrcReg) const override;
140 bool isMov(unsigned Opcode) const override;
142 bool FoldImmediate(MachineInstr *UseMI, MachineInstr *DefMI,
143 unsigned Reg, MachineRegisterInfo *MRI) const final;
145 unsigned getMachineCSELookAheadLimit() const override { return 500; }
147 MachineInstr *convertToThreeAddress(MachineFunction::iterator &MBB,
148 MachineBasicBlock::iterator &MI,
149 LiveVariables *LV) const override;
151 bool isSALU(uint16_t Opcode) const {
152 return get(Opcode).TSFlags & SIInstrFlags::SALU;
155 bool isVALU(uint16_t Opcode) const {
156 return get(Opcode).TSFlags & SIInstrFlags::VALU;
159 bool isSOP1(uint16_t Opcode) const {
160 return get(Opcode).TSFlags & SIInstrFlags::SOP1;
163 bool isSOP2(uint16_t Opcode) const {
164 return get(Opcode).TSFlags & SIInstrFlags::SOP2;
167 bool isSOPC(uint16_t Opcode) const {
168 return get(Opcode).TSFlags & SIInstrFlags::SOPC;
171 bool isSOPK(uint16_t Opcode) const {
172 return get(Opcode).TSFlags & SIInstrFlags::SOPK;
175 bool isSOPP(uint16_t Opcode) const {
176 return get(Opcode).TSFlags & SIInstrFlags::SOPP;
179 bool isVOP1(uint16_t Opcode) const {
180 return get(Opcode).TSFlags & SIInstrFlags::VOP1;
183 bool isVOP2(uint16_t Opcode) const {
184 return get(Opcode).TSFlags & SIInstrFlags::VOP2;
187 bool isVOP3(uint16_t Opcode) const {
188 return get(Opcode).TSFlags & SIInstrFlags::VOP3;
191 bool isVOPC(uint16_t Opcode) const {
192 return get(Opcode).TSFlags & SIInstrFlags::VOPC;
195 bool isMUBUF(uint16_t Opcode) const {
196 return get(Opcode).TSFlags & SIInstrFlags::MUBUF;
199 bool isMTBUF(uint16_t Opcode) const {
200 return get(Opcode).TSFlags & SIInstrFlags::MTBUF;
203 bool isSMRD(uint16_t Opcode) const {
204 return get(Opcode).TSFlags & SIInstrFlags::SMRD;
207 bool isDS(uint16_t Opcode) const {
208 return get(Opcode).TSFlags & SIInstrFlags::DS;
211 bool isMIMG(uint16_t Opcode) const {
212 return get(Opcode).TSFlags & SIInstrFlags::MIMG;
215 bool isFLAT(uint16_t Opcode) const {
216 return get(Opcode).TSFlags & SIInstrFlags::FLAT;
219 bool isWQM(uint16_t Opcode) const {
220 return get(Opcode).TSFlags & SIInstrFlags::WQM;
223 bool isVGPRSpill(uint16_t Opcode) const {
224 return get(Opcode).TSFlags & SIInstrFlags::VGPRSpill;
227 bool isInlineConstant(const APInt &Imm) const;
228 bool isInlineConstant(const MachineOperand &MO, unsigned OpSize) const;
229 bool isLiteralConstant(const MachineOperand &MO, unsigned OpSize) const;
231 bool isImmOperandLegal(const MachineInstr *MI, unsigned OpNo,
232 const MachineOperand &MO) const;
234 /// \brief Return true if this 64-bit VALU instruction has a 32-bit encoding.
235 /// This function will return false if you pass it a 32-bit instruction.
236 bool hasVALU32BitEncoding(unsigned Opcode) const;
238 /// \brief Returns true if this operand uses the constant bus.
239 bool usesConstantBus(const MachineRegisterInfo &MRI,
240 const MachineOperand &MO,
241 unsigned OpSize) const;
243 /// \brief Return true if this instruction has any modifiers.
244 /// e.g. src[012]_mod, omod, clamp.
245 bool hasModifiers(unsigned Opcode) const;
247 bool hasModifiersSet(const MachineInstr &MI,
248 unsigned OpName) const;
250 bool verifyInstruction(const MachineInstr *MI,
251 StringRef &ErrInfo) const override;
253 static unsigned getVALUOp(const MachineInstr &MI);
255 bool isSALUOpSupportedOnVALU(const MachineInstr &MI) const;
257 /// \brief Return the correct register class for \p OpNo. For target-specific
258 /// instructions, this will return the register class that has been defined
259 /// in tablegen. For generic instructions, like REG_SEQUENCE it will return
260 /// the register class of its machine operand.
261 /// to infer the correct register class base on the other operands.
262 const TargetRegisterClass *getOpRegClass(const MachineInstr &MI,
263 unsigned OpNo) const;
265 /// \brief Return the size in bytes of the operand OpNo on the given
266 // instruction opcode.
267 unsigned getOpSize(uint16_t Opcode, unsigned OpNo) const {
268 const MCOperandInfo &OpInfo = get(Opcode).OpInfo[OpNo];
270 if (OpInfo.RegClass == -1) {
271 // If this is an immediate operand, this must be a 32-bit literal.
272 assert(OpInfo.OperandType == MCOI::OPERAND_IMMEDIATE);
276 return RI.getRegClass(OpInfo.RegClass)->getSize();
279 /// \brief This form should usually be preferred since it handles operands
280 /// with unknown register classes.
281 unsigned getOpSize(const MachineInstr &MI, unsigned OpNo) const {
282 return getOpRegClass(MI, OpNo)->getSize();
285 /// \returns true if it is legal for the operand at index \p OpNo
287 bool canReadVGPR(const MachineInstr &MI, unsigned OpNo) const;
289 /// \brief Legalize the \p OpIndex operand of this instruction by inserting
290 /// a MOV. For example:
291 /// ADD_I32_e32 VGPR0, 15
294 /// ADD_I32_e32 VGPR0, VGPR1
296 /// If the operand being legalized is a register, then a COPY will be used
298 void legalizeOpWithMove(MachineInstr *MI, unsigned OpIdx) const;
300 /// \brief Check if \p MO is a legal operand if it was the \p OpIdx Operand
302 bool isOperandLegal(const MachineInstr *MI, unsigned OpIdx,
303 const MachineOperand *MO = nullptr) const;
305 /// \brief Legalize all operands in this instruction. This function may
306 /// create new instruction and insert them before \p MI.
307 void legalizeOperands(MachineInstr *MI) const;
309 /// \brief Split an SMRD instruction into two smaller loads of half the
310 // size storing the results in \p Lo and \p Hi.
311 void splitSMRD(MachineInstr *MI, const TargetRegisterClass *HalfRC,
312 unsigned HalfImmOp, unsigned HalfSGPROp,
313 MachineInstr *&Lo, MachineInstr *&Hi) const;
315 void moveSMRDToVALU(MachineInstr *MI, MachineRegisterInfo &MRI,
316 SmallVectorImpl<MachineInstr *> &Worklist) const;
318 /// \brief Replace this instruction's opcode with the equivalent VALU
319 /// opcode. This function will also move the users of \p MI to the
320 /// VALU if necessary.
321 void moveToVALU(MachineInstr &MI) const;
323 unsigned calculateIndirectAddress(unsigned RegIndex,
324 unsigned Channel) const override;
326 const TargetRegisterClass *getIndirectAddrRegClass() const override;
328 MachineInstrBuilder buildIndirectWrite(MachineBasicBlock *MBB,
329 MachineBasicBlock::iterator I,
332 unsigned OffsetReg) const override;
334 MachineInstrBuilder buildIndirectRead(MachineBasicBlock *MBB,
335 MachineBasicBlock::iterator I,
338 unsigned OffsetReg) const override;
339 void reserveIndirectRegisters(BitVector &Reserved,
340 const MachineFunction &MF) const;
342 void LoadM0(MachineInstr *MoveRel, MachineBasicBlock::iterator I,
343 unsigned SavReg, unsigned IndexReg) const;
345 void insertNOPs(MachineBasicBlock::iterator MI, int Count) const;
347 /// \brief Returns the operand named \p Op. If \p MI does not have an
348 /// operand named \c Op, this function returns nullptr.
350 MachineOperand *getNamedOperand(MachineInstr &MI, unsigned OperandName) const;
353 const MachineOperand *getNamedOperand(const MachineInstr &MI,
354 unsigned OpName) const {
355 return getNamedOperand(const_cast<MachineInstr &>(MI), OpName);
358 uint64_t getDefaultRsrcDataFormat() const;
364 int getVOPe64(uint16_t Opcode);
367 int getVOPe32(uint16_t Opcode);
370 int getCommuteRev(uint16_t Opcode);
373 int getCommuteOrig(uint16_t Opcode);
376 int getAddr64Inst(uint16_t Opcode);
379 int getAtomicRetOp(uint16_t Opcode);
382 int getAtomicNoRetOp(uint16_t Opcode);
384 const uint64_t RSRC_DATA_FORMAT = 0xf00000000000LL;
385 const uint64_t RSRC_TID_ENABLE = 1LL << 55;
387 } // End namespace AMDGPU
390 namespace KernelInputOffsets {
392 /// Offsets in bytes from the start of the input buffer
405 } // End namespace KernelInputOffsets
406 } // End namespace SI
408 } // End namespace llvm