1 //===-- SIInstrInfo.h - SI Instruction Info Interface -----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// \brief Interface definition for SIInstrInfo.
13 //===----------------------------------------------------------------------===//
16 #ifndef LLVM_LIB_TARGET_R600_SIINSTRINFO_H
17 #define LLVM_LIB_TARGET_R600_SIINSTRINFO_H
19 #include "AMDGPUInstrInfo.h"
20 #include "SIDefines.h"
21 #include "SIRegisterInfo.h"
25 class SIInstrInfo : public AMDGPUInstrInfo {
27 const SIRegisterInfo RI;
29 unsigned buildExtractSubReg(MachineBasicBlock::iterator MI,
30 MachineRegisterInfo &MRI,
31 MachineOperand &SuperReg,
32 const TargetRegisterClass *SuperRC,
34 const TargetRegisterClass *SubRC) const;
35 MachineOperand buildExtractSubRegOrImm(MachineBasicBlock::iterator MI,
36 MachineRegisterInfo &MRI,
37 MachineOperand &SuperReg,
38 const TargetRegisterClass *SuperRC,
40 const TargetRegisterClass *SubRC) const;
42 void swapOperands(MachineBasicBlock::iterator Inst) const;
44 void splitScalar64BitUnaryOp(SmallVectorImpl<MachineInstr *> &Worklist,
45 MachineInstr *Inst, unsigned Opcode) const;
47 void splitScalar64BitBinaryOp(SmallVectorImpl<MachineInstr *> &Worklist,
48 MachineInstr *Inst, unsigned Opcode) const;
50 void splitScalar64BitBCNT(SmallVectorImpl<MachineInstr *> &Worklist,
51 MachineInstr *Inst) const;
52 void splitScalar64BitBFE(SmallVectorImpl<MachineInstr *> &Worklist,
53 MachineInstr *Inst) const;
55 void addUsersToMoveToVALUWorklist(
56 unsigned Reg, MachineRegisterInfo &MRI,
57 SmallVectorImpl<MachineInstr *> &Worklist) const;
59 bool checkInstOffsetsDoNotOverlap(MachineInstr *MIa,
60 MachineInstr *MIb) const;
62 unsigned findUsedSGPR(const MachineInstr *MI, int OpIndices[3]) const;
65 MachineInstr *commuteInstructionImpl(MachineInstr *MI,
68 unsigned OpIdx1) const override;
71 explicit SIInstrInfo(const AMDGPUSubtarget &st);
73 const SIRegisterInfo &getRegisterInfo() const override {
77 bool isReallyTriviallyReMaterializable(const MachineInstr *MI,
78 AliasAnalysis *AA) const override;
80 bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2,
82 int64_t &Offset2) const override;
84 bool getMemOpBaseRegImmOfs(MachineInstr *LdSt, unsigned &BaseReg,
86 const TargetRegisterInfo *TRI) const final;
88 bool shouldClusterLoads(MachineInstr *FirstLdSt,
89 MachineInstr *SecondLdSt,
90 unsigned NumLoads) const final;
92 void copyPhysReg(MachineBasicBlock &MBB,
93 MachineBasicBlock::iterator MI, DebugLoc DL,
94 unsigned DestReg, unsigned SrcReg,
95 bool KillSrc) const override;
97 unsigned calculateLDSSpillAddress(MachineBasicBlock &MBB,
98 MachineBasicBlock::iterator MI,
102 unsigned Size) const;
104 void storeRegToStackSlot(MachineBasicBlock &MBB,
105 MachineBasicBlock::iterator MI,
106 unsigned SrcReg, bool isKill, int FrameIndex,
107 const TargetRegisterClass *RC,
108 const TargetRegisterInfo *TRI) const override;
110 void loadRegFromStackSlot(MachineBasicBlock &MBB,
111 MachineBasicBlock::iterator MI,
112 unsigned DestReg, int FrameIndex,
113 const TargetRegisterClass *RC,
114 const TargetRegisterInfo *TRI) const override;
116 bool expandPostRAPseudo(MachineBasicBlock::iterator MI) const override;
118 // \brief Returns an opcode that can be used to move a value to a \p DstRC
119 // register. If there is no hardware instruction that can store to \p
120 // DstRC, then AMDGPU::COPY is returned.
121 unsigned getMovOpcode(const TargetRegisterClass *DstRC) const;
124 int commuteOpcode(const MachineInstr &MI) const;
126 bool findCommutedOpIndices(MachineInstr *MI,
128 unsigned &SrcOpIdx2) const override;
130 bool areMemAccessesTriviallyDisjoint(
131 MachineInstr *MIa, MachineInstr *MIb,
132 AliasAnalysis *AA = nullptr) const override;
134 MachineInstr *buildMovInstr(MachineBasicBlock *MBB,
135 MachineBasicBlock::iterator I,
136 unsigned DstReg, unsigned SrcReg) const override;
137 bool isMov(unsigned Opcode) const override;
139 bool FoldImmediate(MachineInstr *UseMI, MachineInstr *DefMI,
140 unsigned Reg, MachineRegisterInfo *MRI) const final;
142 unsigned getMachineCSELookAheadLimit() const override { return 500; }
144 MachineInstr *convertToThreeAddress(MachineFunction::iterator &MBB,
145 MachineBasicBlock::iterator &MI,
146 LiveVariables *LV) const override;
148 bool isSALU(uint16_t Opcode) const {
149 return get(Opcode).TSFlags & SIInstrFlags::SALU;
152 bool isVALU(uint16_t Opcode) const {
153 return get(Opcode).TSFlags & SIInstrFlags::VALU;
156 bool isSOP1(uint16_t Opcode) const {
157 return get(Opcode).TSFlags & SIInstrFlags::SOP1;
160 bool isSOP2(uint16_t Opcode) const {
161 return get(Opcode).TSFlags & SIInstrFlags::SOP2;
164 bool isSOPC(uint16_t Opcode) const {
165 return get(Opcode).TSFlags & SIInstrFlags::SOPC;
168 bool isSOPK(uint16_t Opcode) const {
169 return get(Opcode).TSFlags & SIInstrFlags::SOPK;
172 bool isSOPP(uint16_t Opcode) const {
173 return get(Opcode).TSFlags & SIInstrFlags::SOPP;
176 bool isVOP1(uint16_t Opcode) const {
177 return get(Opcode).TSFlags & SIInstrFlags::VOP1;
180 bool isVOP2(uint16_t Opcode) const {
181 return get(Opcode).TSFlags & SIInstrFlags::VOP2;
184 bool isVOP3(uint16_t Opcode) const {
185 return get(Opcode).TSFlags & SIInstrFlags::VOP3;
188 bool isVOPC(uint16_t Opcode) const {
189 return get(Opcode).TSFlags & SIInstrFlags::VOPC;
192 bool isMUBUF(uint16_t Opcode) const {
193 return get(Opcode).TSFlags & SIInstrFlags::MUBUF;
196 bool isMTBUF(uint16_t Opcode) const {
197 return get(Opcode).TSFlags & SIInstrFlags::MTBUF;
200 bool isSMRD(uint16_t Opcode) const {
201 return get(Opcode).TSFlags & SIInstrFlags::SMRD;
204 bool isDS(uint16_t Opcode) const {
205 return get(Opcode).TSFlags & SIInstrFlags::DS;
208 bool isMIMG(uint16_t Opcode) const {
209 return get(Opcode).TSFlags & SIInstrFlags::MIMG;
212 bool isFLAT(uint16_t Opcode) const {
213 return get(Opcode).TSFlags & SIInstrFlags::FLAT;
216 bool isWQM(uint16_t Opcode) const {
217 return get(Opcode).TSFlags & SIInstrFlags::WQM;
220 bool isVGPRSpill(uint16_t Opcode) const {
221 return get(Opcode).TSFlags & SIInstrFlags::VGPRSpill;
224 bool isInlineConstant(const APInt &Imm) const;
225 bool isInlineConstant(const MachineOperand &MO, unsigned OpSize) const;
226 bool isLiteralConstant(const MachineOperand &MO, unsigned OpSize) const;
228 bool isImmOperandLegal(const MachineInstr *MI, unsigned OpNo,
229 const MachineOperand &MO) const;
231 /// \brief Return true if this 64-bit VALU instruction has a 32-bit encoding.
232 /// This function will return false if you pass it a 32-bit instruction.
233 bool hasVALU32BitEncoding(unsigned Opcode) const;
235 /// \brief Returns true if this operand uses the constant bus.
236 bool usesConstantBus(const MachineRegisterInfo &MRI,
237 const MachineOperand &MO,
238 unsigned OpSize) const;
240 /// \brief Return true if this instruction has any modifiers.
241 /// e.g. src[012]_mod, omod, clamp.
242 bool hasModifiers(unsigned Opcode) const;
244 bool hasModifiersSet(const MachineInstr &MI,
245 unsigned OpName) const;
247 bool verifyInstruction(const MachineInstr *MI,
248 StringRef &ErrInfo) const override;
250 static unsigned getVALUOp(const MachineInstr &MI);
252 bool isSALUOpSupportedOnVALU(const MachineInstr &MI) const;
254 /// \brief Return the correct register class for \p OpNo. For target-specific
255 /// instructions, this will return the register class that has been defined
256 /// in tablegen. For generic instructions, like REG_SEQUENCE it will return
257 /// the register class of its machine operand.
258 /// to infer the correct register class base on the other operands.
259 const TargetRegisterClass *getOpRegClass(const MachineInstr &MI,
260 unsigned OpNo) const;
262 /// \brief Return the size in bytes of the operand OpNo on the given
263 // instruction opcode.
264 unsigned getOpSize(uint16_t Opcode, unsigned OpNo) const {
265 const MCOperandInfo &OpInfo = get(Opcode).OpInfo[OpNo];
267 if (OpInfo.RegClass == -1) {
268 // If this is an immediate operand, this must be a 32-bit literal.
269 assert(OpInfo.OperandType == MCOI::OPERAND_IMMEDIATE);
273 return RI.getRegClass(OpInfo.RegClass)->getSize();
276 /// \brief This form should usually be preferred since it handles operands
277 /// with unknown register classes.
278 unsigned getOpSize(const MachineInstr &MI, unsigned OpNo) const {
279 return getOpRegClass(MI, OpNo)->getSize();
282 /// \returns true if it is legal for the operand at index \p OpNo
284 bool canReadVGPR(const MachineInstr &MI, unsigned OpNo) const;
286 /// \brief Legalize the \p OpIndex operand of this instruction by inserting
287 /// a MOV. For example:
288 /// ADD_I32_e32 VGPR0, 15
291 /// ADD_I32_e32 VGPR0, VGPR1
293 /// If the operand being legalized is a register, then a COPY will be used
295 void legalizeOpWithMove(MachineInstr *MI, unsigned OpIdx) const;
297 /// \brief Check if \p MO is a legal operand if it was the \p OpIdx Operand
299 bool isOperandLegal(const MachineInstr *MI, unsigned OpIdx,
300 const MachineOperand *MO = nullptr) const;
302 /// \brief Legalize all operands in this instruction. This function may
303 /// create new instruction and insert them before \p MI.
304 void legalizeOperands(MachineInstr *MI) const;
306 /// \brief Split an SMRD instruction into two smaller loads of half the
307 // size storing the results in \p Lo and \p Hi.
308 void splitSMRD(MachineInstr *MI, const TargetRegisterClass *HalfRC,
309 unsigned HalfImmOp, unsigned HalfSGPROp,
310 MachineInstr *&Lo, MachineInstr *&Hi) const;
312 void moveSMRDToVALU(MachineInstr *MI, MachineRegisterInfo &MRI,
313 SmallVectorImpl<MachineInstr *> &Worklist) const;
315 /// \brief Replace this instruction's opcode with the equivalent VALU
316 /// opcode. This function will also move the users of \p MI to the
317 /// VALU if necessary.
318 void moveToVALU(MachineInstr &MI) const;
320 unsigned calculateIndirectAddress(unsigned RegIndex,
321 unsigned Channel) const override;
323 const TargetRegisterClass *getIndirectAddrRegClass() const override;
325 MachineInstrBuilder buildIndirectWrite(MachineBasicBlock *MBB,
326 MachineBasicBlock::iterator I,
329 unsigned OffsetReg) const override;
331 MachineInstrBuilder buildIndirectRead(MachineBasicBlock *MBB,
332 MachineBasicBlock::iterator I,
335 unsigned OffsetReg) const override;
336 void reserveIndirectRegisters(BitVector &Reserved,
337 const MachineFunction &MF) const;
339 void LoadM0(MachineInstr *MoveRel, MachineBasicBlock::iterator I,
340 unsigned SavReg, unsigned IndexReg) const;
342 void insertNOPs(MachineBasicBlock::iterator MI, int Count) const;
344 /// \brief Returns the operand named \p Op. If \p MI does not have an
345 /// operand named \c Op, this function returns nullptr.
347 MachineOperand *getNamedOperand(MachineInstr &MI, unsigned OperandName) const;
350 const MachineOperand *getNamedOperand(const MachineInstr &MI,
351 unsigned OpName) const {
352 return getNamedOperand(const_cast<MachineInstr &>(MI), OpName);
355 uint64_t getDefaultRsrcDataFormat() const;
361 int getVOPe64(uint16_t Opcode);
364 int getVOPe32(uint16_t Opcode);
367 int getCommuteRev(uint16_t Opcode);
370 int getCommuteOrig(uint16_t Opcode);
373 int getAddr64Inst(uint16_t Opcode);
376 int getAtomicRetOp(uint16_t Opcode);
379 int getAtomicNoRetOp(uint16_t Opcode);
381 const uint64_t RSRC_DATA_FORMAT = 0xf00000000000LL;
382 const uint64_t RSRC_TID_ENABLE = 1LL << 55;
384 } // End namespace AMDGPU
387 namespace KernelInputOffsets {
389 /// Offsets in bytes from the start of the input buffer
402 } // End namespace KernelInputOffsets
403 } // End namespace SI
405 } // End namespace llvm