1 //===-- SIInstrInfo.cpp - SI Instruction Information ---------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// \brief SI Implementation of TargetInstrInfo.
13 //===----------------------------------------------------------------------===//
16 #include "SIInstrInfo.h"
17 #include "AMDGPUTargetMachine.h"
18 #include "SIDefines.h"
19 #include "SIMachineFunctionInfo.h"
20 #include "llvm/CodeGen/MachineFrameInfo.h"
21 #include "llvm/CodeGen/MachineInstrBuilder.h"
22 #include "llvm/CodeGen/MachineRegisterInfo.h"
23 #include "llvm/IR/Function.h"
24 #include "llvm/CodeGen/RegisterScavenging.h"
25 #include "llvm/MC/MCInstrDesc.h"
26 #include "llvm/Support/Debug.h"
30 SIInstrInfo::SIInstrInfo(const AMDGPUSubtarget &st)
31 : AMDGPUInstrInfo(st), RI() {}
33 //===----------------------------------------------------------------------===//
34 // TargetInstrInfo callbacks
35 //===----------------------------------------------------------------------===//
37 static unsigned getNumOperandsNoGlue(SDNode *Node) {
38 unsigned N = Node->getNumOperands();
39 while (N && Node->getOperand(N - 1).getValueType() == MVT::Glue)
44 static SDValue findChainOperand(SDNode *Load) {
45 SDValue LastOp = Load->getOperand(getNumOperandsNoGlue(Load) - 1);
46 assert(LastOp.getValueType() == MVT::Other && "Chain missing from load node");
50 /// \brief Returns true if both nodes have the same value for the given
51 /// operand \p Op, or if both nodes do not have this operand.
52 static bool nodesHaveSameOperandValue(SDNode *N0, SDNode* N1, unsigned OpName) {
53 unsigned Opc0 = N0->getMachineOpcode();
54 unsigned Opc1 = N1->getMachineOpcode();
56 int Op0Idx = AMDGPU::getNamedOperandIdx(Opc0, OpName);
57 int Op1Idx = AMDGPU::getNamedOperandIdx(Opc1, OpName);
59 if (Op0Idx == -1 && Op1Idx == -1)
63 if ((Op0Idx == -1 && Op1Idx != -1) ||
64 (Op1Idx == -1 && Op0Idx != -1))
67 // getNamedOperandIdx returns the index for the MachineInstr's operands,
68 // which includes the result as the first operand. We are indexing into the
69 // MachineSDNode's operands, so we need to skip the result operand to get
74 return N0->getOperand(Op0Idx) == N1->getOperand(Op1Idx);
77 bool SIInstrInfo::isReallyTriviallyReMaterializable(const MachineInstr *MI,
78 AliasAnalysis *AA) const {
79 // TODO: The generic check fails for VALU instructions that should be
80 // rematerializable due to implicit reads of exec. We really want all of the
81 // generic logic for this except for this.
82 switch (MI->getOpcode()) {
83 case AMDGPU::V_MOV_B32_e32:
84 case AMDGPU::V_MOV_B32_e64:
85 case AMDGPU::V_MOV_B64_PSEUDO:
92 bool SIInstrInfo::areLoadsFromSameBasePtr(SDNode *Load0, SDNode *Load1,
94 int64_t &Offset1) const {
95 if (!Load0->isMachineOpcode() || !Load1->isMachineOpcode())
98 unsigned Opc0 = Load0->getMachineOpcode();
99 unsigned Opc1 = Load1->getMachineOpcode();
101 // Make sure both are actually loads.
102 if (!get(Opc0).mayLoad() || !get(Opc1).mayLoad())
105 if (isDS(Opc0) && isDS(Opc1)) {
107 // FIXME: Handle this case:
108 if (getNumOperandsNoGlue(Load0) != getNumOperandsNoGlue(Load1))
112 if (Load0->getOperand(1) != Load1->getOperand(1))
116 if (findChainOperand(Load0) != findChainOperand(Load1))
119 // Skip read2 / write2 variants for simplicity.
120 // TODO: We should report true if the used offsets are adjacent (excluded
122 if (AMDGPU::getNamedOperandIdx(Opc0, AMDGPU::OpName::data1) != -1 ||
123 AMDGPU::getNamedOperandIdx(Opc1, AMDGPU::OpName::data1) != -1)
126 Offset0 = cast<ConstantSDNode>(Load0->getOperand(2))->getZExtValue();
127 Offset1 = cast<ConstantSDNode>(Load1->getOperand(2))->getZExtValue();
131 if (isSMRD(Opc0) && isSMRD(Opc1)) {
132 assert(getNumOperandsNoGlue(Load0) == getNumOperandsNoGlue(Load1));
135 if (Load0->getOperand(0) != Load1->getOperand(0))
138 const ConstantSDNode *Load0Offset =
139 dyn_cast<ConstantSDNode>(Load0->getOperand(1));
140 const ConstantSDNode *Load1Offset =
141 dyn_cast<ConstantSDNode>(Load1->getOperand(1));
143 if (!Load0Offset || !Load1Offset)
147 if (findChainOperand(Load0) != findChainOperand(Load1))
150 Offset0 = Load0Offset->getZExtValue();
151 Offset1 = Load1Offset->getZExtValue();
155 // MUBUF and MTBUF can access the same addresses.
156 if ((isMUBUF(Opc0) || isMTBUF(Opc0)) && (isMUBUF(Opc1) || isMTBUF(Opc1))) {
158 // MUBUF and MTBUF have vaddr at different indices.
159 if (!nodesHaveSameOperandValue(Load0, Load1, AMDGPU::OpName::soffset) ||
160 findChainOperand(Load0) != findChainOperand(Load1) ||
161 !nodesHaveSameOperandValue(Load0, Load1, AMDGPU::OpName::vaddr) ||
162 !nodesHaveSameOperandValue(Load0, Load1, AMDGPU::OpName::srsrc))
165 int OffIdx0 = AMDGPU::getNamedOperandIdx(Opc0, AMDGPU::OpName::offset);
166 int OffIdx1 = AMDGPU::getNamedOperandIdx(Opc1, AMDGPU::OpName::offset);
168 if (OffIdx0 == -1 || OffIdx1 == -1)
171 // getNamedOperandIdx returns the index for MachineInstrs. Since they
172 // inlcude the output in the operand list, but SDNodes don't, we need to
173 // subtract the index by one.
177 SDValue Off0 = Load0->getOperand(OffIdx0);
178 SDValue Off1 = Load1->getOperand(OffIdx1);
180 // The offset might be a FrameIndexSDNode.
181 if (!isa<ConstantSDNode>(Off0) || !isa<ConstantSDNode>(Off1))
184 Offset0 = cast<ConstantSDNode>(Off0)->getZExtValue();
185 Offset1 = cast<ConstantSDNode>(Off1)->getZExtValue();
192 static bool isStride64(unsigned Opc) {
194 case AMDGPU::DS_READ2ST64_B32:
195 case AMDGPU::DS_READ2ST64_B64:
196 case AMDGPU::DS_WRITE2ST64_B32:
197 case AMDGPU::DS_WRITE2ST64_B64:
204 bool SIInstrInfo::getMemOpBaseRegImmOfs(MachineInstr *LdSt, unsigned &BaseReg,
206 const TargetRegisterInfo *TRI) const {
207 unsigned Opc = LdSt->getOpcode();
209 const MachineOperand *OffsetImm = getNamedOperand(*LdSt,
210 AMDGPU::OpName::offset);
212 // Normal, single offset LDS instruction.
213 const MachineOperand *AddrReg = getNamedOperand(*LdSt,
214 AMDGPU::OpName::addr);
216 BaseReg = AddrReg->getReg();
217 Offset = OffsetImm->getImm();
221 // The 2 offset instructions use offset0 and offset1 instead. We can treat
222 // these as a load with a single offset if the 2 offsets are consecutive. We
223 // will use this for some partially aligned loads.
224 const MachineOperand *Offset0Imm = getNamedOperand(*LdSt,
225 AMDGPU::OpName::offset0);
226 const MachineOperand *Offset1Imm = getNamedOperand(*LdSt,
227 AMDGPU::OpName::offset1);
229 uint8_t Offset0 = Offset0Imm->getImm();
230 uint8_t Offset1 = Offset1Imm->getImm();
232 if (Offset1 > Offset0 && Offset1 - Offset0 == 1) {
233 // Each of these offsets is in element sized units, so we need to convert
234 // to bytes of the individual reads.
238 EltSize = getOpRegClass(*LdSt, 0)->getSize() / 2;
240 assert(LdSt->mayStore());
241 int Data0Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::data0);
242 EltSize = getOpRegClass(*LdSt, Data0Idx)->getSize();
248 const MachineOperand *AddrReg = getNamedOperand(*LdSt,
249 AMDGPU::OpName::addr);
250 BaseReg = AddrReg->getReg();
251 Offset = EltSize * Offset0;
258 if (isMUBUF(Opc) || isMTBUF(Opc)) {
259 if (AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::soffset) != -1)
262 const MachineOperand *AddrReg = getNamedOperand(*LdSt,
263 AMDGPU::OpName::vaddr);
267 const MachineOperand *OffsetImm = getNamedOperand(*LdSt,
268 AMDGPU::OpName::offset);
269 BaseReg = AddrReg->getReg();
270 Offset = OffsetImm->getImm();
275 const MachineOperand *OffsetImm = getNamedOperand(*LdSt,
276 AMDGPU::OpName::offset);
280 const MachineOperand *SBaseReg = getNamedOperand(*LdSt,
281 AMDGPU::OpName::sbase);
282 BaseReg = SBaseReg->getReg();
283 Offset = OffsetImm->getImm();
290 bool SIInstrInfo::shouldClusterLoads(MachineInstr *FirstLdSt,
291 MachineInstr *SecondLdSt,
292 unsigned NumLoads) const {
293 unsigned Opc0 = FirstLdSt->getOpcode();
294 unsigned Opc1 = SecondLdSt->getOpcode();
296 // TODO: This needs finer tuning
300 if (isDS(Opc0) && isDS(Opc1))
303 if (isSMRD(Opc0) && isSMRD(Opc1))
306 if ((isMUBUF(Opc0) || isMTBUF(Opc0)) && (isMUBUF(Opc1) || isMTBUF(Opc1)))
313 SIInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
314 MachineBasicBlock::iterator MI, DebugLoc DL,
315 unsigned DestReg, unsigned SrcReg,
316 bool KillSrc) const {
318 // If we are trying to copy to or from SCC, there is a bug somewhere else in
319 // the backend. While it may be theoretically possible to do this, it should
320 // never be necessary.
321 assert(DestReg != AMDGPU::SCC && SrcReg != AMDGPU::SCC);
323 static const int16_t Sub0_15[] = {
324 AMDGPU::sub0, AMDGPU::sub1, AMDGPU::sub2, AMDGPU::sub3,
325 AMDGPU::sub4, AMDGPU::sub5, AMDGPU::sub6, AMDGPU::sub7,
326 AMDGPU::sub8, AMDGPU::sub9, AMDGPU::sub10, AMDGPU::sub11,
327 AMDGPU::sub12, AMDGPU::sub13, AMDGPU::sub14, AMDGPU::sub15, 0
330 static const int16_t Sub0_7[] = {
331 AMDGPU::sub0, AMDGPU::sub1, AMDGPU::sub2, AMDGPU::sub3,
332 AMDGPU::sub4, AMDGPU::sub5, AMDGPU::sub6, AMDGPU::sub7, 0
335 static const int16_t Sub0_3[] = {
336 AMDGPU::sub0, AMDGPU::sub1, AMDGPU::sub2, AMDGPU::sub3, 0
339 static const int16_t Sub0_2[] = {
340 AMDGPU::sub0, AMDGPU::sub1, AMDGPU::sub2, 0
343 static const int16_t Sub0_1[] = {
344 AMDGPU::sub0, AMDGPU::sub1, 0
348 const int16_t *SubIndices;
350 if (AMDGPU::SReg_32RegClass.contains(DestReg)) {
351 assert(AMDGPU::SReg_32RegClass.contains(SrcReg));
352 BuildMI(MBB, MI, DL, get(AMDGPU::S_MOV_B32), DestReg)
353 .addReg(SrcReg, getKillRegState(KillSrc));
356 } else if (AMDGPU::SReg_64RegClass.contains(DestReg)) {
357 if (DestReg == AMDGPU::VCC) {
358 if (AMDGPU::SReg_64RegClass.contains(SrcReg)) {
359 BuildMI(MBB, MI, DL, get(AMDGPU::S_MOV_B64), AMDGPU::VCC)
360 .addReg(SrcReg, getKillRegState(KillSrc));
362 // FIXME: Hack until VReg_1 removed.
363 assert(AMDGPU::VGPR_32RegClass.contains(SrcReg));
364 BuildMI(MBB, MI, DL, get(AMDGPU::V_CMP_NE_I32_e32))
366 .addReg(SrcReg, getKillRegState(KillSrc));
372 assert(AMDGPU::SReg_64RegClass.contains(SrcReg));
373 BuildMI(MBB, MI, DL, get(AMDGPU::S_MOV_B64), DestReg)
374 .addReg(SrcReg, getKillRegState(KillSrc));
377 } else if (AMDGPU::SReg_128RegClass.contains(DestReg)) {
378 assert(AMDGPU::SReg_128RegClass.contains(SrcReg));
379 Opcode = AMDGPU::S_MOV_B32;
382 } else if (AMDGPU::SReg_256RegClass.contains(DestReg)) {
383 assert(AMDGPU::SReg_256RegClass.contains(SrcReg));
384 Opcode = AMDGPU::S_MOV_B32;
387 } else if (AMDGPU::SReg_512RegClass.contains(DestReg)) {
388 assert(AMDGPU::SReg_512RegClass.contains(SrcReg));
389 Opcode = AMDGPU::S_MOV_B32;
390 SubIndices = Sub0_15;
392 } else if (AMDGPU::VGPR_32RegClass.contains(DestReg)) {
393 assert(AMDGPU::VGPR_32RegClass.contains(SrcReg) ||
394 AMDGPU::SReg_32RegClass.contains(SrcReg));
395 BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), DestReg)
396 .addReg(SrcReg, getKillRegState(KillSrc));
399 } else if (AMDGPU::VReg_64RegClass.contains(DestReg)) {
400 assert(AMDGPU::VReg_64RegClass.contains(SrcReg) ||
401 AMDGPU::SReg_64RegClass.contains(SrcReg));
402 Opcode = AMDGPU::V_MOV_B32_e32;
405 } else if (AMDGPU::VReg_96RegClass.contains(DestReg)) {
406 assert(AMDGPU::VReg_96RegClass.contains(SrcReg));
407 Opcode = AMDGPU::V_MOV_B32_e32;
410 } else if (AMDGPU::VReg_128RegClass.contains(DestReg)) {
411 assert(AMDGPU::VReg_128RegClass.contains(SrcReg) ||
412 AMDGPU::SReg_128RegClass.contains(SrcReg));
413 Opcode = AMDGPU::V_MOV_B32_e32;
416 } else if (AMDGPU::VReg_256RegClass.contains(DestReg)) {
417 assert(AMDGPU::VReg_256RegClass.contains(SrcReg) ||
418 AMDGPU::SReg_256RegClass.contains(SrcReg));
419 Opcode = AMDGPU::V_MOV_B32_e32;
422 } else if (AMDGPU::VReg_512RegClass.contains(DestReg)) {
423 assert(AMDGPU::VReg_512RegClass.contains(SrcReg) ||
424 AMDGPU::SReg_512RegClass.contains(SrcReg));
425 Opcode = AMDGPU::V_MOV_B32_e32;
426 SubIndices = Sub0_15;
429 llvm_unreachable("Can't copy register!");
432 while (unsigned SubIdx = *SubIndices++) {
433 MachineInstrBuilder Builder = BuildMI(MBB, MI, DL,
434 get(Opcode), RI.getSubReg(DestReg, SubIdx));
436 Builder.addReg(RI.getSubReg(SrcReg, SubIdx), getKillRegState(KillSrc));
439 Builder.addReg(DestReg, RegState::Define | RegState::Implicit);
443 int SIInstrInfo::commuteOpcode(const MachineInstr &MI) const {
444 const unsigned Opcode = MI.getOpcode();
448 // Try to map original to commuted opcode
449 NewOpc = AMDGPU::getCommuteRev(Opcode);
451 // Check if the commuted (REV) opcode exists on the target.
452 return pseudoToMCOpcode(NewOpc) != -1 ? NewOpc : -1;
454 // Try to map commuted to original opcode
455 NewOpc = AMDGPU::getCommuteOrig(Opcode);
457 // Check if the original (non-REV) opcode exists on the target.
458 return pseudoToMCOpcode(NewOpc) != -1 ? NewOpc : -1;
463 unsigned SIInstrInfo::getMovOpcode(const TargetRegisterClass *DstRC) const {
465 if (DstRC->getSize() == 4) {
466 return RI.isSGPRClass(DstRC) ? AMDGPU::S_MOV_B32 : AMDGPU::V_MOV_B32_e32;
467 } else if (DstRC->getSize() == 8 && RI.isSGPRClass(DstRC)) {
468 return AMDGPU::S_MOV_B64;
469 } else if (DstRC->getSize() == 8 && !RI.isSGPRClass(DstRC)) {
470 return AMDGPU::V_MOV_B64_PSEUDO;
475 void SIInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
476 MachineBasicBlock::iterator MI,
477 unsigned SrcReg, bool isKill,
479 const TargetRegisterClass *RC,
480 const TargetRegisterInfo *TRI) const {
481 MachineFunction *MF = MBB.getParent();
482 SIMachineFunctionInfo *MFI = MF->getInfo<SIMachineFunctionInfo>();
483 MachineFrameInfo *FrameInfo = MF->getFrameInfo();
484 DebugLoc DL = MBB.findDebugLoc(MI);
487 if (RI.isSGPRClass(RC)) {
488 // We are only allowed to create one new instruction when spilling
489 // registers, so we need to use pseudo instruction for spilling
491 switch (RC->getSize() * 8) {
492 case 32: Opcode = AMDGPU::SI_SPILL_S32_SAVE; break;
493 case 64: Opcode = AMDGPU::SI_SPILL_S64_SAVE; break;
494 case 128: Opcode = AMDGPU::SI_SPILL_S128_SAVE; break;
495 case 256: Opcode = AMDGPU::SI_SPILL_S256_SAVE; break;
496 case 512: Opcode = AMDGPU::SI_SPILL_S512_SAVE; break;
498 } else if(RI.hasVGPRs(RC) && ST.isVGPRSpillingEnabled(MFI)) {
499 MFI->setHasSpilledVGPRs();
501 switch(RC->getSize() * 8) {
502 case 32: Opcode = AMDGPU::SI_SPILL_V32_SAVE; break;
503 case 64: Opcode = AMDGPU::SI_SPILL_V64_SAVE; break;
504 case 96: Opcode = AMDGPU::SI_SPILL_V96_SAVE; break;
505 case 128: Opcode = AMDGPU::SI_SPILL_V128_SAVE; break;
506 case 256: Opcode = AMDGPU::SI_SPILL_V256_SAVE; break;
507 case 512: Opcode = AMDGPU::SI_SPILL_V512_SAVE; break;
512 MachinePointerInfo PtrInfo
513 = MachinePointerInfo::getFixedStack(*MF, FrameIndex);
514 unsigned Size = FrameInfo->getObjectSize(FrameIndex);
515 unsigned Align = FrameInfo->getObjectAlignment(FrameIndex);
516 MachineMemOperand *MMO
517 = MF->getMachineMemOperand(PtrInfo, MachineMemOperand::MOStore,
520 FrameInfo->setObjectAlignment(FrameIndex, 4);
521 BuildMI(MBB, MI, DL, get(Opcode))
523 .addFrameIndex(FrameIndex)
524 // Place-holder registers, these will be filled in by
525 // SIPrepareScratchRegs.
526 .addReg(AMDGPU::SGPR0_SGPR1_SGPR2_SGPR3, RegState::Undef)
527 .addReg(AMDGPU::SGPR0, RegState::Undef)
530 LLVMContext &Ctx = MF->getFunction()->getContext();
531 Ctx.emitError("SIInstrInfo::storeRegToStackSlot - Do not know how to"
533 BuildMI(MBB, MI, DL, get(AMDGPU::KILL))
538 void SIInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
539 MachineBasicBlock::iterator MI,
540 unsigned DestReg, int FrameIndex,
541 const TargetRegisterClass *RC,
542 const TargetRegisterInfo *TRI) const {
543 MachineFunction *MF = MBB.getParent();
544 const SIMachineFunctionInfo *MFI = MF->getInfo<SIMachineFunctionInfo>();
545 MachineFrameInfo *FrameInfo = MF->getFrameInfo();
546 DebugLoc DL = MBB.findDebugLoc(MI);
549 if (RI.isSGPRClass(RC)){
550 switch(RC->getSize() * 8) {
551 case 32: Opcode = AMDGPU::SI_SPILL_S32_RESTORE; break;
552 case 64: Opcode = AMDGPU::SI_SPILL_S64_RESTORE; break;
553 case 128: Opcode = AMDGPU::SI_SPILL_S128_RESTORE; break;
554 case 256: Opcode = AMDGPU::SI_SPILL_S256_RESTORE; break;
555 case 512: Opcode = AMDGPU::SI_SPILL_S512_RESTORE; break;
557 } else if(RI.hasVGPRs(RC) && ST.isVGPRSpillingEnabled(MFI)) {
558 switch(RC->getSize() * 8) {
559 case 32: Opcode = AMDGPU::SI_SPILL_V32_RESTORE; break;
560 case 64: Opcode = AMDGPU::SI_SPILL_V64_RESTORE; break;
561 case 96: Opcode = AMDGPU::SI_SPILL_V96_RESTORE; break;
562 case 128: Opcode = AMDGPU::SI_SPILL_V128_RESTORE; break;
563 case 256: Opcode = AMDGPU::SI_SPILL_V256_RESTORE; break;
564 case 512: Opcode = AMDGPU::SI_SPILL_V512_RESTORE; break;
570 FrameInfo->setObjectAlignment(FrameIndex, Align);
571 unsigned Size = FrameInfo->getObjectSize(FrameIndex);
573 MachinePointerInfo PtrInfo
574 = MachinePointerInfo::getFixedStack(*MF, FrameIndex);
575 MachineMemOperand *MMO = MF->getMachineMemOperand(
576 PtrInfo, MachineMemOperand::MOLoad, Size, Align);
578 BuildMI(MBB, MI, DL, get(Opcode), DestReg)
579 .addFrameIndex(FrameIndex)
580 // Place-holder registers, these will be filled in by
581 // SIPrepareScratchRegs.
582 .addReg(AMDGPU::SGPR0_SGPR1_SGPR2_SGPR3, RegState::Undef)
583 .addReg(AMDGPU::SGPR0, RegState::Undef)
586 LLVMContext &Ctx = MF->getFunction()->getContext();
587 Ctx.emitError("SIInstrInfo::loadRegFromStackSlot - Do not know how to"
588 " restore register");
589 BuildMI(MBB, MI, DL, get(AMDGPU::IMPLICIT_DEF), DestReg);
593 /// \param @Offset Offset in bytes of the FrameIndex being spilled
594 unsigned SIInstrInfo::calculateLDSSpillAddress(MachineBasicBlock &MBB,
595 MachineBasicBlock::iterator MI,
596 RegScavenger *RS, unsigned TmpReg,
597 unsigned FrameOffset,
598 unsigned Size) const {
599 MachineFunction *MF = MBB.getParent();
600 SIMachineFunctionInfo *MFI = MF->getInfo<SIMachineFunctionInfo>();
601 const AMDGPUSubtarget &ST = MF->getSubtarget<AMDGPUSubtarget>();
602 const SIRegisterInfo *TRI =
603 static_cast<const SIRegisterInfo*>(ST.getRegisterInfo());
604 DebugLoc DL = MBB.findDebugLoc(MI);
605 unsigned WorkGroupSize = MFI->getMaximumWorkGroupSize(*MF);
606 unsigned WavefrontSize = ST.getWavefrontSize();
608 unsigned TIDReg = MFI->getTIDReg();
609 if (!MFI->hasCalculatedTID()) {
610 MachineBasicBlock &Entry = MBB.getParent()->front();
611 MachineBasicBlock::iterator Insert = Entry.front();
612 DebugLoc DL = Insert->getDebugLoc();
614 TIDReg = RI.findUnusedRegister(MF->getRegInfo(), &AMDGPU::VGPR_32RegClass);
615 if (TIDReg == AMDGPU::NoRegister)
619 if (MFI->getShaderType() == ShaderType::COMPUTE &&
620 WorkGroupSize > WavefrontSize) {
622 unsigned TIDIGXReg = TRI->getPreloadedValue(*MF, SIRegisterInfo::TIDIG_X);
623 unsigned TIDIGYReg = TRI->getPreloadedValue(*MF, SIRegisterInfo::TIDIG_Y);
624 unsigned TIDIGZReg = TRI->getPreloadedValue(*MF, SIRegisterInfo::TIDIG_Z);
625 unsigned InputPtrReg =
626 TRI->getPreloadedValue(*MF, SIRegisterInfo::INPUT_PTR);
627 for (unsigned Reg : {TIDIGXReg, TIDIGYReg, TIDIGZReg}) {
628 if (!Entry.isLiveIn(Reg))
629 Entry.addLiveIn(Reg);
632 RS->enterBasicBlock(&Entry);
633 unsigned STmp0 = RS->scavengeRegister(&AMDGPU::SGPR_32RegClass, 0);
634 unsigned STmp1 = RS->scavengeRegister(&AMDGPU::SGPR_32RegClass, 0);
635 BuildMI(Entry, Insert, DL, get(AMDGPU::S_LOAD_DWORD_IMM), STmp0)
637 .addImm(SI::KernelInputOffsets::NGROUPS_Z);
638 BuildMI(Entry, Insert, DL, get(AMDGPU::S_LOAD_DWORD_IMM), STmp1)
640 .addImm(SI::KernelInputOffsets::NGROUPS_Y);
642 // NGROUPS.X * NGROUPS.Y
643 BuildMI(Entry, Insert, DL, get(AMDGPU::S_MUL_I32), STmp1)
646 // (NGROUPS.X * NGROUPS.Y) * TIDIG.X
647 BuildMI(Entry, Insert, DL, get(AMDGPU::V_MUL_U32_U24_e32), TIDReg)
650 // NGROUPS.Z * TIDIG.Y + (NGROUPS.X * NGROPUS.Y * TIDIG.X)
651 BuildMI(Entry, Insert, DL, get(AMDGPU::V_MAD_U32_U24), TIDReg)
655 // (NGROUPS.Z * TIDIG.Y + (NGROUPS.X * NGROPUS.Y * TIDIG.X)) + TIDIG.Z
656 BuildMI(Entry, Insert, DL, get(AMDGPU::V_ADD_I32_e32), TIDReg)
661 BuildMI(Entry, Insert, DL, get(AMDGPU::V_MBCNT_LO_U32_B32_e64),
666 BuildMI(Entry, Insert, DL, get(AMDGPU::V_MBCNT_HI_U32_B32_e64),
672 BuildMI(Entry, Insert, DL, get(AMDGPU::V_LSHLREV_B32_e32),
676 MFI->setTIDReg(TIDReg);
679 // Add FrameIndex to LDS offset
680 unsigned LDSOffset = MFI->LDSSize + (FrameOffset * WorkGroupSize);
681 BuildMI(MBB, MI, DL, get(AMDGPU::V_ADD_I32_e32), TmpReg)
688 void SIInstrInfo::insertNOPs(MachineBasicBlock::iterator MI,
697 BuildMI(*MI->getParent(), MI, MI->getDebugLoc(), get(AMDGPU::S_NOP))
702 bool SIInstrInfo::expandPostRAPseudo(MachineBasicBlock::iterator MI) const {
703 MachineBasicBlock &MBB = *MI->getParent();
704 DebugLoc DL = MBB.findDebugLoc(MI);
705 switch (MI->getOpcode()) {
706 default: return AMDGPUInstrInfo::expandPostRAPseudo(MI);
708 case AMDGPU::SI_CONSTDATA_PTR: {
709 unsigned Reg = MI->getOperand(0).getReg();
710 unsigned RegLo = RI.getSubReg(Reg, AMDGPU::sub0);
711 unsigned RegHi = RI.getSubReg(Reg, AMDGPU::sub1);
713 BuildMI(MBB, MI, DL, get(AMDGPU::S_GETPC_B64), Reg);
715 // Add 32-bit offset from this instruction to the start of the constant data.
716 BuildMI(MBB, MI, DL, get(AMDGPU::S_ADD_U32), RegLo)
718 .addTargetIndex(AMDGPU::TI_CONSTDATA_START)
719 .addReg(AMDGPU::SCC, RegState::Define | RegState::Implicit);
720 BuildMI(MBB, MI, DL, get(AMDGPU::S_ADDC_U32), RegHi)
723 .addReg(AMDGPU::SCC, RegState::Define | RegState::Implicit)
724 .addReg(AMDGPU::SCC, RegState::Implicit);
725 MI->eraseFromParent();
728 case AMDGPU::SGPR_USE:
729 // This is just a placeholder for register allocation.
730 MI->eraseFromParent();
733 case AMDGPU::V_MOV_B64_PSEUDO: {
734 unsigned Dst = MI->getOperand(0).getReg();
735 unsigned DstLo = RI.getSubReg(Dst, AMDGPU::sub0);
736 unsigned DstHi = RI.getSubReg(Dst, AMDGPU::sub1);
738 const MachineOperand &SrcOp = MI->getOperand(1);
739 // FIXME: Will this work for 64-bit floating point immediates?
740 assert(!SrcOp.isFPImm());
742 APInt Imm(64, SrcOp.getImm());
743 BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), DstLo)
744 .addImm(Imm.getLoBits(32).getZExtValue())
745 .addReg(Dst, RegState::Implicit);
746 BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), DstHi)
747 .addImm(Imm.getHiBits(32).getZExtValue())
748 .addReg(Dst, RegState::Implicit);
750 assert(SrcOp.isReg());
751 BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), DstLo)
752 .addReg(RI.getSubReg(SrcOp.getReg(), AMDGPU::sub0))
753 .addReg(Dst, RegState::Implicit);
754 BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), DstHi)
755 .addReg(RI.getSubReg(SrcOp.getReg(), AMDGPU::sub1))
756 .addReg(Dst, RegState::Implicit);
758 MI->eraseFromParent();
762 case AMDGPU::V_CNDMASK_B64_PSEUDO: {
763 unsigned Dst = MI->getOperand(0).getReg();
764 unsigned DstLo = RI.getSubReg(Dst, AMDGPU::sub0);
765 unsigned DstHi = RI.getSubReg(Dst, AMDGPU::sub1);
766 unsigned Src0 = MI->getOperand(1).getReg();
767 unsigned Src1 = MI->getOperand(2).getReg();
768 const MachineOperand &SrcCond = MI->getOperand(3);
770 BuildMI(MBB, MI, DL, get(AMDGPU::V_CNDMASK_B32_e64), DstLo)
771 .addReg(RI.getSubReg(Src0, AMDGPU::sub0))
772 .addReg(RI.getSubReg(Src1, AMDGPU::sub0))
773 .addOperand(SrcCond);
774 BuildMI(MBB, MI, DL, get(AMDGPU::V_CNDMASK_B32_e64), DstHi)
775 .addReg(RI.getSubReg(Src0, AMDGPU::sub1))
776 .addReg(RI.getSubReg(Src1, AMDGPU::sub1))
777 .addOperand(SrcCond);
778 MI->eraseFromParent();
785 MachineInstr *SIInstrInfo::commuteInstruction(MachineInstr *MI,
787 int CommutedOpcode = commuteOpcode(*MI);
788 if (CommutedOpcode == -1)
791 int Src0Idx = AMDGPU::getNamedOperandIdx(MI->getOpcode(),
792 AMDGPU::OpName::src0);
793 assert(Src0Idx != -1 && "Should always have src0 operand");
795 MachineOperand &Src0 = MI->getOperand(Src0Idx);
799 int Src1Idx = AMDGPU::getNamedOperandIdx(MI->getOpcode(),
800 AMDGPU::OpName::src1);
804 MachineOperand &Src1 = MI->getOperand(Src1Idx);
806 // Make sure it's legal to commute operands for VOP2.
807 if (isVOP2(MI->getOpcode()) &&
808 (!isOperandLegal(MI, Src0Idx, &Src1) ||
809 !isOperandLegal(MI, Src1Idx, &Src0))) {
814 // Allow commuting instructions with Imm operands.
815 if (NewMI || !Src1.isImm() ||
816 (!isVOP2(MI->getOpcode()) && !isVOP3(MI->getOpcode()))) {
820 // Be sure to copy the source modifiers to the right place.
821 if (MachineOperand *Src0Mods
822 = getNamedOperand(*MI, AMDGPU::OpName::src0_modifiers)) {
823 MachineOperand *Src1Mods
824 = getNamedOperand(*MI, AMDGPU::OpName::src1_modifiers);
826 int Src0ModsVal = Src0Mods->getImm();
827 if (!Src1Mods && Src0ModsVal != 0)
830 // XXX - This assert might be a lie. It might be useful to have a neg
831 // modifier with 0.0.
832 int Src1ModsVal = Src1Mods->getImm();
833 assert((Src1ModsVal == 0) && "Not expecting modifiers with immediates");
835 Src1Mods->setImm(Src0ModsVal);
836 Src0Mods->setImm(Src1ModsVal);
839 unsigned Reg = Src0.getReg();
840 unsigned SubReg = Src0.getSubReg();
842 Src0.ChangeToImmediate(Src1.getImm());
844 llvm_unreachable("Should only have immediates");
846 Src1.ChangeToRegister(Reg, false);
847 Src1.setSubReg(SubReg);
849 MI = TargetInstrInfo::commuteInstruction(MI, NewMI);
853 MI->setDesc(get(CommutedOpcode));
858 // This needs to be implemented because the source modifiers may be inserted
859 // between the true commutable operands, and the base
860 // TargetInstrInfo::commuteInstruction uses it.
861 bool SIInstrInfo::findCommutedOpIndices(MachineInstr *MI,
863 unsigned &SrcOpIdx2) const {
864 const MCInstrDesc &MCID = MI->getDesc();
865 if (!MCID.isCommutable())
868 unsigned Opc = MI->getOpcode();
869 int Src0Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src0);
873 // FIXME: Workaround TargetInstrInfo::commuteInstruction asserting on
875 if (!MI->getOperand(Src0Idx).isReg())
878 int Src1Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src1);
882 if (!MI->getOperand(Src1Idx).isReg())
885 // If any source modifiers are set, the generic instruction commuting won't
886 // understand how to copy the source modifiers.
887 if (hasModifiersSet(*MI, AMDGPU::OpName::src0_modifiers) ||
888 hasModifiersSet(*MI, AMDGPU::OpName::src1_modifiers))
896 MachineInstr *SIInstrInfo::buildMovInstr(MachineBasicBlock *MBB,
897 MachineBasicBlock::iterator I,
899 unsigned SrcReg) const {
900 return BuildMI(*MBB, I, MBB->findDebugLoc(I), get(AMDGPU::V_MOV_B32_e32),
901 DstReg) .addReg(SrcReg);
904 bool SIInstrInfo::isMov(unsigned Opcode) const {
906 default: return false;
907 case AMDGPU::S_MOV_B32:
908 case AMDGPU::S_MOV_B64:
909 case AMDGPU::V_MOV_B32_e32:
910 case AMDGPU::V_MOV_B32_e64:
915 static void removeModOperands(MachineInstr &MI) {
916 unsigned Opc = MI.getOpcode();
917 int Src0ModIdx = AMDGPU::getNamedOperandIdx(Opc,
918 AMDGPU::OpName::src0_modifiers);
919 int Src1ModIdx = AMDGPU::getNamedOperandIdx(Opc,
920 AMDGPU::OpName::src1_modifiers);
921 int Src2ModIdx = AMDGPU::getNamedOperandIdx(Opc,
922 AMDGPU::OpName::src2_modifiers);
924 MI.RemoveOperand(Src2ModIdx);
925 MI.RemoveOperand(Src1ModIdx);
926 MI.RemoveOperand(Src0ModIdx);
929 bool SIInstrInfo::FoldImmediate(MachineInstr *UseMI, MachineInstr *DefMI,
930 unsigned Reg, MachineRegisterInfo *MRI) const {
931 if (!MRI->hasOneNonDBGUse(Reg))
934 unsigned Opc = UseMI->getOpcode();
935 if (Opc == AMDGPU::V_MAD_F32 || Opc == AMDGPU::V_MAC_F32_e64) {
936 // Don't fold if we are using source modifiers. The new VOP2 instructions
938 if (hasModifiersSet(*UseMI, AMDGPU::OpName::src0_modifiers) ||
939 hasModifiersSet(*UseMI, AMDGPU::OpName::src1_modifiers) ||
940 hasModifiersSet(*UseMI, AMDGPU::OpName::src2_modifiers)) {
944 MachineOperand *Src0 = getNamedOperand(*UseMI, AMDGPU::OpName::src0);
945 MachineOperand *Src1 = getNamedOperand(*UseMI, AMDGPU::OpName::src1);
946 MachineOperand *Src2 = getNamedOperand(*UseMI, AMDGPU::OpName::src2);
948 // Multiplied part is the constant: Use v_madmk_f32
949 // We should only expect these to be on src0 due to canonicalizations.
950 if (Src0->isReg() && Src0->getReg() == Reg) {
951 if (!Src1->isReg() ||
952 (Src1->isReg() && RI.isSGPRClass(MRI->getRegClass(Src1->getReg()))))
955 if (!Src2->isReg() ||
956 (Src2->isReg() && RI.isSGPRClass(MRI->getRegClass(Src2->getReg()))))
959 // We need to do some weird looking operand shuffling since the madmk
960 // operands are out of the normal expected order with the multiplied
961 // constant as the last operand.
963 // v_mad_f32 src0, src1, src2 -> v_madmk_f32 src0 * src2K + src1
968 const int64_t Imm = DefMI->getOperand(1).getImm();
970 // FIXME: This would be a lot easier if we could return a new instruction
971 // instead of having to modify in place.
973 // Remove these first since they are at the end.
974 UseMI->RemoveOperand(AMDGPU::getNamedOperandIdx(Opc,
975 AMDGPU::OpName::omod));
976 UseMI->RemoveOperand(AMDGPU::getNamedOperandIdx(Opc,
977 AMDGPU::OpName::clamp));
979 unsigned Src1Reg = Src1->getReg();
980 unsigned Src1SubReg = Src1->getSubReg();
981 unsigned Src2Reg = Src2->getReg();
982 unsigned Src2SubReg = Src2->getSubReg();
983 Src0->setReg(Src1Reg);
984 Src0->setSubReg(Src1SubReg);
985 Src0->setIsKill(Src1->isKill());
987 Src1->setReg(Src2Reg);
988 Src1->setSubReg(Src2SubReg);
989 Src1->setIsKill(Src2->isKill());
991 if (Opc == AMDGPU::V_MAC_F32_e64) {
992 UseMI->untieRegOperand(
993 AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src2));
996 Src2->ChangeToImmediate(Imm);
998 removeModOperands(*UseMI);
999 UseMI->setDesc(get(AMDGPU::V_MADMK_F32));
1001 bool DeleteDef = MRI->hasOneNonDBGUse(Reg);
1003 DefMI->eraseFromParent();
1008 // Added part is the constant: Use v_madak_f32
1009 if (Src2->isReg() && Src2->getReg() == Reg) {
1010 // Not allowed to use constant bus for another operand.
1011 // We can however allow an inline immediate as src0.
1012 if (!Src0->isImm() &&
1013 (Src0->isReg() && RI.isSGPRClass(MRI->getRegClass(Src0->getReg()))))
1016 if (!Src1->isReg() ||
1017 (Src1->isReg() && RI.isSGPRClass(MRI->getRegClass(Src1->getReg()))))
1020 const int64_t Imm = DefMI->getOperand(1).getImm();
1022 // FIXME: This would be a lot easier if we could return a new instruction
1023 // instead of having to modify in place.
1025 // Remove these first since they are at the end.
1026 UseMI->RemoveOperand(AMDGPU::getNamedOperandIdx(Opc,
1027 AMDGPU::OpName::omod));
1028 UseMI->RemoveOperand(AMDGPU::getNamedOperandIdx(Opc,
1029 AMDGPU::OpName::clamp));
1031 if (Opc == AMDGPU::V_MAC_F32_e64) {
1032 UseMI->untieRegOperand(
1033 AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src2));
1036 // ChangingToImmediate adds Src2 back to the instruction.
1037 Src2->ChangeToImmediate(Imm);
1039 // These come before src2.
1040 removeModOperands(*UseMI);
1041 UseMI->setDesc(get(AMDGPU::V_MADAK_F32));
1043 bool DeleteDef = MRI->hasOneNonDBGUse(Reg);
1045 DefMI->eraseFromParent();
1054 static bool offsetsDoNotOverlap(int WidthA, int OffsetA,
1055 int WidthB, int OffsetB) {
1056 int LowOffset = OffsetA < OffsetB ? OffsetA : OffsetB;
1057 int HighOffset = OffsetA < OffsetB ? OffsetB : OffsetA;
1058 int LowWidth = (LowOffset == OffsetA) ? WidthA : WidthB;
1059 return LowOffset + LowWidth <= HighOffset;
1062 bool SIInstrInfo::checkInstOffsetsDoNotOverlap(MachineInstr *MIa,
1063 MachineInstr *MIb) const {
1064 unsigned BaseReg0, Offset0;
1065 unsigned BaseReg1, Offset1;
1067 if (getMemOpBaseRegImmOfs(MIa, BaseReg0, Offset0, &RI) &&
1068 getMemOpBaseRegImmOfs(MIb, BaseReg1, Offset1, &RI)) {
1069 assert(MIa->hasOneMemOperand() && MIb->hasOneMemOperand() &&
1070 "read2 / write2 not expected here yet");
1071 unsigned Width0 = (*MIa->memoperands_begin())->getSize();
1072 unsigned Width1 = (*MIb->memoperands_begin())->getSize();
1073 if (BaseReg0 == BaseReg1 &&
1074 offsetsDoNotOverlap(Width0, Offset0, Width1, Offset1)) {
1082 bool SIInstrInfo::areMemAccessesTriviallyDisjoint(MachineInstr *MIa,
1084 AliasAnalysis *AA) const {
1085 unsigned Opc0 = MIa->getOpcode();
1086 unsigned Opc1 = MIb->getOpcode();
1088 assert(MIa && (MIa->mayLoad() || MIa->mayStore()) &&
1089 "MIa must load from or modify a memory location");
1090 assert(MIb && (MIb->mayLoad() || MIb->mayStore()) &&
1091 "MIb must load from or modify a memory location");
1093 if (MIa->hasUnmodeledSideEffects() || MIb->hasUnmodeledSideEffects())
1096 // XXX - Can we relax this between address spaces?
1097 if (MIa->hasOrderedMemoryRef() || MIb->hasOrderedMemoryRef())
1100 // TODO: Should we check the address space from the MachineMemOperand? That
1101 // would allow us to distinguish objects we know don't alias based on the
1102 // underlying address space, even if it was lowered to a different one,
1103 // e.g. private accesses lowered to use MUBUF instructions on a scratch
1107 return checkInstOffsetsDoNotOverlap(MIa, MIb);
1109 return !isFLAT(Opc1);
1112 if (isMUBUF(Opc0) || isMTBUF(Opc0)) {
1113 if (isMUBUF(Opc1) || isMTBUF(Opc1))
1114 return checkInstOffsetsDoNotOverlap(MIa, MIb);
1116 return !isFLAT(Opc1) && !isSMRD(Opc1);
1121 return checkInstOffsetsDoNotOverlap(MIa, MIb);
1123 return !isFLAT(Opc1) && !isMUBUF(Opc0) && !isMTBUF(Opc0);
1128 return checkInstOffsetsDoNotOverlap(MIa, MIb);
1136 MachineInstr *SIInstrInfo::convertToThreeAddress(MachineFunction::iterator &MBB,
1137 MachineBasicBlock::iterator &MI,
1138 LiveVariables *LV) const {
1140 switch (MI->getOpcode()) {
1141 default: return nullptr;
1142 case AMDGPU::V_MAC_F32_e64: break;
1143 case AMDGPU::V_MAC_F32_e32: {
1144 const MachineOperand *Src0 = getNamedOperand(*MI, AMDGPU::OpName::src0);
1145 if (Src0->isImm() && !isInlineConstant(*Src0, 4))
1151 const MachineOperand *Dst = getNamedOperand(*MI, AMDGPU::OpName::dst);
1152 const MachineOperand *Src0 = getNamedOperand(*MI, AMDGPU::OpName::src0);
1153 const MachineOperand *Src1 = getNamedOperand(*MI, AMDGPU::OpName::src1);
1154 const MachineOperand *Src2 = getNamedOperand(*MI, AMDGPU::OpName::src2);
1156 return BuildMI(*MBB, MI, MI->getDebugLoc(), get(AMDGPU::V_MAD_F32))
1158 .addImm(0) // Src0 mods
1160 .addImm(0) // Src1 mods
1162 .addImm(0) // Src mods
1168 bool SIInstrInfo::isInlineConstant(const APInt &Imm) const {
1169 int64_t SVal = Imm.getSExtValue();
1170 if (SVal >= -16 && SVal <= 64)
1173 if (Imm.getBitWidth() == 64) {
1174 uint64_t Val = Imm.getZExtValue();
1175 return (DoubleToBits(0.0) == Val) ||
1176 (DoubleToBits(1.0) == Val) ||
1177 (DoubleToBits(-1.0) == Val) ||
1178 (DoubleToBits(0.5) == Val) ||
1179 (DoubleToBits(-0.5) == Val) ||
1180 (DoubleToBits(2.0) == Val) ||
1181 (DoubleToBits(-2.0) == Val) ||
1182 (DoubleToBits(4.0) == Val) ||
1183 (DoubleToBits(-4.0) == Val);
1186 // The actual type of the operand does not seem to matter as long
1187 // as the bits match one of the inline immediate values. For example:
1189 // -nan has the hexadecimal encoding of 0xfffffffe which is -2 in decimal,
1190 // so it is a legal inline immediate.
1192 // 1065353216 has the hexadecimal encoding 0x3f800000 which is 1.0f in
1193 // floating-point, so it is a legal inline immediate.
1194 uint32_t Val = Imm.getZExtValue();
1196 return (FloatToBits(0.0f) == Val) ||
1197 (FloatToBits(1.0f) == Val) ||
1198 (FloatToBits(-1.0f) == Val) ||
1199 (FloatToBits(0.5f) == Val) ||
1200 (FloatToBits(-0.5f) == Val) ||
1201 (FloatToBits(2.0f) == Val) ||
1202 (FloatToBits(-2.0f) == Val) ||
1203 (FloatToBits(4.0f) == Val) ||
1204 (FloatToBits(-4.0f) == Val);
1207 bool SIInstrInfo::isInlineConstant(const MachineOperand &MO,
1208 unsigned OpSize) const {
1210 // MachineOperand provides no way to tell the true operand size, since it
1211 // only records a 64-bit value. We need to know the size to determine if a
1212 // 32-bit floating point immediate bit pattern is legal for an integer
1213 // immediate. It would be for any 32-bit integer operand, but would not be
1214 // for a 64-bit one.
1216 unsigned BitSize = 8 * OpSize;
1217 return isInlineConstant(APInt(BitSize, MO.getImm(), true));
1223 bool SIInstrInfo::isLiteralConstant(const MachineOperand &MO,
1224 unsigned OpSize) const {
1225 return MO.isImm() && !isInlineConstant(MO, OpSize);
1228 static bool compareMachineOp(const MachineOperand &Op0,
1229 const MachineOperand &Op1) {
1230 if (Op0.getType() != Op1.getType())
1233 switch (Op0.getType()) {
1234 case MachineOperand::MO_Register:
1235 return Op0.getReg() == Op1.getReg();
1236 case MachineOperand::MO_Immediate:
1237 return Op0.getImm() == Op1.getImm();
1239 llvm_unreachable("Didn't expect to be comparing these operand types");
1243 bool SIInstrInfo::isImmOperandLegal(const MachineInstr *MI, unsigned OpNo,
1244 const MachineOperand &MO) const {
1245 const MCOperandInfo &OpInfo = get(MI->getOpcode()).OpInfo[OpNo];
1247 assert(MO.isImm() || MO.isTargetIndex() || MO.isFI());
1249 if (OpInfo.OperandType == MCOI::OPERAND_IMMEDIATE)
1252 if (OpInfo.RegClass < 0)
1255 unsigned OpSize = RI.getRegClass(OpInfo.RegClass)->getSize();
1256 if (isLiteralConstant(MO, OpSize))
1257 return RI.opCanUseLiteralConstant(OpInfo.OperandType);
1259 return RI.opCanUseInlineConstant(OpInfo.OperandType);
1262 bool SIInstrInfo::hasVALU32BitEncoding(unsigned Opcode) const {
1263 int Op32 = AMDGPU::getVOPe32(Opcode);
1267 return pseudoToMCOpcode(Op32) != -1;
1270 bool SIInstrInfo::hasModifiers(unsigned Opcode) const {
1271 // The src0_modifier operand is present on all instructions
1272 // that have modifiers.
1274 return AMDGPU::getNamedOperandIdx(Opcode,
1275 AMDGPU::OpName::src0_modifiers) != -1;
1278 bool SIInstrInfo::hasModifiersSet(const MachineInstr &MI,
1279 unsigned OpName) const {
1280 const MachineOperand *Mods = getNamedOperand(MI, OpName);
1281 return Mods && Mods->getImm();
1284 bool SIInstrInfo::usesConstantBus(const MachineRegisterInfo &MRI,
1285 const MachineOperand &MO,
1286 unsigned OpSize) const {
1287 // Literal constants use the constant bus.
1288 if (isLiteralConstant(MO, OpSize))
1291 if (!MO.isReg() || !MO.isUse())
1294 if (TargetRegisterInfo::isVirtualRegister(MO.getReg()))
1295 return RI.isSGPRClass(MRI.getRegClass(MO.getReg()));
1297 // FLAT_SCR is just an SGPR pair.
1298 if (!MO.isImplicit() && (MO.getReg() == AMDGPU::FLAT_SCR))
1301 // EXEC register uses the constant bus.
1302 if (!MO.isImplicit() && MO.getReg() == AMDGPU::EXEC)
1305 // SGPRs use the constant bus
1306 if (MO.getReg() == AMDGPU::M0 || MO.getReg() == AMDGPU::VCC ||
1307 (!MO.isImplicit() &&
1308 (AMDGPU::SGPR_32RegClass.contains(MO.getReg()) ||
1309 AMDGPU::SGPR_64RegClass.contains(MO.getReg())))) {
1316 bool SIInstrInfo::verifyInstruction(const MachineInstr *MI,
1317 StringRef &ErrInfo) const {
1318 uint16_t Opcode = MI->getOpcode();
1319 const MachineRegisterInfo &MRI = MI->getParent()->getParent()->getRegInfo();
1320 int Src0Idx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src0);
1321 int Src1Idx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src1);
1322 int Src2Idx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src2);
1324 // Make sure the number of operands is correct.
1325 const MCInstrDesc &Desc = get(Opcode);
1326 if (!Desc.isVariadic() &&
1327 Desc.getNumOperands() != MI->getNumExplicitOperands()) {
1328 ErrInfo = "Instruction has wrong number of operands.";
1332 // Make sure the register classes are correct
1333 for (int i = 0, e = Desc.getNumOperands(); i != e; ++i) {
1334 if (MI->getOperand(i).isFPImm()) {
1335 ErrInfo = "FPImm Machine Operands are not supported. ISel should bitcast "
1336 "all fp values to integers.";
1340 int RegClass = Desc.OpInfo[i].RegClass;
1342 switch (Desc.OpInfo[i].OperandType) {
1343 case MCOI::OPERAND_REGISTER:
1344 if (MI->getOperand(i).isImm()) {
1345 ErrInfo = "Illegal immediate value for operand.";
1349 case AMDGPU::OPERAND_REG_IMM32:
1351 case AMDGPU::OPERAND_REG_INLINE_C:
1352 if (isLiteralConstant(MI->getOperand(i),
1353 RI.getRegClass(RegClass)->getSize())) {
1354 ErrInfo = "Illegal immediate value for operand.";
1358 case MCOI::OPERAND_IMMEDIATE:
1359 // Check if this operand is an immediate.
1360 // FrameIndex operands will be replaced by immediates, so they are
1362 if (!MI->getOperand(i).isImm() && !MI->getOperand(i).isFI()) {
1363 ErrInfo = "Expected immediate, but got non-immediate";
1371 if (!MI->getOperand(i).isReg())
1374 if (RegClass != -1) {
1375 unsigned Reg = MI->getOperand(i).getReg();
1376 if (TargetRegisterInfo::isVirtualRegister(Reg))
1379 const TargetRegisterClass *RC = RI.getRegClass(RegClass);
1380 if (!RC->contains(Reg)) {
1381 ErrInfo = "Operand has incorrect register class.";
1389 if (isVOP1(Opcode) || isVOP2(Opcode) || isVOP3(Opcode) || isVOPC(Opcode)) {
1390 // Only look at the true operands. Only a real operand can use the constant
1391 // bus, and we don't want to check pseudo-operands like the source modifier
1393 const int OpIndices[] = { Src0Idx, Src1Idx, Src2Idx };
1395 unsigned ConstantBusCount = 0;
1396 unsigned SGPRUsed = AMDGPU::NoRegister;
1397 for (int OpIdx : OpIndices) {
1400 const MachineOperand &MO = MI->getOperand(OpIdx);
1401 if (usesConstantBus(MRI, MO, getOpSize(Opcode, OpIdx))) {
1403 if (MO.getReg() != SGPRUsed)
1405 SGPRUsed = MO.getReg();
1411 if (ConstantBusCount > 1) {
1412 ErrInfo = "VOP* instruction uses the constant bus more than once";
1417 // Verify misc. restrictions on specific instructions.
1418 if (Desc.getOpcode() == AMDGPU::V_DIV_SCALE_F32 ||
1419 Desc.getOpcode() == AMDGPU::V_DIV_SCALE_F64) {
1420 const MachineOperand &Src0 = MI->getOperand(Src0Idx);
1421 const MachineOperand &Src1 = MI->getOperand(Src1Idx);
1422 const MachineOperand &Src2 = MI->getOperand(Src2Idx);
1423 if (Src0.isReg() && Src1.isReg() && Src2.isReg()) {
1424 if (!compareMachineOp(Src0, Src1) &&
1425 !compareMachineOp(Src0, Src2)) {
1426 ErrInfo = "v_div_scale_{f32|f64} require src0 = src1 or src2";
1435 unsigned SIInstrInfo::getVALUOp(const MachineInstr &MI) {
1436 switch (MI.getOpcode()) {
1437 default: return AMDGPU::INSTRUCTION_LIST_END;
1438 case AMDGPU::REG_SEQUENCE: return AMDGPU::REG_SEQUENCE;
1439 case AMDGPU::COPY: return AMDGPU::COPY;
1440 case AMDGPU::PHI: return AMDGPU::PHI;
1441 case AMDGPU::INSERT_SUBREG: return AMDGPU::INSERT_SUBREG;
1442 case AMDGPU::S_MOV_B32:
1443 return MI.getOperand(1).isReg() ?
1444 AMDGPU::COPY : AMDGPU::V_MOV_B32_e32;
1445 case AMDGPU::S_ADD_I32:
1446 case AMDGPU::S_ADD_U32: return AMDGPU::V_ADD_I32_e32;
1447 case AMDGPU::S_ADDC_U32: return AMDGPU::V_ADDC_U32_e32;
1448 case AMDGPU::S_SUB_I32:
1449 case AMDGPU::S_SUB_U32: return AMDGPU::V_SUB_I32_e32;
1450 case AMDGPU::S_SUBB_U32: return AMDGPU::V_SUBB_U32_e32;
1451 case AMDGPU::S_MUL_I32: return AMDGPU::V_MUL_LO_I32;
1452 case AMDGPU::S_AND_B32: return AMDGPU::V_AND_B32_e32;
1453 case AMDGPU::S_OR_B32: return AMDGPU::V_OR_B32_e32;
1454 case AMDGPU::S_XOR_B32: return AMDGPU::V_XOR_B32_e32;
1455 case AMDGPU::S_MIN_I32: return AMDGPU::V_MIN_I32_e32;
1456 case AMDGPU::S_MIN_U32: return AMDGPU::V_MIN_U32_e32;
1457 case AMDGPU::S_MAX_I32: return AMDGPU::V_MAX_I32_e32;
1458 case AMDGPU::S_MAX_U32: return AMDGPU::V_MAX_U32_e32;
1459 case AMDGPU::S_ASHR_I32: return AMDGPU::V_ASHR_I32_e32;
1460 case AMDGPU::S_ASHR_I64: return AMDGPU::V_ASHR_I64;
1461 case AMDGPU::S_LSHL_B32: return AMDGPU::V_LSHL_B32_e32;
1462 case AMDGPU::S_LSHL_B64: return AMDGPU::V_LSHL_B64;
1463 case AMDGPU::S_LSHR_B32: return AMDGPU::V_LSHR_B32_e32;
1464 case AMDGPU::S_LSHR_B64: return AMDGPU::V_LSHR_B64;
1465 case AMDGPU::S_SEXT_I32_I8: return AMDGPU::V_BFE_I32;
1466 case AMDGPU::S_SEXT_I32_I16: return AMDGPU::V_BFE_I32;
1467 case AMDGPU::S_BFE_U32: return AMDGPU::V_BFE_U32;
1468 case AMDGPU::S_BFE_I32: return AMDGPU::V_BFE_I32;
1469 case AMDGPU::S_BFM_B32: return AMDGPU::V_BFM_B32_e64;
1470 case AMDGPU::S_BREV_B32: return AMDGPU::V_BFREV_B32_e32;
1471 case AMDGPU::S_NOT_B32: return AMDGPU::V_NOT_B32_e32;
1472 case AMDGPU::S_NOT_B64: return AMDGPU::V_NOT_B32_e32;
1473 case AMDGPU::S_CMP_EQ_I32: return AMDGPU::V_CMP_EQ_I32_e32;
1474 case AMDGPU::S_CMP_LG_I32: return AMDGPU::V_CMP_NE_I32_e32;
1475 case AMDGPU::S_CMP_GT_I32: return AMDGPU::V_CMP_GT_I32_e32;
1476 case AMDGPU::S_CMP_GE_I32: return AMDGPU::V_CMP_GE_I32_e32;
1477 case AMDGPU::S_CMP_LT_I32: return AMDGPU::V_CMP_LT_I32_e32;
1478 case AMDGPU::S_CMP_LE_I32: return AMDGPU::V_CMP_LE_I32_e32;
1479 case AMDGPU::S_LOAD_DWORD_IMM:
1480 case AMDGPU::S_LOAD_DWORD_SGPR: return AMDGPU::BUFFER_LOAD_DWORD_ADDR64;
1481 case AMDGPU::S_LOAD_DWORDX2_IMM:
1482 case AMDGPU::S_LOAD_DWORDX2_SGPR: return AMDGPU::BUFFER_LOAD_DWORDX2_ADDR64;
1483 case AMDGPU::S_LOAD_DWORDX4_IMM:
1484 case AMDGPU::S_LOAD_DWORDX4_SGPR: return AMDGPU::BUFFER_LOAD_DWORDX4_ADDR64;
1485 case AMDGPU::S_BCNT1_I32_B32: return AMDGPU::V_BCNT_U32_B32_e64;
1486 case AMDGPU::S_FF1_I32_B32: return AMDGPU::V_FFBL_B32_e32;
1487 case AMDGPU::S_FLBIT_I32_B32: return AMDGPU::V_FFBH_U32_e32;
1488 case AMDGPU::S_FLBIT_I32: return AMDGPU::V_FFBH_I32_e64;
1492 bool SIInstrInfo::isSALUOpSupportedOnVALU(const MachineInstr &MI) const {
1493 return getVALUOp(MI) != AMDGPU::INSTRUCTION_LIST_END;
1496 const TargetRegisterClass *SIInstrInfo::getOpRegClass(const MachineInstr &MI,
1497 unsigned OpNo) const {
1498 const MachineRegisterInfo &MRI = MI.getParent()->getParent()->getRegInfo();
1499 const MCInstrDesc &Desc = get(MI.getOpcode());
1500 if (MI.isVariadic() || OpNo >= Desc.getNumOperands() ||
1501 Desc.OpInfo[OpNo].RegClass == -1) {
1502 unsigned Reg = MI.getOperand(OpNo).getReg();
1504 if (TargetRegisterInfo::isVirtualRegister(Reg))
1505 return MRI.getRegClass(Reg);
1506 return RI.getPhysRegClass(Reg);
1509 unsigned RCID = Desc.OpInfo[OpNo].RegClass;
1510 return RI.getRegClass(RCID);
1513 bool SIInstrInfo::canReadVGPR(const MachineInstr &MI, unsigned OpNo) const {
1514 switch (MI.getOpcode()) {
1516 case AMDGPU::REG_SEQUENCE:
1518 case AMDGPU::INSERT_SUBREG:
1519 return RI.hasVGPRs(getOpRegClass(MI, 0));
1521 return RI.hasVGPRs(getOpRegClass(MI, OpNo));
1525 void SIInstrInfo::legalizeOpWithMove(MachineInstr *MI, unsigned OpIdx) const {
1526 MachineBasicBlock::iterator I = MI;
1527 MachineBasicBlock *MBB = MI->getParent();
1528 MachineOperand &MO = MI->getOperand(OpIdx);
1529 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
1530 unsigned RCID = get(MI->getOpcode()).OpInfo[OpIdx].RegClass;
1531 const TargetRegisterClass *RC = RI.getRegClass(RCID);
1532 unsigned Opcode = AMDGPU::V_MOV_B32_e32;
1534 Opcode = AMDGPU::COPY;
1535 else if (RI.isSGPRClass(RC))
1536 Opcode = AMDGPU::S_MOV_B32;
1539 const TargetRegisterClass *VRC = RI.getEquivalentVGPRClass(RC);
1540 if (RI.getCommonSubClass(&AMDGPU::VReg_64RegClass, VRC))
1541 VRC = &AMDGPU::VReg_64RegClass;
1543 VRC = &AMDGPU::VGPR_32RegClass;
1545 unsigned Reg = MRI.createVirtualRegister(VRC);
1546 DebugLoc DL = MBB->findDebugLoc(I);
1547 BuildMI(*MI->getParent(), I, DL, get(Opcode), Reg)
1549 MO.ChangeToRegister(Reg, false);
1552 unsigned SIInstrInfo::buildExtractSubReg(MachineBasicBlock::iterator MI,
1553 MachineRegisterInfo &MRI,
1554 MachineOperand &SuperReg,
1555 const TargetRegisterClass *SuperRC,
1557 const TargetRegisterClass *SubRC)
1559 assert(SuperReg.isReg());
1561 unsigned NewSuperReg = MRI.createVirtualRegister(SuperRC);
1562 unsigned SubReg = MRI.createVirtualRegister(SubRC);
1564 // Just in case the super register is itself a sub-register, copy it to a new
1565 // value so we don't need to worry about merging its subreg index with the
1566 // SubIdx passed to this function. The register coalescer should be able to
1567 // eliminate this extra copy.
1568 MachineBasicBlock *MBB = MI->getParent();
1569 DebugLoc DL = MI->getDebugLoc();
1571 BuildMI(*MBB, MI, DL, get(TargetOpcode::COPY), NewSuperReg)
1572 .addReg(SuperReg.getReg(), 0, SuperReg.getSubReg());
1574 BuildMI(*MBB, MI, DL, get(TargetOpcode::COPY), SubReg)
1575 .addReg(NewSuperReg, 0, SubIdx);
1580 MachineOperand SIInstrInfo::buildExtractSubRegOrImm(
1581 MachineBasicBlock::iterator MII,
1582 MachineRegisterInfo &MRI,
1584 const TargetRegisterClass *SuperRC,
1586 const TargetRegisterClass *SubRC) const {
1588 // XXX - Is there a better way to do this?
1589 if (SubIdx == AMDGPU::sub0)
1590 return MachineOperand::CreateImm(Op.getImm() & 0xFFFFFFFF);
1591 if (SubIdx == AMDGPU::sub1)
1592 return MachineOperand::CreateImm(Op.getImm() >> 32);
1594 llvm_unreachable("Unhandled register index for immediate");
1597 unsigned SubReg = buildExtractSubReg(MII, MRI, Op, SuperRC,
1599 return MachineOperand::CreateReg(SubReg, false);
1602 // Change the order of operands from (0, 1, 2) to (0, 2, 1)
1603 void SIInstrInfo::swapOperands(MachineBasicBlock::iterator Inst) const {
1604 assert(Inst->getNumExplicitOperands() == 3);
1605 MachineOperand Op1 = Inst->getOperand(1);
1606 Inst->RemoveOperand(1);
1607 Inst->addOperand(Op1);
1610 bool SIInstrInfo::isOperandLegal(const MachineInstr *MI, unsigned OpIdx,
1611 const MachineOperand *MO) const {
1612 const MachineRegisterInfo &MRI = MI->getParent()->getParent()->getRegInfo();
1613 const MCInstrDesc &InstDesc = get(MI->getOpcode());
1614 const MCOperandInfo &OpInfo = InstDesc.OpInfo[OpIdx];
1615 const TargetRegisterClass *DefinedRC =
1616 OpInfo.RegClass != -1 ? RI.getRegClass(OpInfo.RegClass) : nullptr;
1618 MO = &MI->getOperand(OpIdx);
1620 if (isVALU(InstDesc.Opcode) &&
1621 usesConstantBus(MRI, *MO, DefinedRC->getSize())) {
1623 MO->isReg() ? MO->getReg() : (unsigned)AMDGPU::NoRegister;
1624 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1627 const MachineOperand &Op = MI->getOperand(i);
1628 if (Op.isReg() && Op.getReg() != SGPRUsed &&
1629 usesConstantBus(MRI, Op, getOpSize(*MI, i))) {
1637 const TargetRegisterClass *RC =
1638 TargetRegisterInfo::isVirtualRegister(MO->getReg()) ?
1639 MRI.getRegClass(MO->getReg()) :
1640 RI.getPhysRegClass(MO->getReg());
1642 // In order to be legal, the common sub-class must be equal to the
1643 // class of the current operand. For example:
1645 // v_mov_b32 s0 ; Operand defined as vsrc_32
1646 // ; RI.getCommonSubClass(s0,vsrc_32) = sgpr ; LEGAL
1648 // s_sendmsg 0, s0 ; Operand defined as m0reg
1649 // ; RI.getCommonSubClass(s0,m0reg) = m0reg ; NOT LEGAL
1651 return RI.getCommonSubClass(RC, RI.getRegClass(OpInfo.RegClass)) == RC;
1655 // Handle non-register types that are treated like immediates.
1656 assert(MO->isImm() || MO->isTargetIndex() || MO->isFI());
1659 // This operand expects an immediate.
1663 return isImmOperandLegal(MI, OpIdx, *MO);
1666 void SIInstrInfo::legalizeOperands(MachineInstr *MI) const {
1667 MachineRegisterInfo &MRI = MI->getParent()->getParent()->getRegInfo();
1669 int Src0Idx = AMDGPU::getNamedOperandIdx(MI->getOpcode(),
1670 AMDGPU::OpName::src0);
1671 int Src1Idx = AMDGPU::getNamedOperandIdx(MI->getOpcode(),
1672 AMDGPU::OpName::src1);
1673 int Src2Idx = AMDGPU::getNamedOperandIdx(MI->getOpcode(),
1674 AMDGPU::OpName::src2);
1677 if (isVOP2(MI->getOpcode()) && Src1Idx != -1) {
1679 if (!isOperandLegal(MI, Src0Idx))
1680 legalizeOpWithMove(MI, Src0Idx);
1683 if (isOperandLegal(MI, Src1Idx))
1686 // Usually src0 of VOP2 instructions allow more types of inputs
1687 // than src1, so try to commute the instruction to decrease our
1688 // chances of having to insert a MOV instruction to legalize src1.
1689 if (MI->isCommutable()) {
1690 if (commuteInstruction(MI))
1691 // If we are successful in commuting, then we know MI is legal, so
1696 legalizeOpWithMove(MI, Src1Idx);
1700 // XXX - Do any VOP3 instructions read VCC?
1702 if (isVOP3(MI->getOpcode())) {
1703 int VOP3Idx[3] = { Src0Idx, Src1Idx, Src2Idx };
1705 // Find the one SGPR operand we are allowed to use.
1706 unsigned SGPRReg = findUsedSGPR(MI, VOP3Idx);
1708 for (unsigned i = 0; i < 3; ++i) {
1709 int Idx = VOP3Idx[i];
1712 MachineOperand &MO = MI->getOperand(Idx);
1715 if (!RI.isSGPRClass(MRI.getRegClass(MO.getReg())))
1716 continue; // VGPRs are legal
1718 assert(MO.getReg() != AMDGPU::SCC && "SCC operand to VOP3 instruction");
1720 if (SGPRReg == AMDGPU::NoRegister || SGPRReg == MO.getReg()) {
1721 SGPRReg = MO.getReg();
1722 // We can use one SGPR in each VOP3 instruction.
1725 } else if (!isLiteralConstant(MO, getOpSize(MI->getOpcode(), Idx))) {
1726 // If it is not a register and not a literal constant, then it must be
1727 // an inline constant which is always legal.
1730 // If we make it this far, then the operand is not legal and we must
1732 legalizeOpWithMove(MI, Idx);
1736 // Legalize REG_SEQUENCE and PHI
1737 // The register class of the operands much be the same type as the register
1738 // class of the output.
1739 if (MI->getOpcode() == AMDGPU::REG_SEQUENCE ||
1740 MI->getOpcode() == AMDGPU::PHI) {
1741 const TargetRegisterClass *RC = nullptr, *SRC = nullptr, *VRC = nullptr;
1742 for (unsigned i = 1, e = MI->getNumOperands(); i != e; i+=2) {
1743 if (!MI->getOperand(i).isReg() ||
1744 !TargetRegisterInfo::isVirtualRegister(MI->getOperand(i).getReg()))
1746 const TargetRegisterClass *OpRC =
1747 MRI.getRegClass(MI->getOperand(i).getReg());
1748 if (RI.hasVGPRs(OpRC)) {
1755 // If any of the operands are VGPR registers, then they all most be
1756 // otherwise we will create illegal VGPR->SGPR copies when legalizing
1758 if (VRC || !RI.isSGPRClass(getOpRegClass(*MI, 0))) {
1761 VRC = RI.getEquivalentVGPRClass(SRC);
1768 // Update all the operands so they have the same type.
1769 for (unsigned i = 1, e = MI->getNumOperands(); i != e; i+=2) {
1770 if (!MI->getOperand(i).isReg() ||
1771 !TargetRegisterInfo::isVirtualRegister(MI->getOperand(i).getReg()))
1773 unsigned DstReg = MRI.createVirtualRegister(RC);
1774 MachineBasicBlock *InsertBB;
1775 MachineBasicBlock::iterator Insert;
1776 if (MI->getOpcode() == AMDGPU::REG_SEQUENCE) {
1777 InsertBB = MI->getParent();
1780 // MI is a PHI instruction.
1781 InsertBB = MI->getOperand(i + 1).getMBB();
1782 Insert = InsertBB->getFirstTerminator();
1784 BuildMI(*InsertBB, Insert, MI->getDebugLoc(),
1785 get(AMDGPU::COPY), DstReg)
1786 .addOperand(MI->getOperand(i));
1787 MI->getOperand(i).setReg(DstReg);
1791 // Legalize INSERT_SUBREG
1792 // src0 must have the same register class as dst
1793 if (MI->getOpcode() == AMDGPU::INSERT_SUBREG) {
1794 unsigned Dst = MI->getOperand(0).getReg();
1795 unsigned Src0 = MI->getOperand(1).getReg();
1796 const TargetRegisterClass *DstRC = MRI.getRegClass(Dst);
1797 const TargetRegisterClass *Src0RC = MRI.getRegClass(Src0);
1798 if (DstRC != Src0RC) {
1799 MachineBasicBlock &MBB = *MI->getParent();
1800 unsigned NewSrc0 = MRI.createVirtualRegister(DstRC);
1801 BuildMI(MBB, MI, MI->getDebugLoc(), get(AMDGPU::COPY), NewSrc0)
1803 MI->getOperand(1).setReg(NewSrc0);
1808 // Legalize MUBUF* instructions
1809 // FIXME: If we start using the non-addr64 instructions for compute, we
1810 // may need to legalize them here.
1812 AMDGPU::getNamedOperandIdx(MI->getOpcode(), AMDGPU::OpName::srsrc);
1813 if (SRsrcIdx != -1) {
1814 // We have an MUBUF instruction
1815 MachineOperand *SRsrc = &MI->getOperand(SRsrcIdx);
1816 unsigned SRsrcRC = get(MI->getOpcode()).OpInfo[SRsrcIdx].RegClass;
1817 if (RI.getCommonSubClass(MRI.getRegClass(SRsrc->getReg()),
1818 RI.getRegClass(SRsrcRC))) {
1819 // The operands are legal.
1820 // FIXME: We may need to legalize operands besided srsrc.
1824 MachineBasicBlock &MBB = *MI->getParent();
1826 // Extract the ptr from the resource descriptor.
1827 unsigned SRsrcPtr = buildExtractSubReg(MI, MRI, *SRsrc,
1828 &AMDGPU::VReg_128RegClass, AMDGPU::sub0_sub1, &AMDGPU::VReg_64RegClass);
1830 // Create an empty resource descriptor
1831 unsigned Zero64 = MRI.createVirtualRegister(&AMDGPU::SReg_64RegClass);
1832 unsigned SRsrcFormatLo = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
1833 unsigned SRsrcFormatHi = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
1834 unsigned NewSRsrc = MRI.createVirtualRegister(&AMDGPU::SReg_128RegClass);
1835 uint64_t RsrcDataFormat = getDefaultRsrcDataFormat();
1838 BuildMI(MBB, MI, MI->getDebugLoc(), get(AMDGPU::S_MOV_B64),
1842 // SRsrcFormatLo = RSRC_DATA_FORMAT{31-0}
1843 BuildMI(MBB, MI, MI->getDebugLoc(), get(AMDGPU::S_MOV_B32),
1845 .addImm(RsrcDataFormat & 0xFFFFFFFF);
1847 // SRsrcFormatHi = RSRC_DATA_FORMAT{63-32}
1848 BuildMI(MBB, MI, MI->getDebugLoc(), get(AMDGPU::S_MOV_B32),
1850 .addImm(RsrcDataFormat >> 32);
1852 // NewSRsrc = {Zero64, SRsrcFormat}
1853 BuildMI(MBB, MI, MI->getDebugLoc(), get(AMDGPU::REG_SEQUENCE), NewSRsrc)
1855 .addImm(AMDGPU::sub0_sub1)
1856 .addReg(SRsrcFormatLo)
1857 .addImm(AMDGPU::sub2)
1858 .addReg(SRsrcFormatHi)
1859 .addImm(AMDGPU::sub3);
1861 MachineOperand *VAddr = getNamedOperand(*MI, AMDGPU::OpName::vaddr);
1862 unsigned NewVAddr = MRI.createVirtualRegister(&AMDGPU::VReg_64RegClass);
1864 // This is already an ADDR64 instruction so we need to add the pointer
1865 // extracted from the resource descriptor to the current value of VAddr.
1866 unsigned NewVAddrLo = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
1867 unsigned NewVAddrHi = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
1869 // NewVaddrLo = SRsrcPtr:sub0 + VAddr:sub0
1870 DebugLoc DL = MI->getDebugLoc();
1871 BuildMI(MBB, MI, DL, get(AMDGPU::V_ADD_I32_e32), NewVAddrLo)
1872 .addReg(SRsrcPtr, 0, AMDGPU::sub0)
1873 .addReg(VAddr->getReg(), 0, AMDGPU::sub0);
1875 // NewVaddrHi = SRsrcPtr:sub1 + VAddr:sub1
1876 BuildMI(MBB, MI, DL, get(AMDGPU::V_ADDC_U32_e32), NewVAddrHi)
1877 .addReg(SRsrcPtr, 0, AMDGPU::sub1)
1878 .addReg(VAddr->getReg(), 0, AMDGPU::sub1);
1880 // NewVaddr = {NewVaddrHi, NewVaddrLo}
1881 BuildMI(MBB, MI, MI->getDebugLoc(), get(AMDGPU::REG_SEQUENCE), NewVAddr)
1883 .addImm(AMDGPU::sub0)
1885 .addImm(AMDGPU::sub1);
1887 // This instructions is the _OFFSET variant, so we need to convert it to
1889 MachineOperand *VData = getNamedOperand(*MI, AMDGPU::OpName::vdata);
1890 MachineOperand *Offset = getNamedOperand(*MI, AMDGPU::OpName::offset);
1891 MachineOperand *SOffset = getNamedOperand(*MI, AMDGPU::OpName::soffset);
1893 // Create the new instruction.
1894 unsigned Addr64Opcode = AMDGPU::getAddr64Inst(MI->getOpcode());
1895 MachineInstr *Addr64 =
1896 BuildMI(MBB, MI, MI->getDebugLoc(), get(Addr64Opcode))
1898 .addReg(AMDGPU::NoRegister) // Dummy value for vaddr.
1899 // This will be replaced later
1900 // with the new value of vaddr.
1902 .addOperand(*SOffset)
1903 .addOperand(*Offset)
1907 .setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
1909 MI->removeFromParent();
1912 // NewVaddr = {NewVaddrHi, NewVaddrLo}
1913 BuildMI(MBB, MI, MI->getDebugLoc(), get(AMDGPU::REG_SEQUENCE), NewVAddr)
1914 .addReg(SRsrcPtr, 0, AMDGPU::sub0)
1915 .addImm(AMDGPU::sub0)
1916 .addReg(SRsrcPtr, 0, AMDGPU::sub1)
1917 .addImm(AMDGPU::sub1);
1919 VAddr = getNamedOperand(*MI, AMDGPU::OpName::vaddr);
1920 SRsrc = getNamedOperand(*MI, AMDGPU::OpName::srsrc);
1923 // Update the instruction to use NewVaddr
1924 VAddr->setReg(NewVAddr);
1925 // Update the instruction to use NewSRsrc
1926 SRsrc->setReg(NewSRsrc);
1930 void SIInstrInfo::splitSMRD(MachineInstr *MI,
1931 const TargetRegisterClass *HalfRC,
1932 unsigned HalfImmOp, unsigned HalfSGPROp,
1933 MachineInstr *&Lo, MachineInstr *&Hi) const {
1935 DebugLoc DL = MI->getDebugLoc();
1936 MachineBasicBlock *MBB = MI->getParent();
1937 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
1938 unsigned RegLo = MRI.createVirtualRegister(HalfRC);
1939 unsigned RegHi = MRI.createVirtualRegister(HalfRC);
1940 unsigned HalfSize = HalfRC->getSize();
1941 const MachineOperand *OffOp =
1942 getNamedOperand(*MI, AMDGPU::OpName::offset);
1943 const MachineOperand *SBase = getNamedOperand(*MI, AMDGPU::OpName::sbase);
1945 // The SMRD has an 8-bit offset in dwords on SI and a 20-bit offset in bytes
1948 bool IsKill = SBase->isKill();
1951 MBB->getParent()->getSubtarget<AMDGPUSubtarget>().getGeneration() >=
1952 AMDGPUSubtarget::VOLCANIC_ISLANDS;
1953 unsigned OffScale = isVI ? 1 : 4;
1954 // Handle the _IMM variant
1955 unsigned LoOffset = OffOp->getImm() * OffScale;
1956 unsigned HiOffset = LoOffset + HalfSize;
1957 Lo = BuildMI(*MBB, MI, DL, get(HalfImmOp), RegLo)
1958 // Use addReg instead of addOperand
1959 // to make sure kill flag is cleared.
1960 .addReg(SBase->getReg(), 0, SBase->getSubReg())
1961 .addImm(LoOffset / OffScale);
1963 if (!isUInt<20>(HiOffset) || (!isVI && !isUInt<8>(HiOffset / OffScale))) {
1964 unsigned OffsetSGPR =
1965 MRI.createVirtualRegister(&AMDGPU::SReg_32RegClass);
1966 BuildMI(*MBB, MI, DL, get(AMDGPU::S_MOV_B32), OffsetSGPR)
1967 .addImm(HiOffset); // The offset in register is in bytes.
1968 Hi = BuildMI(*MBB, MI, DL, get(HalfSGPROp), RegHi)
1969 .addReg(SBase->getReg(), getKillRegState(IsKill),
1971 .addReg(OffsetSGPR);
1973 Hi = BuildMI(*MBB, MI, DL, get(HalfImmOp), RegHi)
1974 .addReg(SBase->getReg(), getKillRegState(IsKill),
1976 .addImm(HiOffset / OffScale);
1979 // Handle the _SGPR variant
1980 MachineOperand *SOff = getNamedOperand(*MI, AMDGPU::OpName::soff);
1981 Lo = BuildMI(*MBB, MI, DL, get(HalfSGPROp), RegLo)
1982 .addReg(SBase->getReg(), 0, SBase->getSubReg())
1984 unsigned OffsetSGPR = MRI.createVirtualRegister(&AMDGPU::SReg_32RegClass);
1985 BuildMI(*MBB, MI, DL, get(AMDGPU::S_ADD_I32), OffsetSGPR)
1988 Hi = BuildMI(*MBB, MI, DL, get(HalfSGPROp))
1989 .addReg(SBase->getReg(), getKillRegState(IsKill),
1991 .addReg(OffsetSGPR);
1994 unsigned SubLo, SubHi;
1997 SubLo = AMDGPU::sub0;
1998 SubHi = AMDGPU::sub1;
2001 SubLo = AMDGPU::sub0_sub1;
2002 SubHi = AMDGPU::sub2_sub3;
2005 SubLo = AMDGPU::sub0_sub1_sub2_sub3;
2006 SubHi = AMDGPU::sub4_sub5_sub6_sub7;
2009 SubLo = AMDGPU::sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7;
2010 SubHi = AMDGPU::sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15;
2013 llvm_unreachable("Unhandled HalfSize");
2016 BuildMI(*MBB, MI, DL, get(AMDGPU::REG_SEQUENCE))
2017 .addOperand(MI->getOperand(0))
2024 void SIInstrInfo::moveSMRDToVALU(MachineInstr *MI, MachineRegisterInfo &MRI) const {
2025 MachineBasicBlock *MBB = MI->getParent();
2026 int DstIdx = AMDGPU::getNamedOperandIdx(MI->getOpcode(), AMDGPU::OpName::dst);
2027 assert(DstIdx != -1);
2028 unsigned DstRCID = get(MI->getOpcode()).OpInfo[DstIdx].RegClass;
2029 switch(RI.getRegClass(DstRCID)->getSize()) {
2033 unsigned NewOpcode = getVALUOp(*MI);
2037 if (MI->getOperand(2).isReg()) {
2038 RegOffset = MI->getOperand(2).getReg();
2041 assert(MI->getOperand(2).isImm());
2042 // SMRD instructions take a dword offsets on SI and byte offset on VI
2043 // and MUBUF instructions always take a byte offset.
2044 ImmOffset = MI->getOperand(2).getImm();
2045 if (MBB->getParent()->getSubtarget<AMDGPUSubtarget>().getGeneration() <=
2046 AMDGPUSubtarget::SEA_ISLANDS)
2048 RegOffset = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
2050 if (isUInt<12>(ImmOffset)) {
2051 BuildMI(*MBB, MI, MI->getDebugLoc(), get(AMDGPU::S_MOV_B32),
2055 BuildMI(*MBB, MI, MI->getDebugLoc(), get(AMDGPU::S_MOV_B32),
2062 unsigned SRsrc = MRI.createVirtualRegister(&AMDGPU::SReg_128RegClass);
2063 unsigned DWord0 = RegOffset;
2064 unsigned DWord1 = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
2065 unsigned DWord2 = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
2066 unsigned DWord3 = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
2067 uint64_t RsrcDataFormat = getDefaultRsrcDataFormat();
2069 BuildMI(*MBB, MI, MI->getDebugLoc(), get(AMDGPU::S_MOV_B32), DWord1)
2071 BuildMI(*MBB, MI, MI->getDebugLoc(), get(AMDGPU::S_MOV_B32), DWord2)
2072 .addImm(RsrcDataFormat & 0xFFFFFFFF);
2073 BuildMI(*MBB, MI, MI->getDebugLoc(), get(AMDGPU::S_MOV_B32), DWord3)
2074 .addImm(RsrcDataFormat >> 32);
2075 BuildMI(*MBB, MI, MI->getDebugLoc(), get(AMDGPU::REG_SEQUENCE), SRsrc)
2077 .addImm(AMDGPU::sub0)
2079 .addImm(AMDGPU::sub1)
2081 .addImm(AMDGPU::sub2)
2083 .addImm(AMDGPU::sub3);
2084 MI->setDesc(get(NewOpcode));
2085 if (MI->getOperand(2).isReg()) {
2086 MI->getOperand(2).setReg(SRsrc);
2088 MI->getOperand(2).ChangeToRegister(SRsrc, false);
2090 MI->addOperand(*MBB->getParent(), MachineOperand::CreateImm(0));
2091 MI->addOperand(*MBB->getParent(), MachineOperand::CreateImm(ImmOffset));
2092 MI->addOperand(*MBB->getParent(), MachineOperand::CreateImm(0)); // glc
2093 MI->addOperand(*MBB->getParent(), MachineOperand::CreateImm(0)); // slc
2094 MI->addOperand(*MBB->getParent(), MachineOperand::CreateImm(0)); // tfe
2096 const TargetRegisterClass *NewDstRC =
2097 RI.getRegClass(get(NewOpcode).OpInfo[0].RegClass);
2099 unsigned DstReg = MI->getOperand(0).getReg();
2100 unsigned NewDstReg = MRI.createVirtualRegister(NewDstRC);
2101 MRI.replaceRegWith(DstReg, NewDstReg);
2105 MachineInstr *Lo, *Hi;
2106 splitSMRD(MI, &AMDGPU::SReg_128RegClass, AMDGPU::S_LOAD_DWORDX4_IMM,
2107 AMDGPU::S_LOAD_DWORDX4_SGPR, Lo, Hi);
2108 MI->eraseFromParent();
2109 moveSMRDToVALU(Lo, MRI);
2110 moveSMRDToVALU(Hi, MRI);
2115 MachineInstr *Lo, *Hi;
2116 splitSMRD(MI, &AMDGPU::SReg_256RegClass, AMDGPU::S_LOAD_DWORDX8_IMM,
2117 AMDGPU::S_LOAD_DWORDX8_SGPR, Lo, Hi);
2118 MI->eraseFromParent();
2119 moveSMRDToVALU(Lo, MRI);
2120 moveSMRDToVALU(Hi, MRI);
2126 void SIInstrInfo::moveToVALU(MachineInstr &TopInst) const {
2127 SmallVector<MachineInstr *, 128> Worklist;
2128 Worklist.push_back(&TopInst);
2130 while (!Worklist.empty()) {
2131 MachineInstr *Inst = Worklist.pop_back_val();
2132 MachineBasicBlock *MBB = Inst->getParent();
2133 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
2135 unsigned Opcode = Inst->getOpcode();
2136 unsigned NewOpcode = getVALUOp(*Inst);
2138 // Handle some special cases
2141 if (isSMRD(Inst->getOpcode())) {
2142 moveSMRDToVALU(Inst, MRI);
2145 case AMDGPU::S_AND_B64:
2146 splitScalar64BitBinaryOp(Worklist, Inst, AMDGPU::V_AND_B32_e64);
2147 Inst->eraseFromParent();
2150 case AMDGPU::S_OR_B64:
2151 splitScalar64BitBinaryOp(Worklist, Inst, AMDGPU::V_OR_B32_e64);
2152 Inst->eraseFromParent();
2155 case AMDGPU::S_XOR_B64:
2156 splitScalar64BitBinaryOp(Worklist, Inst, AMDGPU::V_XOR_B32_e64);
2157 Inst->eraseFromParent();
2160 case AMDGPU::S_NOT_B64:
2161 splitScalar64BitUnaryOp(Worklist, Inst, AMDGPU::V_NOT_B32_e32);
2162 Inst->eraseFromParent();
2165 case AMDGPU::S_BCNT1_I32_B64:
2166 splitScalar64BitBCNT(Worklist, Inst);
2167 Inst->eraseFromParent();
2170 case AMDGPU::S_BFE_I64: {
2171 splitScalar64BitBFE(Worklist, Inst);
2172 Inst->eraseFromParent();
2176 case AMDGPU::S_LSHL_B32:
2177 if (ST.getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS) {
2178 NewOpcode = AMDGPU::V_LSHLREV_B32_e64;
2182 case AMDGPU::S_ASHR_I32:
2183 if (ST.getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS) {
2184 NewOpcode = AMDGPU::V_ASHRREV_I32_e64;
2188 case AMDGPU::S_LSHR_B32:
2189 if (ST.getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS) {
2190 NewOpcode = AMDGPU::V_LSHRREV_B32_e64;
2194 case AMDGPU::S_LSHL_B64:
2195 if (ST.getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS) {
2196 NewOpcode = AMDGPU::V_LSHLREV_B64;
2200 case AMDGPU::S_ASHR_I64:
2201 if (ST.getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS) {
2202 NewOpcode = AMDGPU::V_ASHRREV_I64;
2206 case AMDGPU::S_LSHR_B64:
2207 if (ST.getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS) {
2208 NewOpcode = AMDGPU::V_LSHRREV_B64;
2213 case AMDGPU::S_BFE_U64:
2214 case AMDGPU::S_BFM_B64:
2215 llvm_unreachable("Moving this op to VALU not implemented");
2218 if (NewOpcode == AMDGPU::INSTRUCTION_LIST_END) {
2219 // We cannot move this instruction to the VALU, so we should try to
2220 // legalize its operands instead.
2221 legalizeOperands(Inst);
2225 // Use the new VALU Opcode.
2226 const MCInstrDesc &NewDesc = get(NewOpcode);
2227 Inst->setDesc(NewDesc);
2229 // Remove any references to SCC. Vector instructions can't read from it, and
2230 // We're just about to add the implicit use / defs of VCC, and we don't want
2232 for (unsigned i = Inst->getNumOperands() - 1; i > 0; --i) {
2233 MachineOperand &Op = Inst->getOperand(i);
2234 if (Op.isReg() && Op.getReg() == AMDGPU::SCC)
2235 Inst->RemoveOperand(i);
2238 if (Opcode == AMDGPU::S_SEXT_I32_I8 || Opcode == AMDGPU::S_SEXT_I32_I16) {
2239 // We are converting these to a BFE, so we need to add the missing
2240 // operands for the size and offset.
2241 unsigned Size = (Opcode == AMDGPU::S_SEXT_I32_I8) ? 8 : 16;
2242 Inst->addOperand(MachineOperand::CreateImm(0));
2243 Inst->addOperand(MachineOperand::CreateImm(Size));
2245 } else if (Opcode == AMDGPU::S_BCNT1_I32_B32) {
2246 // The VALU version adds the second operand to the result, so insert an
2248 Inst->addOperand(MachineOperand::CreateImm(0));
2251 Inst->addImplicitDefUseOperands(*Inst->getParent()->getParent());
2253 if (Opcode == AMDGPU::S_BFE_I32 || Opcode == AMDGPU::S_BFE_U32) {
2254 const MachineOperand &OffsetWidthOp = Inst->getOperand(2);
2255 // If we need to move this to VGPRs, we need to unpack the second operand
2256 // back into the 2 separate ones for bit offset and width.
2257 assert(OffsetWidthOp.isImm() &&
2258 "Scalar BFE is only implemented for constant width and offset");
2259 uint32_t Imm = OffsetWidthOp.getImm();
2261 uint32_t Offset = Imm & 0x3f; // Extract bits [5:0].
2262 uint32_t BitWidth = (Imm & 0x7f0000) >> 16; // Extract bits [22:16].
2263 Inst->RemoveOperand(2); // Remove old immediate.
2264 Inst->addOperand(MachineOperand::CreateImm(Offset));
2265 Inst->addOperand(MachineOperand::CreateImm(BitWidth));
2268 // Update the destination register class.
2270 const TargetRegisterClass *NewDstRC = getOpRegClass(*Inst, 0);
2273 // For target instructions, getOpRegClass just returns the virtual
2274 // register class associated with the operand, so we need to find an
2275 // equivalent VGPR register class in order to move the instruction to the
2279 case AMDGPU::REG_SEQUENCE:
2280 case AMDGPU::INSERT_SUBREG:
2281 if (RI.hasVGPRs(NewDstRC))
2283 NewDstRC = RI.getEquivalentVGPRClass(NewDstRC);
2291 unsigned DstReg = Inst->getOperand(0).getReg();
2292 unsigned NewDstReg = MRI.createVirtualRegister(NewDstRC);
2293 MRI.replaceRegWith(DstReg, NewDstReg);
2295 // Legalize the operands
2296 legalizeOperands(Inst);
2298 addUsersToMoveToVALUWorklist(NewDstReg, MRI, Worklist);
2302 //===----------------------------------------------------------------------===//
2303 // Indirect addressing callbacks
2304 //===----------------------------------------------------------------------===//
2306 unsigned SIInstrInfo::calculateIndirectAddress(unsigned RegIndex,
2307 unsigned Channel) const {
2308 assert(Channel == 0);
2312 const TargetRegisterClass *SIInstrInfo::getIndirectAddrRegClass() const {
2313 return &AMDGPU::VGPR_32RegClass;
2316 void SIInstrInfo::splitScalar64BitUnaryOp(
2317 SmallVectorImpl<MachineInstr *> &Worklist,
2319 unsigned Opcode) const {
2320 MachineBasicBlock &MBB = *Inst->getParent();
2321 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
2323 MachineOperand &Dest = Inst->getOperand(0);
2324 MachineOperand &Src0 = Inst->getOperand(1);
2325 DebugLoc DL = Inst->getDebugLoc();
2327 MachineBasicBlock::iterator MII = Inst;
2329 const MCInstrDesc &InstDesc = get(Opcode);
2330 const TargetRegisterClass *Src0RC = Src0.isReg() ?
2331 MRI.getRegClass(Src0.getReg()) :
2332 &AMDGPU::SGPR_32RegClass;
2334 const TargetRegisterClass *Src0SubRC = RI.getSubRegClass(Src0RC, AMDGPU::sub0);
2336 MachineOperand SrcReg0Sub0 = buildExtractSubRegOrImm(MII, MRI, Src0, Src0RC,
2337 AMDGPU::sub0, Src0SubRC);
2339 const TargetRegisterClass *DestRC = MRI.getRegClass(Dest.getReg());
2340 const TargetRegisterClass *NewDestRC = RI.getEquivalentVGPRClass(DestRC);
2341 const TargetRegisterClass *NewDestSubRC = RI.getSubRegClass(NewDestRC, AMDGPU::sub0);
2343 unsigned DestSub0 = MRI.createVirtualRegister(NewDestSubRC);
2344 BuildMI(MBB, MII, DL, InstDesc, DestSub0)
2345 .addOperand(SrcReg0Sub0);
2347 MachineOperand SrcReg0Sub1 = buildExtractSubRegOrImm(MII, MRI, Src0, Src0RC,
2348 AMDGPU::sub1, Src0SubRC);
2350 unsigned DestSub1 = MRI.createVirtualRegister(NewDestSubRC);
2351 BuildMI(MBB, MII, DL, InstDesc, DestSub1)
2352 .addOperand(SrcReg0Sub1);
2354 unsigned FullDestReg = MRI.createVirtualRegister(NewDestRC);
2355 BuildMI(MBB, MII, DL, get(TargetOpcode::REG_SEQUENCE), FullDestReg)
2357 .addImm(AMDGPU::sub0)
2359 .addImm(AMDGPU::sub1);
2361 MRI.replaceRegWith(Dest.getReg(), FullDestReg);
2363 // We don't need to legalizeOperands here because for a single operand, src0
2364 // will support any kind of input.
2366 // Move all users of this moved value.
2367 addUsersToMoveToVALUWorklist(FullDestReg, MRI, Worklist);
2370 void SIInstrInfo::splitScalar64BitBinaryOp(
2371 SmallVectorImpl<MachineInstr *> &Worklist,
2373 unsigned Opcode) const {
2374 MachineBasicBlock &MBB = *Inst->getParent();
2375 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
2377 MachineOperand &Dest = Inst->getOperand(0);
2378 MachineOperand &Src0 = Inst->getOperand(1);
2379 MachineOperand &Src1 = Inst->getOperand(2);
2380 DebugLoc DL = Inst->getDebugLoc();
2382 MachineBasicBlock::iterator MII = Inst;
2384 const MCInstrDesc &InstDesc = get(Opcode);
2385 const TargetRegisterClass *Src0RC = Src0.isReg() ?
2386 MRI.getRegClass(Src0.getReg()) :
2387 &AMDGPU::SGPR_32RegClass;
2389 const TargetRegisterClass *Src0SubRC = RI.getSubRegClass(Src0RC, AMDGPU::sub0);
2390 const TargetRegisterClass *Src1RC = Src1.isReg() ?
2391 MRI.getRegClass(Src1.getReg()) :
2392 &AMDGPU::SGPR_32RegClass;
2394 const TargetRegisterClass *Src1SubRC = RI.getSubRegClass(Src1RC, AMDGPU::sub0);
2396 MachineOperand SrcReg0Sub0 = buildExtractSubRegOrImm(MII, MRI, Src0, Src0RC,
2397 AMDGPU::sub0, Src0SubRC);
2398 MachineOperand SrcReg1Sub0 = buildExtractSubRegOrImm(MII, MRI, Src1, Src1RC,
2399 AMDGPU::sub0, Src1SubRC);
2401 const TargetRegisterClass *DestRC = MRI.getRegClass(Dest.getReg());
2402 const TargetRegisterClass *NewDestRC = RI.getEquivalentVGPRClass(DestRC);
2403 const TargetRegisterClass *NewDestSubRC = RI.getSubRegClass(NewDestRC, AMDGPU::sub0);
2405 unsigned DestSub0 = MRI.createVirtualRegister(NewDestSubRC);
2406 MachineInstr *LoHalf = BuildMI(MBB, MII, DL, InstDesc, DestSub0)
2407 .addOperand(SrcReg0Sub0)
2408 .addOperand(SrcReg1Sub0);
2410 MachineOperand SrcReg0Sub1 = buildExtractSubRegOrImm(MII, MRI, Src0, Src0RC,
2411 AMDGPU::sub1, Src0SubRC);
2412 MachineOperand SrcReg1Sub1 = buildExtractSubRegOrImm(MII, MRI, Src1, Src1RC,
2413 AMDGPU::sub1, Src1SubRC);
2415 unsigned DestSub1 = MRI.createVirtualRegister(NewDestSubRC);
2416 MachineInstr *HiHalf = BuildMI(MBB, MII, DL, InstDesc, DestSub1)
2417 .addOperand(SrcReg0Sub1)
2418 .addOperand(SrcReg1Sub1);
2420 unsigned FullDestReg = MRI.createVirtualRegister(NewDestRC);
2421 BuildMI(MBB, MII, DL, get(TargetOpcode::REG_SEQUENCE), FullDestReg)
2423 .addImm(AMDGPU::sub0)
2425 .addImm(AMDGPU::sub1);
2427 MRI.replaceRegWith(Dest.getReg(), FullDestReg);
2429 // Try to legalize the operands in case we need to swap the order to keep it
2431 legalizeOperands(LoHalf);
2432 legalizeOperands(HiHalf);
2434 // Move all users of this moved vlaue.
2435 addUsersToMoveToVALUWorklist(FullDestReg, MRI, Worklist);
2438 void SIInstrInfo::splitScalar64BitBCNT(SmallVectorImpl<MachineInstr *> &Worklist,
2439 MachineInstr *Inst) const {
2440 MachineBasicBlock &MBB = *Inst->getParent();
2441 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
2443 MachineBasicBlock::iterator MII = Inst;
2444 DebugLoc DL = Inst->getDebugLoc();
2446 MachineOperand &Dest = Inst->getOperand(0);
2447 MachineOperand &Src = Inst->getOperand(1);
2449 const MCInstrDesc &InstDesc = get(AMDGPU::V_BCNT_U32_B32_e64);
2450 const TargetRegisterClass *SrcRC = Src.isReg() ?
2451 MRI.getRegClass(Src.getReg()) :
2452 &AMDGPU::SGPR_32RegClass;
2454 unsigned MidReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
2455 unsigned ResultReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
2457 const TargetRegisterClass *SrcSubRC = RI.getSubRegClass(SrcRC, AMDGPU::sub0);
2459 MachineOperand SrcRegSub0 = buildExtractSubRegOrImm(MII, MRI, Src, SrcRC,
2460 AMDGPU::sub0, SrcSubRC);
2461 MachineOperand SrcRegSub1 = buildExtractSubRegOrImm(MII, MRI, Src, SrcRC,
2462 AMDGPU::sub1, SrcSubRC);
2464 BuildMI(MBB, MII, DL, InstDesc, MidReg)
2465 .addOperand(SrcRegSub0)
2468 BuildMI(MBB, MII, DL, InstDesc, ResultReg)
2469 .addOperand(SrcRegSub1)
2472 MRI.replaceRegWith(Dest.getReg(), ResultReg);
2474 // We don't need to legalize operands here. src0 for etiher instruction can be
2475 // an SGPR, and the second input is unused or determined here.
2476 addUsersToMoveToVALUWorklist(ResultReg, MRI, Worklist);
2479 void SIInstrInfo::splitScalar64BitBFE(SmallVectorImpl<MachineInstr *> &Worklist,
2480 MachineInstr *Inst) const {
2481 MachineBasicBlock &MBB = *Inst->getParent();
2482 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
2483 MachineBasicBlock::iterator MII = Inst;
2484 DebugLoc DL = Inst->getDebugLoc();
2486 MachineOperand &Dest = Inst->getOperand(0);
2487 uint32_t Imm = Inst->getOperand(2).getImm();
2488 uint32_t Offset = Imm & 0x3f; // Extract bits [5:0].
2489 uint32_t BitWidth = (Imm & 0x7f0000) >> 16; // Extract bits [22:16].
2493 // Only sext_inreg cases handled.
2494 assert(Inst->getOpcode() == AMDGPU::S_BFE_I64 &&
2499 if (BitWidth < 32) {
2500 unsigned MidRegLo = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
2501 unsigned MidRegHi = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
2502 unsigned ResultReg = MRI.createVirtualRegister(&AMDGPU::VReg_64RegClass);
2504 BuildMI(MBB, MII, DL, get(AMDGPU::V_BFE_I32), MidRegLo)
2505 .addReg(Inst->getOperand(1).getReg(), 0, AMDGPU::sub0)
2509 BuildMI(MBB, MII, DL, get(AMDGPU::V_ASHRREV_I32_e32), MidRegHi)
2513 BuildMI(MBB, MII, DL, get(TargetOpcode::REG_SEQUENCE), ResultReg)
2515 .addImm(AMDGPU::sub0)
2517 .addImm(AMDGPU::sub1);
2519 MRI.replaceRegWith(Dest.getReg(), ResultReg);
2520 addUsersToMoveToVALUWorklist(ResultReg, MRI, Worklist);
2524 MachineOperand &Src = Inst->getOperand(1);
2525 unsigned TmpReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
2526 unsigned ResultReg = MRI.createVirtualRegister(&AMDGPU::VReg_64RegClass);
2528 BuildMI(MBB, MII, DL, get(AMDGPU::V_ASHRREV_I32_e64), TmpReg)
2530 .addReg(Src.getReg(), 0, AMDGPU::sub0);
2532 BuildMI(MBB, MII, DL, get(TargetOpcode::REG_SEQUENCE), ResultReg)
2533 .addReg(Src.getReg(), 0, AMDGPU::sub0)
2534 .addImm(AMDGPU::sub0)
2536 .addImm(AMDGPU::sub1);
2538 MRI.replaceRegWith(Dest.getReg(), ResultReg);
2539 addUsersToMoveToVALUWorklist(ResultReg, MRI, Worklist);
2542 void SIInstrInfo::addUsersToMoveToVALUWorklist(
2544 MachineRegisterInfo &MRI,
2545 SmallVectorImpl<MachineInstr *> &Worklist) const {
2546 for (MachineRegisterInfo::use_iterator I = MRI.use_begin(DstReg),
2547 E = MRI.use_end(); I != E; ++I) {
2548 MachineInstr &UseMI = *I->getParent();
2549 if (!canReadVGPR(UseMI, I.getOperandNo())) {
2550 Worklist.push_back(&UseMI);
2555 unsigned SIInstrInfo::findUsedSGPR(const MachineInstr *MI,
2556 int OpIndices[3]) const {
2557 const MCInstrDesc &Desc = get(MI->getOpcode());
2559 // Find the one SGPR operand we are allowed to use.
2560 unsigned SGPRReg = AMDGPU::NoRegister;
2562 // First we need to consider the instruction's operand requirements before
2563 // legalizing. Some operands are required to be SGPRs, such as implicit uses
2564 // of VCC, but we are still bound by the constant bus requirement to only use
2567 // If the operand's class is an SGPR, we can never move it.
2569 for (const MachineOperand &MO : MI->implicit_operands()) {
2570 // We only care about reads.
2574 if (MO.getReg() == AMDGPU::VCC)
2577 if (MO.getReg() == AMDGPU::FLAT_SCR)
2578 return AMDGPU::FLAT_SCR;
2581 unsigned UsedSGPRs[3] = { AMDGPU::NoRegister };
2582 const MachineRegisterInfo &MRI = MI->getParent()->getParent()->getRegInfo();
2584 for (unsigned i = 0; i < 3; ++i) {
2585 int Idx = OpIndices[i];
2589 const MachineOperand &MO = MI->getOperand(Idx);
2590 if (RI.isSGPRClassID(Desc.OpInfo[Idx].RegClass))
2591 SGPRReg = MO.getReg();
2593 if (MO.isReg() && RI.isSGPRClass(MRI.getRegClass(MO.getReg())))
2594 UsedSGPRs[i] = MO.getReg();
2597 if (SGPRReg != AMDGPU::NoRegister)
2600 // We don't have a required SGPR operand, so we have a bit more freedom in
2601 // selecting operands to move.
2603 // Try to select the most used SGPR. If an SGPR is equal to one of the
2604 // others, we choose that.
2607 // V_FMA_F32 v0, s0, s0, s0 -> No moves
2608 // V_FMA_F32 v0, s0, s1, s0 -> Move s1
2610 if (UsedSGPRs[0] != AMDGPU::NoRegister) {
2611 if (UsedSGPRs[0] == UsedSGPRs[1] || UsedSGPRs[0] == UsedSGPRs[2])
2612 SGPRReg = UsedSGPRs[0];
2615 if (SGPRReg == AMDGPU::NoRegister && UsedSGPRs[1] != AMDGPU::NoRegister) {
2616 if (UsedSGPRs[1] == UsedSGPRs[2])
2617 SGPRReg = UsedSGPRs[1];
2623 MachineInstrBuilder SIInstrInfo::buildIndirectWrite(
2624 MachineBasicBlock *MBB,
2625 MachineBasicBlock::iterator I,
2627 unsigned Address, unsigned OffsetReg) const {
2628 const DebugLoc &DL = MBB->findDebugLoc(I);
2629 unsigned IndirectBaseReg = AMDGPU::VGPR_32RegClass.getRegister(
2630 getIndirectIndexBegin(*MBB->getParent()));
2632 return BuildMI(*MBB, I, DL, get(AMDGPU::SI_INDIRECT_DST_V1))
2633 .addReg(IndirectBaseReg, RegState::Define)
2634 .addOperand(I->getOperand(0))
2635 .addReg(IndirectBaseReg)
2641 MachineInstrBuilder SIInstrInfo::buildIndirectRead(
2642 MachineBasicBlock *MBB,
2643 MachineBasicBlock::iterator I,
2645 unsigned Address, unsigned OffsetReg) const {
2646 const DebugLoc &DL = MBB->findDebugLoc(I);
2647 unsigned IndirectBaseReg = AMDGPU::VGPR_32RegClass.getRegister(
2648 getIndirectIndexBegin(*MBB->getParent()));
2650 return BuildMI(*MBB, I, DL, get(AMDGPU::SI_INDIRECT_SRC))
2651 .addOperand(I->getOperand(0))
2652 .addOperand(I->getOperand(1))
2653 .addReg(IndirectBaseReg)
2659 void SIInstrInfo::reserveIndirectRegisters(BitVector &Reserved,
2660 const MachineFunction &MF) const {
2661 int End = getIndirectIndexEnd(MF);
2662 int Begin = getIndirectIndexBegin(MF);
2668 for (int Index = Begin; Index <= End; ++Index)
2669 Reserved.set(AMDGPU::VGPR_32RegClass.getRegister(Index));
2671 for (int Index = std::max(0, Begin - 1); Index <= End; ++Index)
2672 Reserved.set(AMDGPU::VReg_64RegClass.getRegister(Index));
2674 for (int Index = std::max(0, Begin - 2); Index <= End; ++Index)
2675 Reserved.set(AMDGPU::VReg_96RegClass.getRegister(Index));
2677 for (int Index = std::max(0, Begin - 3); Index <= End; ++Index)
2678 Reserved.set(AMDGPU::VReg_128RegClass.getRegister(Index));
2680 for (int Index = std::max(0, Begin - 7); Index <= End; ++Index)
2681 Reserved.set(AMDGPU::VReg_256RegClass.getRegister(Index));
2683 for (int Index = std::max(0, Begin - 15); Index <= End; ++Index)
2684 Reserved.set(AMDGPU::VReg_512RegClass.getRegister(Index));
2687 MachineOperand *SIInstrInfo::getNamedOperand(MachineInstr &MI,
2688 unsigned OperandName) const {
2689 int Idx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), OperandName);
2693 return &MI.getOperand(Idx);
2696 uint64_t SIInstrInfo::getDefaultRsrcDataFormat() const {
2697 uint64_t RsrcDataFormat = AMDGPU::RSRC_DATA_FORMAT;
2698 if (ST.isAmdHsaOS()) {
2699 RsrcDataFormat |= (1ULL << 56);
2701 if (ST.getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS)
2703 RsrcDataFormat |= (2ULL << 59);
2706 return RsrcDataFormat;