1 //===-- SIInstrInfo.cpp - SI Instruction Information ---------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// \brief SI Implementation of TargetInstrInfo.
13 //===----------------------------------------------------------------------===//
16 #include "SIInstrInfo.h"
17 #include "AMDGPUTargetMachine.h"
18 #include "SIDefines.h"
19 #include "SIMachineFunctionInfo.h"
20 #include "llvm/CodeGen/MachineFrameInfo.h"
21 #include "llvm/CodeGen/MachineInstrBuilder.h"
22 #include "llvm/CodeGen/MachineRegisterInfo.h"
23 #include "llvm/IR/Function.h"
24 #include "llvm/CodeGen/RegisterScavenging.h"
25 #include "llvm/MC/MCInstrDesc.h"
26 #include "llvm/Support/Debug.h"
30 SIInstrInfo::SIInstrInfo(const AMDGPUSubtarget &st)
31 : AMDGPUInstrInfo(st), RI() {}
33 //===----------------------------------------------------------------------===//
34 // TargetInstrInfo callbacks
35 //===----------------------------------------------------------------------===//
37 static unsigned getNumOperandsNoGlue(SDNode *Node) {
38 unsigned N = Node->getNumOperands();
39 while (N && Node->getOperand(N - 1).getValueType() == MVT::Glue)
44 static SDValue findChainOperand(SDNode *Load) {
45 SDValue LastOp = Load->getOperand(getNumOperandsNoGlue(Load) - 1);
46 assert(LastOp.getValueType() == MVT::Other && "Chain missing from load node");
50 /// \brief Returns true if both nodes have the same value for the given
51 /// operand \p Op, or if both nodes do not have this operand.
52 static bool nodesHaveSameOperandValue(SDNode *N0, SDNode* N1, unsigned OpName) {
53 unsigned Opc0 = N0->getMachineOpcode();
54 unsigned Opc1 = N1->getMachineOpcode();
56 int Op0Idx = AMDGPU::getNamedOperandIdx(Opc0, OpName);
57 int Op1Idx = AMDGPU::getNamedOperandIdx(Opc1, OpName);
59 if (Op0Idx == -1 && Op1Idx == -1)
63 if ((Op0Idx == -1 && Op1Idx != -1) ||
64 (Op1Idx == -1 && Op0Idx != -1))
67 // getNamedOperandIdx returns the index for the MachineInstr's operands,
68 // which includes the result as the first operand. We are indexing into the
69 // MachineSDNode's operands, so we need to skip the result operand to get
74 return N0->getOperand(Op0Idx) == N1->getOperand(Op1Idx);
77 bool SIInstrInfo::isReallyTriviallyReMaterializable(const MachineInstr *MI,
78 AliasAnalysis *AA) const {
79 // TODO: The generic check fails for VALU instructions that should be
80 // rematerializable due to implicit reads of exec. We really want all of the
81 // generic logic for this except for this.
82 switch (MI->getOpcode()) {
83 case AMDGPU::V_MOV_B32_e32:
84 case AMDGPU::V_MOV_B32_e64:
85 case AMDGPU::V_MOV_B64_PSEUDO:
92 bool SIInstrInfo::areLoadsFromSameBasePtr(SDNode *Load0, SDNode *Load1,
94 int64_t &Offset1) const {
95 if (!Load0->isMachineOpcode() || !Load1->isMachineOpcode())
98 unsigned Opc0 = Load0->getMachineOpcode();
99 unsigned Opc1 = Load1->getMachineOpcode();
101 // Make sure both are actually loads.
102 if (!get(Opc0).mayLoad() || !get(Opc1).mayLoad())
105 if (isDS(Opc0) && isDS(Opc1)) {
107 // FIXME: Handle this case:
108 if (getNumOperandsNoGlue(Load0) != getNumOperandsNoGlue(Load1))
112 if (Load0->getOperand(1) != Load1->getOperand(1))
116 if (findChainOperand(Load0) != findChainOperand(Load1))
119 // Skip read2 / write2 variants for simplicity.
120 // TODO: We should report true if the used offsets are adjacent (excluded
122 if (AMDGPU::getNamedOperandIdx(Opc0, AMDGPU::OpName::data1) != -1 ||
123 AMDGPU::getNamedOperandIdx(Opc1, AMDGPU::OpName::data1) != -1)
126 Offset0 = cast<ConstantSDNode>(Load0->getOperand(2))->getZExtValue();
127 Offset1 = cast<ConstantSDNode>(Load1->getOperand(2))->getZExtValue();
131 if (isSMRD(Opc0) && isSMRD(Opc1)) {
132 assert(getNumOperandsNoGlue(Load0) == getNumOperandsNoGlue(Load1));
135 if (Load0->getOperand(0) != Load1->getOperand(0))
138 const ConstantSDNode *Load0Offset =
139 dyn_cast<ConstantSDNode>(Load0->getOperand(1));
140 const ConstantSDNode *Load1Offset =
141 dyn_cast<ConstantSDNode>(Load1->getOperand(1));
143 if (!Load0Offset || !Load1Offset)
147 if (findChainOperand(Load0) != findChainOperand(Load1))
150 Offset0 = Load0Offset->getZExtValue();
151 Offset1 = Load1Offset->getZExtValue();
155 // MUBUF and MTBUF can access the same addresses.
156 if ((isMUBUF(Opc0) || isMTBUF(Opc0)) && (isMUBUF(Opc1) || isMTBUF(Opc1))) {
158 // MUBUF and MTBUF have vaddr at different indices.
159 if (!nodesHaveSameOperandValue(Load0, Load1, AMDGPU::OpName::soffset) ||
160 findChainOperand(Load0) != findChainOperand(Load1) ||
161 !nodesHaveSameOperandValue(Load0, Load1, AMDGPU::OpName::vaddr) ||
162 !nodesHaveSameOperandValue(Load0, Load1, AMDGPU::OpName::srsrc))
165 int OffIdx0 = AMDGPU::getNamedOperandIdx(Opc0, AMDGPU::OpName::offset);
166 int OffIdx1 = AMDGPU::getNamedOperandIdx(Opc1, AMDGPU::OpName::offset);
168 if (OffIdx0 == -1 || OffIdx1 == -1)
171 // getNamedOperandIdx returns the index for MachineInstrs. Since they
172 // inlcude the output in the operand list, but SDNodes don't, we need to
173 // subtract the index by one.
177 SDValue Off0 = Load0->getOperand(OffIdx0);
178 SDValue Off1 = Load1->getOperand(OffIdx1);
180 // The offset might be a FrameIndexSDNode.
181 if (!isa<ConstantSDNode>(Off0) || !isa<ConstantSDNode>(Off1))
184 Offset0 = cast<ConstantSDNode>(Off0)->getZExtValue();
185 Offset1 = cast<ConstantSDNode>(Off1)->getZExtValue();
192 static bool isStride64(unsigned Opc) {
194 case AMDGPU::DS_READ2ST64_B32:
195 case AMDGPU::DS_READ2ST64_B64:
196 case AMDGPU::DS_WRITE2ST64_B32:
197 case AMDGPU::DS_WRITE2ST64_B64:
204 bool SIInstrInfo::getMemOpBaseRegImmOfs(MachineInstr *LdSt, unsigned &BaseReg,
206 const TargetRegisterInfo *TRI) const {
207 unsigned Opc = LdSt->getOpcode();
210 const MachineOperand *OffsetImm = getNamedOperand(*LdSt,
211 AMDGPU::OpName::offset);
213 // Normal, single offset LDS instruction.
214 const MachineOperand *AddrReg = getNamedOperand(*LdSt,
215 AMDGPU::OpName::addr);
217 BaseReg = AddrReg->getReg();
218 Offset = OffsetImm->getImm();
222 // The 2 offset instructions use offset0 and offset1 instead. We can treat
223 // these as a load with a single offset if the 2 offsets are consecutive. We
224 // will use this for some partially aligned loads.
225 const MachineOperand *Offset0Imm = getNamedOperand(*LdSt,
226 AMDGPU::OpName::offset0);
227 const MachineOperand *Offset1Imm = getNamedOperand(*LdSt,
228 AMDGPU::OpName::offset1);
230 uint8_t Offset0 = Offset0Imm->getImm();
231 uint8_t Offset1 = Offset1Imm->getImm();
233 if (Offset1 > Offset0 && Offset1 - Offset0 == 1) {
234 // Each of these offsets is in element sized units, so we need to convert
235 // to bytes of the individual reads.
239 EltSize = getOpRegClass(*LdSt, 0)->getSize() / 2;
241 assert(LdSt->mayStore());
242 int Data0Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::data0);
243 EltSize = getOpRegClass(*LdSt, Data0Idx)->getSize();
249 const MachineOperand *AddrReg = getNamedOperand(*LdSt,
250 AMDGPU::OpName::addr);
251 BaseReg = AddrReg->getReg();
252 Offset = EltSize * Offset0;
259 if (isMUBUF(*LdSt) || isMTBUF(*LdSt)) {
260 if (AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::soffset) != -1)
263 const MachineOperand *AddrReg = getNamedOperand(*LdSt,
264 AMDGPU::OpName::vaddr);
268 const MachineOperand *OffsetImm = getNamedOperand(*LdSt,
269 AMDGPU::OpName::offset);
270 BaseReg = AddrReg->getReg();
271 Offset = OffsetImm->getImm();
276 const MachineOperand *OffsetImm = getNamedOperand(*LdSt,
277 AMDGPU::OpName::offset);
281 const MachineOperand *SBaseReg = getNamedOperand(*LdSt,
282 AMDGPU::OpName::sbase);
283 BaseReg = SBaseReg->getReg();
284 Offset = OffsetImm->getImm();
291 bool SIInstrInfo::shouldClusterLoads(MachineInstr *FirstLdSt,
292 MachineInstr *SecondLdSt,
293 unsigned NumLoads) const {
294 // TODO: This needs finer tuning
298 if (isDS(*FirstLdSt) && isDS(*SecondLdSt))
301 if (isSMRD(*FirstLdSt) && isSMRD(*SecondLdSt))
304 if ((isMUBUF(*FirstLdSt) || isMTBUF(*FirstLdSt)) &&
305 (isMUBUF(*SecondLdSt) || isMTBUF(*SecondLdSt)))
312 SIInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
313 MachineBasicBlock::iterator MI, DebugLoc DL,
314 unsigned DestReg, unsigned SrcReg,
315 bool KillSrc) const {
317 // If we are trying to copy to or from SCC, there is a bug somewhere else in
318 // the backend. While it may be theoretically possible to do this, it should
319 // never be necessary.
320 assert(DestReg != AMDGPU::SCC && SrcReg != AMDGPU::SCC);
322 static const int16_t Sub0_15[] = {
323 AMDGPU::sub0, AMDGPU::sub1, AMDGPU::sub2, AMDGPU::sub3,
324 AMDGPU::sub4, AMDGPU::sub5, AMDGPU::sub6, AMDGPU::sub7,
325 AMDGPU::sub8, AMDGPU::sub9, AMDGPU::sub10, AMDGPU::sub11,
326 AMDGPU::sub12, AMDGPU::sub13, AMDGPU::sub14, AMDGPU::sub15, 0
329 static const int16_t Sub0_7[] = {
330 AMDGPU::sub0, AMDGPU::sub1, AMDGPU::sub2, AMDGPU::sub3,
331 AMDGPU::sub4, AMDGPU::sub5, AMDGPU::sub6, AMDGPU::sub7, 0
334 static const int16_t Sub0_3[] = {
335 AMDGPU::sub0, AMDGPU::sub1, AMDGPU::sub2, AMDGPU::sub3, 0
338 static const int16_t Sub0_2[] = {
339 AMDGPU::sub0, AMDGPU::sub1, AMDGPU::sub2, 0
342 static const int16_t Sub0_1[] = {
343 AMDGPU::sub0, AMDGPU::sub1, 0
347 const int16_t *SubIndices;
349 if (AMDGPU::SReg_32RegClass.contains(DestReg)) {
350 assert(AMDGPU::SReg_32RegClass.contains(SrcReg));
351 BuildMI(MBB, MI, DL, get(AMDGPU::S_MOV_B32), DestReg)
352 .addReg(SrcReg, getKillRegState(KillSrc));
355 } else if (AMDGPU::SReg_64RegClass.contains(DestReg)) {
356 if (DestReg == AMDGPU::VCC) {
357 if (AMDGPU::SReg_64RegClass.contains(SrcReg)) {
358 BuildMI(MBB, MI, DL, get(AMDGPU::S_MOV_B64), AMDGPU::VCC)
359 .addReg(SrcReg, getKillRegState(KillSrc));
361 // FIXME: Hack until VReg_1 removed.
362 assert(AMDGPU::VGPR_32RegClass.contains(SrcReg));
363 BuildMI(MBB, MI, DL, get(AMDGPU::V_CMP_NE_I32_e32))
365 .addReg(SrcReg, getKillRegState(KillSrc));
371 assert(AMDGPU::SReg_64RegClass.contains(SrcReg));
372 BuildMI(MBB, MI, DL, get(AMDGPU::S_MOV_B64), DestReg)
373 .addReg(SrcReg, getKillRegState(KillSrc));
376 } else if (AMDGPU::SReg_128RegClass.contains(DestReg)) {
377 assert(AMDGPU::SReg_128RegClass.contains(SrcReg));
378 Opcode = AMDGPU::S_MOV_B32;
381 } else if (AMDGPU::SReg_256RegClass.contains(DestReg)) {
382 assert(AMDGPU::SReg_256RegClass.contains(SrcReg));
383 Opcode = AMDGPU::S_MOV_B32;
386 } else if (AMDGPU::SReg_512RegClass.contains(DestReg)) {
387 assert(AMDGPU::SReg_512RegClass.contains(SrcReg));
388 Opcode = AMDGPU::S_MOV_B32;
389 SubIndices = Sub0_15;
391 } else if (AMDGPU::VGPR_32RegClass.contains(DestReg)) {
392 assert(AMDGPU::VGPR_32RegClass.contains(SrcReg) ||
393 AMDGPU::SReg_32RegClass.contains(SrcReg));
394 BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), DestReg)
395 .addReg(SrcReg, getKillRegState(KillSrc));
398 } else if (AMDGPU::VReg_64RegClass.contains(DestReg)) {
399 assert(AMDGPU::VReg_64RegClass.contains(SrcReg) ||
400 AMDGPU::SReg_64RegClass.contains(SrcReg));
401 Opcode = AMDGPU::V_MOV_B32_e32;
404 } else if (AMDGPU::VReg_96RegClass.contains(DestReg)) {
405 assert(AMDGPU::VReg_96RegClass.contains(SrcReg));
406 Opcode = AMDGPU::V_MOV_B32_e32;
409 } else if (AMDGPU::VReg_128RegClass.contains(DestReg)) {
410 assert(AMDGPU::VReg_128RegClass.contains(SrcReg) ||
411 AMDGPU::SReg_128RegClass.contains(SrcReg));
412 Opcode = AMDGPU::V_MOV_B32_e32;
415 } else if (AMDGPU::VReg_256RegClass.contains(DestReg)) {
416 assert(AMDGPU::VReg_256RegClass.contains(SrcReg) ||
417 AMDGPU::SReg_256RegClass.contains(SrcReg));
418 Opcode = AMDGPU::V_MOV_B32_e32;
421 } else if (AMDGPU::VReg_512RegClass.contains(DestReg)) {
422 assert(AMDGPU::VReg_512RegClass.contains(SrcReg) ||
423 AMDGPU::SReg_512RegClass.contains(SrcReg));
424 Opcode = AMDGPU::V_MOV_B32_e32;
425 SubIndices = Sub0_15;
428 llvm_unreachable("Can't copy register!");
431 while (unsigned SubIdx = *SubIndices++) {
432 MachineInstrBuilder Builder = BuildMI(MBB, MI, DL,
433 get(Opcode), RI.getSubReg(DestReg, SubIdx));
435 Builder.addReg(RI.getSubReg(SrcReg, SubIdx), getKillRegState(KillSrc));
438 Builder.addReg(DestReg, RegState::Define | RegState::Implicit);
442 int SIInstrInfo::commuteOpcode(const MachineInstr &MI) const {
443 const unsigned Opcode = MI.getOpcode();
447 // Try to map original to commuted opcode
448 NewOpc = AMDGPU::getCommuteRev(Opcode);
450 // Check if the commuted (REV) opcode exists on the target.
451 return pseudoToMCOpcode(NewOpc) != -1 ? NewOpc : -1;
453 // Try to map commuted to original opcode
454 NewOpc = AMDGPU::getCommuteOrig(Opcode);
456 // Check if the original (non-REV) opcode exists on the target.
457 return pseudoToMCOpcode(NewOpc) != -1 ? NewOpc : -1;
462 unsigned SIInstrInfo::getMovOpcode(const TargetRegisterClass *DstRC) const {
464 if (DstRC->getSize() == 4) {
465 return RI.isSGPRClass(DstRC) ? AMDGPU::S_MOV_B32 : AMDGPU::V_MOV_B32_e32;
466 } else if (DstRC->getSize() == 8 && RI.isSGPRClass(DstRC)) {
467 return AMDGPU::S_MOV_B64;
468 } else if (DstRC->getSize() == 8 && !RI.isSGPRClass(DstRC)) {
469 return AMDGPU::V_MOV_B64_PSEUDO;
474 static unsigned getSGPRSpillSaveOpcode(unsigned Size) {
477 return AMDGPU::SI_SPILL_S32_SAVE;
479 return AMDGPU::SI_SPILL_S64_SAVE;
481 return AMDGPU::SI_SPILL_S128_SAVE;
483 return AMDGPU::SI_SPILL_S256_SAVE;
485 return AMDGPU::SI_SPILL_S512_SAVE;
487 llvm_unreachable("unknown register size");
491 static unsigned getVGPRSpillSaveOpcode(unsigned Size) {
494 return AMDGPU::SI_SPILL_V32_SAVE;
496 return AMDGPU::SI_SPILL_V64_SAVE;
498 return AMDGPU::SI_SPILL_V128_SAVE;
500 return AMDGPU::SI_SPILL_V256_SAVE;
502 return AMDGPU::SI_SPILL_V512_SAVE;
504 llvm_unreachable("unknown register size");
508 void SIInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
509 MachineBasicBlock::iterator MI,
510 unsigned SrcReg, bool isKill,
512 const TargetRegisterClass *RC,
513 const TargetRegisterInfo *TRI) const {
514 MachineFunction *MF = MBB.getParent();
515 SIMachineFunctionInfo *MFI = MF->getInfo<SIMachineFunctionInfo>();
516 MachineFrameInfo *FrameInfo = MF->getFrameInfo();
517 DebugLoc DL = MBB.findDebugLoc(MI);
519 unsigned Size = FrameInfo->getObjectSize(FrameIndex);
520 unsigned Align = FrameInfo->getObjectAlignment(FrameIndex);
521 MachinePointerInfo PtrInfo
522 = MachinePointerInfo::getFixedStack(*MF, FrameIndex);
523 MachineMemOperand *MMO
524 = MF->getMachineMemOperand(PtrInfo, MachineMemOperand::MOStore,
527 if (RI.isSGPRClass(RC)) {
528 MFI->setHasSpilledSGPRs();
530 // We are only allowed to create one new instruction when spilling
531 // registers, so we need to use pseudo instruction for spilling
533 unsigned Opcode = getSGPRSpillSaveOpcode(RC->getSize());
534 BuildMI(MBB, MI, DL, get(Opcode))
535 .addReg(SrcReg) // src
536 .addFrameIndex(FrameIndex) // frame_idx
542 if (!ST.isVGPRSpillingEnabled(MFI)) {
543 LLVMContext &Ctx = MF->getFunction()->getContext();
544 Ctx.emitError("SIInstrInfo::storeRegToStackSlot - Do not know how to"
546 BuildMI(MBB, MI, DL, get(AMDGPU::KILL))
552 assert(RI.hasVGPRs(RC) && "Only VGPR spilling expected");
554 unsigned Opcode = getVGPRSpillSaveOpcode(RC->getSize());
555 MFI->setHasSpilledVGPRs();
556 BuildMI(MBB, MI, DL, get(Opcode))
557 .addReg(SrcReg) // src
558 .addFrameIndex(FrameIndex) // frame_idx
559 .addReg(MFI->getScratchRSrcReg()) // scratch_rsrc
560 .addReg(MFI->getScratchWaveOffsetReg()) // scratch_offset
564 static unsigned getSGPRSpillRestoreOpcode(unsigned Size) {
567 return AMDGPU::SI_SPILL_S32_RESTORE;
569 return AMDGPU::SI_SPILL_S64_RESTORE;
571 return AMDGPU::SI_SPILL_S128_RESTORE;
573 return AMDGPU::SI_SPILL_S256_RESTORE;
575 return AMDGPU::SI_SPILL_S512_RESTORE;
577 llvm_unreachable("unknown register size");
581 static unsigned getVGPRSpillRestoreOpcode(unsigned Size) {
584 return AMDGPU::SI_SPILL_V32_RESTORE;
586 return AMDGPU::SI_SPILL_V64_RESTORE;
588 return AMDGPU::SI_SPILL_V128_RESTORE;
590 return AMDGPU::SI_SPILL_V256_RESTORE;
592 return AMDGPU::SI_SPILL_V512_RESTORE;
594 llvm_unreachable("unknown register size");
598 void SIInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
599 MachineBasicBlock::iterator MI,
600 unsigned DestReg, int FrameIndex,
601 const TargetRegisterClass *RC,
602 const TargetRegisterInfo *TRI) const {
603 MachineFunction *MF = MBB.getParent();
604 const SIMachineFunctionInfo *MFI = MF->getInfo<SIMachineFunctionInfo>();
605 MachineFrameInfo *FrameInfo = MF->getFrameInfo();
606 DebugLoc DL = MBB.findDebugLoc(MI);
607 unsigned Align = FrameInfo->getObjectAlignment(FrameIndex);
608 unsigned Size = FrameInfo->getObjectSize(FrameIndex);
610 MachinePointerInfo PtrInfo
611 = MachinePointerInfo::getFixedStack(*MF, FrameIndex);
613 MachineMemOperand *MMO = MF->getMachineMemOperand(
614 PtrInfo, MachineMemOperand::MOLoad, Size, Align);
616 if (RI.isSGPRClass(RC)) {
617 // FIXME: Maybe this should not include a memoperand because it will be
618 // lowered to non-memory instructions.
619 unsigned Opcode = getSGPRSpillRestoreOpcode(RC->getSize());
620 BuildMI(MBB, MI, DL, get(Opcode), DestReg)
621 .addFrameIndex(FrameIndex) // frame_idx
627 if (!ST.isVGPRSpillingEnabled(MFI)) {
628 LLVMContext &Ctx = MF->getFunction()->getContext();
629 Ctx.emitError("SIInstrInfo::loadRegFromStackSlot - Do not know how to"
630 " restore register");
631 BuildMI(MBB, MI, DL, get(AMDGPU::IMPLICIT_DEF), DestReg);
636 assert(RI.hasVGPRs(RC) && "Only VGPR spilling expected");
638 unsigned Opcode = getVGPRSpillRestoreOpcode(RC->getSize());
639 BuildMI(MBB, MI, DL, get(Opcode), DestReg)
640 .addFrameIndex(FrameIndex) // frame_idx
641 .addReg(MFI->getScratchRSrcReg()) // scratch_rsrc
642 .addReg(MFI->getScratchWaveOffsetReg()) // scratch_offset
646 /// \param @Offset Offset in bytes of the FrameIndex being spilled
647 unsigned SIInstrInfo::calculateLDSSpillAddress(MachineBasicBlock &MBB,
648 MachineBasicBlock::iterator MI,
649 RegScavenger *RS, unsigned TmpReg,
650 unsigned FrameOffset,
651 unsigned Size) const {
652 MachineFunction *MF = MBB.getParent();
653 SIMachineFunctionInfo *MFI = MF->getInfo<SIMachineFunctionInfo>();
654 const AMDGPUSubtarget &ST = MF->getSubtarget<AMDGPUSubtarget>();
655 const SIRegisterInfo *TRI =
656 static_cast<const SIRegisterInfo*>(ST.getRegisterInfo());
657 DebugLoc DL = MBB.findDebugLoc(MI);
658 unsigned WorkGroupSize = MFI->getMaximumWorkGroupSize(*MF);
659 unsigned WavefrontSize = ST.getWavefrontSize();
661 unsigned TIDReg = MFI->getTIDReg();
662 if (!MFI->hasCalculatedTID()) {
663 MachineBasicBlock &Entry = MBB.getParent()->front();
664 MachineBasicBlock::iterator Insert = Entry.front();
665 DebugLoc DL = Insert->getDebugLoc();
667 TIDReg = RI.findUnusedRegister(MF->getRegInfo(), &AMDGPU::VGPR_32RegClass);
668 if (TIDReg == AMDGPU::NoRegister)
672 if (MFI->getShaderType() == ShaderType::COMPUTE &&
673 WorkGroupSize > WavefrontSize) {
676 = TRI->getPreloadedValue(*MF, SIRegisterInfo::WORKGROUP_ID_X);
678 = TRI->getPreloadedValue(*MF, SIRegisterInfo::WORKGROUP_ID_Y);
680 = TRI->getPreloadedValue(*MF, SIRegisterInfo::WORKGROUP_ID_Z);
681 unsigned InputPtrReg =
682 TRI->getPreloadedValue(*MF, SIRegisterInfo::KERNARG_SEGMENT_PTR);
683 for (unsigned Reg : {TIDIGXReg, TIDIGYReg, TIDIGZReg}) {
684 if (!Entry.isLiveIn(Reg))
685 Entry.addLiveIn(Reg);
688 RS->enterBasicBlock(&Entry);
689 // FIXME: Can we scavenge an SReg_64 and access the subregs?
690 unsigned STmp0 = RS->scavengeRegister(&AMDGPU::SGPR_32RegClass, 0);
691 unsigned STmp1 = RS->scavengeRegister(&AMDGPU::SGPR_32RegClass, 0);
692 BuildMI(Entry, Insert, DL, get(AMDGPU::S_LOAD_DWORD_IMM), STmp0)
694 .addImm(SI::KernelInputOffsets::NGROUPS_Z);
695 BuildMI(Entry, Insert, DL, get(AMDGPU::S_LOAD_DWORD_IMM), STmp1)
697 .addImm(SI::KernelInputOffsets::NGROUPS_Y);
699 // NGROUPS.X * NGROUPS.Y
700 BuildMI(Entry, Insert, DL, get(AMDGPU::S_MUL_I32), STmp1)
703 // (NGROUPS.X * NGROUPS.Y) * TIDIG.X
704 BuildMI(Entry, Insert, DL, get(AMDGPU::V_MUL_U32_U24_e32), TIDReg)
707 // NGROUPS.Z * TIDIG.Y + (NGROUPS.X * NGROPUS.Y * TIDIG.X)
708 BuildMI(Entry, Insert, DL, get(AMDGPU::V_MAD_U32_U24), TIDReg)
712 // (NGROUPS.Z * TIDIG.Y + (NGROUPS.X * NGROPUS.Y * TIDIG.X)) + TIDIG.Z
713 BuildMI(Entry, Insert, DL, get(AMDGPU::V_ADD_I32_e32), TIDReg)
718 BuildMI(Entry, Insert, DL, get(AMDGPU::V_MBCNT_LO_U32_B32_e64),
723 BuildMI(Entry, Insert, DL, get(AMDGPU::V_MBCNT_HI_U32_B32_e64),
729 BuildMI(Entry, Insert, DL, get(AMDGPU::V_LSHLREV_B32_e32),
733 MFI->setTIDReg(TIDReg);
736 // Add FrameIndex to LDS offset
737 unsigned LDSOffset = MFI->LDSSize + (FrameOffset * WorkGroupSize);
738 BuildMI(MBB, MI, DL, get(AMDGPU::V_ADD_I32_e32), TmpReg)
745 void SIInstrInfo::insertNOPs(MachineBasicBlock::iterator MI,
754 BuildMI(*MI->getParent(), MI, MI->getDebugLoc(), get(AMDGPU::S_NOP))
759 bool SIInstrInfo::expandPostRAPseudo(MachineBasicBlock::iterator MI) const {
760 MachineBasicBlock &MBB = *MI->getParent();
761 DebugLoc DL = MBB.findDebugLoc(MI);
762 switch (MI->getOpcode()) {
763 default: return AMDGPUInstrInfo::expandPostRAPseudo(MI);
765 case AMDGPU::SI_CONSTDATA_PTR: {
766 unsigned Reg = MI->getOperand(0).getReg();
767 unsigned RegLo = RI.getSubReg(Reg, AMDGPU::sub0);
768 unsigned RegHi = RI.getSubReg(Reg, AMDGPU::sub1);
770 BuildMI(MBB, MI, DL, get(AMDGPU::S_GETPC_B64), Reg);
772 // Add 32-bit offset from this instruction to the start of the constant data.
773 BuildMI(MBB, MI, DL, get(AMDGPU::S_ADD_U32), RegLo)
775 .addTargetIndex(AMDGPU::TI_CONSTDATA_START)
776 .addReg(AMDGPU::SCC, RegState::Define | RegState::Implicit);
777 BuildMI(MBB, MI, DL, get(AMDGPU::S_ADDC_U32), RegHi)
780 .addReg(AMDGPU::SCC, RegState::Define | RegState::Implicit)
781 .addReg(AMDGPU::SCC, RegState::Implicit);
782 MI->eraseFromParent();
785 case AMDGPU::SGPR_USE:
786 // This is just a placeholder for register allocation.
787 MI->eraseFromParent();
790 case AMDGPU::V_MOV_B64_PSEUDO: {
791 unsigned Dst = MI->getOperand(0).getReg();
792 unsigned DstLo = RI.getSubReg(Dst, AMDGPU::sub0);
793 unsigned DstHi = RI.getSubReg(Dst, AMDGPU::sub1);
795 const MachineOperand &SrcOp = MI->getOperand(1);
796 // FIXME: Will this work for 64-bit floating point immediates?
797 assert(!SrcOp.isFPImm());
799 APInt Imm(64, SrcOp.getImm());
800 BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), DstLo)
801 .addImm(Imm.getLoBits(32).getZExtValue())
802 .addReg(Dst, RegState::Implicit);
803 BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), DstHi)
804 .addImm(Imm.getHiBits(32).getZExtValue())
805 .addReg(Dst, RegState::Implicit);
807 assert(SrcOp.isReg());
808 BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), DstLo)
809 .addReg(RI.getSubReg(SrcOp.getReg(), AMDGPU::sub0))
810 .addReg(Dst, RegState::Implicit);
811 BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), DstHi)
812 .addReg(RI.getSubReg(SrcOp.getReg(), AMDGPU::sub1))
813 .addReg(Dst, RegState::Implicit);
815 MI->eraseFromParent();
819 case AMDGPU::V_CNDMASK_B64_PSEUDO: {
820 unsigned Dst = MI->getOperand(0).getReg();
821 unsigned DstLo = RI.getSubReg(Dst, AMDGPU::sub0);
822 unsigned DstHi = RI.getSubReg(Dst, AMDGPU::sub1);
823 unsigned Src0 = MI->getOperand(1).getReg();
824 unsigned Src1 = MI->getOperand(2).getReg();
825 const MachineOperand &SrcCond = MI->getOperand(3);
827 BuildMI(MBB, MI, DL, get(AMDGPU::V_CNDMASK_B32_e64), DstLo)
828 .addReg(RI.getSubReg(Src0, AMDGPU::sub0))
829 .addReg(RI.getSubReg(Src1, AMDGPU::sub0))
830 .addOperand(SrcCond);
831 BuildMI(MBB, MI, DL, get(AMDGPU::V_CNDMASK_B32_e64), DstHi)
832 .addReg(RI.getSubReg(Src0, AMDGPU::sub1))
833 .addReg(RI.getSubReg(Src1, AMDGPU::sub1))
834 .addOperand(SrcCond);
835 MI->eraseFromParent();
842 /// Commutes the operands in the given instruction.
843 /// The commutable operands are specified by their indices OpIdx0 and OpIdx1.
845 /// Do not call this method for a non-commutable instruction or for
846 /// non-commutable pair of operand indices OpIdx0 and OpIdx1.
847 /// Even though the instruction is commutable, the method may still
848 /// fail to commute the operands, null pointer is returned in such cases.
849 MachineInstr *SIInstrInfo::commuteInstructionImpl(MachineInstr *MI,
852 unsigned OpIdx1) const {
853 int CommutedOpcode = commuteOpcode(*MI);
854 if (CommutedOpcode == -1)
857 int Src0Idx = AMDGPU::getNamedOperandIdx(MI->getOpcode(),
858 AMDGPU::OpName::src0);
859 MachineOperand &Src0 = MI->getOperand(Src0Idx);
863 int Src1Idx = AMDGPU::getNamedOperandIdx(MI->getOpcode(),
864 AMDGPU::OpName::src1);
866 if ((OpIdx0 != static_cast<unsigned>(Src0Idx) ||
867 OpIdx1 != static_cast<unsigned>(Src1Idx)) &&
868 (OpIdx0 != static_cast<unsigned>(Src1Idx) ||
869 OpIdx1 != static_cast<unsigned>(Src0Idx)))
872 MachineOperand &Src1 = MI->getOperand(Src1Idx);
874 // Make sure it's legal to commute operands for VOP2.
876 (!isOperandLegal(MI, Src0Idx, &Src1) ||
877 !isOperandLegal(MI, Src1Idx, &Src0))) {
882 // Allow commuting instructions with Imm operands.
883 if (NewMI || !Src1.isImm() ||
884 (!isVOP2(*MI) && !isVOP3(*MI))) {
888 // Be sure to copy the source modifiers to the right place.
889 if (MachineOperand *Src0Mods
890 = getNamedOperand(*MI, AMDGPU::OpName::src0_modifiers)) {
891 MachineOperand *Src1Mods
892 = getNamedOperand(*MI, AMDGPU::OpName::src1_modifiers);
894 int Src0ModsVal = Src0Mods->getImm();
895 if (!Src1Mods && Src0ModsVal != 0)
898 // XXX - This assert might be a lie. It might be useful to have a neg
899 // modifier with 0.0.
900 int Src1ModsVal = Src1Mods->getImm();
901 assert((Src1ModsVal == 0) && "Not expecting modifiers with immediates");
903 Src1Mods->setImm(Src0ModsVal);
904 Src0Mods->setImm(Src1ModsVal);
907 unsigned Reg = Src0.getReg();
908 unsigned SubReg = Src0.getSubReg();
910 Src0.ChangeToImmediate(Src1.getImm());
912 llvm_unreachable("Should only have immediates");
914 Src1.ChangeToRegister(Reg, false);
915 Src1.setSubReg(SubReg);
917 MI = TargetInstrInfo::commuteInstructionImpl(MI, NewMI, OpIdx0, OpIdx1);
921 MI->setDesc(get(CommutedOpcode));
926 // This needs to be implemented because the source modifiers may be inserted
927 // between the true commutable operands, and the base
928 // TargetInstrInfo::commuteInstruction uses it.
929 bool SIInstrInfo::findCommutedOpIndices(MachineInstr *MI,
931 unsigned &SrcOpIdx1) const {
932 const MCInstrDesc &MCID = MI->getDesc();
933 if (!MCID.isCommutable())
936 unsigned Opc = MI->getOpcode();
937 int Src0Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src0);
941 // FIXME: Workaround TargetInstrInfo::commuteInstruction asserting on
942 // immediate. Also, immediate src0 operand is not handled in
943 // SIInstrInfo::commuteInstruction();
944 if (!MI->getOperand(Src0Idx).isReg())
947 int Src1Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src1);
951 MachineOperand &Src1 = MI->getOperand(Src1Idx);
953 // SIInstrInfo::commuteInstruction() does support commuting the immediate
954 // operand src1 in 2 and 3 operand instructions.
955 if (!isVOP2(MI->getOpcode()) && !isVOP3(MI->getOpcode()))
957 } else if (Src1.isReg()) {
958 // If any source modifiers are set, the generic instruction commuting won't
959 // understand how to copy the source modifiers.
960 if (hasModifiersSet(*MI, AMDGPU::OpName::src0_modifiers) ||
961 hasModifiersSet(*MI, AMDGPU::OpName::src1_modifiers))
966 return fixCommutedOpIndices(SrcOpIdx0, SrcOpIdx1, Src0Idx, Src1Idx);
969 MachineInstr *SIInstrInfo::buildMovInstr(MachineBasicBlock *MBB,
970 MachineBasicBlock::iterator I,
972 unsigned SrcReg) const {
973 return BuildMI(*MBB, I, MBB->findDebugLoc(I), get(AMDGPU::V_MOV_B32_e32),
974 DstReg) .addReg(SrcReg);
977 bool SIInstrInfo::isMov(unsigned Opcode) const {
979 default: return false;
980 case AMDGPU::S_MOV_B32:
981 case AMDGPU::S_MOV_B64:
982 case AMDGPU::V_MOV_B32_e32:
983 case AMDGPU::V_MOV_B32_e64:
988 static void removeModOperands(MachineInstr &MI) {
989 unsigned Opc = MI.getOpcode();
990 int Src0ModIdx = AMDGPU::getNamedOperandIdx(Opc,
991 AMDGPU::OpName::src0_modifiers);
992 int Src1ModIdx = AMDGPU::getNamedOperandIdx(Opc,
993 AMDGPU::OpName::src1_modifiers);
994 int Src2ModIdx = AMDGPU::getNamedOperandIdx(Opc,
995 AMDGPU::OpName::src2_modifiers);
997 MI.RemoveOperand(Src2ModIdx);
998 MI.RemoveOperand(Src1ModIdx);
999 MI.RemoveOperand(Src0ModIdx);
1002 bool SIInstrInfo::FoldImmediate(MachineInstr *UseMI, MachineInstr *DefMI,
1003 unsigned Reg, MachineRegisterInfo *MRI) const {
1004 if (!MRI->hasOneNonDBGUse(Reg))
1007 unsigned Opc = UseMI->getOpcode();
1008 if (Opc == AMDGPU::V_MAD_F32 || Opc == AMDGPU::V_MAC_F32_e64) {
1009 // Don't fold if we are using source modifiers. The new VOP2 instructions
1011 if (hasModifiersSet(*UseMI, AMDGPU::OpName::src0_modifiers) ||
1012 hasModifiersSet(*UseMI, AMDGPU::OpName::src1_modifiers) ||
1013 hasModifiersSet(*UseMI, AMDGPU::OpName::src2_modifiers)) {
1017 MachineOperand *Src0 = getNamedOperand(*UseMI, AMDGPU::OpName::src0);
1018 MachineOperand *Src1 = getNamedOperand(*UseMI, AMDGPU::OpName::src1);
1019 MachineOperand *Src2 = getNamedOperand(*UseMI, AMDGPU::OpName::src2);
1021 // Multiplied part is the constant: Use v_madmk_f32
1022 // We should only expect these to be on src0 due to canonicalizations.
1023 if (Src0->isReg() && Src0->getReg() == Reg) {
1024 if (!Src1->isReg() ||
1025 (Src1->isReg() && RI.isSGPRClass(MRI->getRegClass(Src1->getReg()))))
1028 if (!Src2->isReg() ||
1029 (Src2->isReg() && RI.isSGPRClass(MRI->getRegClass(Src2->getReg()))))
1032 // We need to do some weird looking operand shuffling since the madmk
1033 // operands are out of the normal expected order with the multiplied
1034 // constant as the last operand.
1036 // v_mad_f32 src0, src1, src2 -> v_madmk_f32 src0 * src2K + src1
1041 const int64_t Imm = DefMI->getOperand(1).getImm();
1043 // FIXME: This would be a lot easier if we could return a new instruction
1044 // instead of having to modify in place.
1046 // Remove these first since they are at the end.
1047 UseMI->RemoveOperand(AMDGPU::getNamedOperandIdx(Opc,
1048 AMDGPU::OpName::omod));
1049 UseMI->RemoveOperand(AMDGPU::getNamedOperandIdx(Opc,
1050 AMDGPU::OpName::clamp));
1052 unsigned Src1Reg = Src1->getReg();
1053 unsigned Src1SubReg = Src1->getSubReg();
1054 unsigned Src2Reg = Src2->getReg();
1055 unsigned Src2SubReg = Src2->getSubReg();
1056 Src0->setReg(Src1Reg);
1057 Src0->setSubReg(Src1SubReg);
1058 Src0->setIsKill(Src1->isKill());
1060 Src1->setReg(Src2Reg);
1061 Src1->setSubReg(Src2SubReg);
1062 Src1->setIsKill(Src2->isKill());
1064 if (Opc == AMDGPU::V_MAC_F32_e64) {
1065 UseMI->untieRegOperand(
1066 AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src2));
1069 Src2->ChangeToImmediate(Imm);
1071 removeModOperands(*UseMI);
1072 UseMI->setDesc(get(AMDGPU::V_MADMK_F32));
1074 bool DeleteDef = MRI->hasOneNonDBGUse(Reg);
1076 DefMI->eraseFromParent();
1081 // Added part is the constant: Use v_madak_f32
1082 if (Src2->isReg() && Src2->getReg() == Reg) {
1083 // Not allowed to use constant bus for another operand.
1084 // We can however allow an inline immediate as src0.
1085 if (!Src0->isImm() &&
1086 (Src0->isReg() && RI.isSGPRClass(MRI->getRegClass(Src0->getReg()))))
1089 if (!Src1->isReg() ||
1090 (Src1->isReg() && RI.isSGPRClass(MRI->getRegClass(Src1->getReg()))))
1093 const int64_t Imm = DefMI->getOperand(1).getImm();
1095 // FIXME: This would be a lot easier if we could return a new instruction
1096 // instead of having to modify in place.
1098 // Remove these first since they are at the end.
1099 UseMI->RemoveOperand(AMDGPU::getNamedOperandIdx(Opc,
1100 AMDGPU::OpName::omod));
1101 UseMI->RemoveOperand(AMDGPU::getNamedOperandIdx(Opc,
1102 AMDGPU::OpName::clamp));
1104 if (Opc == AMDGPU::V_MAC_F32_e64) {
1105 UseMI->untieRegOperand(
1106 AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src2));
1109 // ChangingToImmediate adds Src2 back to the instruction.
1110 Src2->ChangeToImmediate(Imm);
1112 // These come before src2.
1113 removeModOperands(*UseMI);
1114 UseMI->setDesc(get(AMDGPU::V_MADAK_F32));
1116 bool DeleteDef = MRI->hasOneNonDBGUse(Reg);
1118 DefMI->eraseFromParent();
1127 static bool offsetsDoNotOverlap(int WidthA, int OffsetA,
1128 int WidthB, int OffsetB) {
1129 int LowOffset = OffsetA < OffsetB ? OffsetA : OffsetB;
1130 int HighOffset = OffsetA < OffsetB ? OffsetB : OffsetA;
1131 int LowWidth = (LowOffset == OffsetA) ? WidthA : WidthB;
1132 return LowOffset + LowWidth <= HighOffset;
1135 bool SIInstrInfo::checkInstOffsetsDoNotOverlap(MachineInstr *MIa,
1136 MachineInstr *MIb) const {
1137 unsigned BaseReg0, Offset0;
1138 unsigned BaseReg1, Offset1;
1140 if (getMemOpBaseRegImmOfs(MIa, BaseReg0, Offset0, &RI) &&
1141 getMemOpBaseRegImmOfs(MIb, BaseReg1, Offset1, &RI)) {
1142 assert(MIa->hasOneMemOperand() && MIb->hasOneMemOperand() &&
1143 "read2 / write2 not expected here yet");
1144 unsigned Width0 = (*MIa->memoperands_begin())->getSize();
1145 unsigned Width1 = (*MIb->memoperands_begin())->getSize();
1146 if (BaseReg0 == BaseReg1 &&
1147 offsetsDoNotOverlap(Width0, Offset0, Width1, Offset1)) {
1155 bool SIInstrInfo::areMemAccessesTriviallyDisjoint(MachineInstr *MIa,
1157 AliasAnalysis *AA) const {
1158 assert(MIa && (MIa->mayLoad() || MIa->mayStore()) &&
1159 "MIa must load from or modify a memory location");
1160 assert(MIb && (MIb->mayLoad() || MIb->mayStore()) &&
1161 "MIb must load from or modify a memory location");
1163 if (MIa->hasUnmodeledSideEffects() || MIb->hasUnmodeledSideEffects())
1166 // XXX - Can we relax this between address spaces?
1167 if (MIa->hasOrderedMemoryRef() || MIb->hasOrderedMemoryRef())
1170 // TODO: Should we check the address space from the MachineMemOperand? That
1171 // would allow us to distinguish objects we know don't alias based on the
1172 // underlying address space, even if it was lowered to a different one,
1173 // e.g. private accesses lowered to use MUBUF instructions on a scratch
1177 return checkInstOffsetsDoNotOverlap(MIa, MIb);
1179 return !isFLAT(*MIb);
1182 if (isMUBUF(*MIa) || isMTBUF(*MIa)) {
1183 if (isMUBUF(*MIb) || isMTBUF(*MIb))
1184 return checkInstOffsetsDoNotOverlap(MIa, MIb);
1186 return !isFLAT(*MIb) && !isSMRD(*MIb);
1191 return checkInstOffsetsDoNotOverlap(MIa, MIb);
1193 return !isFLAT(*MIb) && !isMUBUF(*MIa) && !isMTBUF(*MIa);
1198 return checkInstOffsetsDoNotOverlap(MIa, MIb);
1206 MachineInstr *SIInstrInfo::convertToThreeAddress(MachineFunction::iterator &MBB,
1207 MachineBasicBlock::iterator &MI,
1208 LiveVariables *LV) const {
1210 switch (MI->getOpcode()) {
1211 default: return nullptr;
1212 case AMDGPU::V_MAC_F32_e64: break;
1213 case AMDGPU::V_MAC_F32_e32: {
1214 const MachineOperand *Src0 = getNamedOperand(*MI, AMDGPU::OpName::src0);
1215 if (Src0->isImm() && !isInlineConstant(*Src0, 4))
1221 const MachineOperand *Dst = getNamedOperand(*MI, AMDGPU::OpName::dst);
1222 const MachineOperand *Src0 = getNamedOperand(*MI, AMDGPU::OpName::src0);
1223 const MachineOperand *Src1 = getNamedOperand(*MI, AMDGPU::OpName::src1);
1224 const MachineOperand *Src2 = getNamedOperand(*MI, AMDGPU::OpName::src2);
1226 return BuildMI(*MBB, MI, MI->getDebugLoc(), get(AMDGPU::V_MAD_F32))
1228 .addImm(0) // Src0 mods
1230 .addImm(0) // Src1 mods
1232 .addImm(0) // Src mods
1238 bool SIInstrInfo::isInlineConstant(const APInt &Imm) const {
1239 int64_t SVal = Imm.getSExtValue();
1240 if (SVal >= -16 && SVal <= 64)
1243 if (Imm.getBitWidth() == 64) {
1244 uint64_t Val = Imm.getZExtValue();
1245 return (DoubleToBits(0.0) == Val) ||
1246 (DoubleToBits(1.0) == Val) ||
1247 (DoubleToBits(-1.0) == Val) ||
1248 (DoubleToBits(0.5) == Val) ||
1249 (DoubleToBits(-0.5) == Val) ||
1250 (DoubleToBits(2.0) == Val) ||
1251 (DoubleToBits(-2.0) == Val) ||
1252 (DoubleToBits(4.0) == Val) ||
1253 (DoubleToBits(-4.0) == Val);
1256 // The actual type of the operand does not seem to matter as long
1257 // as the bits match one of the inline immediate values. For example:
1259 // -nan has the hexadecimal encoding of 0xfffffffe which is -2 in decimal,
1260 // so it is a legal inline immediate.
1262 // 1065353216 has the hexadecimal encoding 0x3f800000 which is 1.0f in
1263 // floating-point, so it is a legal inline immediate.
1264 uint32_t Val = Imm.getZExtValue();
1266 return (FloatToBits(0.0f) == Val) ||
1267 (FloatToBits(1.0f) == Val) ||
1268 (FloatToBits(-1.0f) == Val) ||
1269 (FloatToBits(0.5f) == Val) ||
1270 (FloatToBits(-0.5f) == Val) ||
1271 (FloatToBits(2.0f) == Val) ||
1272 (FloatToBits(-2.0f) == Val) ||
1273 (FloatToBits(4.0f) == Val) ||
1274 (FloatToBits(-4.0f) == Val);
1277 bool SIInstrInfo::isInlineConstant(const MachineOperand &MO,
1278 unsigned OpSize) const {
1280 // MachineOperand provides no way to tell the true operand size, since it
1281 // only records a 64-bit value. We need to know the size to determine if a
1282 // 32-bit floating point immediate bit pattern is legal for an integer
1283 // immediate. It would be for any 32-bit integer operand, but would not be
1284 // for a 64-bit one.
1286 unsigned BitSize = 8 * OpSize;
1287 return isInlineConstant(APInt(BitSize, MO.getImm(), true));
1293 bool SIInstrInfo::isLiteralConstant(const MachineOperand &MO,
1294 unsigned OpSize) const {
1295 return MO.isImm() && !isInlineConstant(MO, OpSize);
1298 static bool compareMachineOp(const MachineOperand &Op0,
1299 const MachineOperand &Op1) {
1300 if (Op0.getType() != Op1.getType())
1303 switch (Op0.getType()) {
1304 case MachineOperand::MO_Register:
1305 return Op0.getReg() == Op1.getReg();
1306 case MachineOperand::MO_Immediate:
1307 return Op0.getImm() == Op1.getImm();
1309 llvm_unreachable("Didn't expect to be comparing these operand types");
1313 bool SIInstrInfo::isImmOperandLegal(const MachineInstr *MI, unsigned OpNo,
1314 const MachineOperand &MO) const {
1315 const MCOperandInfo &OpInfo = get(MI->getOpcode()).OpInfo[OpNo];
1317 assert(MO.isImm() || MO.isTargetIndex() || MO.isFI());
1319 if (OpInfo.OperandType == MCOI::OPERAND_IMMEDIATE)
1322 if (OpInfo.RegClass < 0)
1325 unsigned OpSize = RI.getRegClass(OpInfo.RegClass)->getSize();
1326 if (isLiteralConstant(MO, OpSize))
1327 return RI.opCanUseLiteralConstant(OpInfo.OperandType);
1329 return RI.opCanUseInlineConstant(OpInfo.OperandType);
1332 bool SIInstrInfo::hasVALU32BitEncoding(unsigned Opcode) const {
1333 int Op32 = AMDGPU::getVOPe32(Opcode);
1337 return pseudoToMCOpcode(Op32) != -1;
1340 bool SIInstrInfo::hasModifiers(unsigned Opcode) const {
1341 // The src0_modifier operand is present on all instructions
1342 // that have modifiers.
1344 return AMDGPU::getNamedOperandIdx(Opcode,
1345 AMDGPU::OpName::src0_modifiers) != -1;
1348 bool SIInstrInfo::hasModifiersSet(const MachineInstr &MI,
1349 unsigned OpName) const {
1350 const MachineOperand *Mods = getNamedOperand(MI, OpName);
1351 return Mods && Mods->getImm();
1354 bool SIInstrInfo::usesConstantBus(const MachineRegisterInfo &MRI,
1355 const MachineOperand &MO,
1356 unsigned OpSize) const {
1357 // Literal constants use the constant bus.
1358 if (isLiteralConstant(MO, OpSize))
1361 if (!MO.isReg() || !MO.isUse())
1364 if (TargetRegisterInfo::isVirtualRegister(MO.getReg()))
1365 return RI.isSGPRClass(MRI.getRegClass(MO.getReg()));
1367 // FLAT_SCR is just an SGPR pair.
1368 if (!MO.isImplicit() && (MO.getReg() == AMDGPU::FLAT_SCR))
1371 // EXEC register uses the constant bus.
1372 if (!MO.isImplicit() && MO.getReg() == AMDGPU::EXEC)
1375 // SGPRs use the constant bus
1376 if (MO.getReg() == AMDGPU::M0 || MO.getReg() == AMDGPU::VCC ||
1377 (!MO.isImplicit() &&
1378 (AMDGPU::SGPR_32RegClass.contains(MO.getReg()) ||
1379 AMDGPU::SGPR_64RegClass.contains(MO.getReg())))) {
1386 static unsigned findImplicitSGPRRead(const MachineInstr &MI) {
1387 for (const MachineOperand &MO : MI.implicit_operands()) {
1388 // We only care about reads.
1392 switch (MO.getReg()) {
1395 case AMDGPU::FLAT_SCR:
1403 return AMDGPU::NoRegister;
1406 bool SIInstrInfo::verifyInstruction(const MachineInstr *MI,
1407 StringRef &ErrInfo) const {
1408 uint16_t Opcode = MI->getOpcode();
1409 const MachineRegisterInfo &MRI = MI->getParent()->getParent()->getRegInfo();
1410 int Src0Idx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src0);
1411 int Src1Idx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src1);
1412 int Src2Idx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src2);
1414 // Make sure the number of operands is correct.
1415 const MCInstrDesc &Desc = get(Opcode);
1416 if (!Desc.isVariadic() &&
1417 Desc.getNumOperands() != MI->getNumExplicitOperands()) {
1418 ErrInfo = "Instruction has wrong number of operands.";
1422 // Make sure the register classes are correct
1423 for (int i = 0, e = Desc.getNumOperands(); i != e; ++i) {
1424 if (MI->getOperand(i).isFPImm()) {
1425 ErrInfo = "FPImm Machine Operands are not supported. ISel should bitcast "
1426 "all fp values to integers.";
1430 int RegClass = Desc.OpInfo[i].RegClass;
1432 switch (Desc.OpInfo[i].OperandType) {
1433 case MCOI::OPERAND_REGISTER:
1434 if (MI->getOperand(i).isImm()) {
1435 ErrInfo = "Illegal immediate value for operand.";
1439 case AMDGPU::OPERAND_REG_IMM32:
1441 case AMDGPU::OPERAND_REG_INLINE_C:
1442 if (isLiteralConstant(MI->getOperand(i),
1443 RI.getRegClass(RegClass)->getSize())) {
1444 ErrInfo = "Illegal immediate value for operand.";
1448 case MCOI::OPERAND_IMMEDIATE:
1449 // Check if this operand is an immediate.
1450 // FrameIndex operands will be replaced by immediates, so they are
1452 if (!MI->getOperand(i).isImm() && !MI->getOperand(i).isFI()) {
1453 ErrInfo = "Expected immediate, but got non-immediate";
1461 if (!MI->getOperand(i).isReg())
1464 if (RegClass != -1) {
1465 unsigned Reg = MI->getOperand(i).getReg();
1466 if (TargetRegisterInfo::isVirtualRegister(Reg))
1469 const TargetRegisterClass *RC = RI.getRegClass(RegClass);
1470 if (!RC->contains(Reg)) {
1471 ErrInfo = "Operand has incorrect register class.";
1479 if (isVOP1(*MI) || isVOP2(*MI) || isVOP3(*MI) || isVOPC(*MI)) {
1480 // Only look at the true operands. Only a real operand can use the constant
1481 // bus, and we don't want to check pseudo-operands like the source modifier
1483 const int OpIndices[] = { Src0Idx, Src1Idx, Src2Idx };
1485 unsigned ConstantBusCount = 0;
1486 unsigned SGPRUsed = findImplicitSGPRRead(*MI);
1487 if (SGPRUsed != AMDGPU::NoRegister)
1490 for (int OpIdx : OpIndices) {
1493 const MachineOperand &MO = MI->getOperand(OpIdx);
1494 if (usesConstantBus(MRI, MO, getOpSize(Opcode, OpIdx))) {
1496 if (MO.getReg() != SGPRUsed)
1498 SGPRUsed = MO.getReg();
1504 if (ConstantBusCount > 1) {
1505 ErrInfo = "VOP* instruction uses the constant bus more than once";
1510 // Verify misc. restrictions on specific instructions.
1511 if (Desc.getOpcode() == AMDGPU::V_DIV_SCALE_F32 ||
1512 Desc.getOpcode() == AMDGPU::V_DIV_SCALE_F64) {
1513 const MachineOperand &Src0 = MI->getOperand(Src0Idx);
1514 const MachineOperand &Src1 = MI->getOperand(Src1Idx);
1515 const MachineOperand &Src2 = MI->getOperand(Src2Idx);
1516 if (Src0.isReg() && Src1.isReg() && Src2.isReg()) {
1517 if (!compareMachineOp(Src0, Src1) &&
1518 !compareMachineOp(Src0, Src2)) {
1519 ErrInfo = "v_div_scale_{f32|f64} require src0 = src1 or src2";
1525 // Make sure we aren't losing exec uses in the td files. This mostly requires
1526 // being careful when using let Uses to try to add other use registers.
1527 if (!isGenericOpcode(Opcode) && !isSALU(Opcode) && !isSMRD(Opcode)) {
1528 const MachineOperand *Exec = MI->findRegisterUseOperand(AMDGPU::EXEC);
1529 if (!Exec || !Exec->isImplicit()) {
1530 ErrInfo = "VALU instruction does not implicitly read exec mask";
1538 unsigned SIInstrInfo::getVALUOp(const MachineInstr &MI) {
1539 switch (MI.getOpcode()) {
1540 default: return AMDGPU::INSTRUCTION_LIST_END;
1541 case AMDGPU::REG_SEQUENCE: return AMDGPU::REG_SEQUENCE;
1542 case AMDGPU::COPY: return AMDGPU::COPY;
1543 case AMDGPU::PHI: return AMDGPU::PHI;
1544 case AMDGPU::INSERT_SUBREG: return AMDGPU::INSERT_SUBREG;
1545 case AMDGPU::S_MOV_B32:
1546 return MI.getOperand(1).isReg() ?
1547 AMDGPU::COPY : AMDGPU::V_MOV_B32_e32;
1548 case AMDGPU::S_ADD_I32:
1549 case AMDGPU::S_ADD_U32: return AMDGPU::V_ADD_I32_e32;
1550 case AMDGPU::S_ADDC_U32: return AMDGPU::V_ADDC_U32_e32;
1551 case AMDGPU::S_SUB_I32:
1552 case AMDGPU::S_SUB_U32: return AMDGPU::V_SUB_I32_e32;
1553 case AMDGPU::S_SUBB_U32: return AMDGPU::V_SUBB_U32_e32;
1554 case AMDGPU::S_MUL_I32: return AMDGPU::V_MUL_LO_I32;
1555 case AMDGPU::S_AND_B32: return AMDGPU::V_AND_B32_e32;
1556 case AMDGPU::S_OR_B32: return AMDGPU::V_OR_B32_e32;
1557 case AMDGPU::S_XOR_B32: return AMDGPU::V_XOR_B32_e32;
1558 case AMDGPU::S_MIN_I32: return AMDGPU::V_MIN_I32_e32;
1559 case AMDGPU::S_MIN_U32: return AMDGPU::V_MIN_U32_e32;
1560 case AMDGPU::S_MAX_I32: return AMDGPU::V_MAX_I32_e32;
1561 case AMDGPU::S_MAX_U32: return AMDGPU::V_MAX_U32_e32;
1562 case AMDGPU::S_ASHR_I32: return AMDGPU::V_ASHR_I32_e32;
1563 case AMDGPU::S_ASHR_I64: return AMDGPU::V_ASHR_I64;
1564 case AMDGPU::S_LSHL_B32: return AMDGPU::V_LSHL_B32_e32;
1565 case AMDGPU::S_LSHL_B64: return AMDGPU::V_LSHL_B64;
1566 case AMDGPU::S_LSHR_B32: return AMDGPU::V_LSHR_B32_e32;
1567 case AMDGPU::S_LSHR_B64: return AMDGPU::V_LSHR_B64;
1568 case AMDGPU::S_SEXT_I32_I8: return AMDGPU::V_BFE_I32;
1569 case AMDGPU::S_SEXT_I32_I16: return AMDGPU::V_BFE_I32;
1570 case AMDGPU::S_BFE_U32: return AMDGPU::V_BFE_U32;
1571 case AMDGPU::S_BFE_I32: return AMDGPU::V_BFE_I32;
1572 case AMDGPU::S_BFM_B32: return AMDGPU::V_BFM_B32_e64;
1573 case AMDGPU::S_BREV_B32: return AMDGPU::V_BFREV_B32_e32;
1574 case AMDGPU::S_NOT_B32: return AMDGPU::V_NOT_B32_e32;
1575 case AMDGPU::S_NOT_B64: return AMDGPU::V_NOT_B32_e32;
1576 case AMDGPU::S_CMP_EQ_I32: return AMDGPU::V_CMP_EQ_I32_e32;
1577 case AMDGPU::S_CMP_LG_I32: return AMDGPU::V_CMP_NE_I32_e32;
1578 case AMDGPU::S_CMP_GT_I32: return AMDGPU::V_CMP_GT_I32_e32;
1579 case AMDGPU::S_CMP_GE_I32: return AMDGPU::V_CMP_GE_I32_e32;
1580 case AMDGPU::S_CMP_LT_I32: return AMDGPU::V_CMP_LT_I32_e32;
1581 case AMDGPU::S_CMP_LE_I32: return AMDGPU::V_CMP_LE_I32_e32;
1582 case AMDGPU::S_LOAD_DWORD_IMM:
1583 case AMDGPU::S_LOAD_DWORD_SGPR:
1584 case AMDGPU::S_LOAD_DWORD_IMM_ci:
1585 return AMDGPU::BUFFER_LOAD_DWORD_ADDR64;
1586 case AMDGPU::S_LOAD_DWORDX2_IMM:
1587 case AMDGPU::S_LOAD_DWORDX2_SGPR:
1588 case AMDGPU::S_LOAD_DWORDX2_IMM_ci:
1589 return AMDGPU::BUFFER_LOAD_DWORDX2_ADDR64;
1590 case AMDGPU::S_LOAD_DWORDX4_IMM:
1591 case AMDGPU::S_LOAD_DWORDX4_SGPR:
1592 case AMDGPU::S_LOAD_DWORDX4_IMM_ci:
1593 return AMDGPU::BUFFER_LOAD_DWORDX4_ADDR64;
1594 case AMDGPU::S_BCNT1_I32_B32: return AMDGPU::V_BCNT_U32_B32_e64;
1595 case AMDGPU::S_FF1_I32_B32: return AMDGPU::V_FFBL_B32_e32;
1596 case AMDGPU::S_FLBIT_I32_B32: return AMDGPU::V_FFBH_U32_e32;
1597 case AMDGPU::S_FLBIT_I32: return AMDGPU::V_FFBH_I32_e64;
1601 bool SIInstrInfo::isSALUOpSupportedOnVALU(const MachineInstr &MI) const {
1602 return getVALUOp(MI) != AMDGPU::INSTRUCTION_LIST_END;
1605 const TargetRegisterClass *SIInstrInfo::getOpRegClass(const MachineInstr &MI,
1606 unsigned OpNo) const {
1607 const MachineRegisterInfo &MRI = MI.getParent()->getParent()->getRegInfo();
1608 const MCInstrDesc &Desc = get(MI.getOpcode());
1609 if (MI.isVariadic() || OpNo >= Desc.getNumOperands() ||
1610 Desc.OpInfo[OpNo].RegClass == -1) {
1611 unsigned Reg = MI.getOperand(OpNo).getReg();
1613 if (TargetRegisterInfo::isVirtualRegister(Reg))
1614 return MRI.getRegClass(Reg);
1615 return RI.getPhysRegClass(Reg);
1618 unsigned RCID = Desc.OpInfo[OpNo].RegClass;
1619 return RI.getRegClass(RCID);
1622 bool SIInstrInfo::canReadVGPR(const MachineInstr &MI, unsigned OpNo) const {
1623 switch (MI.getOpcode()) {
1625 case AMDGPU::REG_SEQUENCE:
1627 case AMDGPU::INSERT_SUBREG:
1628 return RI.hasVGPRs(getOpRegClass(MI, 0));
1630 return RI.hasVGPRs(getOpRegClass(MI, OpNo));
1634 void SIInstrInfo::legalizeOpWithMove(MachineInstr *MI, unsigned OpIdx) const {
1635 MachineBasicBlock::iterator I = MI;
1636 MachineBasicBlock *MBB = MI->getParent();
1637 MachineOperand &MO = MI->getOperand(OpIdx);
1638 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
1639 unsigned RCID = get(MI->getOpcode()).OpInfo[OpIdx].RegClass;
1640 const TargetRegisterClass *RC = RI.getRegClass(RCID);
1641 unsigned Opcode = AMDGPU::V_MOV_B32_e32;
1643 Opcode = AMDGPU::COPY;
1644 else if (RI.isSGPRClass(RC))
1645 Opcode = AMDGPU::S_MOV_B32;
1648 const TargetRegisterClass *VRC = RI.getEquivalentVGPRClass(RC);
1649 if (RI.getCommonSubClass(&AMDGPU::VReg_64RegClass, VRC))
1650 VRC = &AMDGPU::VReg_64RegClass;
1652 VRC = &AMDGPU::VGPR_32RegClass;
1654 unsigned Reg = MRI.createVirtualRegister(VRC);
1655 DebugLoc DL = MBB->findDebugLoc(I);
1656 BuildMI(*MI->getParent(), I, DL, get(Opcode), Reg)
1658 MO.ChangeToRegister(Reg, false);
1661 unsigned SIInstrInfo::buildExtractSubReg(MachineBasicBlock::iterator MI,
1662 MachineRegisterInfo &MRI,
1663 MachineOperand &SuperReg,
1664 const TargetRegisterClass *SuperRC,
1666 const TargetRegisterClass *SubRC)
1668 MachineBasicBlock *MBB = MI->getParent();
1669 DebugLoc DL = MI->getDebugLoc();
1670 unsigned SubReg = MRI.createVirtualRegister(SubRC);
1672 if (SuperReg.getSubReg() == AMDGPU::NoSubRegister) {
1673 BuildMI(*MBB, MI, DL, get(TargetOpcode::COPY), SubReg)
1674 .addReg(SuperReg.getReg(), 0, SubIdx);
1678 // Just in case the super register is itself a sub-register, copy it to a new
1679 // value so we don't need to worry about merging its subreg index with the
1680 // SubIdx passed to this function. The register coalescer should be able to
1681 // eliminate this extra copy.
1682 unsigned NewSuperReg = MRI.createVirtualRegister(SuperRC);
1684 BuildMI(*MBB, MI, DL, get(TargetOpcode::COPY), NewSuperReg)
1685 .addReg(SuperReg.getReg(), 0, SuperReg.getSubReg());
1687 BuildMI(*MBB, MI, DL, get(TargetOpcode::COPY), SubReg)
1688 .addReg(NewSuperReg, 0, SubIdx);
1693 MachineOperand SIInstrInfo::buildExtractSubRegOrImm(
1694 MachineBasicBlock::iterator MII,
1695 MachineRegisterInfo &MRI,
1697 const TargetRegisterClass *SuperRC,
1699 const TargetRegisterClass *SubRC) const {
1701 // XXX - Is there a better way to do this?
1702 if (SubIdx == AMDGPU::sub0)
1703 return MachineOperand::CreateImm(Op.getImm() & 0xFFFFFFFF);
1704 if (SubIdx == AMDGPU::sub1)
1705 return MachineOperand::CreateImm(Op.getImm() >> 32);
1707 llvm_unreachable("Unhandled register index for immediate");
1710 unsigned SubReg = buildExtractSubReg(MII, MRI, Op, SuperRC,
1712 return MachineOperand::CreateReg(SubReg, false);
1715 // Change the order of operands from (0, 1, 2) to (0, 2, 1)
1716 void SIInstrInfo::swapOperands(MachineBasicBlock::iterator Inst) const {
1717 assert(Inst->getNumExplicitOperands() == 3);
1718 MachineOperand Op1 = Inst->getOperand(1);
1719 Inst->RemoveOperand(1);
1720 Inst->addOperand(Op1);
1723 bool SIInstrInfo::isOperandLegal(const MachineInstr *MI, unsigned OpIdx,
1724 const MachineOperand *MO) const {
1725 const MachineRegisterInfo &MRI = MI->getParent()->getParent()->getRegInfo();
1726 const MCInstrDesc &InstDesc = get(MI->getOpcode());
1727 const MCOperandInfo &OpInfo = InstDesc.OpInfo[OpIdx];
1728 const TargetRegisterClass *DefinedRC =
1729 OpInfo.RegClass != -1 ? RI.getRegClass(OpInfo.RegClass) : nullptr;
1731 MO = &MI->getOperand(OpIdx);
1734 usesConstantBus(MRI, *MO, DefinedRC->getSize())) {
1736 MO->isReg() ? MO->getReg() : (unsigned)AMDGPU::NoRegister;
1737 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1740 const MachineOperand &Op = MI->getOperand(i);
1741 if (Op.isReg() && Op.getReg() != SGPRUsed &&
1742 usesConstantBus(MRI, Op, getOpSize(*MI, i))) {
1750 const TargetRegisterClass *RC =
1751 TargetRegisterInfo::isVirtualRegister(MO->getReg()) ?
1752 MRI.getRegClass(MO->getReg()) :
1753 RI.getPhysRegClass(MO->getReg());
1755 // In order to be legal, the common sub-class must be equal to the
1756 // class of the current operand. For example:
1758 // v_mov_b32 s0 ; Operand defined as vsrc_32
1759 // ; RI.getCommonSubClass(s0,vsrc_32) = sgpr ; LEGAL
1761 // s_sendmsg 0, s0 ; Operand defined as m0reg
1762 // ; RI.getCommonSubClass(s0,m0reg) = m0reg ; NOT LEGAL
1764 return RI.getCommonSubClass(RC, RI.getRegClass(OpInfo.RegClass)) == RC;
1768 // Handle non-register types that are treated like immediates.
1769 assert(MO->isImm() || MO->isTargetIndex() || MO->isFI());
1772 // This operand expects an immediate.
1776 return isImmOperandLegal(MI, OpIdx, *MO);
1779 // Legalize VOP3 operands. Because all operand types are supported for any
1780 // operand, and since literal constants are not allowed and should never be
1781 // seen, we only need to worry about inserting copies if we use multiple SGPR
1783 void SIInstrInfo::legalizeOperandsVOP3(
1784 MachineRegisterInfo &MRI,
1785 MachineInstr *MI) const {
1786 unsigned Opc = MI->getOpcode();
1789 AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src0),
1790 AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src1),
1791 AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src2)
1794 // Find the one SGPR operand we are allowed to use.
1795 unsigned SGPRReg = findUsedSGPR(MI, VOP3Idx);
1797 for (unsigned i = 0; i < 3; ++i) {
1798 int Idx = VOP3Idx[i];
1801 MachineOperand &MO = MI->getOperand(Idx);
1803 // We should never see a VOP3 instruction with an illegal immediate operand.
1807 if (!RI.isSGPRClass(MRI.getRegClass(MO.getReg())))
1808 continue; // VGPRs are legal
1810 if (SGPRReg == AMDGPU::NoRegister || SGPRReg == MO.getReg()) {
1811 SGPRReg = MO.getReg();
1812 // We can use one SGPR in each VOP3 instruction.
1816 // If we make it this far, then the operand is not legal and we must
1818 legalizeOpWithMove(MI, Idx);
1822 void SIInstrInfo::legalizeOperands(MachineInstr *MI) const {
1823 MachineRegisterInfo &MRI = MI->getParent()->getParent()->getRegInfo();
1824 unsigned Opc = MI->getOpcode();
1828 int Src0Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src0);
1829 int Src1Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src1);
1832 if (!isOperandLegal(MI, Src0Idx))
1833 legalizeOpWithMove(MI, Src0Idx);
1836 if (isOperandLegal(MI, Src1Idx))
1839 // Usually src0 of VOP2 instructions allow more types of inputs
1840 // than src1, so try to commute the instruction to decrease our
1841 // chances of having to insert a MOV instruction to legalize src1.
1842 if (MI->isCommutable()) {
1843 if (commuteInstruction(MI))
1844 // If we are successful in commuting, then we know MI is legal, so
1849 legalizeOpWithMove(MI, Src1Idx);
1855 legalizeOperandsVOP3(MRI, MI);
1859 // Legalize REG_SEQUENCE and PHI
1860 // The register class of the operands much be the same type as the register
1861 // class of the output.
1862 if (MI->getOpcode() == AMDGPU::PHI) {
1863 const TargetRegisterClass *RC = nullptr, *SRC = nullptr, *VRC = nullptr;
1864 for (unsigned i = 1, e = MI->getNumOperands(); i != e; i+=2) {
1865 if (!MI->getOperand(i).isReg() ||
1866 !TargetRegisterInfo::isVirtualRegister(MI->getOperand(i).getReg()))
1868 const TargetRegisterClass *OpRC =
1869 MRI.getRegClass(MI->getOperand(i).getReg());
1870 if (RI.hasVGPRs(OpRC)) {
1877 // If any of the operands are VGPR registers, then they all most be
1878 // otherwise we will create illegal VGPR->SGPR copies when legalizing
1880 if (VRC || !RI.isSGPRClass(getOpRegClass(*MI, 0))) {
1883 VRC = RI.getEquivalentVGPRClass(SRC);
1890 // Update all the operands so they have the same type.
1891 for (unsigned I = 1, E = MI->getNumOperands(); I != E; I += 2) {
1892 MachineOperand &Op = MI->getOperand(I);
1893 if (!Op.isReg() || !TargetRegisterInfo::isVirtualRegister(Op.getReg()))
1895 unsigned DstReg = MRI.createVirtualRegister(RC);
1897 // MI is a PHI instruction.
1898 MachineBasicBlock *InsertBB = MI->getOperand(I + 1).getMBB();
1899 MachineBasicBlock::iterator Insert = InsertBB->getFirstTerminator();
1901 BuildMI(*InsertBB, Insert, MI->getDebugLoc(), get(AMDGPU::COPY), DstReg)
1907 // REG_SEQUENCE doesn't really require operand legalization, but if one has a
1908 // VGPR dest type and SGPR sources, insert copies so all operands are
1909 // VGPRs. This seems to help operand folding / the register coalescer.
1910 if (MI->getOpcode() == AMDGPU::REG_SEQUENCE) {
1911 MachineBasicBlock *MBB = MI->getParent();
1912 const TargetRegisterClass *DstRC = getOpRegClass(*MI, 0);
1913 if (RI.hasVGPRs(DstRC)) {
1914 // Update all the operands so they are VGPR register classes. These may
1915 // not be the same register class because REG_SEQUENCE supports mixing
1916 // subregister index types e.g. sub0_sub1 + sub2 + sub3
1917 for (unsigned I = 1, E = MI->getNumOperands(); I != E; I += 2) {
1918 MachineOperand &Op = MI->getOperand(I);
1919 if (!Op.isReg() || !TargetRegisterInfo::isVirtualRegister(Op.getReg()))
1922 const TargetRegisterClass *OpRC = MRI.getRegClass(Op.getReg());
1923 const TargetRegisterClass *VRC = RI.getEquivalentVGPRClass(OpRC);
1927 unsigned DstReg = MRI.createVirtualRegister(VRC);
1929 BuildMI(*MBB, MI, MI->getDebugLoc(), get(AMDGPU::COPY), DstReg)
1940 // Legalize INSERT_SUBREG
1941 // src0 must have the same register class as dst
1942 if (MI->getOpcode() == AMDGPU::INSERT_SUBREG) {
1943 unsigned Dst = MI->getOperand(0).getReg();
1944 unsigned Src0 = MI->getOperand(1).getReg();
1945 const TargetRegisterClass *DstRC = MRI.getRegClass(Dst);
1946 const TargetRegisterClass *Src0RC = MRI.getRegClass(Src0);
1947 if (DstRC != Src0RC) {
1948 MachineBasicBlock &MBB = *MI->getParent();
1949 unsigned NewSrc0 = MRI.createVirtualRegister(DstRC);
1950 BuildMI(MBB, MI, MI->getDebugLoc(), get(AMDGPU::COPY), NewSrc0)
1952 MI->getOperand(1).setReg(NewSrc0);
1957 // Legalize MUBUF* instructions
1958 // FIXME: If we start using the non-addr64 instructions for compute, we
1959 // may need to legalize them here.
1961 AMDGPU::getNamedOperandIdx(MI->getOpcode(), AMDGPU::OpName::srsrc);
1962 if (SRsrcIdx != -1) {
1963 // We have an MUBUF instruction
1964 MachineOperand *SRsrc = &MI->getOperand(SRsrcIdx);
1965 unsigned SRsrcRC = get(MI->getOpcode()).OpInfo[SRsrcIdx].RegClass;
1966 if (RI.getCommonSubClass(MRI.getRegClass(SRsrc->getReg()),
1967 RI.getRegClass(SRsrcRC))) {
1968 // The operands are legal.
1969 // FIXME: We may need to legalize operands besided srsrc.
1973 MachineBasicBlock &MBB = *MI->getParent();
1975 // Extract the ptr from the resource descriptor.
1976 unsigned SRsrcPtr = buildExtractSubReg(MI, MRI, *SRsrc,
1977 &AMDGPU::VReg_128RegClass, AMDGPU::sub0_sub1, &AMDGPU::VReg_64RegClass);
1979 // Create an empty resource descriptor
1980 unsigned Zero64 = MRI.createVirtualRegister(&AMDGPU::SReg_64RegClass);
1981 unsigned SRsrcFormatLo = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
1982 unsigned SRsrcFormatHi = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
1983 unsigned NewSRsrc = MRI.createVirtualRegister(&AMDGPU::SReg_128RegClass);
1984 uint64_t RsrcDataFormat = getDefaultRsrcDataFormat();
1987 BuildMI(MBB, MI, MI->getDebugLoc(), get(AMDGPU::S_MOV_B64),
1991 // SRsrcFormatLo = RSRC_DATA_FORMAT{31-0}
1992 BuildMI(MBB, MI, MI->getDebugLoc(), get(AMDGPU::S_MOV_B32),
1994 .addImm(RsrcDataFormat & 0xFFFFFFFF);
1996 // SRsrcFormatHi = RSRC_DATA_FORMAT{63-32}
1997 BuildMI(MBB, MI, MI->getDebugLoc(), get(AMDGPU::S_MOV_B32),
1999 .addImm(RsrcDataFormat >> 32);
2001 // NewSRsrc = {Zero64, SRsrcFormat}
2002 BuildMI(MBB, MI, MI->getDebugLoc(), get(AMDGPU::REG_SEQUENCE), NewSRsrc)
2004 .addImm(AMDGPU::sub0_sub1)
2005 .addReg(SRsrcFormatLo)
2006 .addImm(AMDGPU::sub2)
2007 .addReg(SRsrcFormatHi)
2008 .addImm(AMDGPU::sub3);
2010 MachineOperand *VAddr = getNamedOperand(*MI, AMDGPU::OpName::vaddr);
2011 unsigned NewVAddr = MRI.createVirtualRegister(&AMDGPU::VReg_64RegClass);
2013 // This is already an ADDR64 instruction so we need to add the pointer
2014 // extracted from the resource descriptor to the current value of VAddr.
2015 unsigned NewVAddrLo = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
2016 unsigned NewVAddrHi = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
2018 // NewVaddrLo = SRsrcPtr:sub0 + VAddr:sub0
2019 DebugLoc DL = MI->getDebugLoc();
2020 BuildMI(MBB, MI, DL, get(AMDGPU::V_ADD_I32_e32), NewVAddrLo)
2021 .addReg(SRsrcPtr, 0, AMDGPU::sub0)
2022 .addReg(VAddr->getReg(), 0, AMDGPU::sub0);
2024 // NewVaddrHi = SRsrcPtr:sub1 + VAddr:sub1
2025 BuildMI(MBB, MI, DL, get(AMDGPU::V_ADDC_U32_e32), NewVAddrHi)
2026 .addReg(SRsrcPtr, 0, AMDGPU::sub1)
2027 .addReg(VAddr->getReg(), 0, AMDGPU::sub1);
2029 // NewVaddr = {NewVaddrHi, NewVaddrLo}
2030 BuildMI(MBB, MI, MI->getDebugLoc(), get(AMDGPU::REG_SEQUENCE), NewVAddr)
2032 .addImm(AMDGPU::sub0)
2034 .addImm(AMDGPU::sub1);
2036 // This instructions is the _OFFSET variant, so we need to convert it to
2038 assert(MBB.getParent()->getSubtarget<AMDGPUSubtarget>().getGeneration()
2039 < AMDGPUSubtarget::VOLCANIC_ISLANDS &&
2040 "FIXME: Need to emit flat atomics here");
2042 MachineOperand *VData = getNamedOperand(*MI, AMDGPU::OpName::vdata);
2043 MachineOperand *Offset = getNamedOperand(*MI, AMDGPU::OpName::offset);
2044 MachineOperand *SOffset = getNamedOperand(*MI, AMDGPU::OpName::soffset);
2045 unsigned Addr64Opcode = AMDGPU::getAddr64Inst(MI->getOpcode());
2047 // Atomics rith return have have an additional tied operand and are
2048 // missing some of the special bits.
2049 MachineOperand *VDataIn = getNamedOperand(*MI, AMDGPU::OpName::vdata_in);
2050 MachineInstr *Addr64;
2053 // Regular buffer load / store.
2054 MachineInstrBuilder MIB
2055 = BuildMI(MBB, MI, MI->getDebugLoc(), get(Addr64Opcode))
2057 .addReg(AMDGPU::NoRegister) // Dummy value for vaddr.
2058 // This will be replaced later
2059 // with the new value of vaddr.
2061 .addOperand(*SOffset)
2062 .addOperand(*Offset);
2064 // Atomics do not have this operand.
2065 if (const MachineOperand *GLC
2066 = getNamedOperand(*MI, AMDGPU::OpName::glc)) {
2067 MIB.addImm(GLC->getImm());
2070 MIB.addImm(getNamedImmOperand(*MI, AMDGPU::OpName::slc));
2072 if (const MachineOperand *TFE
2073 = getNamedOperand(*MI, AMDGPU::OpName::tfe)) {
2074 MIB.addImm(TFE->getImm());
2077 MIB.setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
2080 // Atomics with return.
2081 Addr64 = BuildMI(MBB, MI, MI->getDebugLoc(), get(Addr64Opcode))
2083 .addOperand(*VDataIn)
2084 .addReg(AMDGPU::NoRegister) // Dummy value for vaddr.
2085 // This will be replaced later
2086 // with the new value of vaddr.
2088 .addOperand(*SOffset)
2089 .addOperand(*Offset)
2090 .addImm(getNamedImmOperand(*MI, AMDGPU::OpName::slc))
2091 .setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
2094 MI->removeFromParent();
2097 // NewVaddr = {NewVaddrHi, NewVaddrLo}
2098 BuildMI(MBB, MI, MI->getDebugLoc(), get(AMDGPU::REG_SEQUENCE), NewVAddr)
2099 .addReg(SRsrcPtr, 0, AMDGPU::sub0)
2100 .addImm(AMDGPU::sub0)
2101 .addReg(SRsrcPtr, 0, AMDGPU::sub1)
2102 .addImm(AMDGPU::sub1);
2104 VAddr = getNamedOperand(*MI, AMDGPU::OpName::vaddr);
2105 SRsrc = getNamedOperand(*MI, AMDGPU::OpName::srsrc);
2108 // Update the instruction to use NewVaddr
2109 VAddr->setReg(NewVAddr);
2110 // Update the instruction to use NewSRsrc
2111 SRsrc->setReg(NewSRsrc);
2115 void SIInstrInfo::splitSMRD(MachineInstr *MI,
2116 const TargetRegisterClass *HalfRC,
2117 unsigned HalfImmOp, unsigned HalfSGPROp,
2118 MachineInstr *&Lo, MachineInstr *&Hi) const {
2120 DebugLoc DL = MI->getDebugLoc();
2121 MachineBasicBlock *MBB = MI->getParent();
2122 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
2123 unsigned RegLo = MRI.createVirtualRegister(HalfRC);
2124 unsigned RegHi = MRI.createVirtualRegister(HalfRC);
2125 unsigned HalfSize = HalfRC->getSize();
2126 const MachineOperand *OffOp =
2127 getNamedOperand(*MI, AMDGPU::OpName::offset);
2128 const MachineOperand *SBase = getNamedOperand(*MI, AMDGPU::OpName::sbase);
2130 // The SMRD has an 8-bit offset in dwords on SI and a 20-bit offset in bytes
2133 bool IsKill = SBase->isKill();
2136 MBB->getParent()->getSubtarget<AMDGPUSubtarget>().getGeneration() >=
2137 AMDGPUSubtarget::VOLCANIC_ISLANDS;
2138 unsigned OffScale = isVI ? 1 : 4;
2139 // Handle the _IMM variant
2140 unsigned LoOffset = OffOp->getImm() * OffScale;
2141 unsigned HiOffset = LoOffset + HalfSize;
2142 Lo = BuildMI(*MBB, MI, DL, get(HalfImmOp), RegLo)
2143 // Use addReg instead of addOperand
2144 // to make sure kill flag is cleared.
2145 .addReg(SBase->getReg(), 0, SBase->getSubReg())
2146 .addImm(LoOffset / OffScale);
2148 if (!isUInt<20>(HiOffset) || (!isVI && !isUInt<8>(HiOffset / OffScale))) {
2149 unsigned OffsetSGPR =
2150 MRI.createVirtualRegister(&AMDGPU::SReg_32RegClass);
2151 BuildMI(*MBB, MI, DL, get(AMDGPU::S_MOV_B32), OffsetSGPR)
2152 .addImm(HiOffset); // The offset in register is in bytes.
2153 Hi = BuildMI(*MBB, MI, DL, get(HalfSGPROp), RegHi)
2154 .addReg(SBase->getReg(), getKillRegState(IsKill),
2156 .addReg(OffsetSGPR);
2158 Hi = BuildMI(*MBB, MI, DL, get(HalfImmOp), RegHi)
2159 .addReg(SBase->getReg(), getKillRegState(IsKill),
2161 .addImm(HiOffset / OffScale);
2164 // Handle the _SGPR variant
2165 MachineOperand *SOff = getNamedOperand(*MI, AMDGPU::OpName::soff);
2166 Lo = BuildMI(*MBB, MI, DL, get(HalfSGPROp), RegLo)
2167 .addReg(SBase->getReg(), 0, SBase->getSubReg())
2169 unsigned OffsetSGPR = MRI.createVirtualRegister(&AMDGPU::SReg_32RegClass);
2170 BuildMI(*MBB, MI, DL, get(AMDGPU::S_ADD_I32), OffsetSGPR)
2171 .addReg(SOff->getReg(), 0, SOff->getSubReg())
2173 Hi = BuildMI(*MBB, MI, DL, get(HalfSGPROp), RegHi)
2174 .addReg(SBase->getReg(), getKillRegState(IsKill),
2176 .addReg(OffsetSGPR);
2179 unsigned SubLo, SubHi;
2180 const TargetRegisterClass *NewDstRC;
2183 SubLo = AMDGPU::sub0;
2184 SubHi = AMDGPU::sub1;
2185 NewDstRC = &AMDGPU::VReg_64RegClass;
2188 SubLo = AMDGPU::sub0_sub1;
2189 SubHi = AMDGPU::sub2_sub3;
2190 NewDstRC = &AMDGPU::VReg_128RegClass;
2193 SubLo = AMDGPU::sub0_sub1_sub2_sub3;
2194 SubHi = AMDGPU::sub4_sub5_sub6_sub7;
2195 NewDstRC = &AMDGPU::VReg_256RegClass;
2198 SubLo = AMDGPU::sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7;
2199 SubHi = AMDGPU::sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15;
2200 NewDstRC = &AMDGPU::VReg_512RegClass;
2203 llvm_unreachable("Unhandled HalfSize");
2206 unsigned OldDst = MI->getOperand(0).getReg();
2207 unsigned NewDst = MRI.createVirtualRegister(NewDstRC);
2209 MRI.replaceRegWith(OldDst, NewDst);
2211 BuildMI(*MBB, MI, DL, get(AMDGPU::REG_SEQUENCE), NewDst)
2218 void SIInstrInfo::moveSMRDToVALU(MachineInstr *MI,
2219 MachineRegisterInfo &MRI,
2220 SmallVectorImpl<MachineInstr *> &Worklist) const {
2221 MachineBasicBlock *MBB = MI->getParent();
2222 int DstIdx = AMDGPU::getNamedOperandIdx(MI->getOpcode(), AMDGPU::OpName::dst);
2223 assert(DstIdx != -1);
2224 unsigned DstRCID = get(MI->getOpcode()).OpInfo[DstIdx].RegClass;
2225 switch(RI.getRegClass(DstRCID)->getSize()) {
2229 unsigned NewOpcode = getVALUOp(*MI);
2233 if (MI->getOperand(2).isReg()) {
2234 RegOffset = MI->getOperand(2).getReg();
2237 assert(MI->getOperand(2).isImm());
2238 // SMRD instructions take a dword offsets on SI and byte offset on VI
2239 // and MUBUF instructions always take a byte offset.
2240 ImmOffset = MI->getOperand(2).getImm();
2241 if (MBB->getParent()->getSubtarget<AMDGPUSubtarget>().getGeneration() <=
2242 AMDGPUSubtarget::SEA_ISLANDS)
2244 RegOffset = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
2246 if (isUInt<12>(ImmOffset)) {
2247 BuildMI(*MBB, MI, MI->getDebugLoc(), get(AMDGPU::S_MOV_B32),
2251 BuildMI(*MBB, MI, MI->getDebugLoc(), get(AMDGPU::S_MOV_B32),
2258 unsigned SRsrc = MRI.createVirtualRegister(&AMDGPU::SReg_128RegClass);
2259 unsigned DWord0 = RegOffset;
2260 unsigned DWord1 = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
2261 unsigned DWord2 = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
2262 unsigned DWord3 = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
2263 uint64_t RsrcDataFormat = getDefaultRsrcDataFormat();
2265 BuildMI(*MBB, MI, MI->getDebugLoc(), get(AMDGPU::S_MOV_B32), DWord1)
2267 BuildMI(*MBB, MI, MI->getDebugLoc(), get(AMDGPU::S_MOV_B32), DWord2)
2268 .addImm(RsrcDataFormat & 0xFFFFFFFF);
2269 BuildMI(*MBB, MI, MI->getDebugLoc(), get(AMDGPU::S_MOV_B32), DWord3)
2270 .addImm(RsrcDataFormat >> 32);
2271 BuildMI(*MBB, MI, MI->getDebugLoc(), get(AMDGPU::REG_SEQUENCE), SRsrc)
2273 .addImm(AMDGPU::sub0)
2275 .addImm(AMDGPU::sub1)
2277 .addImm(AMDGPU::sub2)
2279 .addImm(AMDGPU::sub3);
2281 const MCInstrDesc &NewInstDesc = get(NewOpcode);
2282 const TargetRegisterClass *NewDstRC
2283 = RI.getRegClass(NewInstDesc.OpInfo[0].RegClass);
2284 unsigned NewDstReg = MRI.createVirtualRegister(NewDstRC);
2285 unsigned DstReg = MI->getOperand(0).getReg();
2286 MRI.replaceRegWith(DstReg, NewDstReg);
2288 MachineInstr *NewInst =
2289 BuildMI(*MBB, MI, MI->getDebugLoc(), NewInstDesc, NewDstReg)
2290 .addOperand(MI->getOperand(1)) // sbase
2297 .setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
2298 MI->eraseFromParent();
2300 legalizeOperands(NewInst);
2301 addUsersToMoveToVALUWorklist(NewDstReg, MRI, Worklist);
2305 MachineInstr *Lo, *Hi;
2306 splitSMRD(MI, &AMDGPU::SReg_128RegClass, AMDGPU::S_LOAD_DWORDX4_IMM,
2307 AMDGPU::S_LOAD_DWORDX4_SGPR, Lo, Hi);
2308 MI->eraseFromParent();
2309 moveSMRDToVALU(Lo, MRI, Worklist);
2310 moveSMRDToVALU(Hi, MRI, Worklist);
2315 MachineInstr *Lo, *Hi;
2316 splitSMRD(MI, &AMDGPU::SReg_256RegClass, AMDGPU::S_LOAD_DWORDX8_IMM,
2317 AMDGPU::S_LOAD_DWORDX8_SGPR, Lo, Hi);
2318 MI->eraseFromParent();
2319 moveSMRDToVALU(Lo, MRI, Worklist);
2320 moveSMRDToVALU(Hi, MRI, Worklist);
2326 void SIInstrInfo::moveToVALU(MachineInstr &TopInst) const {
2327 SmallVector<MachineInstr *, 128> Worklist;
2328 Worklist.push_back(&TopInst);
2330 while (!Worklist.empty()) {
2331 MachineInstr *Inst = Worklist.pop_back_val();
2332 MachineBasicBlock *MBB = Inst->getParent();
2333 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
2335 unsigned Opcode = Inst->getOpcode();
2336 unsigned NewOpcode = getVALUOp(*Inst);
2338 // Handle some special cases
2341 if (isSMRD(*Inst)) {
2342 moveSMRDToVALU(Inst, MRI, Worklist);
2346 case AMDGPU::S_AND_B64:
2347 splitScalar64BitBinaryOp(Worklist, Inst, AMDGPU::V_AND_B32_e64);
2348 Inst->eraseFromParent();
2351 case AMDGPU::S_OR_B64:
2352 splitScalar64BitBinaryOp(Worklist, Inst, AMDGPU::V_OR_B32_e64);
2353 Inst->eraseFromParent();
2356 case AMDGPU::S_XOR_B64:
2357 splitScalar64BitBinaryOp(Worklist, Inst, AMDGPU::V_XOR_B32_e64);
2358 Inst->eraseFromParent();
2361 case AMDGPU::S_NOT_B64:
2362 splitScalar64BitUnaryOp(Worklist, Inst, AMDGPU::V_NOT_B32_e32);
2363 Inst->eraseFromParent();
2366 case AMDGPU::S_BCNT1_I32_B64:
2367 splitScalar64BitBCNT(Worklist, Inst);
2368 Inst->eraseFromParent();
2371 case AMDGPU::S_BFE_I64: {
2372 splitScalar64BitBFE(Worklist, Inst);
2373 Inst->eraseFromParent();
2377 case AMDGPU::S_LSHL_B32:
2378 if (ST.getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS) {
2379 NewOpcode = AMDGPU::V_LSHLREV_B32_e64;
2383 case AMDGPU::S_ASHR_I32:
2384 if (ST.getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS) {
2385 NewOpcode = AMDGPU::V_ASHRREV_I32_e64;
2389 case AMDGPU::S_LSHR_B32:
2390 if (ST.getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS) {
2391 NewOpcode = AMDGPU::V_LSHRREV_B32_e64;
2395 case AMDGPU::S_LSHL_B64:
2396 if (ST.getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS) {
2397 NewOpcode = AMDGPU::V_LSHLREV_B64;
2401 case AMDGPU::S_ASHR_I64:
2402 if (ST.getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS) {
2403 NewOpcode = AMDGPU::V_ASHRREV_I64;
2407 case AMDGPU::S_LSHR_B64:
2408 if (ST.getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS) {
2409 NewOpcode = AMDGPU::V_LSHRREV_B64;
2414 case AMDGPU::S_ABS_I32:
2415 lowerScalarAbs(Worklist, Inst);
2416 Inst->eraseFromParent();
2419 case AMDGPU::S_BFE_U64:
2420 case AMDGPU::S_BFM_B64:
2421 llvm_unreachable("Moving this op to VALU not implemented");
2424 if (NewOpcode == AMDGPU::INSTRUCTION_LIST_END) {
2425 // We cannot move this instruction to the VALU, so we should try to
2426 // legalize its operands instead.
2427 legalizeOperands(Inst);
2431 // Use the new VALU Opcode.
2432 const MCInstrDesc &NewDesc = get(NewOpcode);
2433 Inst->setDesc(NewDesc);
2435 // Remove any references to SCC. Vector instructions can't read from it, and
2436 // We're just about to add the implicit use / defs of VCC, and we don't want
2438 for (unsigned i = Inst->getNumOperands() - 1; i > 0; --i) {
2439 MachineOperand &Op = Inst->getOperand(i);
2440 if (Op.isReg() && Op.getReg() == AMDGPU::SCC)
2441 Inst->RemoveOperand(i);
2444 if (Opcode == AMDGPU::S_SEXT_I32_I8 || Opcode == AMDGPU::S_SEXT_I32_I16) {
2445 // We are converting these to a BFE, so we need to add the missing
2446 // operands for the size and offset.
2447 unsigned Size = (Opcode == AMDGPU::S_SEXT_I32_I8) ? 8 : 16;
2448 Inst->addOperand(MachineOperand::CreateImm(0));
2449 Inst->addOperand(MachineOperand::CreateImm(Size));
2451 } else if (Opcode == AMDGPU::S_BCNT1_I32_B32) {
2452 // The VALU version adds the second operand to the result, so insert an
2454 Inst->addOperand(MachineOperand::CreateImm(0));
2457 Inst->addImplicitDefUseOperands(*Inst->getParent()->getParent());
2459 if (Opcode == AMDGPU::S_BFE_I32 || Opcode == AMDGPU::S_BFE_U32) {
2460 const MachineOperand &OffsetWidthOp = Inst->getOperand(2);
2461 // If we need to move this to VGPRs, we need to unpack the second operand
2462 // back into the 2 separate ones for bit offset and width.
2463 assert(OffsetWidthOp.isImm() &&
2464 "Scalar BFE is only implemented for constant width and offset");
2465 uint32_t Imm = OffsetWidthOp.getImm();
2467 uint32_t Offset = Imm & 0x3f; // Extract bits [5:0].
2468 uint32_t BitWidth = (Imm & 0x7f0000) >> 16; // Extract bits [22:16].
2469 Inst->RemoveOperand(2); // Remove old immediate.
2470 Inst->addOperand(MachineOperand::CreateImm(Offset));
2471 Inst->addOperand(MachineOperand::CreateImm(BitWidth));
2474 // Update the destination register class.
2475 const TargetRegisterClass *NewDstRC = getDestEquivalentVGPRClass(*Inst);
2479 unsigned DstReg = Inst->getOperand(0).getReg();
2480 unsigned NewDstReg = MRI.createVirtualRegister(NewDstRC);
2481 MRI.replaceRegWith(DstReg, NewDstReg);
2483 // Legalize the operands
2484 legalizeOperands(Inst);
2486 addUsersToMoveToVALUWorklist(NewDstReg, MRI, Worklist);
2490 //===----------------------------------------------------------------------===//
2491 // Indirect addressing callbacks
2492 //===----------------------------------------------------------------------===//
2494 unsigned SIInstrInfo::calculateIndirectAddress(unsigned RegIndex,
2495 unsigned Channel) const {
2496 assert(Channel == 0);
2500 const TargetRegisterClass *SIInstrInfo::getIndirectAddrRegClass() const {
2501 return &AMDGPU::VGPR_32RegClass;
2504 void SIInstrInfo::lowerScalarAbs(SmallVectorImpl<MachineInstr *> &Worklist,
2505 MachineInstr *Inst) const {
2506 MachineBasicBlock &MBB = *Inst->getParent();
2507 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
2508 MachineBasicBlock::iterator MII = Inst;
2509 DebugLoc DL = Inst->getDebugLoc();
2511 MachineOperand &Dest = Inst->getOperand(0);
2512 MachineOperand &Src = Inst->getOperand(1);
2513 unsigned TmpReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
2514 unsigned ResultReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
2516 BuildMI(MBB, MII, DL, get(AMDGPU::V_SUB_I32_e32), TmpReg)
2518 .addReg(Src.getReg());
2520 BuildMI(MBB, MII, DL, get(AMDGPU::V_MAX_I32_e64), ResultReg)
2521 .addReg(Src.getReg())
2524 MRI.replaceRegWith(Dest.getReg(), ResultReg);
2525 addUsersToMoveToVALUWorklist(ResultReg, MRI, Worklist);
2528 void SIInstrInfo::splitScalar64BitUnaryOp(
2529 SmallVectorImpl<MachineInstr *> &Worklist,
2531 unsigned Opcode) const {
2532 MachineBasicBlock &MBB = *Inst->getParent();
2533 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
2535 MachineOperand &Dest = Inst->getOperand(0);
2536 MachineOperand &Src0 = Inst->getOperand(1);
2537 DebugLoc DL = Inst->getDebugLoc();
2539 MachineBasicBlock::iterator MII = Inst;
2541 const MCInstrDesc &InstDesc = get(Opcode);
2542 const TargetRegisterClass *Src0RC = Src0.isReg() ?
2543 MRI.getRegClass(Src0.getReg()) :
2544 &AMDGPU::SGPR_32RegClass;
2546 const TargetRegisterClass *Src0SubRC = RI.getSubRegClass(Src0RC, AMDGPU::sub0);
2548 MachineOperand SrcReg0Sub0 = buildExtractSubRegOrImm(MII, MRI, Src0, Src0RC,
2549 AMDGPU::sub0, Src0SubRC);
2551 const TargetRegisterClass *DestRC = MRI.getRegClass(Dest.getReg());
2552 const TargetRegisterClass *NewDestRC = RI.getEquivalentVGPRClass(DestRC);
2553 const TargetRegisterClass *NewDestSubRC = RI.getSubRegClass(NewDestRC, AMDGPU::sub0);
2555 unsigned DestSub0 = MRI.createVirtualRegister(NewDestSubRC);
2556 BuildMI(MBB, MII, DL, InstDesc, DestSub0)
2557 .addOperand(SrcReg0Sub0);
2559 MachineOperand SrcReg0Sub1 = buildExtractSubRegOrImm(MII, MRI, Src0, Src0RC,
2560 AMDGPU::sub1, Src0SubRC);
2562 unsigned DestSub1 = MRI.createVirtualRegister(NewDestSubRC);
2563 BuildMI(MBB, MII, DL, InstDesc, DestSub1)
2564 .addOperand(SrcReg0Sub1);
2566 unsigned FullDestReg = MRI.createVirtualRegister(NewDestRC);
2567 BuildMI(MBB, MII, DL, get(TargetOpcode::REG_SEQUENCE), FullDestReg)
2569 .addImm(AMDGPU::sub0)
2571 .addImm(AMDGPU::sub1);
2573 MRI.replaceRegWith(Dest.getReg(), FullDestReg);
2575 // We don't need to legalizeOperands here because for a single operand, src0
2576 // will support any kind of input.
2578 // Move all users of this moved value.
2579 addUsersToMoveToVALUWorklist(FullDestReg, MRI, Worklist);
2582 void SIInstrInfo::splitScalar64BitBinaryOp(
2583 SmallVectorImpl<MachineInstr *> &Worklist,
2585 unsigned Opcode) const {
2586 MachineBasicBlock &MBB = *Inst->getParent();
2587 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
2589 MachineOperand &Dest = Inst->getOperand(0);
2590 MachineOperand &Src0 = Inst->getOperand(1);
2591 MachineOperand &Src1 = Inst->getOperand(2);
2592 DebugLoc DL = Inst->getDebugLoc();
2594 MachineBasicBlock::iterator MII = Inst;
2596 const MCInstrDesc &InstDesc = get(Opcode);
2597 const TargetRegisterClass *Src0RC = Src0.isReg() ?
2598 MRI.getRegClass(Src0.getReg()) :
2599 &AMDGPU::SGPR_32RegClass;
2601 const TargetRegisterClass *Src0SubRC = RI.getSubRegClass(Src0RC, AMDGPU::sub0);
2602 const TargetRegisterClass *Src1RC = Src1.isReg() ?
2603 MRI.getRegClass(Src1.getReg()) :
2604 &AMDGPU::SGPR_32RegClass;
2606 const TargetRegisterClass *Src1SubRC = RI.getSubRegClass(Src1RC, AMDGPU::sub0);
2608 MachineOperand SrcReg0Sub0 = buildExtractSubRegOrImm(MII, MRI, Src0, Src0RC,
2609 AMDGPU::sub0, Src0SubRC);
2610 MachineOperand SrcReg1Sub0 = buildExtractSubRegOrImm(MII, MRI, Src1, Src1RC,
2611 AMDGPU::sub0, Src1SubRC);
2613 const TargetRegisterClass *DestRC = MRI.getRegClass(Dest.getReg());
2614 const TargetRegisterClass *NewDestRC = RI.getEquivalentVGPRClass(DestRC);
2615 const TargetRegisterClass *NewDestSubRC = RI.getSubRegClass(NewDestRC, AMDGPU::sub0);
2617 unsigned DestSub0 = MRI.createVirtualRegister(NewDestSubRC);
2618 MachineInstr *LoHalf = BuildMI(MBB, MII, DL, InstDesc, DestSub0)
2619 .addOperand(SrcReg0Sub0)
2620 .addOperand(SrcReg1Sub0);
2622 MachineOperand SrcReg0Sub1 = buildExtractSubRegOrImm(MII, MRI, Src0, Src0RC,
2623 AMDGPU::sub1, Src0SubRC);
2624 MachineOperand SrcReg1Sub1 = buildExtractSubRegOrImm(MII, MRI, Src1, Src1RC,
2625 AMDGPU::sub1, Src1SubRC);
2627 unsigned DestSub1 = MRI.createVirtualRegister(NewDestSubRC);
2628 MachineInstr *HiHalf = BuildMI(MBB, MII, DL, InstDesc, DestSub1)
2629 .addOperand(SrcReg0Sub1)
2630 .addOperand(SrcReg1Sub1);
2632 unsigned FullDestReg = MRI.createVirtualRegister(NewDestRC);
2633 BuildMI(MBB, MII, DL, get(TargetOpcode::REG_SEQUENCE), FullDestReg)
2635 .addImm(AMDGPU::sub0)
2637 .addImm(AMDGPU::sub1);
2639 MRI.replaceRegWith(Dest.getReg(), FullDestReg);
2641 // Try to legalize the operands in case we need to swap the order to keep it
2643 legalizeOperands(LoHalf);
2644 legalizeOperands(HiHalf);
2646 // Move all users of this moved vlaue.
2647 addUsersToMoveToVALUWorklist(FullDestReg, MRI, Worklist);
2650 void SIInstrInfo::splitScalar64BitBCNT(SmallVectorImpl<MachineInstr *> &Worklist,
2651 MachineInstr *Inst) const {
2652 MachineBasicBlock &MBB = *Inst->getParent();
2653 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
2655 MachineBasicBlock::iterator MII = Inst;
2656 DebugLoc DL = Inst->getDebugLoc();
2658 MachineOperand &Dest = Inst->getOperand(0);
2659 MachineOperand &Src = Inst->getOperand(1);
2661 const MCInstrDesc &InstDesc = get(AMDGPU::V_BCNT_U32_B32_e64);
2662 const TargetRegisterClass *SrcRC = Src.isReg() ?
2663 MRI.getRegClass(Src.getReg()) :
2664 &AMDGPU::SGPR_32RegClass;
2666 unsigned MidReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
2667 unsigned ResultReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
2669 const TargetRegisterClass *SrcSubRC = RI.getSubRegClass(SrcRC, AMDGPU::sub0);
2671 MachineOperand SrcRegSub0 = buildExtractSubRegOrImm(MII, MRI, Src, SrcRC,
2672 AMDGPU::sub0, SrcSubRC);
2673 MachineOperand SrcRegSub1 = buildExtractSubRegOrImm(MII, MRI, Src, SrcRC,
2674 AMDGPU::sub1, SrcSubRC);
2676 BuildMI(MBB, MII, DL, InstDesc, MidReg)
2677 .addOperand(SrcRegSub0)
2680 BuildMI(MBB, MII, DL, InstDesc, ResultReg)
2681 .addOperand(SrcRegSub1)
2684 MRI.replaceRegWith(Dest.getReg(), ResultReg);
2686 // We don't need to legalize operands here. src0 for etiher instruction can be
2687 // an SGPR, and the second input is unused or determined here.
2688 addUsersToMoveToVALUWorklist(ResultReg, MRI, Worklist);
2691 void SIInstrInfo::splitScalar64BitBFE(SmallVectorImpl<MachineInstr *> &Worklist,
2692 MachineInstr *Inst) const {
2693 MachineBasicBlock &MBB = *Inst->getParent();
2694 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
2695 MachineBasicBlock::iterator MII = Inst;
2696 DebugLoc DL = Inst->getDebugLoc();
2698 MachineOperand &Dest = Inst->getOperand(0);
2699 uint32_t Imm = Inst->getOperand(2).getImm();
2700 uint32_t Offset = Imm & 0x3f; // Extract bits [5:0].
2701 uint32_t BitWidth = (Imm & 0x7f0000) >> 16; // Extract bits [22:16].
2705 // Only sext_inreg cases handled.
2706 assert(Inst->getOpcode() == AMDGPU::S_BFE_I64 &&
2711 if (BitWidth < 32) {
2712 unsigned MidRegLo = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
2713 unsigned MidRegHi = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
2714 unsigned ResultReg = MRI.createVirtualRegister(&AMDGPU::VReg_64RegClass);
2716 BuildMI(MBB, MII, DL, get(AMDGPU::V_BFE_I32), MidRegLo)
2717 .addReg(Inst->getOperand(1).getReg(), 0, AMDGPU::sub0)
2721 BuildMI(MBB, MII, DL, get(AMDGPU::V_ASHRREV_I32_e32), MidRegHi)
2725 BuildMI(MBB, MII, DL, get(TargetOpcode::REG_SEQUENCE), ResultReg)
2727 .addImm(AMDGPU::sub0)
2729 .addImm(AMDGPU::sub1);
2731 MRI.replaceRegWith(Dest.getReg(), ResultReg);
2732 addUsersToMoveToVALUWorklist(ResultReg, MRI, Worklist);
2736 MachineOperand &Src = Inst->getOperand(1);
2737 unsigned TmpReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
2738 unsigned ResultReg = MRI.createVirtualRegister(&AMDGPU::VReg_64RegClass);
2740 BuildMI(MBB, MII, DL, get(AMDGPU::V_ASHRREV_I32_e64), TmpReg)
2742 .addReg(Src.getReg(), 0, AMDGPU::sub0);
2744 BuildMI(MBB, MII, DL, get(TargetOpcode::REG_SEQUENCE), ResultReg)
2745 .addReg(Src.getReg(), 0, AMDGPU::sub0)
2746 .addImm(AMDGPU::sub0)
2748 .addImm(AMDGPU::sub1);
2750 MRI.replaceRegWith(Dest.getReg(), ResultReg);
2751 addUsersToMoveToVALUWorklist(ResultReg, MRI, Worklist);
2754 void SIInstrInfo::addUsersToMoveToVALUWorklist(
2756 MachineRegisterInfo &MRI,
2757 SmallVectorImpl<MachineInstr *> &Worklist) const {
2758 for (MachineRegisterInfo::use_iterator I = MRI.use_begin(DstReg),
2759 E = MRI.use_end(); I != E; ++I) {
2760 MachineInstr &UseMI = *I->getParent();
2761 if (!canReadVGPR(UseMI, I.getOperandNo())) {
2762 Worklist.push_back(&UseMI);
2767 const TargetRegisterClass *SIInstrInfo::getDestEquivalentVGPRClass(
2768 const MachineInstr &Inst) const {
2769 const TargetRegisterClass *NewDstRC = getOpRegClass(Inst, 0);
2771 switch (Inst.getOpcode()) {
2772 // For target instructions, getOpRegClass just returns the virtual register
2773 // class associated with the operand, so we need to find an equivalent VGPR
2774 // register class in order to move the instruction to the VALU.
2777 case AMDGPU::REG_SEQUENCE:
2778 case AMDGPU::INSERT_SUBREG:
2779 if (RI.hasVGPRs(NewDstRC))
2782 NewDstRC = RI.getEquivalentVGPRClass(NewDstRC);
2791 // Find the one SGPR operand we are allowed to use.
2792 unsigned SIInstrInfo::findUsedSGPR(const MachineInstr *MI,
2793 int OpIndices[3]) const {
2794 const MCInstrDesc &Desc = MI->getDesc();
2796 // Find the one SGPR operand we are allowed to use.
2798 // First we need to consider the instruction's operand requirements before
2799 // legalizing. Some operands are required to be SGPRs, such as implicit uses
2800 // of VCC, but we are still bound by the constant bus requirement to only use
2803 // If the operand's class is an SGPR, we can never move it.
2805 unsigned SGPRReg = findImplicitSGPRRead(*MI);
2806 if (SGPRReg != AMDGPU::NoRegister)
2809 unsigned UsedSGPRs[3] = { AMDGPU::NoRegister };
2810 const MachineRegisterInfo &MRI = MI->getParent()->getParent()->getRegInfo();
2812 for (unsigned i = 0; i < 3; ++i) {
2813 int Idx = OpIndices[i];
2817 const MachineOperand &MO = MI->getOperand(Idx);
2821 // Is this operand statically required to be an SGPR based on the operand
2823 const TargetRegisterClass *OpRC = RI.getRegClass(Desc.OpInfo[Idx].RegClass);
2824 bool IsRequiredSGPR = RI.isSGPRClass(OpRC);
2828 // If this could be a VGPR or an SGPR, Check the dynamic register class.
2829 unsigned Reg = MO.getReg();
2830 const TargetRegisterClass *RegRC = MRI.getRegClass(Reg);
2831 if (RI.isSGPRClass(RegRC))
2835 // We don't have a required SGPR operand, so we have a bit more freedom in
2836 // selecting operands to move.
2838 // Try to select the most used SGPR. If an SGPR is equal to one of the
2839 // others, we choose that.
2842 // V_FMA_F32 v0, s0, s0, s0 -> No moves
2843 // V_FMA_F32 v0, s0, s1, s0 -> Move s1
2845 // TODO: If some of the operands are 64-bit SGPRs and some 32, we should
2848 if (UsedSGPRs[0] != AMDGPU::NoRegister) {
2849 if (UsedSGPRs[0] == UsedSGPRs[1] || UsedSGPRs[0] == UsedSGPRs[2])
2850 SGPRReg = UsedSGPRs[0];
2853 if (SGPRReg == AMDGPU::NoRegister && UsedSGPRs[1] != AMDGPU::NoRegister) {
2854 if (UsedSGPRs[1] == UsedSGPRs[2])
2855 SGPRReg = UsedSGPRs[1];
2861 MachineInstrBuilder SIInstrInfo::buildIndirectWrite(
2862 MachineBasicBlock *MBB,
2863 MachineBasicBlock::iterator I,
2865 unsigned Address, unsigned OffsetReg) const {
2866 const DebugLoc &DL = MBB->findDebugLoc(I);
2867 unsigned IndirectBaseReg = AMDGPU::VGPR_32RegClass.getRegister(
2868 getIndirectIndexBegin(*MBB->getParent()));
2870 return BuildMI(*MBB, I, DL, get(AMDGPU::SI_INDIRECT_DST_V1))
2871 .addReg(IndirectBaseReg, RegState::Define)
2872 .addOperand(I->getOperand(0))
2873 .addReg(IndirectBaseReg)
2879 MachineInstrBuilder SIInstrInfo::buildIndirectRead(
2880 MachineBasicBlock *MBB,
2881 MachineBasicBlock::iterator I,
2883 unsigned Address, unsigned OffsetReg) const {
2884 const DebugLoc &DL = MBB->findDebugLoc(I);
2885 unsigned IndirectBaseReg = AMDGPU::VGPR_32RegClass.getRegister(
2886 getIndirectIndexBegin(*MBB->getParent()));
2888 return BuildMI(*MBB, I, DL, get(AMDGPU::SI_INDIRECT_SRC_V1))
2889 .addOperand(I->getOperand(0))
2890 .addOperand(I->getOperand(1))
2891 .addReg(IndirectBaseReg)
2897 void SIInstrInfo::reserveIndirectRegisters(BitVector &Reserved,
2898 const MachineFunction &MF) const {
2899 int End = getIndirectIndexEnd(MF);
2900 int Begin = getIndirectIndexBegin(MF);
2906 for (int Index = Begin; Index <= End; ++Index)
2907 Reserved.set(AMDGPU::VGPR_32RegClass.getRegister(Index));
2909 for (int Index = std::max(0, Begin - 1); Index <= End; ++Index)
2910 Reserved.set(AMDGPU::VReg_64RegClass.getRegister(Index));
2912 for (int Index = std::max(0, Begin - 2); Index <= End; ++Index)
2913 Reserved.set(AMDGPU::VReg_96RegClass.getRegister(Index));
2915 for (int Index = std::max(0, Begin - 3); Index <= End; ++Index)
2916 Reserved.set(AMDGPU::VReg_128RegClass.getRegister(Index));
2918 for (int Index = std::max(0, Begin - 7); Index <= End; ++Index)
2919 Reserved.set(AMDGPU::VReg_256RegClass.getRegister(Index));
2921 for (int Index = std::max(0, Begin - 15); Index <= End; ++Index)
2922 Reserved.set(AMDGPU::VReg_512RegClass.getRegister(Index));
2925 MachineOperand *SIInstrInfo::getNamedOperand(MachineInstr &MI,
2926 unsigned OperandName) const {
2927 int Idx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), OperandName);
2931 return &MI.getOperand(Idx);
2934 uint64_t SIInstrInfo::getDefaultRsrcDataFormat() const {
2935 uint64_t RsrcDataFormat = AMDGPU::RSRC_DATA_FORMAT;
2936 if (ST.isAmdHsaOS()) {
2937 RsrcDataFormat |= (1ULL << 56);
2939 if (ST.getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS)
2941 RsrcDataFormat |= (2ULL << 59);
2944 return RsrcDataFormat;
2947 uint64_t SIInstrInfo::getScratchRsrcWords23() const {
2948 uint64_t Rsrc23 = getDefaultRsrcDataFormat() |
2949 AMDGPU::RSRC_TID_ENABLE |
2950 0xffffffff; // Size;
2952 // If TID_ENABLE is set, DATA_FORMAT specifies stride bits [14:17].
2953 // Clear them unless we want a huge stride.
2954 if (ST.getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS)
2955 Rsrc23 &= ~AMDGPU::RSRC_DATA_FORMAT;