1 //===-- SIInstrInfo.cpp - SI Instruction Information ---------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// \brief SI Implementation of TargetInstrInfo.
13 //===----------------------------------------------------------------------===//
16 #include "SIInstrInfo.h"
17 #include "AMDGPUTargetMachine.h"
18 #include "SIDefines.h"
19 #include "SIMachineFunctionInfo.h"
20 #include "llvm/CodeGen/MachineFrameInfo.h"
21 #include "llvm/CodeGen/MachineInstrBuilder.h"
22 #include "llvm/CodeGen/MachineRegisterInfo.h"
23 #include "llvm/IR/Function.h"
24 #include "llvm/CodeGen/RegisterScavenging.h"
25 #include "llvm/MC/MCInstrDesc.h"
26 #include "llvm/Support/Debug.h"
30 SIInstrInfo::SIInstrInfo(const AMDGPUSubtarget &st)
31 : AMDGPUInstrInfo(st), RI() {}
33 //===----------------------------------------------------------------------===//
34 // TargetInstrInfo callbacks
35 //===----------------------------------------------------------------------===//
37 static unsigned getNumOperandsNoGlue(SDNode *Node) {
38 unsigned N = Node->getNumOperands();
39 while (N && Node->getOperand(N - 1).getValueType() == MVT::Glue)
44 static SDValue findChainOperand(SDNode *Load) {
45 SDValue LastOp = Load->getOperand(getNumOperandsNoGlue(Load) - 1);
46 assert(LastOp.getValueType() == MVT::Other && "Chain missing from load node");
50 /// \brief Returns true if both nodes have the same value for the given
51 /// operand \p Op, or if both nodes do not have this operand.
52 static bool nodesHaveSameOperandValue(SDNode *N0, SDNode* N1, unsigned OpName) {
53 unsigned Opc0 = N0->getMachineOpcode();
54 unsigned Opc1 = N1->getMachineOpcode();
56 int Op0Idx = AMDGPU::getNamedOperandIdx(Opc0, OpName);
57 int Op1Idx = AMDGPU::getNamedOperandIdx(Opc1, OpName);
59 if (Op0Idx == -1 && Op1Idx == -1)
63 if ((Op0Idx == -1 && Op1Idx != -1) ||
64 (Op1Idx == -1 && Op0Idx != -1))
67 // getNamedOperandIdx returns the index for the MachineInstr's operands,
68 // which includes the result as the first operand. We are indexing into the
69 // MachineSDNode's operands, so we need to skip the result operand to get
74 return N0->getOperand(Op0Idx) == N1->getOperand(Op1Idx);
77 bool SIInstrInfo::isReallyTriviallyReMaterializable(const MachineInstr *MI,
78 AliasAnalysis *AA) const {
79 // TODO: The generic check fails for VALU instructions that should be
80 // rematerializable due to implicit reads of exec. We really want all of the
81 // generic logic for this except for this.
82 switch (MI->getOpcode()) {
83 case AMDGPU::V_MOV_B32_e32:
84 case AMDGPU::V_MOV_B32_e64:
85 case AMDGPU::V_MOV_B64_PSEUDO:
92 bool SIInstrInfo::areLoadsFromSameBasePtr(SDNode *Load0, SDNode *Load1,
94 int64_t &Offset1) const {
95 if (!Load0->isMachineOpcode() || !Load1->isMachineOpcode())
98 unsigned Opc0 = Load0->getMachineOpcode();
99 unsigned Opc1 = Load1->getMachineOpcode();
101 // Make sure both are actually loads.
102 if (!get(Opc0).mayLoad() || !get(Opc1).mayLoad())
105 if (isDS(Opc0) && isDS(Opc1)) {
107 // FIXME: Handle this case:
108 if (getNumOperandsNoGlue(Load0) != getNumOperandsNoGlue(Load1))
112 if (Load0->getOperand(1) != Load1->getOperand(1))
116 if (findChainOperand(Load0) != findChainOperand(Load1))
119 // Skip read2 / write2 variants for simplicity.
120 // TODO: We should report true if the used offsets are adjacent (excluded
122 if (AMDGPU::getNamedOperandIdx(Opc0, AMDGPU::OpName::data1) != -1 ||
123 AMDGPU::getNamedOperandIdx(Opc1, AMDGPU::OpName::data1) != -1)
126 Offset0 = cast<ConstantSDNode>(Load0->getOperand(2))->getZExtValue();
127 Offset1 = cast<ConstantSDNode>(Load1->getOperand(2))->getZExtValue();
131 if (isSMRD(Opc0) && isSMRD(Opc1)) {
132 assert(getNumOperandsNoGlue(Load0) == getNumOperandsNoGlue(Load1));
135 if (Load0->getOperand(0) != Load1->getOperand(0))
138 const ConstantSDNode *Load0Offset =
139 dyn_cast<ConstantSDNode>(Load0->getOperand(1));
140 const ConstantSDNode *Load1Offset =
141 dyn_cast<ConstantSDNode>(Load1->getOperand(1));
143 if (!Load0Offset || !Load1Offset)
147 if (findChainOperand(Load0) != findChainOperand(Load1))
150 Offset0 = Load0Offset->getZExtValue();
151 Offset1 = Load1Offset->getZExtValue();
155 // MUBUF and MTBUF can access the same addresses.
156 if ((isMUBUF(Opc0) || isMTBUF(Opc0)) && (isMUBUF(Opc1) || isMTBUF(Opc1))) {
158 // MUBUF and MTBUF have vaddr at different indices.
159 if (!nodesHaveSameOperandValue(Load0, Load1, AMDGPU::OpName::soffset) ||
160 findChainOperand(Load0) != findChainOperand(Load1) ||
161 !nodesHaveSameOperandValue(Load0, Load1, AMDGPU::OpName::vaddr) ||
162 !nodesHaveSameOperandValue(Load0, Load1, AMDGPU::OpName::srsrc))
165 int OffIdx0 = AMDGPU::getNamedOperandIdx(Opc0, AMDGPU::OpName::offset);
166 int OffIdx1 = AMDGPU::getNamedOperandIdx(Opc1, AMDGPU::OpName::offset);
168 if (OffIdx0 == -1 || OffIdx1 == -1)
171 // getNamedOperandIdx returns the index for MachineInstrs. Since they
172 // inlcude the output in the operand list, but SDNodes don't, we need to
173 // subtract the index by one.
177 SDValue Off0 = Load0->getOperand(OffIdx0);
178 SDValue Off1 = Load1->getOperand(OffIdx1);
180 // The offset might be a FrameIndexSDNode.
181 if (!isa<ConstantSDNode>(Off0) || !isa<ConstantSDNode>(Off1))
184 Offset0 = cast<ConstantSDNode>(Off0)->getZExtValue();
185 Offset1 = cast<ConstantSDNode>(Off1)->getZExtValue();
192 static bool isStride64(unsigned Opc) {
194 case AMDGPU::DS_READ2ST64_B32:
195 case AMDGPU::DS_READ2ST64_B64:
196 case AMDGPU::DS_WRITE2ST64_B32:
197 case AMDGPU::DS_WRITE2ST64_B64:
204 bool SIInstrInfo::getMemOpBaseRegImmOfs(MachineInstr *LdSt, unsigned &BaseReg,
206 const TargetRegisterInfo *TRI) const {
207 unsigned Opc = LdSt->getOpcode();
210 const MachineOperand *OffsetImm = getNamedOperand(*LdSt,
211 AMDGPU::OpName::offset);
213 // Normal, single offset LDS instruction.
214 const MachineOperand *AddrReg = getNamedOperand(*LdSt,
215 AMDGPU::OpName::addr);
217 BaseReg = AddrReg->getReg();
218 Offset = OffsetImm->getImm();
222 // The 2 offset instructions use offset0 and offset1 instead. We can treat
223 // these as a load with a single offset if the 2 offsets are consecutive. We
224 // will use this for some partially aligned loads.
225 const MachineOperand *Offset0Imm = getNamedOperand(*LdSt,
226 AMDGPU::OpName::offset0);
227 const MachineOperand *Offset1Imm = getNamedOperand(*LdSt,
228 AMDGPU::OpName::offset1);
230 uint8_t Offset0 = Offset0Imm->getImm();
231 uint8_t Offset1 = Offset1Imm->getImm();
233 if (Offset1 > Offset0 && Offset1 - Offset0 == 1) {
234 // Each of these offsets is in element sized units, so we need to convert
235 // to bytes of the individual reads.
239 EltSize = getOpRegClass(*LdSt, 0)->getSize() / 2;
241 assert(LdSt->mayStore());
242 int Data0Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::data0);
243 EltSize = getOpRegClass(*LdSt, Data0Idx)->getSize();
249 const MachineOperand *AddrReg = getNamedOperand(*LdSt,
250 AMDGPU::OpName::addr);
251 BaseReg = AddrReg->getReg();
252 Offset = EltSize * Offset0;
259 if (isMUBUF(*LdSt) || isMTBUF(*LdSt)) {
260 if (AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::soffset) != -1)
263 const MachineOperand *AddrReg = getNamedOperand(*LdSt,
264 AMDGPU::OpName::vaddr);
268 const MachineOperand *OffsetImm = getNamedOperand(*LdSt,
269 AMDGPU::OpName::offset);
270 BaseReg = AddrReg->getReg();
271 Offset = OffsetImm->getImm();
276 const MachineOperand *OffsetImm = getNamedOperand(*LdSt,
277 AMDGPU::OpName::offset);
281 const MachineOperand *SBaseReg = getNamedOperand(*LdSt,
282 AMDGPU::OpName::sbase);
283 BaseReg = SBaseReg->getReg();
284 Offset = OffsetImm->getImm();
291 bool SIInstrInfo::shouldClusterLoads(MachineInstr *FirstLdSt,
292 MachineInstr *SecondLdSt,
293 unsigned NumLoads) const {
294 // TODO: This needs finer tuning
298 if (isDS(*FirstLdSt) && isDS(*SecondLdSt))
301 if (isSMRD(*FirstLdSt) && isSMRD(*SecondLdSt))
304 if ((isMUBUF(*FirstLdSt) || isMTBUF(*FirstLdSt)) &&
305 (isMUBUF(*SecondLdSt) || isMTBUF(*SecondLdSt)))
312 SIInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
313 MachineBasicBlock::iterator MI, DebugLoc DL,
314 unsigned DestReg, unsigned SrcReg,
315 bool KillSrc) const {
317 // If we are trying to copy to or from SCC, there is a bug somewhere else in
318 // the backend. While it may be theoretically possible to do this, it should
319 // never be necessary.
320 assert(DestReg != AMDGPU::SCC && SrcReg != AMDGPU::SCC);
322 static const int16_t Sub0_15[] = {
323 AMDGPU::sub0, AMDGPU::sub1, AMDGPU::sub2, AMDGPU::sub3,
324 AMDGPU::sub4, AMDGPU::sub5, AMDGPU::sub6, AMDGPU::sub7,
325 AMDGPU::sub8, AMDGPU::sub9, AMDGPU::sub10, AMDGPU::sub11,
326 AMDGPU::sub12, AMDGPU::sub13, AMDGPU::sub14, AMDGPU::sub15, 0
329 static const int16_t Sub0_7[] = {
330 AMDGPU::sub0, AMDGPU::sub1, AMDGPU::sub2, AMDGPU::sub3,
331 AMDGPU::sub4, AMDGPU::sub5, AMDGPU::sub6, AMDGPU::sub7, 0
334 static const int16_t Sub0_3[] = {
335 AMDGPU::sub0, AMDGPU::sub1, AMDGPU::sub2, AMDGPU::sub3, 0
338 static const int16_t Sub0_2[] = {
339 AMDGPU::sub0, AMDGPU::sub1, AMDGPU::sub2, 0
342 static const int16_t Sub0_1[] = {
343 AMDGPU::sub0, AMDGPU::sub1, 0
347 const int16_t *SubIndices;
349 if (AMDGPU::SReg_32RegClass.contains(DestReg)) {
350 assert(AMDGPU::SReg_32RegClass.contains(SrcReg));
351 BuildMI(MBB, MI, DL, get(AMDGPU::S_MOV_B32), DestReg)
352 .addReg(SrcReg, getKillRegState(KillSrc));
355 } else if (AMDGPU::SReg_64RegClass.contains(DestReg)) {
356 if (DestReg == AMDGPU::VCC) {
357 if (AMDGPU::SReg_64RegClass.contains(SrcReg)) {
358 BuildMI(MBB, MI, DL, get(AMDGPU::S_MOV_B64), AMDGPU::VCC)
359 .addReg(SrcReg, getKillRegState(KillSrc));
361 // FIXME: Hack until VReg_1 removed.
362 assert(AMDGPU::VGPR_32RegClass.contains(SrcReg));
363 BuildMI(MBB, MI, DL, get(AMDGPU::V_CMP_NE_I32_e32))
365 .addReg(SrcReg, getKillRegState(KillSrc));
371 assert(AMDGPU::SReg_64RegClass.contains(SrcReg));
372 BuildMI(MBB, MI, DL, get(AMDGPU::S_MOV_B64), DestReg)
373 .addReg(SrcReg, getKillRegState(KillSrc));
376 } else if (AMDGPU::SReg_128RegClass.contains(DestReg)) {
377 assert(AMDGPU::SReg_128RegClass.contains(SrcReg));
378 Opcode = AMDGPU::S_MOV_B32;
381 } else if (AMDGPU::SReg_256RegClass.contains(DestReg)) {
382 assert(AMDGPU::SReg_256RegClass.contains(SrcReg));
383 Opcode = AMDGPU::S_MOV_B32;
386 } else if (AMDGPU::SReg_512RegClass.contains(DestReg)) {
387 assert(AMDGPU::SReg_512RegClass.contains(SrcReg));
388 Opcode = AMDGPU::S_MOV_B32;
389 SubIndices = Sub0_15;
391 } else if (AMDGPU::VGPR_32RegClass.contains(DestReg)) {
392 assert(AMDGPU::VGPR_32RegClass.contains(SrcReg) ||
393 AMDGPU::SReg_32RegClass.contains(SrcReg));
394 BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), DestReg)
395 .addReg(SrcReg, getKillRegState(KillSrc));
398 } else if (AMDGPU::VReg_64RegClass.contains(DestReg)) {
399 assert(AMDGPU::VReg_64RegClass.contains(SrcReg) ||
400 AMDGPU::SReg_64RegClass.contains(SrcReg));
401 Opcode = AMDGPU::V_MOV_B32_e32;
404 } else if (AMDGPU::VReg_96RegClass.contains(DestReg)) {
405 assert(AMDGPU::VReg_96RegClass.contains(SrcReg));
406 Opcode = AMDGPU::V_MOV_B32_e32;
409 } else if (AMDGPU::VReg_128RegClass.contains(DestReg)) {
410 assert(AMDGPU::VReg_128RegClass.contains(SrcReg) ||
411 AMDGPU::SReg_128RegClass.contains(SrcReg));
412 Opcode = AMDGPU::V_MOV_B32_e32;
415 } else if (AMDGPU::VReg_256RegClass.contains(DestReg)) {
416 assert(AMDGPU::VReg_256RegClass.contains(SrcReg) ||
417 AMDGPU::SReg_256RegClass.contains(SrcReg));
418 Opcode = AMDGPU::V_MOV_B32_e32;
421 } else if (AMDGPU::VReg_512RegClass.contains(DestReg)) {
422 assert(AMDGPU::VReg_512RegClass.contains(SrcReg) ||
423 AMDGPU::SReg_512RegClass.contains(SrcReg));
424 Opcode = AMDGPU::V_MOV_B32_e32;
425 SubIndices = Sub0_15;
428 llvm_unreachable("Can't copy register!");
431 while (unsigned SubIdx = *SubIndices++) {
432 MachineInstrBuilder Builder = BuildMI(MBB, MI, DL,
433 get(Opcode), RI.getSubReg(DestReg, SubIdx));
435 Builder.addReg(RI.getSubReg(SrcReg, SubIdx), getKillRegState(KillSrc));
438 Builder.addReg(DestReg, RegState::Define | RegState::Implicit);
442 int SIInstrInfo::commuteOpcode(const MachineInstr &MI) const {
443 const unsigned Opcode = MI.getOpcode();
447 // Try to map original to commuted opcode
448 NewOpc = AMDGPU::getCommuteRev(Opcode);
450 // Check if the commuted (REV) opcode exists on the target.
451 return pseudoToMCOpcode(NewOpc) != -1 ? NewOpc : -1;
453 // Try to map commuted to original opcode
454 NewOpc = AMDGPU::getCommuteOrig(Opcode);
456 // Check if the original (non-REV) opcode exists on the target.
457 return pseudoToMCOpcode(NewOpc) != -1 ? NewOpc : -1;
462 unsigned SIInstrInfo::getMovOpcode(const TargetRegisterClass *DstRC) const {
464 if (DstRC->getSize() == 4) {
465 return RI.isSGPRClass(DstRC) ? AMDGPU::S_MOV_B32 : AMDGPU::V_MOV_B32_e32;
466 } else if (DstRC->getSize() == 8 && RI.isSGPRClass(DstRC)) {
467 return AMDGPU::S_MOV_B64;
468 } else if (DstRC->getSize() == 8 && !RI.isSGPRClass(DstRC)) {
469 return AMDGPU::V_MOV_B64_PSEUDO;
474 void SIInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
475 MachineBasicBlock::iterator MI,
476 unsigned SrcReg, bool isKill,
478 const TargetRegisterClass *RC,
479 const TargetRegisterInfo *TRI) const {
480 MachineFunction *MF = MBB.getParent();
481 SIMachineFunctionInfo *MFI = MF->getInfo<SIMachineFunctionInfo>();
482 MachineFrameInfo *FrameInfo = MF->getFrameInfo();
483 DebugLoc DL = MBB.findDebugLoc(MI);
486 if (RI.isSGPRClass(RC)) {
487 // We are only allowed to create one new instruction when spilling
488 // registers, so we need to use pseudo instruction for spilling
490 switch (RC->getSize() * 8) {
491 case 32: Opcode = AMDGPU::SI_SPILL_S32_SAVE; break;
492 case 64: Opcode = AMDGPU::SI_SPILL_S64_SAVE; break;
493 case 128: Opcode = AMDGPU::SI_SPILL_S128_SAVE; break;
494 case 256: Opcode = AMDGPU::SI_SPILL_S256_SAVE; break;
495 case 512: Opcode = AMDGPU::SI_SPILL_S512_SAVE; break;
497 } else if(RI.hasVGPRs(RC) && ST.isVGPRSpillingEnabled(MFI)) {
498 MFI->setHasSpilledVGPRs();
500 switch(RC->getSize() * 8) {
501 case 32: Opcode = AMDGPU::SI_SPILL_V32_SAVE; break;
502 case 64: Opcode = AMDGPU::SI_SPILL_V64_SAVE; break;
503 case 96: Opcode = AMDGPU::SI_SPILL_V96_SAVE; break;
504 case 128: Opcode = AMDGPU::SI_SPILL_V128_SAVE; break;
505 case 256: Opcode = AMDGPU::SI_SPILL_V256_SAVE; break;
506 case 512: Opcode = AMDGPU::SI_SPILL_V512_SAVE; break;
511 MachinePointerInfo PtrInfo
512 = MachinePointerInfo::getFixedStack(*MF, FrameIndex);
513 unsigned Size = FrameInfo->getObjectSize(FrameIndex);
514 unsigned Align = FrameInfo->getObjectAlignment(FrameIndex);
515 MachineMemOperand *MMO
516 = MF->getMachineMemOperand(PtrInfo, MachineMemOperand::MOStore,
519 FrameInfo->setObjectAlignment(FrameIndex, 4);
520 BuildMI(MBB, MI, DL, get(Opcode))
522 .addFrameIndex(FrameIndex)
523 // Place-holder registers, these will be filled in by
524 // SIPrepareScratchRegs.
525 .addReg(AMDGPU::SGPR0_SGPR1_SGPR2_SGPR3, RegState::Undef)
526 .addReg(AMDGPU::SGPR0, RegState::Undef)
529 LLVMContext &Ctx = MF->getFunction()->getContext();
530 Ctx.emitError("SIInstrInfo::storeRegToStackSlot - Do not know how to"
532 BuildMI(MBB, MI, DL, get(AMDGPU::KILL))
537 void SIInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
538 MachineBasicBlock::iterator MI,
539 unsigned DestReg, int FrameIndex,
540 const TargetRegisterClass *RC,
541 const TargetRegisterInfo *TRI) const {
542 MachineFunction *MF = MBB.getParent();
543 const SIMachineFunctionInfo *MFI = MF->getInfo<SIMachineFunctionInfo>();
544 MachineFrameInfo *FrameInfo = MF->getFrameInfo();
545 DebugLoc DL = MBB.findDebugLoc(MI);
548 if (RI.isSGPRClass(RC)){
549 switch(RC->getSize() * 8) {
550 case 32: Opcode = AMDGPU::SI_SPILL_S32_RESTORE; break;
551 case 64: Opcode = AMDGPU::SI_SPILL_S64_RESTORE; break;
552 case 128: Opcode = AMDGPU::SI_SPILL_S128_RESTORE; break;
553 case 256: Opcode = AMDGPU::SI_SPILL_S256_RESTORE; break;
554 case 512: Opcode = AMDGPU::SI_SPILL_S512_RESTORE; break;
556 } else if(RI.hasVGPRs(RC) && ST.isVGPRSpillingEnabled(MFI)) {
557 switch(RC->getSize() * 8) {
558 case 32: Opcode = AMDGPU::SI_SPILL_V32_RESTORE; break;
559 case 64: Opcode = AMDGPU::SI_SPILL_V64_RESTORE; break;
560 case 96: Opcode = AMDGPU::SI_SPILL_V96_RESTORE; break;
561 case 128: Opcode = AMDGPU::SI_SPILL_V128_RESTORE; break;
562 case 256: Opcode = AMDGPU::SI_SPILL_V256_RESTORE; break;
563 case 512: Opcode = AMDGPU::SI_SPILL_V512_RESTORE; break;
569 FrameInfo->setObjectAlignment(FrameIndex, Align);
570 unsigned Size = FrameInfo->getObjectSize(FrameIndex);
572 MachinePointerInfo PtrInfo
573 = MachinePointerInfo::getFixedStack(*MF, FrameIndex);
574 MachineMemOperand *MMO = MF->getMachineMemOperand(
575 PtrInfo, MachineMemOperand::MOLoad, Size, Align);
577 BuildMI(MBB, MI, DL, get(Opcode), DestReg)
578 .addFrameIndex(FrameIndex)
579 // Place-holder registers, these will be filled in by
580 // SIPrepareScratchRegs.
581 .addReg(AMDGPU::SGPR0_SGPR1_SGPR2_SGPR3, RegState::Undef)
582 .addReg(AMDGPU::SGPR0, RegState::Undef)
585 LLVMContext &Ctx = MF->getFunction()->getContext();
586 Ctx.emitError("SIInstrInfo::loadRegFromStackSlot - Do not know how to"
587 " restore register");
588 BuildMI(MBB, MI, DL, get(AMDGPU::IMPLICIT_DEF), DestReg);
592 /// \param @Offset Offset in bytes of the FrameIndex being spilled
593 unsigned SIInstrInfo::calculateLDSSpillAddress(MachineBasicBlock &MBB,
594 MachineBasicBlock::iterator MI,
595 RegScavenger *RS, unsigned TmpReg,
596 unsigned FrameOffset,
597 unsigned Size) const {
598 MachineFunction *MF = MBB.getParent();
599 SIMachineFunctionInfo *MFI = MF->getInfo<SIMachineFunctionInfo>();
600 const AMDGPUSubtarget &ST = MF->getSubtarget<AMDGPUSubtarget>();
601 const SIRegisterInfo *TRI =
602 static_cast<const SIRegisterInfo*>(ST.getRegisterInfo());
603 DebugLoc DL = MBB.findDebugLoc(MI);
604 unsigned WorkGroupSize = MFI->getMaximumWorkGroupSize(*MF);
605 unsigned WavefrontSize = ST.getWavefrontSize();
607 unsigned TIDReg = MFI->getTIDReg();
608 if (!MFI->hasCalculatedTID()) {
609 MachineBasicBlock &Entry = MBB.getParent()->front();
610 MachineBasicBlock::iterator Insert = Entry.front();
611 DebugLoc DL = Insert->getDebugLoc();
613 TIDReg = RI.findUnusedRegister(MF->getRegInfo(), &AMDGPU::VGPR_32RegClass);
614 if (TIDReg == AMDGPU::NoRegister)
618 if (MFI->getShaderType() == ShaderType::COMPUTE &&
619 WorkGroupSize > WavefrontSize) {
621 unsigned TIDIGXReg = TRI->getPreloadedValue(*MF, SIRegisterInfo::TIDIG_X);
622 unsigned TIDIGYReg = TRI->getPreloadedValue(*MF, SIRegisterInfo::TIDIG_Y);
623 unsigned TIDIGZReg = TRI->getPreloadedValue(*MF, SIRegisterInfo::TIDIG_Z);
624 unsigned InputPtrReg =
625 TRI->getPreloadedValue(*MF, SIRegisterInfo::INPUT_PTR);
626 for (unsigned Reg : {TIDIGXReg, TIDIGYReg, TIDIGZReg}) {
627 if (!Entry.isLiveIn(Reg))
628 Entry.addLiveIn(Reg);
631 RS->enterBasicBlock(&Entry);
632 unsigned STmp0 = RS->scavengeRegister(&AMDGPU::SGPR_32RegClass, 0);
633 unsigned STmp1 = RS->scavengeRegister(&AMDGPU::SGPR_32RegClass, 0);
634 BuildMI(Entry, Insert, DL, get(AMDGPU::S_LOAD_DWORD_IMM), STmp0)
636 .addImm(SI::KernelInputOffsets::NGROUPS_Z);
637 BuildMI(Entry, Insert, DL, get(AMDGPU::S_LOAD_DWORD_IMM), STmp1)
639 .addImm(SI::KernelInputOffsets::NGROUPS_Y);
641 // NGROUPS.X * NGROUPS.Y
642 BuildMI(Entry, Insert, DL, get(AMDGPU::S_MUL_I32), STmp1)
645 // (NGROUPS.X * NGROUPS.Y) * TIDIG.X
646 BuildMI(Entry, Insert, DL, get(AMDGPU::V_MUL_U32_U24_e32), TIDReg)
649 // NGROUPS.Z * TIDIG.Y + (NGROUPS.X * NGROPUS.Y * TIDIG.X)
650 BuildMI(Entry, Insert, DL, get(AMDGPU::V_MAD_U32_U24), TIDReg)
654 // (NGROUPS.Z * TIDIG.Y + (NGROUPS.X * NGROPUS.Y * TIDIG.X)) + TIDIG.Z
655 BuildMI(Entry, Insert, DL, get(AMDGPU::V_ADD_I32_e32), TIDReg)
660 BuildMI(Entry, Insert, DL, get(AMDGPU::V_MBCNT_LO_U32_B32_e64),
665 BuildMI(Entry, Insert, DL, get(AMDGPU::V_MBCNT_HI_U32_B32_e64),
671 BuildMI(Entry, Insert, DL, get(AMDGPU::V_LSHLREV_B32_e32),
675 MFI->setTIDReg(TIDReg);
678 // Add FrameIndex to LDS offset
679 unsigned LDSOffset = MFI->LDSSize + (FrameOffset * WorkGroupSize);
680 BuildMI(MBB, MI, DL, get(AMDGPU::V_ADD_I32_e32), TmpReg)
687 void SIInstrInfo::insertNOPs(MachineBasicBlock::iterator MI,
696 BuildMI(*MI->getParent(), MI, MI->getDebugLoc(), get(AMDGPU::S_NOP))
701 bool SIInstrInfo::expandPostRAPseudo(MachineBasicBlock::iterator MI) const {
702 MachineBasicBlock &MBB = *MI->getParent();
703 DebugLoc DL = MBB.findDebugLoc(MI);
704 switch (MI->getOpcode()) {
705 default: return AMDGPUInstrInfo::expandPostRAPseudo(MI);
707 case AMDGPU::SI_CONSTDATA_PTR: {
708 unsigned Reg = MI->getOperand(0).getReg();
709 unsigned RegLo = RI.getSubReg(Reg, AMDGPU::sub0);
710 unsigned RegHi = RI.getSubReg(Reg, AMDGPU::sub1);
712 BuildMI(MBB, MI, DL, get(AMDGPU::S_GETPC_B64), Reg);
714 // Add 32-bit offset from this instruction to the start of the constant data.
715 BuildMI(MBB, MI, DL, get(AMDGPU::S_ADD_U32), RegLo)
717 .addTargetIndex(AMDGPU::TI_CONSTDATA_START)
718 .addReg(AMDGPU::SCC, RegState::Define | RegState::Implicit);
719 BuildMI(MBB, MI, DL, get(AMDGPU::S_ADDC_U32), RegHi)
722 .addReg(AMDGPU::SCC, RegState::Define | RegState::Implicit)
723 .addReg(AMDGPU::SCC, RegState::Implicit);
724 MI->eraseFromParent();
727 case AMDGPU::SGPR_USE:
728 // This is just a placeholder for register allocation.
729 MI->eraseFromParent();
732 case AMDGPU::V_MOV_B64_PSEUDO: {
733 unsigned Dst = MI->getOperand(0).getReg();
734 unsigned DstLo = RI.getSubReg(Dst, AMDGPU::sub0);
735 unsigned DstHi = RI.getSubReg(Dst, AMDGPU::sub1);
737 const MachineOperand &SrcOp = MI->getOperand(1);
738 // FIXME: Will this work for 64-bit floating point immediates?
739 assert(!SrcOp.isFPImm());
741 APInt Imm(64, SrcOp.getImm());
742 BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), DstLo)
743 .addImm(Imm.getLoBits(32).getZExtValue())
744 .addReg(Dst, RegState::Implicit);
745 BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), DstHi)
746 .addImm(Imm.getHiBits(32).getZExtValue())
747 .addReg(Dst, RegState::Implicit);
749 assert(SrcOp.isReg());
750 BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), DstLo)
751 .addReg(RI.getSubReg(SrcOp.getReg(), AMDGPU::sub0))
752 .addReg(Dst, RegState::Implicit);
753 BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), DstHi)
754 .addReg(RI.getSubReg(SrcOp.getReg(), AMDGPU::sub1))
755 .addReg(Dst, RegState::Implicit);
757 MI->eraseFromParent();
761 case AMDGPU::V_CNDMASK_B64_PSEUDO: {
762 unsigned Dst = MI->getOperand(0).getReg();
763 unsigned DstLo = RI.getSubReg(Dst, AMDGPU::sub0);
764 unsigned DstHi = RI.getSubReg(Dst, AMDGPU::sub1);
765 unsigned Src0 = MI->getOperand(1).getReg();
766 unsigned Src1 = MI->getOperand(2).getReg();
767 const MachineOperand &SrcCond = MI->getOperand(3);
769 BuildMI(MBB, MI, DL, get(AMDGPU::V_CNDMASK_B32_e64), DstLo)
770 .addReg(RI.getSubReg(Src0, AMDGPU::sub0))
771 .addReg(RI.getSubReg(Src1, AMDGPU::sub0))
772 .addOperand(SrcCond);
773 BuildMI(MBB, MI, DL, get(AMDGPU::V_CNDMASK_B32_e64), DstHi)
774 .addReg(RI.getSubReg(Src0, AMDGPU::sub1))
775 .addReg(RI.getSubReg(Src1, AMDGPU::sub1))
776 .addOperand(SrcCond);
777 MI->eraseFromParent();
784 /// Commutes the operands in the given instruction.
785 /// The commutable operands are specified by their indices OpIdx0 and OpIdx1.
787 /// Do not call this method for a non-commutable instruction or for
788 /// non-commutable pair of operand indices OpIdx0 and OpIdx1.
789 /// Even though the instruction is commutable, the method may still
790 /// fail to commute the operands, null pointer is returned in such cases.
791 MachineInstr *SIInstrInfo::commuteInstructionImpl(MachineInstr *MI,
794 unsigned OpIdx1) const {
795 int CommutedOpcode = commuteOpcode(*MI);
796 if (CommutedOpcode == -1)
799 int Src0Idx = AMDGPU::getNamedOperandIdx(MI->getOpcode(),
800 AMDGPU::OpName::src0);
801 MachineOperand &Src0 = MI->getOperand(Src0Idx);
805 int Src1Idx = AMDGPU::getNamedOperandIdx(MI->getOpcode(),
806 AMDGPU::OpName::src1);
808 if ((OpIdx0 != static_cast<unsigned>(Src0Idx) ||
809 OpIdx1 != static_cast<unsigned>(Src1Idx)) &&
810 (OpIdx0 != static_cast<unsigned>(Src1Idx) ||
811 OpIdx1 != static_cast<unsigned>(Src0Idx)))
814 MachineOperand &Src1 = MI->getOperand(Src1Idx);
816 // Make sure it's legal to commute operands for VOP2.
818 (!isOperandLegal(MI, Src0Idx, &Src1) ||
819 !isOperandLegal(MI, Src1Idx, &Src0))) {
824 // Allow commuting instructions with Imm operands.
825 if (NewMI || !Src1.isImm() ||
826 (!isVOP2(*MI) && !isVOP3(*MI))) {
830 // Be sure to copy the source modifiers to the right place.
831 if (MachineOperand *Src0Mods
832 = getNamedOperand(*MI, AMDGPU::OpName::src0_modifiers)) {
833 MachineOperand *Src1Mods
834 = getNamedOperand(*MI, AMDGPU::OpName::src1_modifiers);
836 int Src0ModsVal = Src0Mods->getImm();
837 if (!Src1Mods && Src0ModsVal != 0)
840 // XXX - This assert might be a lie. It might be useful to have a neg
841 // modifier with 0.0.
842 int Src1ModsVal = Src1Mods->getImm();
843 assert((Src1ModsVal == 0) && "Not expecting modifiers with immediates");
845 Src1Mods->setImm(Src0ModsVal);
846 Src0Mods->setImm(Src1ModsVal);
849 unsigned Reg = Src0.getReg();
850 unsigned SubReg = Src0.getSubReg();
852 Src0.ChangeToImmediate(Src1.getImm());
854 llvm_unreachable("Should only have immediates");
856 Src1.ChangeToRegister(Reg, false);
857 Src1.setSubReg(SubReg);
859 MI = TargetInstrInfo::commuteInstructionImpl(MI, NewMI, OpIdx0, OpIdx1);
863 MI->setDesc(get(CommutedOpcode));
868 // This needs to be implemented because the source modifiers may be inserted
869 // between the true commutable operands, and the base
870 // TargetInstrInfo::commuteInstruction uses it.
871 bool SIInstrInfo::findCommutedOpIndices(MachineInstr *MI,
873 unsigned &SrcOpIdx1) const {
874 const MCInstrDesc &MCID = MI->getDesc();
875 if (!MCID.isCommutable())
878 unsigned Opc = MI->getOpcode();
879 int Src0Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src0);
883 // FIXME: Workaround TargetInstrInfo::commuteInstruction asserting on
884 // immediate. Also, immediate src0 operand is not handled in
885 // SIInstrInfo::commuteInstruction();
886 if (!MI->getOperand(Src0Idx).isReg())
889 int Src1Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src1);
893 MachineOperand &Src1 = MI->getOperand(Src1Idx);
895 // SIInstrInfo::commuteInstruction() does support commuting the immediate
896 // operand src1 in 2 and 3 operand instructions.
897 if (!isVOP2(MI->getOpcode()) && !isVOP3(MI->getOpcode()))
899 } else if (Src1.isReg()) {
900 // If any source modifiers are set, the generic instruction commuting won't
901 // understand how to copy the source modifiers.
902 if (hasModifiersSet(*MI, AMDGPU::OpName::src0_modifiers) ||
903 hasModifiersSet(*MI, AMDGPU::OpName::src1_modifiers))
908 return fixCommutedOpIndices(SrcOpIdx0, SrcOpIdx1, Src0Idx, Src1Idx);
911 MachineInstr *SIInstrInfo::buildMovInstr(MachineBasicBlock *MBB,
912 MachineBasicBlock::iterator I,
914 unsigned SrcReg) const {
915 return BuildMI(*MBB, I, MBB->findDebugLoc(I), get(AMDGPU::V_MOV_B32_e32),
916 DstReg) .addReg(SrcReg);
919 bool SIInstrInfo::isMov(unsigned Opcode) const {
921 default: return false;
922 case AMDGPU::S_MOV_B32:
923 case AMDGPU::S_MOV_B64:
924 case AMDGPU::V_MOV_B32_e32:
925 case AMDGPU::V_MOV_B32_e64:
930 static void removeModOperands(MachineInstr &MI) {
931 unsigned Opc = MI.getOpcode();
932 int Src0ModIdx = AMDGPU::getNamedOperandIdx(Opc,
933 AMDGPU::OpName::src0_modifiers);
934 int Src1ModIdx = AMDGPU::getNamedOperandIdx(Opc,
935 AMDGPU::OpName::src1_modifiers);
936 int Src2ModIdx = AMDGPU::getNamedOperandIdx(Opc,
937 AMDGPU::OpName::src2_modifiers);
939 MI.RemoveOperand(Src2ModIdx);
940 MI.RemoveOperand(Src1ModIdx);
941 MI.RemoveOperand(Src0ModIdx);
944 bool SIInstrInfo::FoldImmediate(MachineInstr *UseMI, MachineInstr *DefMI,
945 unsigned Reg, MachineRegisterInfo *MRI) const {
946 if (!MRI->hasOneNonDBGUse(Reg))
949 unsigned Opc = UseMI->getOpcode();
950 if (Opc == AMDGPU::V_MAD_F32 || Opc == AMDGPU::V_MAC_F32_e64) {
951 // Don't fold if we are using source modifiers. The new VOP2 instructions
953 if (hasModifiersSet(*UseMI, AMDGPU::OpName::src0_modifiers) ||
954 hasModifiersSet(*UseMI, AMDGPU::OpName::src1_modifiers) ||
955 hasModifiersSet(*UseMI, AMDGPU::OpName::src2_modifiers)) {
959 MachineOperand *Src0 = getNamedOperand(*UseMI, AMDGPU::OpName::src0);
960 MachineOperand *Src1 = getNamedOperand(*UseMI, AMDGPU::OpName::src1);
961 MachineOperand *Src2 = getNamedOperand(*UseMI, AMDGPU::OpName::src2);
963 // Multiplied part is the constant: Use v_madmk_f32
964 // We should only expect these to be on src0 due to canonicalizations.
965 if (Src0->isReg() && Src0->getReg() == Reg) {
966 if (!Src1->isReg() ||
967 (Src1->isReg() && RI.isSGPRClass(MRI->getRegClass(Src1->getReg()))))
970 if (!Src2->isReg() ||
971 (Src2->isReg() && RI.isSGPRClass(MRI->getRegClass(Src2->getReg()))))
974 // We need to do some weird looking operand shuffling since the madmk
975 // operands are out of the normal expected order with the multiplied
976 // constant as the last operand.
978 // v_mad_f32 src0, src1, src2 -> v_madmk_f32 src0 * src2K + src1
983 const int64_t Imm = DefMI->getOperand(1).getImm();
985 // FIXME: This would be a lot easier if we could return a new instruction
986 // instead of having to modify in place.
988 // Remove these first since they are at the end.
989 UseMI->RemoveOperand(AMDGPU::getNamedOperandIdx(Opc,
990 AMDGPU::OpName::omod));
991 UseMI->RemoveOperand(AMDGPU::getNamedOperandIdx(Opc,
992 AMDGPU::OpName::clamp));
994 unsigned Src1Reg = Src1->getReg();
995 unsigned Src1SubReg = Src1->getSubReg();
996 unsigned Src2Reg = Src2->getReg();
997 unsigned Src2SubReg = Src2->getSubReg();
998 Src0->setReg(Src1Reg);
999 Src0->setSubReg(Src1SubReg);
1000 Src0->setIsKill(Src1->isKill());
1002 Src1->setReg(Src2Reg);
1003 Src1->setSubReg(Src2SubReg);
1004 Src1->setIsKill(Src2->isKill());
1006 if (Opc == AMDGPU::V_MAC_F32_e64) {
1007 UseMI->untieRegOperand(
1008 AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src2));
1011 Src2->ChangeToImmediate(Imm);
1013 removeModOperands(*UseMI);
1014 UseMI->setDesc(get(AMDGPU::V_MADMK_F32));
1016 bool DeleteDef = MRI->hasOneNonDBGUse(Reg);
1018 DefMI->eraseFromParent();
1023 // Added part is the constant: Use v_madak_f32
1024 if (Src2->isReg() && Src2->getReg() == Reg) {
1025 // Not allowed to use constant bus for another operand.
1026 // We can however allow an inline immediate as src0.
1027 if (!Src0->isImm() &&
1028 (Src0->isReg() && RI.isSGPRClass(MRI->getRegClass(Src0->getReg()))))
1031 if (!Src1->isReg() ||
1032 (Src1->isReg() && RI.isSGPRClass(MRI->getRegClass(Src1->getReg()))))
1035 const int64_t Imm = DefMI->getOperand(1).getImm();
1037 // FIXME: This would be a lot easier if we could return a new instruction
1038 // instead of having to modify in place.
1040 // Remove these first since they are at the end.
1041 UseMI->RemoveOperand(AMDGPU::getNamedOperandIdx(Opc,
1042 AMDGPU::OpName::omod));
1043 UseMI->RemoveOperand(AMDGPU::getNamedOperandIdx(Opc,
1044 AMDGPU::OpName::clamp));
1046 if (Opc == AMDGPU::V_MAC_F32_e64) {
1047 UseMI->untieRegOperand(
1048 AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src2));
1051 // ChangingToImmediate adds Src2 back to the instruction.
1052 Src2->ChangeToImmediate(Imm);
1054 // These come before src2.
1055 removeModOperands(*UseMI);
1056 UseMI->setDesc(get(AMDGPU::V_MADAK_F32));
1058 bool DeleteDef = MRI->hasOneNonDBGUse(Reg);
1060 DefMI->eraseFromParent();
1069 static bool offsetsDoNotOverlap(int WidthA, int OffsetA,
1070 int WidthB, int OffsetB) {
1071 int LowOffset = OffsetA < OffsetB ? OffsetA : OffsetB;
1072 int HighOffset = OffsetA < OffsetB ? OffsetB : OffsetA;
1073 int LowWidth = (LowOffset == OffsetA) ? WidthA : WidthB;
1074 return LowOffset + LowWidth <= HighOffset;
1077 bool SIInstrInfo::checkInstOffsetsDoNotOverlap(MachineInstr *MIa,
1078 MachineInstr *MIb) const {
1079 unsigned BaseReg0, Offset0;
1080 unsigned BaseReg1, Offset1;
1082 if (getMemOpBaseRegImmOfs(MIa, BaseReg0, Offset0, &RI) &&
1083 getMemOpBaseRegImmOfs(MIb, BaseReg1, Offset1, &RI)) {
1084 assert(MIa->hasOneMemOperand() && MIb->hasOneMemOperand() &&
1085 "read2 / write2 not expected here yet");
1086 unsigned Width0 = (*MIa->memoperands_begin())->getSize();
1087 unsigned Width1 = (*MIb->memoperands_begin())->getSize();
1088 if (BaseReg0 == BaseReg1 &&
1089 offsetsDoNotOverlap(Width0, Offset0, Width1, Offset1)) {
1097 bool SIInstrInfo::areMemAccessesTriviallyDisjoint(MachineInstr *MIa,
1099 AliasAnalysis *AA) const {
1100 assert(MIa && (MIa->mayLoad() || MIa->mayStore()) &&
1101 "MIa must load from or modify a memory location");
1102 assert(MIb && (MIb->mayLoad() || MIb->mayStore()) &&
1103 "MIb must load from or modify a memory location");
1105 if (MIa->hasUnmodeledSideEffects() || MIb->hasUnmodeledSideEffects())
1108 // XXX - Can we relax this between address spaces?
1109 if (MIa->hasOrderedMemoryRef() || MIb->hasOrderedMemoryRef())
1112 // TODO: Should we check the address space from the MachineMemOperand? That
1113 // would allow us to distinguish objects we know don't alias based on the
1114 // underlying address space, even if it was lowered to a different one,
1115 // e.g. private accesses lowered to use MUBUF instructions on a scratch
1119 return checkInstOffsetsDoNotOverlap(MIa, MIb);
1121 return !isFLAT(*MIb);
1124 if (isMUBUF(*MIa) || isMTBUF(*MIa)) {
1125 if (isMUBUF(*MIb) || isMTBUF(*MIb))
1126 return checkInstOffsetsDoNotOverlap(MIa, MIb);
1128 return !isFLAT(*MIb) && !isSMRD(*MIb);
1133 return checkInstOffsetsDoNotOverlap(MIa, MIb);
1135 return !isFLAT(*MIb) && !isMUBUF(*MIa) && !isMTBUF(*MIa);
1140 return checkInstOffsetsDoNotOverlap(MIa, MIb);
1148 MachineInstr *SIInstrInfo::convertToThreeAddress(MachineFunction::iterator &MBB,
1149 MachineBasicBlock::iterator &MI,
1150 LiveVariables *LV) const {
1152 switch (MI->getOpcode()) {
1153 default: return nullptr;
1154 case AMDGPU::V_MAC_F32_e64: break;
1155 case AMDGPU::V_MAC_F32_e32: {
1156 const MachineOperand *Src0 = getNamedOperand(*MI, AMDGPU::OpName::src0);
1157 if (Src0->isImm() && !isInlineConstant(*Src0, 4))
1163 const MachineOperand *Dst = getNamedOperand(*MI, AMDGPU::OpName::dst);
1164 const MachineOperand *Src0 = getNamedOperand(*MI, AMDGPU::OpName::src0);
1165 const MachineOperand *Src1 = getNamedOperand(*MI, AMDGPU::OpName::src1);
1166 const MachineOperand *Src2 = getNamedOperand(*MI, AMDGPU::OpName::src2);
1168 return BuildMI(*MBB, MI, MI->getDebugLoc(), get(AMDGPU::V_MAD_F32))
1170 .addImm(0) // Src0 mods
1172 .addImm(0) // Src1 mods
1174 .addImm(0) // Src mods
1180 bool SIInstrInfo::isInlineConstant(const APInt &Imm) const {
1181 int64_t SVal = Imm.getSExtValue();
1182 if (SVal >= -16 && SVal <= 64)
1185 if (Imm.getBitWidth() == 64) {
1186 uint64_t Val = Imm.getZExtValue();
1187 return (DoubleToBits(0.0) == Val) ||
1188 (DoubleToBits(1.0) == Val) ||
1189 (DoubleToBits(-1.0) == Val) ||
1190 (DoubleToBits(0.5) == Val) ||
1191 (DoubleToBits(-0.5) == Val) ||
1192 (DoubleToBits(2.0) == Val) ||
1193 (DoubleToBits(-2.0) == Val) ||
1194 (DoubleToBits(4.0) == Val) ||
1195 (DoubleToBits(-4.0) == Val);
1198 // The actual type of the operand does not seem to matter as long
1199 // as the bits match one of the inline immediate values. For example:
1201 // -nan has the hexadecimal encoding of 0xfffffffe which is -2 in decimal,
1202 // so it is a legal inline immediate.
1204 // 1065353216 has the hexadecimal encoding 0x3f800000 which is 1.0f in
1205 // floating-point, so it is a legal inline immediate.
1206 uint32_t Val = Imm.getZExtValue();
1208 return (FloatToBits(0.0f) == Val) ||
1209 (FloatToBits(1.0f) == Val) ||
1210 (FloatToBits(-1.0f) == Val) ||
1211 (FloatToBits(0.5f) == Val) ||
1212 (FloatToBits(-0.5f) == Val) ||
1213 (FloatToBits(2.0f) == Val) ||
1214 (FloatToBits(-2.0f) == Val) ||
1215 (FloatToBits(4.0f) == Val) ||
1216 (FloatToBits(-4.0f) == Val);
1219 bool SIInstrInfo::isInlineConstant(const MachineOperand &MO,
1220 unsigned OpSize) const {
1222 // MachineOperand provides no way to tell the true operand size, since it
1223 // only records a 64-bit value. We need to know the size to determine if a
1224 // 32-bit floating point immediate bit pattern is legal for an integer
1225 // immediate. It would be for any 32-bit integer operand, but would not be
1226 // for a 64-bit one.
1228 unsigned BitSize = 8 * OpSize;
1229 return isInlineConstant(APInt(BitSize, MO.getImm(), true));
1235 bool SIInstrInfo::isLiteralConstant(const MachineOperand &MO,
1236 unsigned OpSize) const {
1237 return MO.isImm() && !isInlineConstant(MO, OpSize);
1240 static bool compareMachineOp(const MachineOperand &Op0,
1241 const MachineOperand &Op1) {
1242 if (Op0.getType() != Op1.getType())
1245 switch (Op0.getType()) {
1246 case MachineOperand::MO_Register:
1247 return Op0.getReg() == Op1.getReg();
1248 case MachineOperand::MO_Immediate:
1249 return Op0.getImm() == Op1.getImm();
1251 llvm_unreachable("Didn't expect to be comparing these operand types");
1255 bool SIInstrInfo::isImmOperandLegal(const MachineInstr *MI, unsigned OpNo,
1256 const MachineOperand &MO) const {
1257 const MCOperandInfo &OpInfo = get(MI->getOpcode()).OpInfo[OpNo];
1259 assert(MO.isImm() || MO.isTargetIndex() || MO.isFI());
1261 if (OpInfo.OperandType == MCOI::OPERAND_IMMEDIATE)
1264 if (OpInfo.RegClass < 0)
1267 unsigned OpSize = RI.getRegClass(OpInfo.RegClass)->getSize();
1268 if (isLiteralConstant(MO, OpSize))
1269 return RI.opCanUseLiteralConstant(OpInfo.OperandType);
1271 return RI.opCanUseInlineConstant(OpInfo.OperandType);
1274 bool SIInstrInfo::hasVALU32BitEncoding(unsigned Opcode) const {
1275 int Op32 = AMDGPU::getVOPe32(Opcode);
1279 return pseudoToMCOpcode(Op32) != -1;
1282 bool SIInstrInfo::hasModifiers(unsigned Opcode) const {
1283 // The src0_modifier operand is present on all instructions
1284 // that have modifiers.
1286 return AMDGPU::getNamedOperandIdx(Opcode,
1287 AMDGPU::OpName::src0_modifiers) != -1;
1290 bool SIInstrInfo::hasModifiersSet(const MachineInstr &MI,
1291 unsigned OpName) const {
1292 const MachineOperand *Mods = getNamedOperand(MI, OpName);
1293 return Mods && Mods->getImm();
1296 bool SIInstrInfo::usesConstantBus(const MachineRegisterInfo &MRI,
1297 const MachineOperand &MO,
1298 unsigned OpSize) const {
1299 // Literal constants use the constant bus.
1300 if (isLiteralConstant(MO, OpSize))
1303 if (!MO.isReg() || !MO.isUse())
1306 if (TargetRegisterInfo::isVirtualRegister(MO.getReg()))
1307 return RI.isSGPRClass(MRI.getRegClass(MO.getReg()));
1309 // FLAT_SCR is just an SGPR pair.
1310 if (!MO.isImplicit() && (MO.getReg() == AMDGPU::FLAT_SCR))
1313 // EXEC register uses the constant bus.
1314 if (!MO.isImplicit() && MO.getReg() == AMDGPU::EXEC)
1317 // SGPRs use the constant bus
1318 if (MO.getReg() == AMDGPU::M0 || MO.getReg() == AMDGPU::VCC ||
1319 (!MO.isImplicit() &&
1320 (AMDGPU::SGPR_32RegClass.contains(MO.getReg()) ||
1321 AMDGPU::SGPR_64RegClass.contains(MO.getReg())))) {
1328 static unsigned findImplicitSGPRRead(const MachineInstr &MI) {
1329 for (const MachineOperand &MO : MI.implicit_operands()) {
1330 // We only care about reads.
1334 switch (MO.getReg()) {
1337 case AMDGPU::FLAT_SCR:
1345 return AMDGPU::NoRegister;
1348 bool SIInstrInfo::verifyInstruction(const MachineInstr *MI,
1349 StringRef &ErrInfo) const {
1350 uint16_t Opcode = MI->getOpcode();
1351 const MachineRegisterInfo &MRI = MI->getParent()->getParent()->getRegInfo();
1352 int Src0Idx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src0);
1353 int Src1Idx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src1);
1354 int Src2Idx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src2);
1356 // Make sure the number of operands is correct.
1357 const MCInstrDesc &Desc = get(Opcode);
1358 if (!Desc.isVariadic() &&
1359 Desc.getNumOperands() != MI->getNumExplicitOperands()) {
1360 ErrInfo = "Instruction has wrong number of operands.";
1364 // Make sure the register classes are correct
1365 for (int i = 0, e = Desc.getNumOperands(); i != e; ++i) {
1366 if (MI->getOperand(i).isFPImm()) {
1367 ErrInfo = "FPImm Machine Operands are not supported. ISel should bitcast "
1368 "all fp values to integers.";
1372 int RegClass = Desc.OpInfo[i].RegClass;
1374 switch (Desc.OpInfo[i].OperandType) {
1375 case MCOI::OPERAND_REGISTER:
1376 if (MI->getOperand(i).isImm()) {
1377 ErrInfo = "Illegal immediate value for operand.";
1381 case AMDGPU::OPERAND_REG_IMM32:
1383 case AMDGPU::OPERAND_REG_INLINE_C:
1384 if (isLiteralConstant(MI->getOperand(i),
1385 RI.getRegClass(RegClass)->getSize())) {
1386 ErrInfo = "Illegal immediate value for operand.";
1390 case MCOI::OPERAND_IMMEDIATE:
1391 // Check if this operand is an immediate.
1392 // FrameIndex operands will be replaced by immediates, so they are
1394 if (!MI->getOperand(i).isImm() && !MI->getOperand(i).isFI()) {
1395 ErrInfo = "Expected immediate, but got non-immediate";
1403 if (!MI->getOperand(i).isReg())
1406 if (RegClass != -1) {
1407 unsigned Reg = MI->getOperand(i).getReg();
1408 if (TargetRegisterInfo::isVirtualRegister(Reg))
1411 const TargetRegisterClass *RC = RI.getRegClass(RegClass);
1412 if (!RC->contains(Reg)) {
1413 ErrInfo = "Operand has incorrect register class.";
1421 if (isVOP1(*MI) || isVOP2(*MI) || isVOP3(*MI) || isVOPC(*MI)) {
1422 // Only look at the true operands. Only a real operand can use the constant
1423 // bus, and we don't want to check pseudo-operands like the source modifier
1425 const int OpIndices[] = { Src0Idx, Src1Idx, Src2Idx };
1427 unsigned ConstantBusCount = 0;
1428 unsigned SGPRUsed = findImplicitSGPRRead(*MI);
1429 if (SGPRUsed != AMDGPU::NoRegister)
1432 for (int OpIdx : OpIndices) {
1435 const MachineOperand &MO = MI->getOperand(OpIdx);
1436 if (usesConstantBus(MRI, MO, getOpSize(Opcode, OpIdx))) {
1438 if (MO.getReg() != SGPRUsed)
1440 SGPRUsed = MO.getReg();
1446 if (ConstantBusCount > 1) {
1447 ErrInfo = "VOP* instruction uses the constant bus more than once";
1452 // Verify misc. restrictions on specific instructions.
1453 if (Desc.getOpcode() == AMDGPU::V_DIV_SCALE_F32 ||
1454 Desc.getOpcode() == AMDGPU::V_DIV_SCALE_F64) {
1455 const MachineOperand &Src0 = MI->getOperand(Src0Idx);
1456 const MachineOperand &Src1 = MI->getOperand(Src1Idx);
1457 const MachineOperand &Src2 = MI->getOperand(Src2Idx);
1458 if (Src0.isReg() && Src1.isReg() && Src2.isReg()) {
1459 if (!compareMachineOp(Src0, Src1) &&
1460 !compareMachineOp(Src0, Src2)) {
1461 ErrInfo = "v_div_scale_{f32|f64} require src0 = src1 or src2";
1467 // Make sure we aren't losing exec uses in the td files. This mostly requires
1468 // being careful when using let Uses to try to add other use registers.
1469 if (!isGenericOpcode(Opcode) && !isSALU(Opcode) && !isSMRD(Opcode)) {
1470 const MachineOperand *Exec = MI->findRegisterUseOperand(AMDGPU::EXEC);
1471 if (!Exec || !Exec->isImplicit()) {
1472 ErrInfo = "VALU instruction does not implicitly read exec mask";
1480 unsigned SIInstrInfo::getVALUOp(const MachineInstr &MI) {
1481 switch (MI.getOpcode()) {
1482 default: return AMDGPU::INSTRUCTION_LIST_END;
1483 case AMDGPU::REG_SEQUENCE: return AMDGPU::REG_SEQUENCE;
1484 case AMDGPU::COPY: return AMDGPU::COPY;
1485 case AMDGPU::PHI: return AMDGPU::PHI;
1486 case AMDGPU::INSERT_SUBREG: return AMDGPU::INSERT_SUBREG;
1487 case AMDGPU::S_MOV_B32:
1488 return MI.getOperand(1).isReg() ?
1489 AMDGPU::COPY : AMDGPU::V_MOV_B32_e32;
1490 case AMDGPU::S_ADD_I32:
1491 case AMDGPU::S_ADD_U32: return AMDGPU::V_ADD_I32_e32;
1492 case AMDGPU::S_ADDC_U32: return AMDGPU::V_ADDC_U32_e32;
1493 case AMDGPU::S_SUB_I32:
1494 case AMDGPU::S_SUB_U32: return AMDGPU::V_SUB_I32_e32;
1495 case AMDGPU::S_SUBB_U32: return AMDGPU::V_SUBB_U32_e32;
1496 case AMDGPU::S_MUL_I32: return AMDGPU::V_MUL_LO_I32;
1497 case AMDGPU::S_AND_B32: return AMDGPU::V_AND_B32_e32;
1498 case AMDGPU::S_OR_B32: return AMDGPU::V_OR_B32_e32;
1499 case AMDGPU::S_XOR_B32: return AMDGPU::V_XOR_B32_e32;
1500 case AMDGPU::S_MIN_I32: return AMDGPU::V_MIN_I32_e32;
1501 case AMDGPU::S_MIN_U32: return AMDGPU::V_MIN_U32_e32;
1502 case AMDGPU::S_MAX_I32: return AMDGPU::V_MAX_I32_e32;
1503 case AMDGPU::S_MAX_U32: return AMDGPU::V_MAX_U32_e32;
1504 case AMDGPU::S_ASHR_I32: return AMDGPU::V_ASHR_I32_e32;
1505 case AMDGPU::S_ASHR_I64: return AMDGPU::V_ASHR_I64;
1506 case AMDGPU::S_LSHL_B32: return AMDGPU::V_LSHL_B32_e32;
1507 case AMDGPU::S_LSHL_B64: return AMDGPU::V_LSHL_B64;
1508 case AMDGPU::S_LSHR_B32: return AMDGPU::V_LSHR_B32_e32;
1509 case AMDGPU::S_LSHR_B64: return AMDGPU::V_LSHR_B64;
1510 case AMDGPU::S_SEXT_I32_I8: return AMDGPU::V_BFE_I32;
1511 case AMDGPU::S_SEXT_I32_I16: return AMDGPU::V_BFE_I32;
1512 case AMDGPU::S_BFE_U32: return AMDGPU::V_BFE_U32;
1513 case AMDGPU::S_BFE_I32: return AMDGPU::V_BFE_I32;
1514 case AMDGPU::S_BFM_B32: return AMDGPU::V_BFM_B32_e64;
1515 case AMDGPU::S_BREV_B32: return AMDGPU::V_BFREV_B32_e32;
1516 case AMDGPU::S_NOT_B32: return AMDGPU::V_NOT_B32_e32;
1517 case AMDGPU::S_NOT_B64: return AMDGPU::V_NOT_B32_e32;
1518 case AMDGPU::S_CMP_EQ_I32: return AMDGPU::V_CMP_EQ_I32_e32;
1519 case AMDGPU::S_CMP_LG_I32: return AMDGPU::V_CMP_NE_I32_e32;
1520 case AMDGPU::S_CMP_GT_I32: return AMDGPU::V_CMP_GT_I32_e32;
1521 case AMDGPU::S_CMP_GE_I32: return AMDGPU::V_CMP_GE_I32_e32;
1522 case AMDGPU::S_CMP_LT_I32: return AMDGPU::V_CMP_LT_I32_e32;
1523 case AMDGPU::S_CMP_LE_I32: return AMDGPU::V_CMP_LE_I32_e32;
1524 case AMDGPU::S_LOAD_DWORD_IMM:
1525 case AMDGPU::S_LOAD_DWORD_SGPR:
1526 case AMDGPU::S_LOAD_DWORD_IMM_ci:
1527 return AMDGPU::BUFFER_LOAD_DWORD_ADDR64;
1528 case AMDGPU::S_LOAD_DWORDX2_IMM:
1529 case AMDGPU::S_LOAD_DWORDX2_SGPR:
1530 case AMDGPU::S_LOAD_DWORDX2_IMM_ci:
1531 return AMDGPU::BUFFER_LOAD_DWORDX2_ADDR64;
1532 case AMDGPU::S_LOAD_DWORDX4_IMM:
1533 case AMDGPU::S_LOAD_DWORDX4_SGPR:
1534 case AMDGPU::S_LOAD_DWORDX4_IMM_ci:
1535 return AMDGPU::BUFFER_LOAD_DWORDX4_ADDR64;
1536 case AMDGPU::S_BCNT1_I32_B32: return AMDGPU::V_BCNT_U32_B32_e64;
1537 case AMDGPU::S_FF1_I32_B32: return AMDGPU::V_FFBL_B32_e32;
1538 case AMDGPU::S_FLBIT_I32_B32: return AMDGPU::V_FFBH_U32_e32;
1539 case AMDGPU::S_FLBIT_I32: return AMDGPU::V_FFBH_I32_e64;
1543 bool SIInstrInfo::isSALUOpSupportedOnVALU(const MachineInstr &MI) const {
1544 return getVALUOp(MI) != AMDGPU::INSTRUCTION_LIST_END;
1547 const TargetRegisterClass *SIInstrInfo::getOpRegClass(const MachineInstr &MI,
1548 unsigned OpNo) const {
1549 const MachineRegisterInfo &MRI = MI.getParent()->getParent()->getRegInfo();
1550 const MCInstrDesc &Desc = get(MI.getOpcode());
1551 if (MI.isVariadic() || OpNo >= Desc.getNumOperands() ||
1552 Desc.OpInfo[OpNo].RegClass == -1) {
1553 unsigned Reg = MI.getOperand(OpNo).getReg();
1555 if (TargetRegisterInfo::isVirtualRegister(Reg))
1556 return MRI.getRegClass(Reg);
1557 return RI.getPhysRegClass(Reg);
1560 unsigned RCID = Desc.OpInfo[OpNo].RegClass;
1561 return RI.getRegClass(RCID);
1564 bool SIInstrInfo::canReadVGPR(const MachineInstr &MI, unsigned OpNo) const {
1565 switch (MI.getOpcode()) {
1567 case AMDGPU::REG_SEQUENCE:
1569 case AMDGPU::INSERT_SUBREG:
1570 return RI.hasVGPRs(getOpRegClass(MI, 0));
1572 return RI.hasVGPRs(getOpRegClass(MI, OpNo));
1576 void SIInstrInfo::legalizeOpWithMove(MachineInstr *MI, unsigned OpIdx) const {
1577 MachineBasicBlock::iterator I = MI;
1578 MachineBasicBlock *MBB = MI->getParent();
1579 MachineOperand &MO = MI->getOperand(OpIdx);
1580 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
1581 unsigned RCID = get(MI->getOpcode()).OpInfo[OpIdx].RegClass;
1582 const TargetRegisterClass *RC = RI.getRegClass(RCID);
1583 unsigned Opcode = AMDGPU::V_MOV_B32_e32;
1585 Opcode = AMDGPU::COPY;
1586 else if (RI.isSGPRClass(RC))
1587 Opcode = AMDGPU::S_MOV_B32;
1590 const TargetRegisterClass *VRC = RI.getEquivalentVGPRClass(RC);
1591 if (RI.getCommonSubClass(&AMDGPU::VReg_64RegClass, VRC))
1592 VRC = &AMDGPU::VReg_64RegClass;
1594 VRC = &AMDGPU::VGPR_32RegClass;
1596 unsigned Reg = MRI.createVirtualRegister(VRC);
1597 DebugLoc DL = MBB->findDebugLoc(I);
1598 BuildMI(*MI->getParent(), I, DL, get(Opcode), Reg)
1600 MO.ChangeToRegister(Reg, false);
1603 unsigned SIInstrInfo::buildExtractSubReg(MachineBasicBlock::iterator MI,
1604 MachineRegisterInfo &MRI,
1605 MachineOperand &SuperReg,
1606 const TargetRegisterClass *SuperRC,
1608 const TargetRegisterClass *SubRC)
1610 MachineBasicBlock *MBB = MI->getParent();
1611 DebugLoc DL = MI->getDebugLoc();
1612 unsigned SubReg = MRI.createVirtualRegister(SubRC);
1614 if (SuperReg.getSubReg() == AMDGPU::NoSubRegister) {
1615 BuildMI(*MBB, MI, DL, get(TargetOpcode::COPY), SubReg)
1616 .addReg(SuperReg.getReg(), 0, SubIdx);
1620 // Just in case the super register is itself a sub-register, copy it to a new
1621 // value so we don't need to worry about merging its subreg index with the
1622 // SubIdx passed to this function. The register coalescer should be able to
1623 // eliminate this extra copy.
1624 unsigned NewSuperReg = MRI.createVirtualRegister(SuperRC);
1626 BuildMI(*MBB, MI, DL, get(TargetOpcode::COPY), NewSuperReg)
1627 .addReg(SuperReg.getReg(), 0, SuperReg.getSubReg());
1629 BuildMI(*MBB, MI, DL, get(TargetOpcode::COPY), SubReg)
1630 .addReg(NewSuperReg, 0, SubIdx);
1635 MachineOperand SIInstrInfo::buildExtractSubRegOrImm(
1636 MachineBasicBlock::iterator MII,
1637 MachineRegisterInfo &MRI,
1639 const TargetRegisterClass *SuperRC,
1641 const TargetRegisterClass *SubRC) const {
1643 // XXX - Is there a better way to do this?
1644 if (SubIdx == AMDGPU::sub0)
1645 return MachineOperand::CreateImm(Op.getImm() & 0xFFFFFFFF);
1646 if (SubIdx == AMDGPU::sub1)
1647 return MachineOperand::CreateImm(Op.getImm() >> 32);
1649 llvm_unreachable("Unhandled register index for immediate");
1652 unsigned SubReg = buildExtractSubReg(MII, MRI, Op, SuperRC,
1654 return MachineOperand::CreateReg(SubReg, false);
1657 // Change the order of operands from (0, 1, 2) to (0, 2, 1)
1658 void SIInstrInfo::swapOperands(MachineBasicBlock::iterator Inst) const {
1659 assert(Inst->getNumExplicitOperands() == 3);
1660 MachineOperand Op1 = Inst->getOperand(1);
1661 Inst->RemoveOperand(1);
1662 Inst->addOperand(Op1);
1665 bool SIInstrInfo::isOperandLegal(const MachineInstr *MI, unsigned OpIdx,
1666 const MachineOperand *MO) const {
1667 const MachineRegisterInfo &MRI = MI->getParent()->getParent()->getRegInfo();
1668 const MCInstrDesc &InstDesc = get(MI->getOpcode());
1669 const MCOperandInfo &OpInfo = InstDesc.OpInfo[OpIdx];
1670 const TargetRegisterClass *DefinedRC =
1671 OpInfo.RegClass != -1 ? RI.getRegClass(OpInfo.RegClass) : nullptr;
1673 MO = &MI->getOperand(OpIdx);
1676 usesConstantBus(MRI, *MO, DefinedRC->getSize())) {
1678 MO->isReg() ? MO->getReg() : (unsigned)AMDGPU::NoRegister;
1679 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1682 const MachineOperand &Op = MI->getOperand(i);
1683 if (Op.isReg() && Op.getReg() != SGPRUsed &&
1684 usesConstantBus(MRI, Op, getOpSize(*MI, i))) {
1692 const TargetRegisterClass *RC =
1693 TargetRegisterInfo::isVirtualRegister(MO->getReg()) ?
1694 MRI.getRegClass(MO->getReg()) :
1695 RI.getPhysRegClass(MO->getReg());
1697 // In order to be legal, the common sub-class must be equal to the
1698 // class of the current operand. For example:
1700 // v_mov_b32 s0 ; Operand defined as vsrc_32
1701 // ; RI.getCommonSubClass(s0,vsrc_32) = sgpr ; LEGAL
1703 // s_sendmsg 0, s0 ; Operand defined as m0reg
1704 // ; RI.getCommonSubClass(s0,m0reg) = m0reg ; NOT LEGAL
1706 return RI.getCommonSubClass(RC, RI.getRegClass(OpInfo.RegClass)) == RC;
1710 // Handle non-register types that are treated like immediates.
1711 assert(MO->isImm() || MO->isTargetIndex() || MO->isFI());
1714 // This operand expects an immediate.
1718 return isImmOperandLegal(MI, OpIdx, *MO);
1721 // Legalize VOP3 operands. Because all operand types are supported for any
1722 // operand, and since literal constants are not allowed and should never be
1723 // seen, we only need to worry about inserting copies if we use multiple SGPR
1725 void SIInstrInfo::legalizeOperandsVOP3(
1726 MachineRegisterInfo &MRI,
1727 MachineInstr *MI) const {
1728 unsigned Opc = MI->getOpcode();
1731 AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src0),
1732 AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src1),
1733 AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src2)
1736 // Find the one SGPR operand we are allowed to use.
1737 unsigned SGPRReg = findUsedSGPR(MI, VOP3Idx);
1739 for (unsigned i = 0; i < 3; ++i) {
1740 int Idx = VOP3Idx[i];
1743 MachineOperand &MO = MI->getOperand(Idx);
1745 // We should never see a VOP3 instruction with an illegal immediate operand.
1749 if (!RI.isSGPRClass(MRI.getRegClass(MO.getReg())))
1750 continue; // VGPRs are legal
1752 if (SGPRReg == AMDGPU::NoRegister || SGPRReg == MO.getReg()) {
1753 SGPRReg = MO.getReg();
1754 // We can use one SGPR in each VOP3 instruction.
1758 // If we make it this far, then the operand is not legal and we must
1760 legalizeOpWithMove(MI, Idx);
1764 void SIInstrInfo::legalizeOperands(MachineInstr *MI) const {
1765 MachineRegisterInfo &MRI = MI->getParent()->getParent()->getRegInfo();
1766 unsigned Opc = MI->getOpcode();
1770 int Src0Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src0);
1771 int Src1Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src1);
1774 if (!isOperandLegal(MI, Src0Idx))
1775 legalizeOpWithMove(MI, Src0Idx);
1778 if (isOperandLegal(MI, Src1Idx))
1781 // Usually src0 of VOP2 instructions allow more types of inputs
1782 // than src1, so try to commute the instruction to decrease our
1783 // chances of having to insert a MOV instruction to legalize src1.
1784 if (MI->isCommutable()) {
1785 if (commuteInstruction(MI))
1786 // If we are successful in commuting, then we know MI is legal, so
1791 legalizeOpWithMove(MI, Src1Idx);
1797 legalizeOperandsVOP3(MRI, MI);
1801 // Legalize REG_SEQUENCE and PHI
1802 // The register class of the operands much be the same type as the register
1803 // class of the output.
1804 if (MI->getOpcode() == AMDGPU::PHI) {
1805 const TargetRegisterClass *RC = nullptr, *SRC = nullptr, *VRC = nullptr;
1806 for (unsigned i = 1, e = MI->getNumOperands(); i != e; i+=2) {
1807 if (!MI->getOperand(i).isReg() ||
1808 !TargetRegisterInfo::isVirtualRegister(MI->getOperand(i).getReg()))
1810 const TargetRegisterClass *OpRC =
1811 MRI.getRegClass(MI->getOperand(i).getReg());
1812 if (RI.hasVGPRs(OpRC)) {
1819 // If any of the operands are VGPR registers, then they all most be
1820 // otherwise we will create illegal VGPR->SGPR copies when legalizing
1822 if (VRC || !RI.isSGPRClass(getOpRegClass(*MI, 0))) {
1825 VRC = RI.getEquivalentVGPRClass(SRC);
1832 // Update all the operands so they have the same type.
1833 for (unsigned I = 1, E = MI->getNumOperands(); I != E; I += 2) {
1834 MachineOperand &Op = MI->getOperand(I);
1835 if (!Op.isReg() || !TargetRegisterInfo::isVirtualRegister(Op.getReg()))
1837 unsigned DstReg = MRI.createVirtualRegister(RC);
1839 // MI is a PHI instruction.
1840 MachineBasicBlock *InsertBB = MI->getOperand(I + 1).getMBB();
1841 MachineBasicBlock::iterator Insert = InsertBB->getFirstTerminator();
1843 BuildMI(*InsertBB, Insert, MI->getDebugLoc(), get(AMDGPU::COPY), DstReg)
1849 // REG_SEQUENCE doesn't really require operand legalization, but if one has a
1850 // VGPR dest type and SGPR sources, insert copies so all operands are
1851 // VGPRs. This seems to help operand folding / the register coalescer.
1852 if (MI->getOpcode() == AMDGPU::REG_SEQUENCE) {
1853 MachineBasicBlock *MBB = MI->getParent();
1854 const TargetRegisterClass *DstRC = getOpRegClass(*MI, 0);
1855 if (RI.hasVGPRs(DstRC)) {
1856 // Update all the operands so they are VGPR register classes. These may
1857 // not be the same register class because REG_SEQUENCE supports mixing
1858 // subregister index types e.g. sub0_sub1 + sub2 + sub3
1859 for (unsigned I = 1, E = MI->getNumOperands(); I != E; I += 2) {
1860 MachineOperand &Op = MI->getOperand(I);
1861 if (!Op.isReg() || !TargetRegisterInfo::isVirtualRegister(Op.getReg()))
1864 const TargetRegisterClass *OpRC = MRI.getRegClass(Op.getReg());
1865 const TargetRegisterClass *VRC = RI.getEquivalentVGPRClass(OpRC);
1869 unsigned DstReg = MRI.createVirtualRegister(VRC);
1871 BuildMI(*MBB, MI, MI->getDebugLoc(), get(AMDGPU::COPY), DstReg)
1882 // Legalize INSERT_SUBREG
1883 // src0 must have the same register class as dst
1884 if (MI->getOpcode() == AMDGPU::INSERT_SUBREG) {
1885 unsigned Dst = MI->getOperand(0).getReg();
1886 unsigned Src0 = MI->getOperand(1).getReg();
1887 const TargetRegisterClass *DstRC = MRI.getRegClass(Dst);
1888 const TargetRegisterClass *Src0RC = MRI.getRegClass(Src0);
1889 if (DstRC != Src0RC) {
1890 MachineBasicBlock &MBB = *MI->getParent();
1891 unsigned NewSrc0 = MRI.createVirtualRegister(DstRC);
1892 BuildMI(MBB, MI, MI->getDebugLoc(), get(AMDGPU::COPY), NewSrc0)
1894 MI->getOperand(1).setReg(NewSrc0);
1899 // Legalize MUBUF* instructions
1900 // FIXME: If we start using the non-addr64 instructions for compute, we
1901 // may need to legalize them here.
1903 AMDGPU::getNamedOperandIdx(MI->getOpcode(), AMDGPU::OpName::srsrc);
1904 if (SRsrcIdx != -1) {
1905 // We have an MUBUF instruction
1906 MachineOperand *SRsrc = &MI->getOperand(SRsrcIdx);
1907 unsigned SRsrcRC = get(MI->getOpcode()).OpInfo[SRsrcIdx].RegClass;
1908 if (RI.getCommonSubClass(MRI.getRegClass(SRsrc->getReg()),
1909 RI.getRegClass(SRsrcRC))) {
1910 // The operands are legal.
1911 // FIXME: We may need to legalize operands besided srsrc.
1915 MachineBasicBlock &MBB = *MI->getParent();
1917 // Extract the ptr from the resource descriptor.
1918 unsigned SRsrcPtr = buildExtractSubReg(MI, MRI, *SRsrc,
1919 &AMDGPU::VReg_128RegClass, AMDGPU::sub0_sub1, &AMDGPU::VReg_64RegClass);
1921 // Create an empty resource descriptor
1922 unsigned Zero64 = MRI.createVirtualRegister(&AMDGPU::SReg_64RegClass);
1923 unsigned SRsrcFormatLo = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
1924 unsigned SRsrcFormatHi = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
1925 unsigned NewSRsrc = MRI.createVirtualRegister(&AMDGPU::SReg_128RegClass);
1926 uint64_t RsrcDataFormat = getDefaultRsrcDataFormat();
1929 BuildMI(MBB, MI, MI->getDebugLoc(), get(AMDGPU::S_MOV_B64),
1933 // SRsrcFormatLo = RSRC_DATA_FORMAT{31-0}
1934 BuildMI(MBB, MI, MI->getDebugLoc(), get(AMDGPU::S_MOV_B32),
1936 .addImm(RsrcDataFormat & 0xFFFFFFFF);
1938 // SRsrcFormatHi = RSRC_DATA_FORMAT{63-32}
1939 BuildMI(MBB, MI, MI->getDebugLoc(), get(AMDGPU::S_MOV_B32),
1941 .addImm(RsrcDataFormat >> 32);
1943 // NewSRsrc = {Zero64, SRsrcFormat}
1944 BuildMI(MBB, MI, MI->getDebugLoc(), get(AMDGPU::REG_SEQUENCE), NewSRsrc)
1946 .addImm(AMDGPU::sub0_sub1)
1947 .addReg(SRsrcFormatLo)
1948 .addImm(AMDGPU::sub2)
1949 .addReg(SRsrcFormatHi)
1950 .addImm(AMDGPU::sub3);
1952 MachineOperand *VAddr = getNamedOperand(*MI, AMDGPU::OpName::vaddr);
1953 unsigned NewVAddr = MRI.createVirtualRegister(&AMDGPU::VReg_64RegClass);
1955 // This is already an ADDR64 instruction so we need to add the pointer
1956 // extracted from the resource descriptor to the current value of VAddr.
1957 unsigned NewVAddrLo = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
1958 unsigned NewVAddrHi = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
1960 // NewVaddrLo = SRsrcPtr:sub0 + VAddr:sub0
1961 DebugLoc DL = MI->getDebugLoc();
1962 BuildMI(MBB, MI, DL, get(AMDGPU::V_ADD_I32_e32), NewVAddrLo)
1963 .addReg(SRsrcPtr, 0, AMDGPU::sub0)
1964 .addReg(VAddr->getReg(), 0, AMDGPU::sub0);
1966 // NewVaddrHi = SRsrcPtr:sub1 + VAddr:sub1
1967 BuildMI(MBB, MI, DL, get(AMDGPU::V_ADDC_U32_e32), NewVAddrHi)
1968 .addReg(SRsrcPtr, 0, AMDGPU::sub1)
1969 .addReg(VAddr->getReg(), 0, AMDGPU::sub1);
1971 // NewVaddr = {NewVaddrHi, NewVaddrLo}
1972 BuildMI(MBB, MI, MI->getDebugLoc(), get(AMDGPU::REG_SEQUENCE), NewVAddr)
1974 .addImm(AMDGPU::sub0)
1976 .addImm(AMDGPU::sub1);
1978 // This instructions is the _OFFSET variant, so we need to convert it to
1980 assert(MBB.getParent()->getSubtarget<AMDGPUSubtarget>().getGeneration()
1981 < AMDGPUSubtarget::VOLCANIC_ISLANDS &&
1982 "FIXME: Need to emit flat atomics here");
1984 MachineOperand *VData = getNamedOperand(*MI, AMDGPU::OpName::vdata);
1985 MachineOperand *Offset = getNamedOperand(*MI, AMDGPU::OpName::offset);
1986 MachineOperand *SOffset = getNamedOperand(*MI, AMDGPU::OpName::soffset);
1987 unsigned Addr64Opcode = AMDGPU::getAddr64Inst(MI->getOpcode());
1989 // Atomics rith return have have an additional tied operand and are
1990 // missing some of the special bits.
1991 MachineOperand *VDataIn = getNamedOperand(*MI, AMDGPU::OpName::vdata_in);
1992 MachineInstr *Addr64;
1995 // Regular buffer load / store.
1996 MachineInstrBuilder MIB
1997 = BuildMI(MBB, MI, MI->getDebugLoc(), get(Addr64Opcode))
1999 .addReg(AMDGPU::NoRegister) // Dummy value for vaddr.
2000 // This will be replaced later
2001 // with the new value of vaddr.
2003 .addOperand(*SOffset)
2004 .addOperand(*Offset);
2006 // Atomics do not have this operand.
2007 if (const MachineOperand *GLC
2008 = getNamedOperand(*MI, AMDGPU::OpName::glc)) {
2009 MIB.addImm(GLC->getImm());
2012 MIB.addImm(getNamedImmOperand(*MI, AMDGPU::OpName::slc));
2014 if (const MachineOperand *TFE
2015 = getNamedOperand(*MI, AMDGPU::OpName::tfe)) {
2016 MIB.addImm(TFE->getImm());
2019 MIB.setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
2022 // Atomics with return.
2023 Addr64 = BuildMI(MBB, MI, MI->getDebugLoc(), get(Addr64Opcode))
2025 .addOperand(*VDataIn)
2026 .addReg(AMDGPU::NoRegister) // Dummy value for vaddr.
2027 // This will be replaced later
2028 // with the new value of vaddr.
2030 .addOperand(*SOffset)
2031 .addOperand(*Offset)
2032 .addImm(getNamedImmOperand(*MI, AMDGPU::OpName::slc))
2033 .setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
2036 MI->removeFromParent();
2039 // NewVaddr = {NewVaddrHi, NewVaddrLo}
2040 BuildMI(MBB, MI, MI->getDebugLoc(), get(AMDGPU::REG_SEQUENCE), NewVAddr)
2041 .addReg(SRsrcPtr, 0, AMDGPU::sub0)
2042 .addImm(AMDGPU::sub0)
2043 .addReg(SRsrcPtr, 0, AMDGPU::sub1)
2044 .addImm(AMDGPU::sub1);
2046 VAddr = getNamedOperand(*MI, AMDGPU::OpName::vaddr);
2047 SRsrc = getNamedOperand(*MI, AMDGPU::OpName::srsrc);
2050 // Update the instruction to use NewVaddr
2051 VAddr->setReg(NewVAddr);
2052 // Update the instruction to use NewSRsrc
2053 SRsrc->setReg(NewSRsrc);
2057 void SIInstrInfo::splitSMRD(MachineInstr *MI,
2058 const TargetRegisterClass *HalfRC,
2059 unsigned HalfImmOp, unsigned HalfSGPROp,
2060 MachineInstr *&Lo, MachineInstr *&Hi) const {
2062 DebugLoc DL = MI->getDebugLoc();
2063 MachineBasicBlock *MBB = MI->getParent();
2064 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
2065 unsigned RegLo = MRI.createVirtualRegister(HalfRC);
2066 unsigned RegHi = MRI.createVirtualRegister(HalfRC);
2067 unsigned HalfSize = HalfRC->getSize();
2068 const MachineOperand *OffOp =
2069 getNamedOperand(*MI, AMDGPU::OpName::offset);
2070 const MachineOperand *SBase = getNamedOperand(*MI, AMDGPU::OpName::sbase);
2072 // The SMRD has an 8-bit offset in dwords on SI and a 20-bit offset in bytes
2075 bool IsKill = SBase->isKill();
2078 MBB->getParent()->getSubtarget<AMDGPUSubtarget>().getGeneration() >=
2079 AMDGPUSubtarget::VOLCANIC_ISLANDS;
2080 unsigned OffScale = isVI ? 1 : 4;
2081 // Handle the _IMM variant
2082 unsigned LoOffset = OffOp->getImm() * OffScale;
2083 unsigned HiOffset = LoOffset + HalfSize;
2084 Lo = BuildMI(*MBB, MI, DL, get(HalfImmOp), RegLo)
2085 // Use addReg instead of addOperand
2086 // to make sure kill flag is cleared.
2087 .addReg(SBase->getReg(), 0, SBase->getSubReg())
2088 .addImm(LoOffset / OffScale);
2090 if (!isUInt<20>(HiOffset) || (!isVI && !isUInt<8>(HiOffset / OffScale))) {
2091 unsigned OffsetSGPR =
2092 MRI.createVirtualRegister(&AMDGPU::SReg_32RegClass);
2093 BuildMI(*MBB, MI, DL, get(AMDGPU::S_MOV_B32), OffsetSGPR)
2094 .addImm(HiOffset); // The offset in register is in bytes.
2095 Hi = BuildMI(*MBB, MI, DL, get(HalfSGPROp), RegHi)
2096 .addReg(SBase->getReg(), getKillRegState(IsKill),
2098 .addReg(OffsetSGPR);
2100 Hi = BuildMI(*MBB, MI, DL, get(HalfImmOp), RegHi)
2101 .addReg(SBase->getReg(), getKillRegState(IsKill),
2103 .addImm(HiOffset / OffScale);
2106 // Handle the _SGPR variant
2107 MachineOperand *SOff = getNamedOperand(*MI, AMDGPU::OpName::soff);
2108 Lo = BuildMI(*MBB, MI, DL, get(HalfSGPROp), RegLo)
2109 .addReg(SBase->getReg(), 0, SBase->getSubReg())
2111 unsigned OffsetSGPR = MRI.createVirtualRegister(&AMDGPU::SReg_32RegClass);
2112 BuildMI(*MBB, MI, DL, get(AMDGPU::S_ADD_I32), OffsetSGPR)
2113 .addReg(SOff->getReg(), 0, SOff->getSubReg())
2115 Hi = BuildMI(*MBB, MI, DL, get(HalfSGPROp), RegHi)
2116 .addReg(SBase->getReg(), getKillRegState(IsKill),
2118 .addReg(OffsetSGPR);
2121 unsigned SubLo, SubHi;
2122 const TargetRegisterClass *NewDstRC;
2125 SubLo = AMDGPU::sub0;
2126 SubHi = AMDGPU::sub1;
2127 NewDstRC = &AMDGPU::VReg_64RegClass;
2130 SubLo = AMDGPU::sub0_sub1;
2131 SubHi = AMDGPU::sub2_sub3;
2132 NewDstRC = &AMDGPU::VReg_128RegClass;
2135 SubLo = AMDGPU::sub0_sub1_sub2_sub3;
2136 SubHi = AMDGPU::sub4_sub5_sub6_sub7;
2137 NewDstRC = &AMDGPU::VReg_256RegClass;
2140 SubLo = AMDGPU::sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7;
2141 SubHi = AMDGPU::sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15;
2142 NewDstRC = &AMDGPU::VReg_512RegClass;
2145 llvm_unreachable("Unhandled HalfSize");
2148 unsigned OldDst = MI->getOperand(0).getReg();
2149 unsigned NewDst = MRI.createVirtualRegister(NewDstRC);
2151 MRI.replaceRegWith(OldDst, NewDst);
2153 BuildMI(*MBB, MI, DL, get(AMDGPU::REG_SEQUENCE), NewDst)
2160 void SIInstrInfo::moveSMRDToVALU(MachineInstr *MI,
2161 MachineRegisterInfo &MRI,
2162 SmallVectorImpl<MachineInstr *> &Worklist) const {
2163 MachineBasicBlock *MBB = MI->getParent();
2164 int DstIdx = AMDGPU::getNamedOperandIdx(MI->getOpcode(), AMDGPU::OpName::dst);
2165 assert(DstIdx != -1);
2166 unsigned DstRCID = get(MI->getOpcode()).OpInfo[DstIdx].RegClass;
2167 switch(RI.getRegClass(DstRCID)->getSize()) {
2171 unsigned NewOpcode = getVALUOp(*MI);
2175 if (MI->getOperand(2).isReg()) {
2176 RegOffset = MI->getOperand(2).getReg();
2179 assert(MI->getOperand(2).isImm());
2180 // SMRD instructions take a dword offsets on SI and byte offset on VI
2181 // and MUBUF instructions always take a byte offset.
2182 ImmOffset = MI->getOperand(2).getImm();
2183 if (MBB->getParent()->getSubtarget<AMDGPUSubtarget>().getGeneration() <=
2184 AMDGPUSubtarget::SEA_ISLANDS)
2186 RegOffset = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
2188 if (isUInt<12>(ImmOffset)) {
2189 BuildMI(*MBB, MI, MI->getDebugLoc(), get(AMDGPU::S_MOV_B32),
2193 BuildMI(*MBB, MI, MI->getDebugLoc(), get(AMDGPU::S_MOV_B32),
2200 unsigned SRsrc = MRI.createVirtualRegister(&AMDGPU::SReg_128RegClass);
2201 unsigned DWord0 = RegOffset;
2202 unsigned DWord1 = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
2203 unsigned DWord2 = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
2204 unsigned DWord3 = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
2205 uint64_t RsrcDataFormat = getDefaultRsrcDataFormat();
2207 BuildMI(*MBB, MI, MI->getDebugLoc(), get(AMDGPU::S_MOV_B32), DWord1)
2209 BuildMI(*MBB, MI, MI->getDebugLoc(), get(AMDGPU::S_MOV_B32), DWord2)
2210 .addImm(RsrcDataFormat & 0xFFFFFFFF);
2211 BuildMI(*MBB, MI, MI->getDebugLoc(), get(AMDGPU::S_MOV_B32), DWord3)
2212 .addImm(RsrcDataFormat >> 32);
2213 BuildMI(*MBB, MI, MI->getDebugLoc(), get(AMDGPU::REG_SEQUENCE), SRsrc)
2215 .addImm(AMDGPU::sub0)
2217 .addImm(AMDGPU::sub1)
2219 .addImm(AMDGPU::sub2)
2221 .addImm(AMDGPU::sub3);
2223 const MCInstrDesc &NewInstDesc = get(NewOpcode);
2224 const TargetRegisterClass *NewDstRC
2225 = RI.getRegClass(NewInstDesc.OpInfo[0].RegClass);
2226 unsigned NewDstReg = MRI.createVirtualRegister(NewDstRC);
2227 unsigned DstReg = MI->getOperand(0).getReg();
2228 MRI.replaceRegWith(DstReg, NewDstReg);
2230 MachineInstr *NewInst =
2231 BuildMI(*MBB, MI, MI->getDebugLoc(), NewInstDesc, NewDstReg)
2232 .addOperand(MI->getOperand(1)) // sbase
2239 .setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
2240 MI->eraseFromParent();
2242 legalizeOperands(NewInst);
2243 addUsersToMoveToVALUWorklist(NewDstReg, MRI, Worklist);
2247 MachineInstr *Lo, *Hi;
2248 splitSMRD(MI, &AMDGPU::SReg_128RegClass, AMDGPU::S_LOAD_DWORDX4_IMM,
2249 AMDGPU::S_LOAD_DWORDX4_SGPR, Lo, Hi);
2250 MI->eraseFromParent();
2251 moveSMRDToVALU(Lo, MRI, Worklist);
2252 moveSMRDToVALU(Hi, MRI, Worklist);
2257 MachineInstr *Lo, *Hi;
2258 splitSMRD(MI, &AMDGPU::SReg_256RegClass, AMDGPU::S_LOAD_DWORDX8_IMM,
2259 AMDGPU::S_LOAD_DWORDX8_SGPR, Lo, Hi);
2260 MI->eraseFromParent();
2261 moveSMRDToVALU(Lo, MRI, Worklist);
2262 moveSMRDToVALU(Hi, MRI, Worklist);
2268 void SIInstrInfo::moveToVALU(MachineInstr &TopInst) const {
2269 SmallVector<MachineInstr *, 128> Worklist;
2270 Worklist.push_back(&TopInst);
2272 while (!Worklist.empty()) {
2273 MachineInstr *Inst = Worklist.pop_back_val();
2274 MachineBasicBlock *MBB = Inst->getParent();
2275 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
2277 unsigned Opcode = Inst->getOpcode();
2278 unsigned NewOpcode = getVALUOp(*Inst);
2280 // Handle some special cases
2283 if (isSMRD(*Inst)) {
2284 moveSMRDToVALU(Inst, MRI, Worklist);
2288 case AMDGPU::S_AND_B64:
2289 splitScalar64BitBinaryOp(Worklist, Inst, AMDGPU::V_AND_B32_e64);
2290 Inst->eraseFromParent();
2293 case AMDGPU::S_OR_B64:
2294 splitScalar64BitBinaryOp(Worklist, Inst, AMDGPU::V_OR_B32_e64);
2295 Inst->eraseFromParent();
2298 case AMDGPU::S_XOR_B64:
2299 splitScalar64BitBinaryOp(Worklist, Inst, AMDGPU::V_XOR_B32_e64);
2300 Inst->eraseFromParent();
2303 case AMDGPU::S_NOT_B64:
2304 splitScalar64BitUnaryOp(Worklist, Inst, AMDGPU::V_NOT_B32_e32);
2305 Inst->eraseFromParent();
2308 case AMDGPU::S_BCNT1_I32_B64:
2309 splitScalar64BitBCNT(Worklist, Inst);
2310 Inst->eraseFromParent();
2313 case AMDGPU::S_BFE_I64: {
2314 splitScalar64BitBFE(Worklist, Inst);
2315 Inst->eraseFromParent();
2319 case AMDGPU::S_LSHL_B32:
2320 if (ST.getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS) {
2321 NewOpcode = AMDGPU::V_LSHLREV_B32_e64;
2325 case AMDGPU::S_ASHR_I32:
2326 if (ST.getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS) {
2327 NewOpcode = AMDGPU::V_ASHRREV_I32_e64;
2331 case AMDGPU::S_LSHR_B32:
2332 if (ST.getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS) {
2333 NewOpcode = AMDGPU::V_LSHRREV_B32_e64;
2337 case AMDGPU::S_LSHL_B64:
2338 if (ST.getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS) {
2339 NewOpcode = AMDGPU::V_LSHLREV_B64;
2343 case AMDGPU::S_ASHR_I64:
2344 if (ST.getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS) {
2345 NewOpcode = AMDGPU::V_ASHRREV_I64;
2349 case AMDGPU::S_LSHR_B64:
2350 if (ST.getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS) {
2351 NewOpcode = AMDGPU::V_LSHRREV_B64;
2356 case AMDGPU::S_BFE_U64:
2357 case AMDGPU::S_BFM_B64:
2358 llvm_unreachable("Moving this op to VALU not implemented");
2361 if (NewOpcode == AMDGPU::INSTRUCTION_LIST_END) {
2362 // We cannot move this instruction to the VALU, so we should try to
2363 // legalize its operands instead.
2364 legalizeOperands(Inst);
2368 // Use the new VALU Opcode.
2369 const MCInstrDesc &NewDesc = get(NewOpcode);
2370 Inst->setDesc(NewDesc);
2372 // Remove any references to SCC. Vector instructions can't read from it, and
2373 // We're just about to add the implicit use / defs of VCC, and we don't want
2375 for (unsigned i = Inst->getNumOperands() - 1; i > 0; --i) {
2376 MachineOperand &Op = Inst->getOperand(i);
2377 if (Op.isReg() && Op.getReg() == AMDGPU::SCC)
2378 Inst->RemoveOperand(i);
2381 if (Opcode == AMDGPU::S_SEXT_I32_I8 || Opcode == AMDGPU::S_SEXT_I32_I16) {
2382 // We are converting these to a BFE, so we need to add the missing
2383 // operands for the size and offset.
2384 unsigned Size = (Opcode == AMDGPU::S_SEXT_I32_I8) ? 8 : 16;
2385 Inst->addOperand(MachineOperand::CreateImm(0));
2386 Inst->addOperand(MachineOperand::CreateImm(Size));
2388 } else if (Opcode == AMDGPU::S_BCNT1_I32_B32) {
2389 // The VALU version adds the second operand to the result, so insert an
2391 Inst->addOperand(MachineOperand::CreateImm(0));
2394 Inst->addImplicitDefUseOperands(*Inst->getParent()->getParent());
2396 if (Opcode == AMDGPU::S_BFE_I32 || Opcode == AMDGPU::S_BFE_U32) {
2397 const MachineOperand &OffsetWidthOp = Inst->getOperand(2);
2398 // If we need to move this to VGPRs, we need to unpack the second operand
2399 // back into the 2 separate ones for bit offset and width.
2400 assert(OffsetWidthOp.isImm() &&
2401 "Scalar BFE is only implemented for constant width and offset");
2402 uint32_t Imm = OffsetWidthOp.getImm();
2404 uint32_t Offset = Imm & 0x3f; // Extract bits [5:0].
2405 uint32_t BitWidth = (Imm & 0x7f0000) >> 16; // Extract bits [22:16].
2406 Inst->RemoveOperand(2); // Remove old immediate.
2407 Inst->addOperand(MachineOperand::CreateImm(Offset));
2408 Inst->addOperand(MachineOperand::CreateImm(BitWidth));
2411 // Update the destination register class.
2412 const TargetRegisterClass *NewDstRC = getDestEquivalentVGPRClass(*Inst);
2416 unsigned DstReg = Inst->getOperand(0).getReg();
2417 unsigned NewDstReg = MRI.createVirtualRegister(NewDstRC);
2418 MRI.replaceRegWith(DstReg, NewDstReg);
2420 // Legalize the operands
2421 legalizeOperands(Inst);
2423 addUsersToMoveToVALUWorklist(NewDstReg, MRI, Worklist);
2427 //===----------------------------------------------------------------------===//
2428 // Indirect addressing callbacks
2429 //===----------------------------------------------------------------------===//
2431 unsigned SIInstrInfo::calculateIndirectAddress(unsigned RegIndex,
2432 unsigned Channel) const {
2433 assert(Channel == 0);
2437 const TargetRegisterClass *SIInstrInfo::getIndirectAddrRegClass() const {
2438 return &AMDGPU::VGPR_32RegClass;
2441 void SIInstrInfo::splitScalar64BitUnaryOp(
2442 SmallVectorImpl<MachineInstr *> &Worklist,
2444 unsigned Opcode) const {
2445 MachineBasicBlock &MBB = *Inst->getParent();
2446 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
2448 MachineOperand &Dest = Inst->getOperand(0);
2449 MachineOperand &Src0 = Inst->getOperand(1);
2450 DebugLoc DL = Inst->getDebugLoc();
2452 MachineBasicBlock::iterator MII = Inst;
2454 const MCInstrDesc &InstDesc = get(Opcode);
2455 const TargetRegisterClass *Src0RC = Src0.isReg() ?
2456 MRI.getRegClass(Src0.getReg()) :
2457 &AMDGPU::SGPR_32RegClass;
2459 const TargetRegisterClass *Src0SubRC = RI.getSubRegClass(Src0RC, AMDGPU::sub0);
2461 MachineOperand SrcReg0Sub0 = buildExtractSubRegOrImm(MII, MRI, Src0, Src0RC,
2462 AMDGPU::sub0, Src0SubRC);
2464 const TargetRegisterClass *DestRC = MRI.getRegClass(Dest.getReg());
2465 const TargetRegisterClass *NewDestRC = RI.getEquivalentVGPRClass(DestRC);
2466 const TargetRegisterClass *NewDestSubRC = RI.getSubRegClass(NewDestRC, AMDGPU::sub0);
2468 unsigned DestSub0 = MRI.createVirtualRegister(NewDestSubRC);
2469 BuildMI(MBB, MII, DL, InstDesc, DestSub0)
2470 .addOperand(SrcReg0Sub0);
2472 MachineOperand SrcReg0Sub1 = buildExtractSubRegOrImm(MII, MRI, Src0, Src0RC,
2473 AMDGPU::sub1, Src0SubRC);
2475 unsigned DestSub1 = MRI.createVirtualRegister(NewDestSubRC);
2476 BuildMI(MBB, MII, DL, InstDesc, DestSub1)
2477 .addOperand(SrcReg0Sub1);
2479 unsigned FullDestReg = MRI.createVirtualRegister(NewDestRC);
2480 BuildMI(MBB, MII, DL, get(TargetOpcode::REG_SEQUENCE), FullDestReg)
2482 .addImm(AMDGPU::sub0)
2484 .addImm(AMDGPU::sub1);
2486 MRI.replaceRegWith(Dest.getReg(), FullDestReg);
2488 // We don't need to legalizeOperands here because for a single operand, src0
2489 // will support any kind of input.
2491 // Move all users of this moved value.
2492 addUsersToMoveToVALUWorklist(FullDestReg, MRI, Worklist);
2495 void SIInstrInfo::splitScalar64BitBinaryOp(
2496 SmallVectorImpl<MachineInstr *> &Worklist,
2498 unsigned Opcode) const {
2499 MachineBasicBlock &MBB = *Inst->getParent();
2500 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
2502 MachineOperand &Dest = Inst->getOperand(0);
2503 MachineOperand &Src0 = Inst->getOperand(1);
2504 MachineOperand &Src1 = Inst->getOperand(2);
2505 DebugLoc DL = Inst->getDebugLoc();
2507 MachineBasicBlock::iterator MII = Inst;
2509 const MCInstrDesc &InstDesc = get(Opcode);
2510 const TargetRegisterClass *Src0RC = Src0.isReg() ?
2511 MRI.getRegClass(Src0.getReg()) :
2512 &AMDGPU::SGPR_32RegClass;
2514 const TargetRegisterClass *Src0SubRC = RI.getSubRegClass(Src0RC, AMDGPU::sub0);
2515 const TargetRegisterClass *Src1RC = Src1.isReg() ?
2516 MRI.getRegClass(Src1.getReg()) :
2517 &AMDGPU::SGPR_32RegClass;
2519 const TargetRegisterClass *Src1SubRC = RI.getSubRegClass(Src1RC, AMDGPU::sub0);
2521 MachineOperand SrcReg0Sub0 = buildExtractSubRegOrImm(MII, MRI, Src0, Src0RC,
2522 AMDGPU::sub0, Src0SubRC);
2523 MachineOperand SrcReg1Sub0 = buildExtractSubRegOrImm(MII, MRI, Src1, Src1RC,
2524 AMDGPU::sub0, Src1SubRC);
2526 const TargetRegisterClass *DestRC = MRI.getRegClass(Dest.getReg());
2527 const TargetRegisterClass *NewDestRC = RI.getEquivalentVGPRClass(DestRC);
2528 const TargetRegisterClass *NewDestSubRC = RI.getSubRegClass(NewDestRC, AMDGPU::sub0);
2530 unsigned DestSub0 = MRI.createVirtualRegister(NewDestSubRC);
2531 MachineInstr *LoHalf = BuildMI(MBB, MII, DL, InstDesc, DestSub0)
2532 .addOperand(SrcReg0Sub0)
2533 .addOperand(SrcReg1Sub0);
2535 MachineOperand SrcReg0Sub1 = buildExtractSubRegOrImm(MII, MRI, Src0, Src0RC,
2536 AMDGPU::sub1, Src0SubRC);
2537 MachineOperand SrcReg1Sub1 = buildExtractSubRegOrImm(MII, MRI, Src1, Src1RC,
2538 AMDGPU::sub1, Src1SubRC);
2540 unsigned DestSub1 = MRI.createVirtualRegister(NewDestSubRC);
2541 MachineInstr *HiHalf = BuildMI(MBB, MII, DL, InstDesc, DestSub1)
2542 .addOperand(SrcReg0Sub1)
2543 .addOperand(SrcReg1Sub1);
2545 unsigned FullDestReg = MRI.createVirtualRegister(NewDestRC);
2546 BuildMI(MBB, MII, DL, get(TargetOpcode::REG_SEQUENCE), FullDestReg)
2548 .addImm(AMDGPU::sub0)
2550 .addImm(AMDGPU::sub1);
2552 MRI.replaceRegWith(Dest.getReg(), FullDestReg);
2554 // Try to legalize the operands in case we need to swap the order to keep it
2556 legalizeOperands(LoHalf);
2557 legalizeOperands(HiHalf);
2559 // Move all users of this moved vlaue.
2560 addUsersToMoveToVALUWorklist(FullDestReg, MRI, Worklist);
2563 void SIInstrInfo::splitScalar64BitBCNT(SmallVectorImpl<MachineInstr *> &Worklist,
2564 MachineInstr *Inst) const {
2565 MachineBasicBlock &MBB = *Inst->getParent();
2566 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
2568 MachineBasicBlock::iterator MII = Inst;
2569 DebugLoc DL = Inst->getDebugLoc();
2571 MachineOperand &Dest = Inst->getOperand(0);
2572 MachineOperand &Src = Inst->getOperand(1);
2574 const MCInstrDesc &InstDesc = get(AMDGPU::V_BCNT_U32_B32_e64);
2575 const TargetRegisterClass *SrcRC = Src.isReg() ?
2576 MRI.getRegClass(Src.getReg()) :
2577 &AMDGPU::SGPR_32RegClass;
2579 unsigned MidReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
2580 unsigned ResultReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
2582 const TargetRegisterClass *SrcSubRC = RI.getSubRegClass(SrcRC, AMDGPU::sub0);
2584 MachineOperand SrcRegSub0 = buildExtractSubRegOrImm(MII, MRI, Src, SrcRC,
2585 AMDGPU::sub0, SrcSubRC);
2586 MachineOperand SrcRegSub1 = buildExtractSubRegOrImm(MII, MRI, Src, SrcRC,
2587 AMDGPU::sub1, SrcSubRC);
2589 BuildMI(MBB, MII, DL, InstDesc, MidReg)
2590 .addOperand(SrcRegSub0)
2593 BuildMI(MBB, MII, DL, InstDesc, ResultReg)
2594 .addOperand(SrcRegSub1)
2597 MRI.replaceRegWith(Dest.getReg(), ResultReg);
2599 // We don't need to legalize operands here. src0 for etiher instruction can be
2600 // an SGPR, and the second input is unused or determined here.
2601 addUsersToMoveToVALUWorklist(ResultReg, MRI, Worklist);
2604 void SIInstrInfo::splitScalar64BitBFE(SmallVectorImpl<MachineInstr *> &Worklist,
2605 MachineInstr *Inst) const {
2606 MachineBasicBlock &MBB = *Inst->getParent();
2607 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
2608 MachineBasicBlock::iterator MII = Inst;
2609 DebugLoc DL = Inst->getDebugLoc();
2611 MachineOperand &Dest = Inst->getOperand(0);
2612 uint32_t Imm = Inst->getOperand(2).getImm();
2613 uint32_t Offset = Imm & 0x3f; // Extract bits [5:0].
2614 uint32_t BitWidth = (Imm & 0x7f0000) >> 16; // Extract bits [22:16].
2618 // Only sext_inreg cases handled.
2619 assert(Inst->getOpcode() == AMDGPU::S_BFE_I64 &&
2624 if (BitWidth < 32) {
2625 unsigned MidRegLo = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
2626 unsigned MidRegHi = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
2627 unsigned ResultReg = MRI.createVirtualRegister(&AMDGPU::VReg_64RegClass);
2629 BuildMI(MBB, MII, DL, get(AMDGPU::V_BFE_I32), MidRegLo)
2630 .addReg(Inst->getOperand(1).getReg(), 0, AMDGPU::sub0)
2634 BuildMI(MBB, MII, DL, get(AMDGPU::V_ASHRREV_I32_e32), MidRegHi)
2638 BuildMI(MBB, MII, DL, get(TargetOpcode::REG_SEQUENCE), ResultReg)
2640 .addImm(AMDGPU::sub0)
2642 .addImm(AMDGPU::sub1);
2644 MRI.replaceRegWith(Dest.getReg(), ResultReg);
2645 addUsersToMoveToVALUWorklist(ResultReg, MRI, Worklist);
2649 MachineOperand &Src = Inst->getOperand(1);
2650 unsigned TmpReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
2651 unsigned ResultReg = MRI.createVirtualRegister(&AMDGPU::VReg_64RegClass);
2653 BuildMI(MBB, MII, DL, get(AMDGPU::V_ASHRREV_I32_e64), TmpReg)
2655 .addReg(Src.getReg(), 0, AMDGPU::sub0);
2657 BuildMI(MBB, MII, DL, get(TargetOpcode::REG_SEQUENCE), ResultReg)
2658 .addReg(Src.getReg(), 0, AMDGPU::sub0)
2659 .addImm(AMDGPU::sub0)
2661 .addImm(AMDGPU::sub1);
2663 MRI.replaceRegWith(Dest.getReg(), ResultReg);
2664 addUsersToMoveToVALUWorklist(ResultReg, MRI, Worklist);
2667 void SIInstrInfo::addUsersToMoveToVALUWorklist(
2669 MachineRegisterInfo &MRI,
2670 SmallVectorImpl<MachineInstr *> &Worklist) const {
2671 for (MachineRegisterInfo::use_iterator I = MRI.use_begin(DstReg),
2672 E = MRI.use_end(); I != E; ++I) {
2673 MachineInstr &UseMI = *I->getParent();
2674 if (!canReadVGPR(UseMI, I.getOperandNo())) {
2675 Worklist.push_back(&UseMI);
2680 const TargetRegisterClass *SIInstrInfo::getDestEquivalentVGPRClass(
2681 const MachineInstr &Inst) const {
2682 const TargetRegisterClass *NewDstRC = getOpRegClass(Inst, 0);
2684 switch (Inst.getOpcode()) {
2685 // For target instructions, getOpRegClass just returns the virtual register
2686 // class associated with the operand, so we need to find an equivalent VGPR
2687 // register class in order to move the instruction to the VALU.
2690 case AMDGPU::REG_SEQUENCE:
2691 case AMDGPU::INSERT_SUBREG:
2692 if (RI.hasVGPRs(NewDstRC))
2695 NewDstRC = RI.getEquivalentVGPRClass(NewDstRC);
2704 // Find the one SGPR operand we are allowed to use.
2705 unsigned SIInstrInfo::findUsedSGPR(const MachineInstr *MI,
2706 int OpIndices[3]) const {
2707 const MCInstrDesc &Desc = MI->getDesc();
2709 // Find the one SGPR operand we are allowed to use.
2711 // First we need to consider the instruction's operand requirements before
2712 // legalizing. Some operands are required to be SGPRs, such as implicit uses
2713 // of VCC, but we are still bound by the constant bus requirement to only use
2716 // If the operand's class is an SGPR, we can never move it.
2718 unsigned SGPRReg = findImplicitSGPRRead(*MI);
2719 if (SGPRReg != AMDGPU::NoRegister)
2722 unsigned UsedSGPRs[3] = { AMDGPU::NoRegister };
2723 const MachineRegisterInfo &MRI = MI->getParent()->getParent()->getRegInfo();
2725 for (unsigned i = 0; i < 3; ++i) {
2726 int Idx = OpIndices[i];
2730 const MachineOperand &MO = MI->getOperand(Idx);
2734 // Is this operand statically required to be an SGPR based on the operand
2736 const TargetRegisterClass *OpRC = RI.getRegClass(Desc.OpInfo[Idx].RegClass);
2737 bool IsRequiredSGPR = RI.isSGPRClass(OpRC);
2741 // If this could be a VGPR or an SGPR, Check the dynamic register class.
2742 unsigned Reg = MO.getReg();
2743 const TargetRegisterClass *RegRC = MRI.getRegClass(Reg);
2744 if (RI.isSGPRClass(RegRC))
2748 // We don't have a required SGPR operand, so we have a bit more freedom in
2749 // selecting operands to move.
2751 // Try to select the most used SGPR. If an SGPR is equal to one of the
2752 // others, we choose that.
2755 // V_FMA_F32 v0, s0, s0, s0 -> No moves
2756 // V_FMA_F32 v0, s0, s1, s0 -> Move s1
2758 // TODO: If some of the operands are 64-bit SGPRs and some 32, we should
2761 if (UsedSGPRs[0] != AMDGPU::NoRegister) {
2762 if (UsedSGPRs[0] == UsedSGPRs[1] || UsedSGPRs[0] == UsedSGPRs[2])
2763 SGPRReg = UsedSGPRs[0];
2766 if (SGPRReg == AMDGPU::NoRegister && UsedSGPRs[1] != AMDGPU::NoRegister) {
2767 if (UsedSGPRs[1] == UsedSGPRs[2])
2768 SGPRReg = UsedSGPRs[1];
2774 MachineInstrBuilder SIInstrInfo::buildIndirectWrite(
2775 MachineBasicBlock *MBB,
2776 MachineBasicBlock::iterator I,
2778 unsigned Address, unsigned OffsetReg) const {
2779 const DebugLoc &DL = MBB->findDebugLoc(I);
2780 unsigned IndirectBaseReg = AMDGPU::VGPR_32RegClass.getRegister(
2781 getIndirectIndexBegin(*MBB->getParent()));
2783 return BuildMI(*MBB, I, DL, get(AMDGPU::SI_INDIRECT_DST_V1))
2784 .addReg(IndirectBaseReg, RegState::Define)
2785 .addOperand(I->getOperand(0))
2786 .addReg(IndirectBaseReg)
2792 MachineInstrBuilder SIInstrInfo::buildIndirectRead(
2793 MachineBasicBlock *MBB,
2794 MachineBasicBlock::iterator I,
2796 unsigned Address, unsigned OffsetReg) const {
2797 const DebugLoc &DL = MBB->findDebugLoc(I);
2798 unsigned IndirectBaseReg = AMDGPU::VGPR_32RegClass.getRegister(
2799 getIndirectIndexBegin(*MBB->getParent()));
2801 return BuildMI(*MBB, I, DL, get(AMDGPU::SI_INDIRECT_SRC_V1))
2802 .addOperand(I->getOperand(0))
2803 .addOperand(I->getOperand(1))
2804 .addReg(IndirectBaseReg)
2810 void SIInstrInfo::reserveIndirectRegisters(BitVector &Reserved,
2811 const MachineFunction &MF) const {
2812 int End = getIndirectIndexEnd(MF);
2813 int Begin = getIndirectIndexBegin(MF);
2819 for (int Index = Begin; Index <= End; ++Index)
2820 Reserved.set(AMDGPU::VGPR_32RegClass.getRegister(Index));
2822 for (int Index = std::max(0, Begin - 1); Index <= End; ++Index)
2823 Reserved.set(AMDGPU::VReg_64RegClass.getRegister(Index));
2825 for (int Index = std::max(0, Begin - 2); Index <= End; ++Index)
2826 Reserved.set(AMDGPU::VReg_96RegClass.getRegister(Index));
2828 for (int Index = std::max(0, Begin - 3); Index <= End; ++Index)
2829 Reserved.set(AMDGPU::VReg_128RegClass.getRegister(Index));
2831 for (int Index = std::max(0, Begin - 7); Index <= End; ++Index)
2832 Reserved.set(AMDGPU::VReg_256RegClass.getRegister(Index));
2834 for (int Index = std::max(0, Begin - 15); Index <= End; ++Index)
2835 Reserved.set(AMDGPU::VReg_512RegClass.getRegister(Index));
2838 MachineOperand *SIInstrInfo::getNamedOperand(MachineInstr &MI,
2839 unsigned OperandName) const {
2840 int Idx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), OperandName);
2844 return &MI.getOperand(Idx);
2847 uint64_t SIInstrInfo::getDefaultRsrcDataFormat() const {
2848 uint64_t RsrcDataFormat = AMDGPU::RSRC_DATA_FORMAT;
2849 if (ST.isAmdHsaOS()) {
2850 RsrcDataFormat |= (1ULL << 56);
2852 if (ST.getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS)
2854 RsrcDataFormat |= (2ULL << 59);
2857 return RsrcDataFormat;
2860 uint64_t SIInstrInfo::getScratchRsrcWords23() const {
2861 uint64_t Rsrc23 = getDefaultRsrcDataFormat() |
2862 AMDGPU::RSRC_TID_ENABLE |
2863 0xffffffff; // Size;
2865 // If TID_ENABLE is set, DATA_FORMAT specifies stride bits [14:17].
2866 // Clear them unless we want a huge stride.
2867 if (ST.getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS)
2868 Rsrc23 &= ~AMDGPU::RSRC_DATA_FORMAT;