1 //===-- SIInstrInfo.cpp - SI Instruction Information ---------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// \brief SI Implementation of TargetInstrInfo.
13 //===----------------------------------------------------------------------===//
16 #include "SIInstrInfo.h"
17 #include "AMDGPUTargetMachine.h"
18 #include "SIDefines.h"
19 #include "SIMachineFunctionInfo.h"
20 #include "llvm/CodeGen/MachineFrameInfo.h"
21 #include "llvm/CodeGen/MachineInstrBuilder.h"
22 #include "llvm/CodeGen/MachineRegisterInfo.h"
23 #include "llvm/IR/Function.h"
24 #include "llvm/CodeGen/RegisterScavenging.h"
25 #include "llvm/MC/MCInstrDesc.h"
26 #include "llvm/Support/Debug.h"
30 SIInstrInfo::SIInstrInfo(const AMDGPUSubtarget &st)
31 : AMDGPUInstrInfo(st), RI() {}
33 //===----------------------------------------------------------------------===//
34 // TargetInstrInfo callbacks
35 //===----------------------------------------------------------------------===//
37 static unsigned getNumOperandsNoGlue(SDNode *Node) {
38 unsigned N = Node->getNumOperands();
39 while (N && Node->getOperand(N - 1).getValueType() == MVT::Glue)
44 static SDValue findChainOperand(SDNode *Load) {
45 SDValue LastOp = Load->getOperand(getNumOperandsNoGlue(Load) - 1);
46 assert(LastOp.getValueType() == MVT::Other && "Chain missing from load node");
50 /// \brief Returns true if both nodes have the same value for the given
51 /// operand \p Op, or if both nodes do not have this operand.
52 static bool nodesHaveSameOperandValue(SDNode *N0, SDNode* N1, unsigned OpName) {
53 unsigned Opc0 = N0->getMachineOpcode();
54 unsigned Opc1 = N1->getMachineOpcode();
56 int Op0Idx = AMDGPU::getNamedOperandIdx(Opc0, OpName);
57 int Op1Idx = AMDGPU::getNamedOperandIdx(Opc1, OpName);
59 if (Op0Idx == -1 && Op1Idx == -1)
63 if ((Op0Idx == -1 && Op1Idx != -1) ||
64 (Op1Idx == -1 && Op0Idx != -1))
67 // getNamedOperandIdx returns the index for the MachineInstr's operands,
68 // which includes the result as the first operand. We are indexing into the
69 // MachineSDNode's operands, so we need to skip the result operand to get
74 return N0->getOperand(Op0Idx) == N1->getOperand(Op1Idx);
77 bool SIInstrInfo::isReallyTriviallyReMaterializable(const MachineInstr *MI,
78 AliasAnalysis *AA) const {
79 // TODO: The generic check fails for VALU instructions that should be
80 // rematerializable due to implicit reads of exec. We really want all of the
81 // generic logic for this except for this.
82 switch (MI->getOpcode()) {
83 case AMDGPU::V_MOV_B32_e32:
84 case AMDGPU::V_MOV_B32_e64:
85 case AMDGPU::V_MOV_B64_PSEUDO:
92 bool SIInstrInfo::areLoadsFromSameBasePtr(SDNode *Load0, SDNode *Load1,
94 int64_t &Offset1) const {
95 if (!Load0->isMachineOpcode() || !Load1->isMachineOpcode())
98 unsigned Opc0 = Load0->getMachineOpcode();
99 unsigned Opc1 = Load1->getMachineOpcode();
101 // Make sure both are actually loads.
102 if (!get(Opc0).mayLoad() || !get(Opc1).mayLoad())
105 if (isDS(Opc0) && isDS(Opc1)) {
107 // FIXME: Handle this case:
108 if (getNumOperandsNoGlue(Load0) != getNumOperandsNoGlue(Load1))
112 if (Load0->getOperand(1) != Load1->getOperand(1))
116 if (findChainOperand(Load0) != findChainOperand(Load1))
119 // Skip read2 / write2 variants for simplicity.
120 // TODO: We should report true if the used offsets are adjacent (excluded
122 if (AMDGPU::getNamedOperandIdx(Opc0, AMDGPU::OpName::data1) != -1 ||
123 AMDGPU::getNamedOperandIdx(Opc1, AMDGPU::OpName::data1) != -1)
126 Offset0 = cast<ConstantSDNode>(Load0->getOperand(2))->getZExtValue();
127 Offset1 = cast<ConstantSDNode>(Load1->getOperand(2))->getZExtValue();
131 if (isSMRD(Opc0) && isSMRD(Opc1)) {
132 assert(getNumOperandsNoGlue(Load0) == getNumOperandsNoGlue(Load1));
135 if (Load0->getOperand(0) != Load1->getOperand(0))
138 const ConstantSDNode *Load0Offset =
139 dyn_cast<ConstantSDNode>(Load0->getOperand(1));
140 const ConstantSDNode *Load1Offset =
141 dyn_cast<ConstantSDNode>(Load1->getOperand(1));
143 if (!Load0Offset || !Load1Offset)
147 if (findChainOperand(Load0) != findChainOperand(Load1))
150 Offset0 = Load0Offset->getZExtValue();
151 Offset1 = Load1Offset->getZExtValue();
155 // MUBUF and MTBUF can access the same addresses.
156 if ((isMUBUF(Opc0) || isMTBUF(Opc0)) && (isMUBUF(Opc1) || isMTBUF(Opc1))) {
158 // MUBUF and MTBUF have vaddr at different indices.
159 if (!nodesHaveSameOperandValue(Load0, Load1, AMDGPU::OpName::soffset) ||
160 findChainOperand(Load0) != findChainOperand(Load1) ||
161 !nodesHaveSameOperandValue(Load0, Load1, AMDGPU::OpName::vaddr) ||
162 !nodesHaveSameOperandValue(Load0, Load1, AMDGPU::OpName::srsrc))
165 int OffIdx0 = AMDGPU::getNamedOperandIdx(Opc0, AMDGPU::OpName::offset);
166 int OffIdx1 = AMDGPU::getNamedOperandIdx(Opc1, AMDGPU::OpName::offset);
168 if (OffIdx0 == -1 || OffIdx1 == -1)
171 // getNamedOperandIdx returns the index for MachineInstrs. Since they
172 // inlcude the output in the operand list, but SDNodes don't, we need to
173 // subtract the index by one.
177 SDValue Off0 = Load0->getOperand(OffIdx0);
178 SDValue Off1 = Load1->getOperand(OffIdx1);
180 // The offset might be a FrameIndexSDNode.
181 if (!isa<ConstantSDNode>(Off0) || !isa<ConstantSDNode>(Off1))
184 Offset0 = cast<ConstantSDNode>(Off0)->getZExtValue();
185 Offset1 = cast<ConstantSDNode>(Off1)->getZExtValue();
192 static bool isStride64(unsigned Opc) {
194 case AMDGPU::DS_READ2ST64_B32:
195 case AMDGPU::DS_READ2ST64_B64:
196 case AMDGPU::DS_WRITE2ST64_B32:
197 case AMDGPU::DS_WRITE2ST64_B64:
204 bool SIInstrInfo::getMemOpBaseRegImmOfs(MachineInstr *LdSt, unsigned &BaseReg,
206 const TargetRegisterInfo *TRI) const {
207 unsigned Opc = LdSt->getOpcode();
210 const MachineOperand *OffsetImm = getNamedOperand(*LdSt,
211 AMDGPU::OpName::offset);
213 // Normal, single offset LDS instruction.
214 const MachineOperand *AddrReg = getNamedOperand(*LdSt,
215 AMDGPU::OpName::addr);
217 BaseReg = AddrReg->getReg();
218 Offset = OffsetImm->getImm();
222 // The 2 offset instructions use offset0 and offset1 instead. We can treat
223 // these as a load with a single offset if the 2 offsets are consecutive. We
224 // will use this for some partially aligned loads.
225 const MachineOperand *Offset0Imm = getNamedOperand(*LdSt,
226 AMDGPU::OpName::offset0);
227 const MachineOperand *Offset1Imm = getNamedOperand(*LdSt,
228 AMDGPU::OpName::offset1);
230 uint8_t Offset0 = Offset0Imm->getImm();
231 uint8_t Offset1 = Offset1Imm->getImm();
233 if (Offset1 > Offset0 && Offset1 - Offset0 == 1) {
234 // Each of these offsets is in element sized units, so we need to convert
235 // to bytes of the individual reads.
239 EltSize = getOpRegClass(*LdSt, 0)->getSize() / 2;
241 assert(LdSt->mayStore());
242 int Data0Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::data0);
243 EltSize = getOpRegClass(*LdSt, Data0Idx)->getSize();
249 const MachineOperand *AddrReg = getNamedOperand(*LdSt,
250 AMDGPU::OpName::addr);
251 BaseReg = AddrReg->getReg();
252 Offset = EltSize * Offset0;
259 if (isMUBUF(*LdSt) || isMTBUF(*LdSt)) {
260 if (AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::soffset) != -1)
263 const MachineOperand *AddrReg = getNamedOperand(*LdSt,
264 AMDGPU::OpName::vaddr);
268 const MachineOperand *OffsetImm = getNamedOperand(*LdSt,
269 AMDGPU::OpName::offset);
270 BaseReg = AddrReg->getReg();
271 Offset = OffsetImm->getImm();
276 const MachineOperand *OffsetImm = getNamedOperand(*LdSt,
277 AMDGPU::OpName::offset);
281 const MachineOperand *SBaseReg = getNamedOperand(*LdSt,
282 AMDGPU::OpName::sbase);
283 BaseReg = SBaseReg->getReg();
284 Offset = OffsetImm->getImm();
291 bool SIInstrInfo::shouldClusterLoads(MachineInstr *FirstLdSt,
292 MachineInstr *SecondLdSt,
293 unsigned NumLoads) const {
294 // TODO: This needs finer tuning
298 if (isDS(*FirstLdSt) && isDS(*SecondLdSt))
301 if (isSMRD(*FirstLdSt) && isSMRD(*SecondLdSt))
304 if ((isMUBUF(*FirstLdSt) || isMTBUF(*FirstLdSt)) &&
305 (isMUBUF(*SecondLdSt) || isMTBUF(*SecondLdSt)))
312 SIInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
313 MachineBasicBlock::iterator MI, DebugLoc DL,
314 unsigned DestReg, unsigned SrcReg,
315 bool KillSrc) const {
317 // If we are trying to copy to or from SCC, there is a bug somewhere else in
318 // the backend. While it may be theoretically possible to do this, it should
319 // never be necessary.
320 assert(DestReg != AMDGPU::SCC && SrcReg != AMDGPU::SCC);
322 static const int16_t Sub0_15[] = {
323 AMDGPU::sub0, AMDGPU::sub1, AMDGPU::sub2, AMDGPU::sub3,
324 AMDGPU::sub4, AMDGPU::sub5, AMDGPU::sub6, AMDGPU::sub7,
325 AMDGPU::sub8, AMDGPU::sub9, AMDGPU::sub10, AMDGPU::sub11,
326 AMDGPU::sub12, AMDGPU::sub13, AMDGPU::sub14, AMDGPU::sub15,
329 static const int16_t Sub0_7[] = {
330 AMDGPU::sub0, AMDGPU::sub1, AMDGPU::sub2, AMDGPU::sub3,
331 AMDGPU::sub4, AMDGPU::sub5, AMDGPU::sub6, AMDGPU::sub7,
334 static const int16_t Sub0_3[] = {
335 AMDGPU::sub0, AMDGPU::sub1, AMDGPU::sub2, AMDGPU::sub3,
338 static const int16_t Sub0_2[] = {
339 AMDGPU::sub0, AMDGPU::sub1, AMDGPU::sub2,
342 static const int16_t Sub0_1[] = {
343 AMDGPU::sub0, AMDGPU::sub1,
347 ArrayRef<int16_t> SubIndices;
350 if (AMDGPU::SReg_32RegClass.contains(DestReg)) {
351 assert(AMDGPU::SReg_32RegClass.contains(SrcReg));
352 BuildMI(MBB, MI, DL, get(AMDGPU::S_MOV_B32), DestReg)
353 .addReg(SrcReg, getKillRegState(KillSrc));
356 } else if (AMDGPU::SReg_64RegClass.contains(DestReg)) {
357 if (DestReg == AMDGPU::VCC) {
358 if (AMDGPU::SReg_64RegClass.contains(SrcReg)) {
359 BuildMI(MBB, MI, DL, get(AMDGPU::S_MOV_B64), AMDGPU::VCC)
360 .addReg(SrcReg, getKillRegState(KillSrc));
362 // FIXME: Hack until VReg_1 removed.
363 assert(AMDGPU::VGPR_32RegClass.contains(SrcReg));
364 BuildMI(MBB, MI, DL, get(AMDGPU::V_CMP_NE_I32_e32))
366 .addReg(SrcReg, getKillRegState(KillSrc));
372 assert(AMDGPU::SReg_64RegClass.contains(SrcReg));
373 BuildMI(MBB, MI, DL, get(AMDGPU::S_MOV_B64), DestReg)
374 .addReg(SrcReg, getKillRegState(KillSrc));
377 } else if (AMDGPU::SReg_128RegClass.contains(DestReg)) {
378 assert(AMDGPU::SReg_128RegClass.contains(SrcReg));
379 Opcode = AMDGPU::S_MOV_B32;
382 } else if (AMDGPU::SReg_256RegClass.contains(DestReg)) {
383 assert(AMDGPU::SReg_256RegClass.contains(SrcReg));
384 Opcode = AMDGPU::S_MOV_B32;
387 } else if (AMDGPU::SReg_512RegClass.contains(DestReg)) {
388 assert(AMDGPU::SReg_512RegClass.contains(SrcReg));
389 Opcode = AMDGPU::S_MOV_B32;
390 SubIndices = Sub0_15;
392 } else if (AMDGPU::VGPR_32RegClass.contains(DestReg)) {
393 assert(AMDGPU::VGPR_32RegClass.contains(SrcReg) ||
394 AMDGPU::SReg_32RegClass.contains(SrcReg));
395 BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), DestReg)
396 .addReg(SrcReg, getKillRegState(KillSrc));
399 } else if (AMDGPU::VReg_64RegClass.contains(DestReg)) {
400 assert(AMDGPU::VReg_64RegClass.contains(SrcReg) ||
401 AMDGPU::SReg_64RegClass.contains(SrcReg));
402 Opcode = AMDGPU::V_MOV_B32_e32;
405 } else if (AMDGPU::VReg_96RegClass.contains(DestReg)) {
406 assert(AMDGPU::VReg_96RegClass.contains(SrcReg));
407 Opcode = AMDGPU::V_MOV_B32_e32;
410 } else if (AMDGPU::VReg_128RegClass.contains(DestReg)) {
411 assert(AMDGPU::VReg_128RegClass.contains(SrcReg) ||
412 AMDGPU::SReg_128RegClass.contains(SrcReg));
413 Opcode = AMDGPU::V_MOV_B32_e32;
416 } else if (AMDGPU::VReg_256RegClass.contains(DestReg)) {
417 assert(AMDGPU::VReg_256RegClass.contains(SrcReg) ||
418 AMDGPU::SReg_256RegClass.contains(SrcReg));
419 Opcode = AMDGPU::V_MOV_B32_e32;
422 } else if (AMDGPU::VReg_512RegClass.contains(DestReg)) {
423 assert(AMDGPU::VReg_512RegClass.contains(SrcReg) ||
424 AMDGPU::SReg_512RegClass.contains(SrcReg));
425 Opcode = AMDGPU::V_MOV_B32_e32;
426 SubIndices = Sub0_15;
429 llvm_unreachable("Can't copy register!");
432 if (RI.getHWRegIndex(DestReg) <= RI.getHWRegIndex(SrcReg))
437 for (unsigned Idx = 0; Idx < SubIndices.size(); ++Idx) {
440 SubIdx = SubIndices[Idx];
442 SubIdx = SubIndices[SubIndices.size() - Idx - 1];
444 MachineInstrBuilder Builder = BuildMI(MBB, MI, DL,
445 get(Opcode), RI.getSubReg(DestReg, SubIdx));
447 Builder.addReg(RI.getSubReg(SrcReg, SubIdx));
449 if (Idx == SubIndices.size() - 1)
450 Builder.addReg(SrcReg, RegState::Kill | RegState::Implicit);
453 Builder.addReg(DestReg, RegState::Define | RegState::Implicit);
457 int SIInstrInfo::commuteOpcode(const MachineInstr &MI) const {
458 const unsigned Opcode = MI.getOpcode();
462 // Try to map original to commuted opcode
463 NewOpc = AMDGPU::getCommuteRev(Opcode);
465 // Check if the commuted (REV) opcode exists on the target.
466 return pseudoToMCOpcode(NewOpc) != -1 ? NewOpc : -1;
468 // Try to map commuted to original opcode
469 NewOpc = AMDGPU::getCommuteOrig(Opcode);
471 // Check if the original (non-REV) opcode exists on the target.
472 return pseudoToMCOpcode(NewOpc) != -1 ? NewOpc : -1;
477 unsigned SIInstrInfo::getMovOpcode(const TargetRegisterClass *DstRC) const {
479 if (DstRC->getSize() == 4) {
480 return RI.isSGPRClass(DstRC) ? AMDGPU::S_MOV_B32 : AMDGPU::V_MOV_B32_e32;
481 } else if (DstRC->getSize() == 8 && RI.isSGPRClass(DstRC)) {
482 return AMDGPU::S_MOV_B64;
483 } else if (DstRC->getSize() == 8 && !RI.isSGPRClass(DstRC)) {
484 return AMDGPU::V_MOV_B64_PSEUDO;
489 static unsigned getSGPRSpillSaveOpcode(unsigned Size) {
492 return AMDGPU::SI_SPILL_S32_SAVE;
494 return AMDGPU::SI_SPILL_S64_SAVE;
496 return AMDGPU::SI_SPILL_S128_SAVE;
498 return AMDGPU::SI_SPILL_S256_SAVE;
500 return AMDGPU::SI_SPILL_S512_SAVE;
502 llvm_unreachable("unknown register size");
506 static unsigned getVGPRSpillSaveOpcode(unsigned Size) {
509 return AMDGPU::SI_SPILL_V32_SAVE;
511 return AMDGPU::SI_SPILL_V64_SAVE;
513 return AMDGPU::SI_SPILL_V128_SAVE;
515 return AMDGPU::SI_SPILL_V256_SAVE;
517 return AMDGPU::SI_SPILL_V512_SAVE;
519 llvm_unreachable("unknown register size");
523 void SIInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
524 MachineBasicBlock::iterator MI,
525 unsigned SrcReg, bool isKill,
527 const TargetRegisterClass *RC,
528 const TargetRegisterInfo *TRI) const {
529 MachineFunction *MF = MBB.getParent();
530 SIMachineFunctionInfo *MFI = MF->getInfo<SIMachineFunctionInfo>();
531 MachineFrameInfo *FrameInfo = MF->getFrameInfo();
532 DebugLoc DL = MBB.findDebugLoc(MI);
534 unsigned Size = FrameInfo->getObjectSize(FrameIndex);
535 unsigned Align = FrameInfo->getObjectAlignment(FrameIndex);
536 MachinePointerInfo PtrInfo
537 = MachinePointerInfo::getFixedStack(*MF, FrameIndex);
538 MachineMemOperand *MMO
539 = MF->getMachineMemOperand(PtrInfo, MachineMemOperand::MOStore,
542 if (RI.isSGPRClass(RC)) {
543 MFI->setHasSpilledSGPRs();
545 // We are only allowed to create one new instruction when spilling
546 // registers, so we need to use pseudo instruction for spilling
548 unsigned Opcode = getSGPRSpillSaveOpcode(RC->getSize());
549 BuildMI(MBB, MI, DL, get(Opcode))
550 .addReg(SrcReg) // src
551 .addFrameIndex(FrameIndex) // frame_idx
557 if (!ST.isVGPRSpillingEnabled(MFI)) {
558 LLVMContext &Ctx = MF->getFunction()->getContext();
559 Ctx.emitError("SIInstrInfo::storeRegToStackSlot - Do not know how to"
561 BuildMI(MBB, MI, DL, get(AMDGPU::KILL))
567 assert(RI.hasVGPRs(RC) && "Only VGPR spilling expected");
569 unsigned Opcode = getVGPRSpillSaveOpcode(RC->getSize());
570 MFI->setHasSpilledVGPRs();
571 BuildMI(MBB, MI, DL, get(Opcode))
572 .addReg(SrcReg) // src
573 .addFrameIndex(FrameIndex) // frame_idx
574 .addReg(MFI->getScratchRSrcReg()) // scratch_rsrc
575 .addReg(MFI->getScratchWaveOffsetReg()) // scratch_offset
579 static unsigned getSGPRSpillRestoreOpcode(unsigned Size) {
582 return AMDGPU::SI_SPILL_S32_RESTORE;
584 return AMDGPU::SI_SPILL_S64_RESTORE;
586 return AMDGPU::SI_SPILL_S128_RESTORE;
588 return AMDGPU::SI_SPILL_S256_RESTORE;
590 return AMDGPU::SI_SPILL_S512_RESTORE;
592 llvm_unreachable("unknown register size");
596 static unsigned getVGPRSpillRestoreOpcode(unsigned Size) {
599 return AMDGPU::SI_SPILL_V32_RESTORE;
601 return AMDGPU::SI_SPILL_V64_RESTORE;
603 return AMDGPU::SI_SPILL_V128_RESTORE;
605 return AMDGPU::SI_SPILL_V256_RESTORE;
607 return AMDGPU::SI_SPILL_V512_RESTORE;
609 llvm_unreachable("unknown register size");
613 void SIInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
614 MachineBasicBlock::iterator MI,
615 unsigned DestReg, int FrameIndex,
616 const TargetRegisterClass *RC,
617 const TargetRegisterInfo *TRI) const {
618 MachineFunction *MF = MBB.getParent();
619 const SIMachineFunctionInfo *MFI = MF->getInfo<SIMachineFunctionInfo>();
620 MachineFrameInfo *FrameInfo = MF->getFrameInfo();
621 DebugLoc DL = MBB.findDebugLoc(MI);
622 unsigned Align = FrameInfo->getObjectAlignment(FrameIndex);
623 unsigned Size = FrameInfo->getObjectSize(FrameIndex);
625 MachinePointerInfo PtrInfo
626 = MachinePointerInfo::getFixedStack(*MF, FrameIndex);
628 MachineMemOperand *MMO = MF->getMachineMemOperand(
629 PtrInfo, MachineMemOperand::MOLoad, Size, Align);
631 if (RI.isSGPRClass(RC)) {
632 // FIXME: Maybe this should not include a memoperand because it will be
633 // lowered to non-memory instructions.
634 unsigned Opcode = getSGPRSpillRestoreOpcode(RC->getSize());
635 BuildMI(MBB, MI, DL, get(Opcode), DestReg)
636 .addFrameIndex(FrameIndex) // frame_idx
642 if (!ST.isVGPRSpillingEnabled(MFI)) {
643 LLVMContext &Ctx = MF->getFunction()->getContext();
644 Ctx.emitError("SIInstrInfo::loadRegFromStackSlot - Do not know how to"
645 " restore register");
646 BuildMI(MBB, MI, DL, get(AMDGPU::IMPLICIT_DEF), DestReg);
651 assert(RI.hasVGPRs(RC) && "Only VGPR spilling expected");
653 unsigned Opcode = getVGPRSpillRestoreOpcode(RC->getSize());
654 BuildMI(MBB, MI, DL, get(Opcode), DestReg)
655 .addFrameIndex(FrameIndex) // frame_idx
656 .addReg(MFI->getScratchRSrcReg()) // scratch_rsrc
657 .addReg(MFI->getScratchWaveOffsetReg()) // scratch_offset
661 /// \param @Offset Offset in bytes of the FrameIndex being spilled
662 unsigned SIInstrInfo::calculateLDSSpillAddress(MachineBasicBlock &MBB,
663 MachineBasicBlock::iterator MI,
664 RegScavenger *RS, unsigned TmpReg,
665 unsigned FrameOffset,
666 unsigned Size) const {
667 MachineFunction *MF = MBB.getParent();
668 SIMachineFunctionInfo *MFI = MF->getInfo<SIMachineFunctionInfo>();
669 const AMDGPUSubtarget &ST = MF->getSubtarget<AMDGPUSubtarget>();
670 const SIRegisterInfo *TRI =
671 static_cast<const SIRegisterInfo*>(ST.getRegisterInfo());
672 DebugLoc DL = MBB.findDebugLoc(MI);
673 unsigned WorkGroupSize = MFI->getMaximumWorkGroupSize(*MF);
674 unsigned WavefrontSize = ST.getWavefrontSize();
676 unsigned TIDReg = MFI->getTIDReg();
677 if (!MFI->hasCalculatedTID()) {
678 MachineBasicBlock &Entry = MBB.getParent()->front();
679 MachineBasicBlock::iterator Insert = Entry.front();
680 DebugLoc DL = Insert->getDebugLoc();
682 TIDReg = RI.findUnusedRegister(MF->getRegInfo(), &AMDGPU::VGPR_32RegClass);
683 if (TIDReg == AMDGPU::NoRegister)
687 if (MFI->getShaderType() == ShaderType::COMPUTE &&
688 WorkGroupSize > WavefrontSize) {
691 = TRI->getPreloadedValue(*MF, SIRegisterInfo::WORKGROUP_ID_X);
693 = TRI->getPreloadedValue(*MF, SIRegisterInfo::WORKGROUP_ID_Y);
695 = TRI->getPreloadedValue(*MF, SIRegisterInfo::WORKGROUP_ID_Z);
696 unsigned InputPtrReg =
697 TRI->getPreloadedValue(*MF, SIRegisterInfo::KERNARG_SEGMENT_PTR);
698 for (unsigned Reg : {TIDIGXReg, TIDIGYReg, TIDIGZReg}) {
699 if (!Entry.isLiveIn(Reg))
700 Entry.addLiveIn(Reg);
703 RS->enterBasicBlock(&Entry);
704 // FIXME: Can we scavenge an SReg_64 and access the subregs?
705 unsigned STmp0 = RS->scavengeRegister(&AMDGPU::SGPR_32RegClass, 0);
706 unsigned STmp1 = RS->scavengeRegister(&AMDGPU::SGPR_32RegClass, 0);
707 BuildMI(Entry, Insert, DL, get(AMDGPU::S_LOAD_DWORD_IMM), STmp0)
709 .addImm(SI::KernelInputOffsets::NGROUPS_Z);
710 BuildMI(Entry, Insert, DL, get(AMDGPU::S_LOAD_DWORD_IMM), STmp1)
712 .addImm(SI::KernelInputOffsets::NGROUPS_Y);
714 // NGROUPS.X * NGROUPS.Y
715 BuildMI(Entry, Insert, DL, get(AMDGPU::S_MUL_I32), STmp1)
718 // (NGROUPS.X * NGROUPS.Y) * TIDIG.X
719 BuildMI(Entry, Insert, DL, get(AMDGPU::V_MUL_U32_U24_e32), TIDReg)
722 // NGROUPS.Z * TIDIG.Y + (NGROUPS.X * NGROPUS.Y * TIDIG.X)
723 BuildMI(Entry, Insert, DL, get(AMDGPU::V_MAD_U32_U24), TIDReg)
727 // (NGROUPS.Z * TIDIG.Y + (NGROUPS.X * NGROPUS.Y * TIDIG.X)) + TIDIG.Z
728 BuildMI(Entry, Insert, DL, get(AMDGPU::V_ADD_I32_e32), TIDReg)
733 BuildMI(Entry, Insert, DL, get(AMDGPU::V_MBCNT_LO_U32_B32_e64),
738 BuildMI(Entry, Insert, DL, get(AMDGPU::V_MBCNT_HI_U32_B32_e64),
744 BuildMI(Entry, Insert, DL, get(AMDGPU::V_LSHLREV_B32_e32),
748 MFI->setTIDReg(TIDReg);
751 // Add FrameIndex to LDS offset
752 unsigned LDSOffset = MFI->LDSSize + (FrameOffset * WorkGroupSize);
753 BuildMI(MBB, MI, DL, get(AMDGPU::V_ADD_I32_e32), TmpReg)
760 void SIInstrInfo::insertWaitStates(MachineBasicBlock::iterator MI,
769 BuildMI(*MI->getParent(), MI, MI->getDebugLoc(), get(AMDGPU::S_NOP))
774 bool SIInstrInfo::expandPostRAPseudo(MachineBasicBlock::iterator MI) const {
775 MachineBasicBlock &MBB = *MI->getParent();
776 DebugLoc DL = MBB.findDebugLoc(MI);
777 switch (MI->getOpcode()) {
778 default: return AMDGPUInstrInfo::expandPostRAPseudo(MI);
780 case AMDGPU::SGPR_USE:
781 // This is just a placeholder for register allocation.
782 MI->eraseFromParent();
785 case AMDGPU::V_MOV_B64_PSEUDO: {
786 unsigned Dst = MI->getOperand(0).getReg();
787 unsigned DstLo = RI.getSubReg(Dst, AMDGPU::sub0);
788 unsigned DstHi = RI.getSubReg(Dst, AMDGPU::sub1);
790 const MachineOperand &SrcOp = MI->getOperand(1);
791 // FIXME: Will this work for 64-bit floating point immediates?
792 assert(!SrcOp.isFPImm());
794 APInt Imm(64, SrcOp.getImm());
795 BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), DstLo)
796 .addImm(Imm.getLoBits(32).getZExtValue())
797 .addReg(Dst, RegState::Implicit);
798 BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), DstHi)
799 .addImm(Imm.getHiBits(32).getZExtValue())
800 .addReg(Dst, RegState::Implicit);
802 assert(SrcOp.isReg());
803 BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), DstLo)
804 .addReg(RI.getSubReg(SrcOp.getReg(), AMDGPU::sub0))
805 .addReg(Dst, RegState::Implicit);
806 BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), DstHi)
807 .addReg(RI.getSubReg(SrcOp.getReg(), AMDGPU::sub1))
808 .addReg(Dst, RegState::Implicit);
810 MI->eraseFromParent();
814 case AMDGPU::V_CNDMASK_B64_PSEUDO: {
815 unsigned Dst = MI->getOperand(0).getReg();
816 unsigned DstLo = RI.getSubReg(Dst, AMDGPU::sub0);
817 unsigned DstHi = RI.getSubReg(Dst, AMDGPU::sub1);
818 unsigned Src0 = MI->getOperand(1).getReg();
819 unsigned Src1 = MI->getOperand(2).getReg();
820 const MachineOperand &SrcCond = MI->getOperand(3);
822 BuildMI(MBB, MI, DL, get(AMDGPU::V_CNDMASK_B32_e64), DstLo)
823 .addReg(RI.getSubReg(Src0, AMDGPU::sub0))
824 .addReg(RI.getSubReg(Src1, AMDGPU::sub0))
825 .addOperand(SrcCond);
826 BuildMI(MBB, MI, DL, get(AMDGPU::V_CNDMASK_B32_e64), DstHi)
827 .addReg(RI.getSubReg(Src0, AMDGPU::sub1))
828 .addReg(RI.getSubReg(Src1, AMDGPU::sub1))
829 .addOperand(SrcCond);
830 MI->eraseFromParent();
834 case AMDGPU::SI_CONSTDATA_PTR: {
835 const SIRegisterInfo *TRI =
836 static_cast<const SIRegisterInfo *>(ST.getRegisterInfo());
837 MachineFunction &MF = *MBB.getParent();
838 unsigned Reg = MI->getOperand(0).getReg();
839 unsigned RegLo = TRI->getSubReg(Reg, AMDGPU::sub0);
840 unsigned RegHi = TRI->getSubReg(Reg, AMDGPU::sub1);
842 // Create a bundle so these instructions won't be re-ordered by the
843 // post-RA scheduler.
844 MIBundleBuilder Bundler(MBB, MI);
845 Bundler.append(BuildMI(MF, DL, get(AMDGPU::S_GETPC_B64), Reg));
847 // Add 32-bit offset from this instruction to the start of the
849 Bundler.append(BuildMI(MF, DL, get(AMDGPU::S_ADD_U32), RegLo)
851 .addOperand(MI->getOperand(1)));
852 Bundler.append(BuildMI(MF, DL, get(AMDGPU::S_ADDC_U32), RegHi)
856 llvm::finalizeBundle(MBB, Bundler.begin());
858 MI->eraseFromParent();
865 /// Commutes the operands in the given instruction.
866 /// The commutable operands are specified by their indices OpIdx0 and OpIdx1.
868 /// Do not call this method for a non-commutable instruction or for
869 /// non-commutable pair of operand indices OpIdx0 and OpIdx1.
870 /// Even though the instruction is commutable, the method may still
871 /// fail to commute the operands, null pointer is returned in such cases.
872 MachineInstr *SIInstrInfo::commuteInstructionImpl(MachineInstr *MI,
875 unsigned OpIdx1) const {
876 int CommutedOpcode = commuteOpcode(*MI);
877 if (CommutedOpcode == -1)
880 int Src0Idx = AMDGPU::getNamedOperandIdx(MI->getOpcode(),
881 AMDGPU::OpName::src0);
882 MachineOperand &Src0 = MI->getOperand(Src0Idx);
886 int Src1Idx = AMDGPU::getNamedOperandIdx(MI->getOpcode(),
887 AMDGPU::OpName::src1);
889 if ((OpIdx0 != static_cast<unsigned>(Src0Idx) ||
890 OpIdx1 != static_cast<unsigned>(Src1Idx)) &&
891 (OpIdx0 != static_cast<unsigned>(Src1Idx) ||
892 OpIdx1 != static_cast<unsigned>(Src0Idx)))
895 MachineOperand &Src1 = MI->getOperand(Src1Idx);
899 const MCInstrDesc &InstrDesc = MI->getDesc();
900 // For VOP2 instructions, any operand type is valid to use for src0. Make
901 // sure we can use the src1 as src0.
903 // We could be stricter here and only allow commuting if there is a reason
904 // to do so. i.e. if both operands are VGPRs there is no real benefit,
905 // although MachineCSE attempts to find matches by commuting.
906 const MachineRegisterInfo &MRI = MI->getParent()->getParent()->getRegInfo();
907 if (!isLegalRegOperand(MRI, InstrDesc.OpInfo[Src1Idx], Src0))
912 // Allow commuting instructions with Imm operands.
913 if (NewMI || !Src1.isImm() ||
914 (!isVOP2(*MI) && !isVOP3(*MI))) {
917 // Be sure to copy the source modifiers to the right place.
918 if (MachineOperand *Src0Mods
919 = getNamedOperand(*MI, AMDGPU::OpName::src0_modifiers)) {
920 MachineOperand *Src1Mods
921 = getNamedOperand(*MI, AMDGPU::OpName::src1_modifiers);
923 int Src0ModsVal = Src0Mods->getImm();
924 if (!Src1Mods && Src0ModsVal != 0)
927 // XXX - This assert might be a lie. It might be useful to have a neg
928 // modifier with 0.0.
929 int Src1ModsVal = Src1Mods->getImm();
930 assert((Src1ModsVal == 0) && "Not expecting modifiers with immediates");
932 Src1Mods->setImm(Src0ModsVal);
933 Src0Mods->setImm(Src1ModsVal);
936 unsigned Reg = Src0.getReg();
937 unsigned SubReg = Src0.getSubReg();
939 Src0.ChangeToImmediate(Src1.getImm());
941 llvm_unreachable("Should only have immediates");
943 Src1.ChangeToRegister(Reg, false);
944 Src1.setSubReg(SubReg);
946 MI = TargetInstrInfo::commuteInstructionImpl(MI, NewMI, OpIdx0, OpIdx1);
950 MI->setDesc(get(CommutedOpcode));
955 // This needs to be implemented because the source modifiers may be inserted
956 // between the true commutable operands, and the base
957 // TargetInstrInfo::commuteInstruction uses it.
958 bool SIInstrInfo::findCommutedOpIndices(MachineInstr *MI,
960 unsigned &SrcOpIdx1) const {
961 const MCInstrDesc &MCID = MI->getDesc();
962 if (!MCID.isCommutable())
965 unsigned Opc = MI->getOpcode();
966 int Src0Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src0);
970 // FIXME: Workaround TargetInstrInfo::commuteInstruction asserting on
971 // immediate. Also, immediate src0 operand is not handled in
972 // SIInstrInfo::commuteInstruction();
973 if (!MI->getOperand(Src0Idx).isReg())
976 int Src1Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src1);
980 MachineOperand &Src1 = MI->getOperand(Src1Idx);
982 // SIInstrInfo::commuteInstruction() does support commuting the immediate
983 // operand src1 in 2 and 3 operand instructions.
984 if (!isVOP2(MI->getOpcode()) && !isVOP3(MI->getOpcode()))
986 } else if (Src1.isReg()) {
987 // If any source modifiers are set, the generic instruction commuting won't
988 // understand how to copy the source modifiers.
989 if (hasModifiersSet(*MI, AMDGPU::OpName::src0_modifiers) ||
990 hasModifiersSet(*MI, AMDGPU::OpName::src1_modifiers))
995 return fixCommutedOpIndices(SrcOpIdx0, SrcOpIdx1, Src0Idx, Src1Idx);
998 MachineInstr *SIInstrInfo::buildMovInstr(MachineBasicBlock *MBB,
999 MachineBasicBlock::iterator I,
1001 unsigned SrcReg) const {
1002 return BuildMI(*MBB, I, MBB->findDebugLoc(I), get(AMDGPU::V_MOV_B32_e32),
1003 DstReg) .addReg(SrcReg);
1006 bool SIInstrInfo::isMov(unsigned Opcode) const {
1008 default: return false;
1009 case AMDGPU::S_MOV_B32:
1010 case AMDGPU::S_MOV_B64:
1011 case AMDGPU::V_MOV_B32_e32:
1012 case AMDGPU::V_MOV_B32_e64:
1017 static void removeModOperands(MachineInstr &MI) {
1018 unsigned Opc = MI.getOpcode();
1019 int Src0ModIdx = AMDGPU::getNamedOperandIdx(Opc,
1020 AMDGPU::OpName::src0_modifiers);
1021 int Src1ModIdx = AMDGPU::getNamedOperandIdx(Opc,
1022 AMDGPU::OpName::src1_modifiers);
1023 int Src2ModIdx = AMDGPU::getNamedOperandIdx(Opc,
1024 AMDGPU::OpName::src2_modifiers);
1026 MI.RemoveOperand(Src2ModIdx);
1027 MI.RemoveOperand(Src1ModIdx);
1028 MI.RemoveOperand(Src0ModIdx);
1031 bool SIInstrInfo::FoldImmediate(MachineInstr *UseMI, MachineInstr *DefMI,
1032 unsigned Reg, MachineRegisterInfo *MRI) const {
1033 if (!MRI->hasOneNonDBGUse(Reg))
1036 unsigned Opc = UseMI->getOpcode();
1037 if (Opc == AMDGPU::V_MAD_F32 || Opc == AMDGPU::V_MAC_F32_e64) {
1038 // Don't fold if we are using source modifiers. The new VOP2 instructions
1040 if (hasModifiersSet(*UseMI, AMDGPU::OpName::src0_modifiers) ||
1041 hasModifiersSet(*UseMI, AMDGPU::OpName::src1_modifiers) ||
1042 hasModifiersSet(*UseMI, AMDGPU::OpName::src2_modifiers)) {
1046 MachineOperand *Src0 = getNamedOperand(*UseMI, AMDGPU::OpName::src0);
1047 MachineOperand *Src1 = getNamedOperand(*UseMI, AMDGPU::OpName::src1);
1048 MachineOperand *Src2 = getNamedOperand(*UseMI, AMDGPU::OpName::src2);
1050 // Multiplied part is the constant: Use v_madmk_f32
1051 // We should only expect these to be on src0 due to canonicalizations.
1052 if (Src0->isReg() && Src0->getReg() == Reg) {
1053 if (!Src1->isReg() ||
1054 (Src1->isReg() && RI.isSGPRClass(MRI->getRegClass(Src1->getReg()))))
1057 if (!Src2->isReg() ||
1058 (Src2->isReg() && RI.isSGPRClass(MRI->getRegClass(Src2->getReg()))))
1061 // We need to do some weird looking operand shuffling since the madmk
1062 // operands are out of the normal expected order with the multiplied
1063 // constant as the last operand.
1065 // v_mad_f32 src0, src1, src2 -> v_madmk_f32 src0 * src2K + src1
1070 const int64_t Imm = DefMI->getOperand(1).getImm();
1072 // FIXME: This would be a lot easier if we could return a new instruction
1073 // instead of having to modify in place.
1075 // Remove these first since they are at the end.
1076 UseMI->RemoveOperand(AMDGPU::getNamedOperandIdx(Opc,
1077 AMDGPU::OpName::omod));
1078 UseMI->RemoveOperand(AMDGPU::getNamedOperandIdx(Opc,
1079 AMDGPU::OpName::clamp));
1081 unsigned Src1Reg = Src1->getReg();
1082 unsigned Src1SubReg = Src1->getSubReg();
1083 unsigned Src2Reg = Src2->getReg();
1084 unsigned Src2SubReg = Src2->getSubReg();
1085 Src0->setReg(Src1Reg);
1086 Src0->setSubReg(Src1SubReg);
1087 Src0->setIsKill(Src1->isKill());
1089 Src1->setReg(Src2Reg);
1090 Src1->setSubReg(Src2SubReg);
1091 Src1->setIsKill(Src2->isKill());
1093 if (Opc == AMDGPU::V_MAC_F32_e64) {
1094 UseMI->untieRegOperand(
1095 AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src2));
1098 Src2->ChangeToImmediate(Imm);
1100 removeModOperands(*UseMI);
1101 UseMI->setDesc(get(AMDGPU::V_MADMK_F32));
1103 bool DeleteDef = MRI->hasOneNonDBGUse(Reg);
1105 DefMI->eraseFromParent();
1110 // Added part is the constant: Use v_madak_f32
1111 if (Src2->isReg() && Src2->getReg() == Reg) {
1112 // Not allowed to use constant bus for another operand.
1113 // We can however allow an inline immediate as src0.
1114 if (!Src0->isImm() &&
1115 (Src0->isReg() && RI.isSGPRClass(MRI->getRegClass(Src0->getReg()))))
1118 if (!Src1->isReg() ||
1119 (Src1->isReg() && RI.isSGPRClass(MRI->getRegClass(Src1->getReg()))))
1122 const int64_t Imm = DefMI->getOperand(1).getImm();
1124 // FIXME: This would be a lot easier if we could return a new instruction
1125 // instead of having to modify in place.
1127 // Remove these first since they are at the end.
1128 UseMI->RemoveOperand(AMDGPU::getNamedOperandIdx(Opc,
1129 AMDGPU::OpName::omod));
1130 UseMI->RemoveOperand(AMDGPU::getNamedOperandIdx(Opc,
1131 AMDGPU::OpName::clamp));
1133 if (Opc == AMDGPU::V_MAC_F32_e64) {
1134 UseMI->untieRegOperand(
1135 AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src2));
1138 // ChangingToImmediate adds Src2 back to the instruction.
1139 Src2->ChangeToImmediate(Imm);
1141 // These come before src2.
1142 removeModOperands(*UseMI);
1143 UseMI->setDesc(get(AMDGPU::V_MADAK_F32));
1145 bool DeleteDef = MRI->hasOneNonDBGUse(Reg);
1147 DefMI->eraseFromParent();
1156 static bool offsetsDoNotOverlap(int WidthA, int OffsetA,
1157 int WidthB, int OffsetB) {
1158 int LowOffset = OffsetA < OffsetB ? OffsetA : OffsetB;
1159 int HighOffset = OffsetA < OffsetB ? OffsetB : OffsetA;
1160 int LowWidth = (LowOffset == OffsetA) ? WidthA : WidthB;
1161 return LowOffset + LowWidth <= HighOffset;
1164 bool SIInstrInfo::checkInstOffsetsDoNotOverlap(MachineInstr *MIa,
1165 MachineInstr *MIb) const {
1166 unsigned BaseReg0, Offset0;
1167 unsigned BaseReg1, Offset1;
1169 if (getMemOpBaseRegImmOfs(MIa, BaseReg0, Offset0, &RI) &&
1170 getMemOpBaseRegImmOfs(MIb, BaseReg1, Offset1, &RI)) {
1171 assert(MIa->hasOneMemOperand() && MIb->hasOneMemOperand() &&
1172 "read2 / write2 not expected here yet");
1173 unsigned Width0 = (*MIa->memoperands_begin())->getSize();
1174 unsigned Width1 = (*MIb->memoperands_begin())->getSize();
1175 if (BaseReg0 == BaseReg1 &&
1176 offsetsDoNotOverlap(Width0, Offset0, Width1, Offset1)) {
1184 bool SIInstrInfo::areMemAccessesTriviallyDisjoint(MachineInstr *MIa,
1186 AliasAnalysis *AA) const {
1187 assert(MIa && (MIa->mayLoad() || MIa->mayStore()) &&
1188 "MIa must load from or modify a memory location");
1189 assert(MIb && (MIb->mayLoad() || MIb->mayStore()) &&
1190 "MIb must load from or modify a memory location");
1192 if (MIa->hasUnmodeledSideEffects() || MIb->hasUnmodeledSideEffects())
1195 // XXX - Can we relax this between address spaces?
1196 if (MIa->hasOrderedMemoryRef() || MIb->hasOrderedMemoryRef())
1199 // TODO: Should we check the address space from the MachineMemOperand? That
1200 // would allow us to distinguish objects we know don't alias based on the
1201 // underlying address space, even if it was lowered to a different one,
1202 // e.g. private accesses lowered to use MUBUF instructions on a scratch
1206 return checkInstOffsetsDoNotOverlap(MIa, MIb);
1208 return !isFLAT(*MIb);
1211 if (isMUBUF(*MIa) || isMTBUF(*MIa)) {
1212 if (isMUBUF(*MIb) || isMTBUF(*MIb))
1213 return checkInstOffsetsDoNotOverlap(MIa, MIb);
1215 return !isFLAT(*MIb) && !isSMRD(*MIb);
1220 return checkInstOffsetsDoNotOverlap(MIa, MIb);
1222 return !isFLAT(*MIb) && !isMUBUF(*MIa) && !isMTBUF(*MIa);
1227 return checkInstOffsetsDoNotOverlap(MIa, MIb);
1235 MachineInstr *SIInstrInfo::convertToThreeAddress(MachineFunction::iterator &MBB,
1236 MachineBasicBlock::iterator &MI,
1237 LiveVariables *LV) const {
1239 switch (MI->getOpcode()) {
1240 default: return nullptr;
1241 case AMDGPU::V_MAC_F32_e64: break;
1242 case AMDGPU::V_MAC_F32_e32: {
1243 const MachineOperand *Src0 = getNamedOperand(*MI, AMDGPU::OpName::src0);
1244 if (Src0->isImm() && !isInlineConstant(*Src0, 4))
1250 const MachineOperand *Dst = getNamedOperand(*MI, AMDGPU::OpName::dst);
1251 const MachineOperand *Src0 = getNamedOperand(*MI, AMDGPU::OpName::src0);
1252 const MachineOperand *Src1 = getNamedOperand(*MI, AMDGPU::OpName::src1);
1253 const MachineOperand *Src2 = getNamedOperand(*MI, AMDGPU::OpName::src2);
1255 return BuildMI(*MBB, MI, MI->getDebugLoc(), get(AMDGPU::V_MAD_F32))
1257 .addImm(0) // Src0 mods
1259 .addImm(0) // Src1 mods
1261 .addImm(0) // Src mods
1267 bool SIInstrInfo::isInlineConstant(const APInt &Imm) const {
1268 int64_t SVal = Imm.getSExtValue();
1269 if (SVal >= -16 && SVal <= 64)
1272 if (Imm.getBitWidth() == 64) {
1273 uint64_t Val = Imm.getZExtValue();
1274 return (DoubleToBits(0.0) == Val) ||
1275 (DoubleToBits(1.0) == Val) ||
1276 (DoubleToBits(-1.0) == Val) ||
1277 (DoubleToBits(0.5) == Val) ||
1278 (DoubleToBits(-0.5) == Val) ||
1279 (DoubleToBits(2.0) == Val) ||
1280 (DoubleToBits(-2.0) == Val) ||
1281 (DoubleToBits(4.0) == Val) ||
1282 (DoubleToBits(-4.0) == Val);
1285 // The actual type of the operand does not seem to matter as long
1286 // as the bits match one of the inline immediate values. For example:
1288 // -nan has the hexadecimal encoding of 0xfffffffe which is -2 in decimal,
1289 // so it is a legal inline immediate.
1291 // 1065353216 has the hexadecimal encoding 0x3f800000 which is 1.0f in
1292 // floating-point, so it is a legal inline immediate.
1293 uint32_t Val = Imm.getZExtValue();
1295 return (FloatToBits(0.0f) == Val) ||
1296 (FloatToBits(1.0f) == Val) ||
1297 (FloatToBits(-1.0f) == Val) ||
1298 (FloatToBits(0.5f) == Val) ||
1299 (FloatToBits(-0.5f) == Val) ||
1300 (FloatToBits(2.0f) == Val) ||
1301 (FloatToBits(-2.0f) == Val) ||
1302 (FloatToBits(4.0f) == Val) ||
1303 (FloatToBits(-4.0f) == Val);
1306 bool SIInstrInfo::isInlineConstant(const MachineOperand &MO,
1307 unsigned OpSize) const {
1309 // MachineOperand provides no way to tell the true operand size, since it
1310 // only records a 64-bit value. We need to know the size to determine if a
1311 // 32-bit floating point immediate bit pattern is legal for an integer
1312 // immediate. It would be for any 32-bit integer operand, but would not be
1313 // for a 64-bit one.
1315 unsigned BitSize = 8 * OpSize;
1316 return isInlineConstant(APInt(BitSize, MO.getImm(), true));
1322 bool SIInstrInfo::isLiteralConstant(const MachineOperand &MO,
1323 unsigned OpSize) const {
1324 return MO.isImm() && !isInlineConstant(MO, OpSize);
1327 static bool compareMachineOp(const MachineOperand &Op0,
1328 const MachineOperand &Op1) {
1329 if (Op0.getType() != Op1.getType())
1332 switch (Op0.getType()) {
1333 case MachineOperand::MO_Register:
1334 return Op0.getReg() == Op1.getReg();
1335 case MachineOperand::MO_Immediate:
1336 return Op0.getImm() == Op1.getImm();
1338 llvm_unreachable("Didn't expect to be comparing these operand types");
1342 bool SIInstrInfo::isImmOperandLegal(const MachineInstr *MI, unsigned OpNo,
1343 const MachineOperand &MO) const {
1344 const MCOperandInfo &OpInfo = get(MI->getOpcode()).OpInfo[OpNo];
1346 assert(MO.isImm() || MO.isTargetIndex() || MO.isFI());
1348 if (OpInfo.OperandType == MCOI::OPERAND_IMMEDIATE)
1351 if (OpInfo.RegClass < 0)
1354 unsigned OpSize = RI.getRegClass(OpInfo.RegClass)->getSize();
1355 if (isLiteralConstant(MO, OpSize))
1356 return RI.opCanUseLiteralConstant(OpInfo.OperandType);
1358 return RI.opCanUseInlineConstant(OpInfo.OperandType);
1361 bool SIInstrInfo::hasVALU32BitEncoding(unsigned Opcode) const {
1362 int Op32 = AMDGPU::getVOPe32(Opcode);
1366 return pseudoToMCOpcode(Op32) != -1;
1369 bool SIInstrInfo::hasModifiers(unsigned Opcode) const {
1370 // The src0_modifier operand is present on all instructions
1371 // that have modifiers.
1373 return AMDGPU::getNamedOperandIdx(Opcode,
1374 AMDGPU::OpName::src0_modifiers) != -1;
1377 bool SIInstrInfo::hasModifiersSet(const MachineInstr &MI,
1378 unsigned OpName) const {
1379 const MachineOperand *Mods = getNamedOperand(MI, OpName);
1380 return Mods && Mods->getImm();
1383 bool SIInstrInfo::usesConstantBus(const MachineRegisterInfo &MRI,
1384 const MachineOperand &MO,
1385 unsigned OpSize) const {
1386 // Literal constants use the constant bus.
1387 if (isLiteralConstant(MO, OpSize))
1390 if (!MO.isReg() || !MO.isUse())
1393 if (TargetRegisterInfo::isVirtualRegister(MO.getReg()))
1394 return RI.isSGPRClass(MRI.getRegClass(MO.getReg()));
1396 // FLAT_SCR is just an SGPR pair.
1397 if (!MO.isImplicit() && (MO.getReg() == AMDGPU::FLAT_SCR))
1400 // EXEC register uses the constant bus.
1401 if (!MO.isImplicit() && MO.getReg() == AMDGPU::EXEC)
1404 // SGPRs use the constant bus
1405 if (MO.getReg() == AMDGPU::M0 || MO.getReg() == AMDGPU::VCC ||
1406 (!MO.isImplicit() &&
1407 (AMDGPU::SGPR_32RegClass.contains(MO.getReg()) ||
1408 AMDGPU::SGPR_64RegClass.contains(MO.getReg())))) {
1415 static unsigned findImplicitSGPRRead(const MachineInstr &MI) {
1416 for (const MachineOperand &MO : MI.implicit_operands()) {
1417 // We only care about reads.
1421 switch (MO.getReg()) {
1424 case AMDGPU::FLAT_SCR:
1432 return AMDGPU::NoRegister;
1435 bool SIInstrInfo::verifyInstruction(const MachineInstr *MI,
1436 StringRef &ErrInfo) const {
1437 uint16_t Opcode = MI->getOpcode();
1438 const MachineRegisterInfo &MRI = MI->getParent()->getParent()->getRegInfo();
1439 int Src0Idx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src0);
1440 int Src1Idx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src1);
1441 int Src2Idx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src2);
1443 // Make sure the number of operands is correct.
1444 const MCInstrDesc &Desc = get(Opcode);
1445 if (!Desc.isVariadic() &&
1446 Desc.getNumOperands() != MI->getNumExplicitOperands()) {
1447 ErrInfo = "Instruction has wrong number of operands.";
1451 // Make sure the register classes are correct.
1452 for (int i = 0, e = Desc.getNumOperands(); i != e; ++i) {
1453 if (MI->getOperand(i).isFPImm()) {
1454 ErrInfo = "FPImm Machine Operands are not supported. ISel should bitcast "
1455 "all fp values to integers.";
1459 int RegClass = Desc.OpInfo[i].RegClass;
1461 switch (Desc.OpInfo[i].OperandType) {
1462 case MCOI::OPERAND_REGISTER:
1463 if (MI->getOperand(i).isImm()) {
1464 ErrInfo = "Illegal immediate value for operand.";
1468 case AMDGPU::OPERAND_REG_IMM32:
1470 case AMDGPU::OPERAND_REG_INLINE_C:
1471 if (isLiteralConstant(MI->getOperand(i),
1472 RI.getRegClass(RegClass)->getSize())) {
1473 ErrInfo = "Illegal immediate value for operand.";
1477 case MCOI::OPERAND_IMMEDIATE:
1478 // Check if this operand is an immediate.
1479 // FrameIndex operands will be replaced by immediates, so they are
1481 if (!MI->getOperand(i).isImm() && !MI->getOperand(i).isFI()) {
1482 ErrInfo = "Expected immediate, but got non-immediate";
1490 if (!MI->getOperand(i).isReg())
1493 if (RegClass != -1) {
1494 unsigned Reg = MI->getOperand(i).getReg();
1495 if (TargetRegisterInfo::isVirtualRegister(Reg))
1498 const TargetRegisterClass *RC = RI.getRegClass(RegClass);
1499 if (!RC->contains(Reg)) {
1500 ErrInfo = "Operand has incorrect register class.";
1508 if (isVOP1(*MI) || isVOP2(*MI) || isVOP3(*MI) || isVOPC(*MI)) {
1509 // Only look at the true operands. Only a real operand can use the constant
1510 // bus, and we don't want to check pseudo-operands like the source modifier
1512 const int OpIndices[] = { Src0Idx, Src1Idx, Src2Idx };
1514 unsigned ConstantBusCount = 0;
1515 unsigned SGPRUsed = findImplicitSGPRRead(*MI);
1516 if (SGPRUsed != AMDGPU::NoRegister)
1519 for (int OpIdx : OpIndices) {
1522 const MachineOperand &MO = MI->getOperand(OpIdx);
1523 if (usesConstantBus(MRI, MO, getOpSize(Opcode, OpIdx))) {
1525 if (MO.getReg() != SGPRUsed)
1527 SGPRUsed = MO.getReg();
1533 if (ConstantBusCount > 1) {
1534 ErrInfo = "VOP* instruction uses the constant bus more than once";
1539 // Verify misc. restrictions on specific instructions.
1540 if (Desc.getOpcode() == AMDGPU::V_DIV_SCALE_F32 ||
1541 Desc.getOpcode() == AMDGPU::V_DIV_SCALE_F64) {
1542 const MachineOperand &Src0 = MI->getOperand(Src0Idx);
1543 const MachineOperand &Src1 = MI->getOperand(Src1Idx);
1544 const MachineOperand &Src2 = MI->getOperand(Src2Idx);
1545 if (Src0.isReg() && Src1.isReg() && Src2.isReg()) {
1546 if (!compareMachineOp(Src0, Src1) &&
1547 !compareMachineOp(Src0, Src2)) {
1548 ErrInfo = "v_div_scale_{f32|f64} require src0 = src1 or src2";
1554 // Make sure we aren't losing exec uses in the td files. This mostly requires
1555 // being careful when using let Uses to try to add other use registers.
1556 if (!isGenericOpcode(Opcode) && !isSALU(Opcode) && !isSMRD(Opcode)) {
1557 const MachineOperand *Exec = MI->findRegisterUseOperand(AMDGPU::EXEC);
1558 if (!Exec || !Exec->isImplicit()) {
1559 ErrInfo = "VALU instruction does not implicitly read exec mask";
1567 unsigned SIInstrInfo::getVALUOp(const MachineInstr &MI) {
1568 switch (MI.getOpcode()) {
1569 default: return AMDGPU::INSTRUCTION_LIST_END;
1570 case AMDGPU::REG_SEQUENCE: return AMDGPU::REG_SEQUENCE;
1571 case AMDGPU::COPY: return AMDGPU::COPY;
1572 case AMDGPU::PHI: return AMDGPU::PHI;
1573 case AMDGPU::INSERT_SUBREG: return AMDGPU::INSERT_SUBREG;
1574 case AMDGPU::S_MOV_B32:
1575 return MI.getOperand(1).isReg() ?
1576 AMDGPU::COPY : AMDGPU::V_MOV_B32_e32;
1577 case AMDGPU::S_ADD_I32:
1578 case AMDGPU::S_ADD_U32: return AMDGPU::V_ADD_I32_e32;
1579 case AMDGPU::S_ADDC_U32: return AMDGPU::V_ADDC_U32_e32;
1580 case AMDGPU::S_SUB_I32:
1581 case AMDGPU::S_SUB_U32: return AMDGPU::V_SUB_I32_e32;
1582 case AMDGPU::S_SUBB_U32: return AMDGPU::V_SUBB_U32_e32;
1583 case AMDGPU::S_MUL_I32: return AMDGPU::V_MUL_LO_I32;
1584 case AMDGPU::S_AND_B32: return AMDGPU::V_AND_B32_e32;
1585 case AMDGPU::S_OR_B32: return AMDGPU::V_OR_B32_e32;
1586 case AMDGPU::S_XOR_B32: return AMDGPU::V_XOR_B32_e32;
1587 case AMDGPU::S_MIN_I32: return AMDGPU::V_MIN_I32_e32;
1588 case AMDGPU::S_MIN_U32: return AMDGPU::V_MIN_U32_e32;
1589 case AMDGPU::S_MAX_I32: return AMDGPU::V_MAX_I32_e32;
1590 case AMDGPU::S_MAX_U32: return AMDGPU::V_MAX_U32_e32;
1591 case AMDGPU::S_ASHR_I32: return AMDGPU::V_ASHR_I32_e32;
1592 case AMDGPU::S_ASHR_I64: return AMDGPU::V_ASHR_I64;
1593 case AMDGPU::S_LSHL_B32: return AMDGPU::V_LSHL_B32_e32;
1594 case AMDGPU::S_LSHL_B64: return AMDGPU::V_LSHL_B64;
1595 case AMDGPU::S_LSHR_B32: return AMDGPU::V_LSHR_B32_e32;
1596 case AMDGPU::S_LSHR_B64: return AMDGPU::V_LSHR_B64;
1597 case AMDGPU::S_SEXT_I32_I8: return AMDGPU::V_BFE_I32;
1598 case AMDGPU::S_SEXT_I32_I16: return AMDGPU::V_BFE_I32;
1599 case AMDGPU::S_BFE_U32: return AMDGPU::V_BFE_U32;
1600 case AMDGPU::S_BFE_I32: return AMDGPU::V_BFE_I32;
1601 case AMDGPU::S_BFM_B32: return AMDGPU::V_BFM_B32_e64;
1602 case AMDGPU::S_BREV_B32: return AMDGPU::V_BFREV_B32_e32;
1603 case AMDGPU::S_NOT_B32: return AMDGPU::V_NOT_B32_e32;
1604 case AMDGPU::S_NOT_B64: return AMDGPU::V_NOT_B32_e32;
1605 case AMDGPU::S_CMP_EQ_I32: return AMDGPU::V_CMP_EQ_I32_e32;
1606 case AMDGPU::S_CMP_LG_I32: return AMDGPU::V_CMP_NE_I32_e32;
1607 case AMDGPU::S_CMP_GT_I32: return AMDGPU::V_CMP_GT_I32_e32;
1608 case AMDGPU::S_CMP_GE_I32: return AMDGPU::V_CMP_GE_I32_e32;
1609 case AMDGPU::S_CMP_LT_I32: return AMDGPU::V_CMP_LT_I32_e32;
1610 case AMDGPU::S_CMP_LE_I32: return AMDGPU::V_CMP_LE_I32_e32;
1611 case AMDGPU::S_LOAD_DWORD_IMM:
1612 case AMDGPU::S_LOAD_DWORD_SGPR:
1613 case AMDGPU::S_LOAD_DWORD_IMM_ci:
1614 return AMDGPU::BUFFER_LOAD_DWORD_ADDR64;
1615 case AMDGPU::S_LOAD_DWORDX2_IMM:
1616 case AMDGPU::S_LOAD_DWORDX2_SGPR:
1617 case AMDGPU::S_LOAD_DWORDX2_IMM_ci:
1618 return AMDGPU::BUFFER_LOAD_DWORDX2_ADDR64;
1619 case AMDGPU::S_LOAD_DWORDX4_IMM:
1620 case AMDGPU::S_LOAD_DWORDX4_SGPR:
1621 case AMDGPU::S_LOAD_DWORDX4_IMM_ci:
1622 return AMDGPU::BUFFER_LOAD_DWORDX4_ADDR64;
1623 case AMDGPU::S_BCNT1_I32_B32: return AMDGPU::V_BCNT_U32_B32_e64;
1624 case AMDGPU::S_FF1_I32_B32: return AMDGPU::V_FFBL_B32_e32;
1625 case AMDGPU::S_FLBIT_I32_B32: return AMDGPU::V_FFBH_U32_e32;
1626 case AMDGPU::S_FLBIT_I32: return AMDGPU::V_FFBH_I32_e64;
1630 bool SIInstrInfo::isSALUOpSupportedOnVALU(const MachineInstr &MI) const {
1631 return getVALUOp(MI) != AMDGPU::INSTRUCTION_LIST_END;
1634 const TargetRegisterClass *SIInstrInfo::getOpRegClass(const MachineInstr &MI,
1635 unsigned OpNo) const {
1636 const MachineRegisterInfo &MRI = MI.getParent()->getParent()->getRegInfo();
1637 const MCInstrDesc &Desc = get(MI.getOpcode());
1638 if (MI.isVariadic() || OpNo >= Desc.getNumOperands() ||
1639 Desc.OpInfo[OpNo].RegClass == -1) {
1640 unsigned Reg = MI.getOperand(OpNo).getReg();
1642 if (TargetRegisterInfo::isVirtualRegister(Reg))
1643 return MRI.getRegClass(Reg);
1644 return RI.getPhysRegClass(Reg);
1647 unsigned RCID = Desc.OpInfo[OpNo].RegClass;
1648 return RI.getRegClass(RCID);
1651 bool SIInstrInfo::canReadVGPR(const MachineInstr &MI, unsigned OpNo) const {
1652 switch (MI.getOpcode()) {
1654 case AMDGPU::REG_SEQUENCE:
1656 case AMDGPU::INSERT_SUBREG:
1657 return RI.hasVGPRs(getOpRegClass(MI, 0));
1659 return RI.hasVGPRs(getOpRegClass(MI, OpNo));
1663 void SIInstrInfo::legalizeOpWithMove(MachineInstr *MI, unsigned OpIdx) const {
1664 MachineBasicBlock::iterator I = MI;
1665 MachineBasicBlock *MBB = MI->getParent();
1666 MachineOperand &MO = MI->getOperand(OpIdx);
1667 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
1668 unsigned RCID = get(MI->getOpcode()).OpInfo[OpIdx].RegClass;
1669 const TargetRegisterClass *RC = RI.getRegClass(RCID);
1670 unsigned Opcode = AMDGPU::V_MOV_B32_e32;
1672 Opcode = AMDGPU::COPY;
1673 else if (RI.isSGPRClass(RC))
1674 Opcode = AMDGPU::S_MOV_B32;
1677 const TargetRegisterClass *VRC = RI.getEquivalentVGPRClass(RC);
1678 if (RI.getCommonSubClass(&AMDGPU::VReg_64RegClass, VRC))
1679 VRC = &AMDGPU::VReg_64RegClass;
1681 VRC = &AMDGPU::VGPR_32RegClass;
1683 unsigned Reg = MRI.createVirtualRegister(VRC);
1684 DebugLoc DL = MBB->findDebugLoc(I);
1685 BuildMI(*MI->getParent(), I, DL, get(Opcode), Reg)
1687 MO.ChangeToRegister(Reg, false);
1690 unsigned SIInstrInfo::buildExtractSubReg(MachineBasicBlock::iterator MI,
1691 MachineRegisterInfo &MRI,
1692 MachineOperand &SuperReg,
1693 const TargetRegisterClass *SuperRC,
1695 const TargetRegisterClass *SubRC)
1697 MachineBasicBlock *MBB = MI->getParent();
1698 DebugLoc DL = MI->getDebugLoc();
1699 unsigned SubReg = MRI.createVirtualRegister(SubRC);
1701 if (SuperReg.getSubReg() == AMDGPU::NoSubRegister) {
1702 BuildMI(*MBB, MI, DL, get(TargetOpcode::COPY), SubReg)
1703 .addReg(SuperReg.getReg(), 0, SubIdx);
1707 // Just in case the super register is itself a sub-register, copy it to a new
1708 // value so we don't need to worry about merging its subreg index with the
1709 // SubIdx passed to this function. The register coalescer should be able to
1710 // eliminate this extra copy.
1711 unsigned NewSuperReg = MRI.createVirtualRegister(SuperRC);
1713 BuildMI(*MBB, MI, DL, get(TargetOpcode::COPY), NewSuperReg)
1714 .addReg(SuperReg.getReg(), 0, SuperReg.getSubReg());
1716 BuildMI(*MBB, MI, DL, get(TargetOpcode::COPY), SubReg)
1717 .addReg(NewSuperReg, 0, SubIdx);
1722 MachineOperand SIInstrInfo::buildExtractSubRegOrImm(
1723 MachineBasicBlock::iterator MII,
1724 MachineRegisterInfo &MRI,
1726 const TargetRegisterClass *SuperRC,
1728 const TargetRegisterClass *SubRC) const {
1730 // XXX - Is there a better way to do this?
1731 if (SubIdx == AMDGPU::sub0)
1732 return MachineOperand::CreateImm(Op.getImm() & 0xFFFFFFFF);
1733 if (SubIdx == AMDGPU::sub1)
1734 return MachineOperand::CreateImm(Op.getImm() >> 32);
1736 llvm_unreachable("Unhandled register index for immediate");
1739 unsigned SubReg = buildExtractSubReg(MII, MRI, Op, SuperRC,
1741 return MachineOperand::CreateReg(SubReg, false);
1744 // Change the order of operands from (0, 1, 2) to (0, 2, 1)
1745 void SIInstrInfo::swapOperands(MachineBasicBlock::iterator Inst) const {
1746 assert(Inst->getNumExplicitOperands() == 3);
1747 MachineOperand Op1 = Inst->getOperand(1);
1748 Inst->RemoveOperand(1);
1749 Inst->addOperand(Op1);
1752 bool SIInstrInfo::isLegalRegOperand(const MachineRegisterInfo &MRI,
1753 const MCOperandInfo &OpInfo,
1754 const MachineOperand &MO) const {
1758 unsigned Reg = MO.getReg();
1759 const TargetRegisterClass *RC =
1760 TargetRegisterInfo::isVirtualRegister(Reg) ?
1761 MRI.getRegClass(Reg) :
1762 RI.getPhysRegClass(Reg);
1764 // In order to be legal, the common sub-class must be equal to the
1765 // class of the current operand. For example:
1767 // v_mov_b32 s0 ; Operand defined as vsrc_32
1768 // ; RI.getCommonSubClass(s0,vsrc_32) = sgpr ; LEGAL
1770 // s_sendmsg 0, s0 ; Operand defined as m0reg
1771 // ; RI.getCommonSubClass(s0,m0reg) = m0reg ; NOT LEGAL
1773 return RI.getCommonSubClass(RC, RI.getRegClass(OpInfo.RegClass)) == RC;
1776 bool SIInstrInfo::isLegalVSrcOperand(const MachineRegisterInfo &MRI,
1777 const MCOperandInfo &OpInfo,
1778 const MachineOperand &MO) const {
1780 return isLegalRegOperand(MRI, OpInfo, MO);
1782 // Handle non-register types that are treated like immediates.
1783 assert(MO.isImm() || MO.isTargetIndex() || MO.isFI());
1787 bool SIInstrInfo::isOperandLegal(const MachineInstr *MI, unsigned OpIdx,
1788 const MachineOperand *MO) const {
1789 const MachineRegisterInfo &MRI = MI->getParent()->getParent()->getRegInfo();
1790 const MCInstrDesc &InstDesc = get(MI->getOpcode());
1791 const MCOperandInfo &OpInfo = InstDesc.OpInfo[OpIdx];
1792 const TargetRegisterClass *DefinedRC =
1793 OpInfo.RegClass != -1 ? RI.getRegClass(OpInfo.RegClass) : nullptr;
1795 MO = &MI->getOperand(OpIdx);
1798 usesConstantBus(MRI, *MO, DefinedRC->getSize())) {
1800 MO->isReg() ? MO->getReg() : (unsigned)AMDGPU::NoRegister;
1801 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1804 const MachineOperand &Op = MI->getOperand(i);
1805 if (Op.isReg() && Op.getReg() != SGPRUsed &&
1806 usesConstantBus(MRI, Op, getOpSize(*MI, i))) {
1814 return isLegalRegOperand(MRI, OpInfo, *MO);
1818 // Handle non-register types that are treated like immediates.
1819 assert(MO->isImm() || MO->isTargetIndex() || MO->isFI());
1822 // This operand expects an immediate.
1826 return isImmOperandLegal(MI, OpIdx, *MO);
1829 void SIInstrInfo::legalizeOperandsVOP2(MachineRegisterInfo &MRI,
1830 MachineInstr *MI) const {
1831 unsigned Opc = MI->getOpcode();
1832 const MCInstrDesc &InstrDesc = get(Opc);
1834 int Src1Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src1);
1835 MachineOperand &Src1 = MI->getOperand(Src1Idx);
1837 // If there is an implicit SGPR use such as VCC use for v_addc_u32/v_subb_u32
1838 // we need to only have one constant bus use.
1840 // Note we do not need to worry about literal constants here. They are
1841 // disabled for the operand type for instructions because they will always
1842 // violate the one constant bus use rule.
1843 bool HasImplicitSGPR = findImplicitSGPRRead(*MI) != AMDGPU::NoRegister;
1844 if (HasImplicitSGPR) {
1845 int Src0Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src0);
1846 MachineOperand &Src0 = MI->getOperand(Src0Idx);
1848 if (Src0.isReg() && RI.isSGPRReg(MRI, Src0.getReg()))
1849 legalizeOpWithMove(MI, Src0Idx);
1852 // VOP2 src0 instructions support all operand types, so we don't need to check
1853 // their legality. If src1 is already legal, we don't need to do anything.
1854 if (isLegalRegOperand(MRI, InstrDesc.OpInfo[Src1Idx], Src1))
1857 // We do not use commuteInstruction here because it is too aggressive and will
1858 // commute if it is possible. We only want to commute here if it improves
1859 // legality. This can be called a fairly large number of times so don't waste
1860 // compile time pointlessly swapping and checking legality again.
1861 if (HasImplicitSGPR || !MI->isCommutable()) {
1862 legalizeOpWithMove(MI, Src1Idx);
1866 int Src0Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src0);
1867 MachineOperand &Src0 = MI->getOperand(Src0Idx);
1869 // If src0 can be used as src1, commuting will make the operands legal.
1870 // Otherwise we have to give up and insert a move.
1872 // TODO: Other immediate-like operand kinds could be commuted if there was a
1873 // MachineOperand::ChangeTo* for them.
1874 if ((!Src1.isImm() && !Src1.isReg()) ||
1875 !isLegalRegOperand(MRI, InstrDesc.OpInfo[Src1Idx], Src0)) {
1876 legalizeOpWithMove(MI, Src1Idx);
1880 int CommutedOpc = commuteOpcode(*MI);
1881 if (CommutedOpc == -1) {
1882 legalizeOpWithMove(MI, Src1Idx);
1886 MI->setDesc(get(CommutedOpc));
1888 unsigned Src0Reg = Src0.getReg();
1889 unsigned Src0SubReg = Src0.getSubReg();
1890 bool Src0Kill = Src0.isKill();
1893 Src0.ChangeToImmediate(Src1.getImm());
1894 else if (Src1.isReg()) {
1895 Src0.ChangeToRegister(Src1.getReg(), false, false, Src1.isKill());
1896 Src0.setSubReg(Src1.getSubReg());
1898 llvm_unreachable("Should only have register or immediate operands");
1900 Src1.ChangeToRegister(Src0Reg, false, false, Src0Kill);
1901 Src1.setSubReg(Src0SubReg);
1904 // Legalize VOP3 operands. Because all operand types are supported for any
1905 // operand, and since literal constants are not allowed and should never be
1906 // seen, we only need to worry about inserting copies if we use multiple SGPR
1908 void SIInstrInfo::legalizeOperandsVOP3(
1909 MachineRegisterInfo &MRI,
1910 MachineInstr *MI) const {
1911 unsigned Opc = MI->getOpcode();
1914 AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src0),
1915 AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src1),
1916 AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src2)
1919 // Find the one SGPR operand we are allowed to use.
1920 unsigned SGPRReg = findUsedSGPR(MI, VOP3Idx);
1922 for (unsigned i = 0; i < 3; ++i) {
1923 int Idx = VOP3Idx[i];
1926 MachineOperand &MO = MI->getOperand(Idx);
1928 // We should never see a VOP3 instruction with an illegal immediate operand.
1932 if (!RI.isSGPRClass(MRI.getRegClass(MO.getReg())))
1933 continue; // VGPRs are legal
1935 if (SGPRReg == AMDGPU::NoRegister || SGPRReg == MO.getReg()) {
1936 SGPRReg = MO.getReg();
1937 // We can use one SGPR in each VOP3 instruction.
1941 // If we make it this far, then the operand is not legal and we must
1943 legalizeOpWithMove(MI, Idx);
1947 void SIInstrInfo::legalizeOperands(MachineInstr *MI) const {
1948 MachineRegisterInfo &MRI = MI->getParent()->getParent()->getRegInfo();
1952 legalizeOperandsVOP2(MRI, MI);
1958 legalizeOperandsVOP3(MRI, MI);
1962 // Legalize REG_SEQUENCE and PHI
1963 // The register class of the operands much be the same type as the register
1964 // class of the output.
1965 if (MI->getOpcode() == AMDGPU::PHI) {
1966 const TargetRegisterClass *RC = nullptr, *SRC = nullptr, *VRC = nullptr;
1967 for (unsigned i = 1, e = MI->getNumOperands(); i != e; i+=2) {
1968 if (!MI->getOperand(i).isReg() ||
1969 !TargetRegisterInfo::isVirtualRegister(MI->getOperand(i).getReg()))
1971 const TargetRegisterClass *OpRC =
1972 MRI.getRegClass(MI->getOperand(i).getReg());
1973 if (RI.hasVGPRs(OpRC)) {
1980 // If any of the operands are VGPR registers, then they all most be
1981 // otherwise we will create illegal VGPR->SGPR copies when legalizing
1983 if (VRC || !RI.isSGPRClass(getOpRegClass(*MI, 0))) {
1986 VRC = RI.getEquivalentVGPRClass(SRC);
1993 // Update all the operands so they have the same type.
1994 for (unsigned I = 1, E = MI->getNumOperands(); I != E; I += 2) {
1995 MachineOperand &Op = MI->getOperand(I);
1996 if (!Op.isReg() || !TargetRegisterInfo::isVirtualRegister(Op.getReg()))
1998 unsigned DstReg = MRI.createVirtualRegister(RC);
2000 // MI is a PHI instruction.
2001 MachineBasicBlock *InsertBB = MI->getOperand(I + 1).getMBB();
2002 MachineBasicBlock::iterator Insert = InsertBB->getFirstTerminator();
2004 BuildMI(*InsertBB, Insert, MI->getDebugLoc(), get(AMDGPU::COPY), DstReg)
2010 // REG_SEQUENCE doesn't really require operand legalization, but if one has a
2011 // VGPR dest type and SGPR sources, insert copies so all operands are
2012 // VGPRs. This seems to help operand folding / the register coalescer.
2013 if (MI->getOpcode() == AMDGPU::REG_SEQUENCE) {
2014 MachineBasicBlock *MBB = MI->getParent();
2015 const TargetRegisterClass *DstRC = getOpRegClass(*MI, 0);
2016 if (RI.hasVGPRs(DstRC)) {
2017 // Update all the operands so they are VGPR register classes. These may
2018 // not be the same register class because REG_SEQUENCE supports mixing
2019 // subregister index types e.g. sub0_sub1 + sub2 + sub3
2020 for (unsigned I = 1, E = MI->getNumOperands(); I != E; I += 2) {
2021 MachineOperand &Op = MI->getOperand(I);
2022 if (!Op.isReg() || !TargetRegisterInfo::isVirtualRegister(Op.getReg()))
2025 const TargetRegisterClass *OpRC = MRI.getRegClass(Op.getReg());
2026 const TargetRegisterClass *VRC = RI.getEquivalentVGPRClass(OpRC);
2030 unsigned DstReg = MRI.createVirtualRegister(VRC);
2032 BuildMI(*MBB, MI, MI->getDebugLoc(), get(AMDGPU::COPY), DstReg)
2043 // Legalize INSERT_SUBREG
2044 // src0 must have the same register class as dst
2045 if (MI->getOpcode() == AMDGPU::INSERT_SUBREG) {
2046 unsigned Dst = MI->getOperand(0).getReg();
2047 unsigned Src0 = MI->getOperand(1).getReg();
2048 const TargetRegisterClass *DstRC = MRI.getRegClass(Dst);
2049 const TargetRegisterClass *Src0RC = MRI.getRegClass(Src0);
2050 if (DstRC != Src0RC) {
2051 MachineBasicBlock &MBB = *MI->getParent();
2052 unsigned NewSrc0 = MRI.createVirtualRegister(DstRC);
2053 BuildMI(MBB, MI, MI->getDebugLoc(), get(AMDGPU::COPY), NewSrc0)
2055 MI->getOperand(1).setReg(NewSrc0);
2060 // Legalize MUBUF* instructions
2061 // FIXME: If we start using the non-addr64 instructions for compute, we
2062 // may need to legalize them here.
2064 AMDGPU::getNamedOperandIdx(MI->getOpcode(), AMDGPU::OpName::srsrc);
2065 if (SRsrcIdx != -1) {
2066 // We have an MUBUF instruction
2067 MachineOperand *SRsrc = &MI->getOperand(SRsrcIdx);
2068 unsigned SRsrcRC = get(MI->getOpcode()).OpInfo[SRsrcIdx].RegClass;
2069 if (RI.getCommonSubClass(MRI.getRegClass(SRsrc->getReg()),
2070 RI.getRegClass(SRsrcRC))) {
2071 // The operands are legal.
2072 // FIXME: We may need to legalize operands besided srsrc.
2076 MachineBasicBlock &MBB = *MI->getParent();
2078 // Extract the ptr from the resource descriptor.
2079 unsigned SRsrcPtr = buildExtractSubReg(MI, MRI, *SRsrc,
2080 &AMDGPU::VReg_128RegClass, AMDGPU::sub0_sub1, &AMDGPU::VReg_64RegClass);
2082 // Create an empty resource descriptor
2083 unsigned Zero64 = MRI.createVirtualRegister(&AMDGPU::SReg_64RegClass);
2084 unsigned SRsrcFormatLo = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
2085 unsigned SRsrcFormatHi = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
2086 unsigned NewSRsrc = MRI.createVirtualRegister(&AMDGPU::SReg_128RegClass);
2087 uint64_t RsrcDataFormat = getDefaultRsrcDataFormat();
2090 BuildMI(MBB, MI, MI->getDebugLoc(), get(AMDGPU::S_MOV_B64),
2094 // SRsrcFormatLo = RSRC_DATA_FORMAT{31-0}
2095 BuildMI(MBB, MI, MI->getDebugLoc(), get(AMDGPU::S_MOV_B32),
2097 .addImm(RsrcDataFormat & 0xFFFFFFFF);
2099 // SRsrcFormatHi = RSRC_DATA_FORMAT{63-32}
2100 BuildMI(MBB, MI, MI->getDebugLoc(), get(AMDGPU::S_MOV_B32),
2102 .addImm(RsrcDataFormat >> 32);
2104 // NewSRsrc = {Zero64, SRsrcFormat}
2105 BuildMI(MBB, MI, MI->getDebugLoc(), get(AMDGPU::REG_SEQUENCE), NewSRsrc)
2107 .addImm(AMDGPU::sub0_sub1)
2108 .addReg(SRsrcFormatLo)
2109 .addImm(AMDGPU::sub2)
2110 .addReg(SRsrcFormatHi)
2111 .addImm(AMDGPU::sub3);
2113 MachineOperand *VAddr = getNamedOperand(*MI, AMDGPU::OpName::vaddr);
2114 unsigned NewVAddr = MRI.createVirtualRegister(&AMDGPU::VReg_64RegClass);
2116 // This is already an ADDR64 instruction so we need to add the pointer
2117 // extracted from the resource descriptor to the current value of VAddr.
2118 unsigned NewVAddrLo = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
2119 unsigned NewVAddrHi = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
2121 // NewVaddrLo = SRsrcPtr:sub0 + VAddr:sub0
2122 DebugLoc DL = MI->getDebugLoc();
2123 BuildMI(MBB, MI, DL, get(AMDGPU::V_ADD_I32_e32), NewVAddrLo)
2124 .addReg(SRsrcPtr, 0, AMDGPU::sub0)
2125 .addReg(VAddr->getReg(), 0, AMDGPU::sub0);
2127 // NewVaddrHi = SRsrcPtr:sub1 + VAddr:sub1
2128 BuildMI(MBB, MI, DL, get(AMDGPU::V_ADDC_U32_e32), NewVAddrHi)
2129 .addReg(SRsrcPtr, 0, AMDGPU::sub1)
2130 .addReg(VAddr->getReg(), 0, AMDGPU::sub1);
2132 // NewVaddr = {NewVaddrHi, NewVaddrLo}
2133 BuildMI(MBB, MI, MI->getDebugLoc(), get(AMDGPU::REG_SEQUENCE), NewVAddr)
2135 .addImm(AMDGPU::sub0)
2137 .addImm(AMDGPU::sub1);
2139 // This instructions is the _OFFSET variant, so we need to convert it to
2141 assert(MBB.getParent()->getSubtarget<AMDGPUSubtarget>().getGeneration()
2142 < AMDGPUSubtarget::VOLCANIC_ISLANDS &&
2143 "FIXME: Need to emit flat atomics here");
2145 MachineOperand *VData = getNamedOperand(*MI, AMDGPU::OpName::vdata);
2146 MachineOperand *Offset = getNamedOperand(*MI, AMDGPU::OpName::offset);
2147 MachineOperand *SOffset = getNamedOperand(*MI, AMDGPU::OpName::soffset);
2148 unsigned Addr64Opcode = AMDGPU::getAddr64Inst(MI->getOpcode());
2150 // Atomics rith return have have an additional tied operand and are
2151 // missing some of the special bits.
2152 MachineOperand *VDataIn = getNamedOperand(*MI, AMDGPU::OpName::vdata_in);
2153 MachineInstr *Addr64;
2156 // Regular buffer load / store.
2157 MachineInstrBuilder MIB
2158 = BuildMI(MBB, MI, MI->getDebugLoc(), get(Addr64Opcode))
2160 .addReg(AMDGPU::NoRegister) // Dummy value for vaddr.
2161 // This will be replaced later
2162 // with the new value of vaddr.
2164 .addOperand(*SOffset)
2165 .addOperand(*Offset);
2167 // Atomics do not have this operand.
2168 if (const MachineOperand *GLC
2169 = getNamedOperand(*MI, AMDGPU::OpName::glc)) {
2170 MIB.addImm(GLC->getImm());
2173 MIB.addImm(getNamedImmOperand(*MI, AMDGPU::OpName::slc));
2175 if (const MachineOperand *TFE
2176 = getNamedOperand(*MI, AMDGPU::OpName::tfe)) {
2177 MIB.addImm(TFE->getImm());
2180 MIB.setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
2183 // Atomics with return.
2184 Addr64 = BuildMI(MBB, MI, MI->getDebugLoc(), get(Addr64Opcode))
2186 .addOperand(*VDataIn)
2187 .addReg(AMDGPU::NoRegister) // Dummy value for vaddr.
2188 // This will be replaced later
2189 // with the new value of vaddr.
2191 .addOperand(*SOffset)
2192 .addOperand(*Offset)
2193 .addImm(getNamedImmOperand(*MI, AMDGPU::OpName::slc))
2194 .setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
2197 MI->removeFromParent();
2200 // NewVaddr = {NewVaddrHi, NewVaddrLo}
2201 BuildMI(MBB, MI, MI->getDebugLoc(), get(AMDGPU::REG_SEQUENCE), NewVAddr)
2202 .addReg(SRsrcPtr, 0, AMDGPU::sub0)
2203 .addImm(AMDGPU::sub0)
2204 .addReg(SRsrcPtr, 0, AMDGPU::sub1)
2205 .addImm(AMDGPU::sub1);
2207 VAddr = getNamedOperand(*MI, AMDGPU::OpName::vaddr);
2208 SRsrc = getNamedOperand(*MI, AMDGPU::OpName::srsrc);
2211 // Update the instruction to use NewVaddr
2212 VAddr->setReg(NewVAddr);
2213 // Update the instruction to use NewSRsrc
2214 SRsrc->setReg(NewSRsrc);
2218 void SIInstrInfo::splitSMRD(MachineInstr *MI,
2219 const TargetRegisterClass *HalfRC,
2220 unsigned HalfImmOp, unsigned HalfSGPROp,
2221 MachineInstr *&Lo, MachineInstr *&Hi) const {
2223 DebugLoc DL = MI->getDebugLoc();
2224 MachineBasicBlock *MBB = MI->getParent();
2225 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
2226 unsigned RegLo = MRI.createVirtualRegister(HalfRC);
2227 unsigned RegHi = MRI.createVirtualRegister(HalfRC);
2228 unsigned HalfSize = HalfRC->getSize();
2229 const MachineOperand *OffOp =
2230 getNamedOperand(*MI, AMDGPU::OpName::offset);
2231 const MachineOperand *SBase = getNamedOperand(*MI, AMDGPU::OpName::sbase);
2233 // The SMRD has an 8-bit offset in dwords on SI and a 20-bit offset in bytes
2236 bool IsKill = SBase->isKill();
2239 MBB->getParent()->getSubtarget<AMDGPUSubtarget>().getGeneration() >=
2240 AMDGPUSubtarget::VOLCANIC_ISLANDS;
2241 unsigned OffScale = isVI ? 1 : 4;
2242 // Handle the _IMM variant
2243 unsigned LoOffset = OffOp->getImm() * OffScale;
2244 unsigned HiOffset = LoOffset + HalfSize;
2245 Lo = BuildMI(*MBB, MI, DL, get(HalfImmOp), RegLo)
2246 // Use addReg instead of addOperand
2247 // to make sure kill flag is cleared.
2248 .addReg(SBase->getReg(), 0, SBase->getSubReg())
2249 .addImm(LoOffset / OffScale);
2251 if (!isUInt<20>(HiOffset) || (!isVI && !isUInt<8>(HiOffset / OffScale))) {
2252 unsigned OffsetSGPR =
2253 MRI.createVirtualRegister(&AMDGPU::SReg_32RegClass);
2254 BuildMI(*MBB, MI, DL, get(AMDGPU::S_MOV_B32), OffsetSGPR)
2255 .addImm(HiOffset); // The offset in register is in bytes.
2256 Hi = BuildMI(*MBB, MI, DL, get(HalfSGPROp), RegHi)
2257 .addReg(SBase->getReg(), getKillRegState(IsKill),
2259 .addReg(OffsetSGPR);
2261 Hi = BuildMI(*MBB, MI, DL, get(HalfImmOp), RegHi)
2262 .addReg(SBase->getReg(), getKillRegState(IsKill),
2264 .addImm(HiOffset / OffScale);
2267 // Handle the _SGPR variant
2268 MachineOperand *SOff = getNamedOperand(*MI, AMDGPU::OpName::soff);
2269 Lo = BuildMI(*MBB, MI, DL, get(HalfSGPROp), RegLo)
2270 .addReg(SBase->getReg(), 0, SBase->getSubReg())
2272 unsigned OffsetSGPR = MRI.createVirtualRegister(&AMDGPU::SReg_32RegClass);
2273 BuildMI(*MBB, MI, DL, get(AMDGPU::S_ADD_I32), OffsetSGPR)
2274 .addReg(SOff->getReg(), 0, SOff->getSubReg())
2276 Hi = BuildMI(*MBB, MI, DL, get(HalfSGPROp), RegHi)
2277 .addReg(SBase->getReg(), getKillRegState(IsKill),
2279 .addReg(OffsetSGPR);
2282 unsigned SubLo, SubHi;
2283 const TargetRegisterClass *NewDstRC;
2286 SubLo = AMDGPU::sub0;
2287 SubHi = AMDGPU::sub1;
2288 NewDstRC = &AMDGPU::VReg_64RegClass;
2291 SubLo = AMDGPU::sub0_sub1;
2292 SubHi = AMDGPU::sub2_sub3;
2293 NewDstRC = &AMDGPU::VReg_128RegClass;
2296 SubLo = AMDGPU::sub0_sub1_sub2_sub3;
2297 SubHi = AMDGPU::sub4_sub5_sub6_sub7;
2298 NewDstRC = &AMDGPU::VReg_256RegClass;
2301 SubLo = AMDGPU::sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7;
2302 SubHi = AMDGPU::sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15;
2303 NewDstRC = &AMDGPU::VReg_512RegClass;
2306 llvm_unreachable("Unhandled HalfSize");
2309 unsigned OldDst = MI->getOperand(0).getReg();
2310 unsigned NewDst = MRI.createVirtualRegister(NewDstRC);
2312 MRI.replaceRegWith(OldDst, NewDst);
2314 BuildMI(*MBB, MI, DL, get(AMDGPU::REG_SEQUENCE), NewDst)
2321 void SIInstrInfo::moveSMRDToVALU(MachineInstr *MI,
2322 MachineRegisterInfo &MRI,
2323 SmallVectorImpl<MachineInstr *> &Worklist) const {
2324 MachineBasicBlock *MBB = MI->getParent();
2325 int DstIdx = AMDGPU::getNamedOperandIdx(MI->getOpcode(), AMDGPU::OpName::dst);
2326 assert(DstIdx != -1);
2327 unsigned DstRCID = get(MI->getOpcode()).OpInfo[DstIdx].RegClass;
2328 switch(RI.getRegClass(DstRCID)->getSize()) {
2332 unsigned NewOpcode = getVALUOp(*MI);
2336 if (MI->getOperand(2).isReg()) {
2337 RegOffset = MI->getOperand(2).getReg();
2340 assert(MI->getOperand(2).isImm());
2341 // SMRD instructions take a dword offsets on SI and byte offset on VI
2342 // and MUBUF instructions always take a byte offset.
2343 ImmOffset = MI->getOperand(2).getImm();
2344 if (MBB->getParent()->getSubtarget<AMDGPUSubtarget>().getGeneration() <=
2345 AMDGPUSubtarget::SEA_ISLANDS)
2347 RegOffset = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
2349 if (isUInt<12>(ImmOffset)) {
2350 BuildMI(*MBB, MI, MI->getDebugLoc(), get(AMDGPU::S_MOV_B32),
2354 BuildMI(*MBB, MI, MI->getDebugLoc(), get(AMDGPU::S_MOV_B32),
2361 unsigned SRsrc = MRI.createVirtualRegister(&AMDGPU::SReg_128RegClass);
2362 unsigned DWord0 = RegOffset;
2363 unsigned DWord1 = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
2364 unsigned DWord2 = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
2365 unsigned DWord3 = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
2366 uint64_t RsrcDataFormat = getDefaultRsrcDataFormat();
2368 BuildMI(*MBB, MI, MI->getDebugLoc(), get(AMDGPU::S_MOV_B32), DWord1)
2370 BuildMI(*MBB, MI, MI->getDebugLoc(), get(AMDGPU::S_MOV_B32), DWord2)
2371 .addImm(RsrcDataFormat & 0xFFFFFFFF);
2372 BuildMI(*MBB, MI, MI->getDebugLoc(), get(AMDGPU::S_MOV_B32), DWord3)
2373 .addImm(RsrcDataFormat >> 32);
2374 BuildMI(*MBB, MI, MI->getDebugLoc(), get(AMDGPU::REG_SEQUENCE), SRsrc)
2376 .addImm(AMDGPU::sub0)
2378 .addImm(AMDGPU::sub1)
2380 .addImm(AMDGPU::sub2)
2382 .addImm(AMDGPU::sub3);
2384 const MCInstrDesc &NewInstDesc = get(NewOpcode);
2385 const TargetRegisterClass *NewDstRC
2386 = RI.getRegClass(NewInstDesc.OpInfo[0].RegClass);
2387 unsigned NewDstReg = MRI.createVirtualRegister(NewDstRC);
2388 unsigned DstReg = MI->getOperand(0).getReg();
2389 MRI.replaceRegWith(DstReg, NewDstReg);
2391 MachineInstr *NewInst =
2392 BuildMI(*MBB, MI, MI->getDebugLoc(), NewInstDesc, NewDstReg)
2393 .addOperand(MI->getOperand(1)) // sbase
2400 .setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
2401 MI->eraseFromParent();
2403 legalizeOperands(NewInst);
2404 addUsersToMoveToVALUWorklist(NewDstReg, MRI, Worklist);
2408 MachineInstr *Lo, *Hi;
2409 splitSMRD(MI, &AMDGPU::SReg_128RegClass, AMDGPU::S_LOAD_DWORDX4_IMM,
2410 AMDGPU::S_LOAD_DWORDX4_SGPR, Lo, Hi);
2411 MI->eraseFromParent();
2412 moveSMRDToVALU(Lo, MRI, Worklist);
2413 moveSMRDToVALU(Hi, MRI, Worklist);
2418 MachineInstr *Lo, *Hi;
2419 splitSMRD(MI, &AMDGPU::SReg_256RegClass, AMDGPU::S_LOAD_DWORDX8_IMM,
2420 AMDGPU::S_LOAD_DWORDX8_SGPR, Lo, Hi);
2421 MI->eraseFromParent();
2422 moveSMRDToVALU(Lo, MRI, Worklist);
2423 moveSMRDToVALU(Hi, MRI, Worklist);
2429 void SIInstrInfo::moveToVALU(MachineInstr &TopInst) const {
2430 SmallVector<MachineInstr *, 128> Worklist;
2431 Worklist.push_back(&TopInst);
2433 while (!Worklist.empty()) {
2434 MachineInstr *Inst = Worklist.pop_back_val();
2435 MachineBasicBlock *MBB = Inst->getParent();
2436 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
2438 unsigned Opcode = Inst->getOpcode();
2439 unsigned NewOpcode = getVALUOp(*Inst);
2441 // Handle some special cases
2444 if (isSMRD(*Inst)) {
2445 moveSMRDToVALU(Inst, MRI, Worklist);
2449 case AMDGPU::S_AND_B64:
2450 splitScalar64BitBinaryOp(Worklist, Inst, AMDGPU::V_AND_B32_e64);
2451 Inst->eraseFromParent();
2454 case AMDGPU::S_OR_B64:
2455 splitScalar64BitBinaryOp(Worklist, Inst, AMDGPU::V_OR_B32_e64);
2456 Inst->eraseFromParent();
2459 case AMDGPU::S_XOR_B64:
2460 splitScalar64BitBinaryOp(Worklist, Inst, AMDGPU::V_XOR_B32_e64);
2461 Inst->eraseFromParent();
2464 case AMDGPU::S_NOT_B64:
2465 splitScalar64BitUnaryOp(Worklist, Inst, AMDGPU::V_NOT_B32_e32);
2466 Inst->eraseFromParent();
2469 case AMDGPU::S_BCNT1_I32_B64:
2470 splitScalar64BitBCNT(Worklist, Inst);
2471 Inst->eraseFromParent();
2474 case AMDGPU::S_BFE_I64: {
2475 splitScalar64BitBFE(Worklist, Inst);
2476 Inst->eraseFromParent();
2480 case AMDGPU::S_LSHL_B32:
2481 if (ST.getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS) {
2482 NewOpcode = AMDGPU::V_LSHLREV_B32_e64;
2486 case AMDGPU::S_ASHR_I32:
2487 if (ST.getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS) {
2488 NewOpcode = AMDGPU::V_ASHRREV_I32_e64;
2492 case AMDGPU::S_LSHR_B32:
2493 if (ST.getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS) {
2494 NewOpcode = AMDGPU::V_LSHRREV_B32_e64;
2498 case AMDGPU::S_LSHL_B64:
2499 if (ST.getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS) {
2500 NewOpcode = AMDGPU::V_LSHLREV_B64;
2504 case AMDGPU::S_ASHR_I64:
2505 if (ST.getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS) {
2506 NewOpcode = AMDGPU::V_ASHRREV_I64;
2510 case AMDGPU::S_LSHR_B64:
2511 if (ST.getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS) {
2512 NewOpcode = AMDGPU::V_LSHRREV_B64;
2517 case AMDGPU::S_ABS_I32:
2518 lowerScalarAbs(Worklist, Inst);
2519 Inst->eraseFromParent();
2522 case AMDGPU::S_BFE_U64:
2523 case AMDGPU::S_BFM_B64:
2524 llvm_unreachable("Moving this op to VALU not implemented");
2527 if (NewOpcode == AMDGPU::INSTRUCTION_LIST_END) {
2528 // We cannot move this instruction to the VALU, so we should try to
2529 // legalize its operands instead.
2530 legalizeOperands(Inst);
2534 // Use the new VALU Opcode.
2535 const MCInstrDesc &NewDesc = get(NewOpcode);
2536 Inst->setDesc(NewDesc);
2538 // Remove any references to SCC. Vector instructions can't read from it, and
2539 // We're just about to add the implicit use / defs of VCC, and we don't want
2541 for (unsigned i = Inst->getNumOperands() - 1; i > 0; --i) {
2542 MachineOperand &Op = Inst->getOperand(i);
2543 if (Op.isReg() && Op.getReg() == AMDGPU::SCC)
2544 Inst->RemoveOperand(i);
2547 if (Opcode == AMDGPU::S_SEXT_I32_I8 || Opcode == AMDGPU::S_SEXT_I32_I16) {
2548 // We are converting these to a BFE, so we need to add the missing
2549 // operands for the size and offset.
2550 unsigned Size = (Opcode == AMDGPU::S_SEXT_I32_I8) ? 8 : 16;
2551 Inst->addOperand(MachineOperand::CreateImm(0));
2552 Inst->addOperand(MachineOperand::CreateImm(Size));
2554 } else if (Opcode == AMDGPU::S_BCNT1_I32_B32) {
2555 // The VALU version adds the second operand to the result, so insert an
2557 Inst->addOperand(MachineOperand::CreateImm(0));
2560 Inst->addImplicitDefUseOperands(*Inst->getParent()->getParent());
2562 if (Opcode == AMDGPU::S_BFE_I32 || Opcode == AMDGPU::S_BFE_U32) {
2563 const MachineOperand &OffsetWidthOp = Inst->getOperand(2);
2564 // If we need to move this to VGPRs, we need to unpack the second operand
2565 // back into the 2 separate ones for bit offset and width.
2566 assert(OffsetWidthOp.isImm() &&
2567 "Scalar BFE is only implemented for constant width and offset");
2568 uint32_t Imm = OffsetWidthOp.getImm();
2570 uint32_t Offset = Imm & 0x3f; // Extract bits [5:0].
2571 uint32_t BitWidth = (Imm & 0x7f0000) >> 16; // Extract bits [22:16].
2572 Inst->RemoveOperand(2); // Remove old immediate.
2573 Inst->addOperand(MachineOperand::CreateImm(Offset));
2574 Inst->addOperand(MachineOperand::CreateImm(BitWidth));
2577 // Update the destination register class.
2578 const TargetRegisterClass *NewDstRC = getDestEquivalentVGPRClass(*Inst);
2582 unsigned DstReg = Inst->getOperand(0).getReg();
2583 unsigned NewDstReg = MRI.createVirtualRegister(NewDstRC);
2584 MRI.replaceRegWith(DstReg, NewDstReg);
2586 // Legalize the operands
2587 legalizeOperands(Inst);
2589 addUsersToMoveToVALUWorklist(NewDstReg, MRI, Worklist);
2593 //===----------------------------------------------------------------------===//
2594 // Indirect addressing callbacks
2595 //===----------------------------------------------------------------------===//
2597 unsigned SIInstrInfo::calculateIndirectAddress(unsigned RegIndex,
2598 unsigned Channel) const {
2599 assert(Channel == 0);
2603 const TargetRegisterClass *SIInstrInfo::getIndirectAddrRegClass() const {
2604 return &AMDGPU::VGPR_32RegClass;
2607 void SIInstrInfo::lowerScalarAbs(SmallVectorImpl<MachineInstr *> &Worklist,
2608 MachineInstr *Inst) const {
2609 MachineBasicBlock &MBB = *Inst->getParent();
2610 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
2611 MachineBasicBlock::iterator MII = Inst;
2612 DebugLoc DL = Inst->getDebugLoc();
2614 MachineOperand &Dest = Inst->getOperand(0);
2615 MachineOperand &Src = Inst->getOperand(1);
2616 unsigned TmpReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
2617 unsigned ResultReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
2619 BuildMI(MBB, MII, DL, get(AMDGPU::V_SUB_I32_e32), TmpReg)
2621 .addReg(Src.getReg());
2623 BuildMI(MBB, MII, DL, get(AMDGPU::V_MAX_I32_e64), ResultReg)
2624 .addReg(Src.getReg())
2627 MRI.replaceRegWith(Dest.getReg(), ResultReg);
2628 addUsersToMoveToVALUWorklist(ResultReg, MRI, Worklist);
2631 void SIInstrInfo::splitScalar64BitUnaryOp(
2632 SmallVectorImpl<MachineInstr *> &Worklist,
2634 unsigned Opcode) const {
2635 MachineBasicBlock &MBB = *Inst->getParent();
2636 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
2638 MachineOperand &Dest = Inst->getOperand(0);
2639 MachineOperand &Src0 = Inst->getOperand(1);
2640 DebugLoc DL = Inst->getDebugLoc();
2642 MachineBasicBlock::iterator MII = Inst;
2644 const MCInstrDesc &InstDesc = get(Opcode);
2645 const TargetRegisterClass *Src0RC = Src0.isReg() ?
2646 MRI.getRegClass(Src0.getReg()) :
2647 &AMDGPU::SGPR_32RegClass;
2649 const TargetRegisterClass *Src0SubRC = RI.getSubRegClass(Src0RC, AMDGPU::sub0);
2651 MachineOperand SrcReg0Sub0 = buildExtractSubRegOrImm(MII, MRI, Src0, Src0RC,
2652 AMDGPU::sub0, Src0SubRC);
2654 const TargetRegisterClass *DestRC = MRI.getRegClass(Dest.getReg());
2655 const TargetRegisterClass *NewDestRC = RI.getEquivalentVGPRClass(DestRC);
2656 const TargetRegisterClass *NewDestSubRC = RI.getSubRegClass(NewDestRC, AMDGPU::sub0);
2658 unsigned DestSub0 = MRI.createVirtualRegister(NewDestSubRC);
2659 BuildMI(MBB, MII, DL, InstDesc, DestSub0)
2660 .addOperand(SrcReg0Sub0);
2662 MachineOperand SrcReg0Sub1 = buildExtractSubRegOrImm(MII, MRI, Src0, Src0RC,
2663 AMDGPU::sub1, Src0SubRC);
2665 unsigned DestSub1 = MRI.createVirtualRegister(NewDestSubRC);
2666 BuildMI(MBB, MII, DL, InstDesc, DestSub1)
2667 .addOperand(SrcReg0Sub1);
2669 unsigned FullDestReg = MRI.createVirtualRegister(NewDestRC);
2670 BuildMI(MBB, MII, DL, get(TargetOpcode::REG_SEQUENCE), FullDestReg)
2672 .addImm(AMDGPU::sub0)
2674 .addImm(AMDGPU::sub1);
2676 MRI.replaceRegWith(Dest.getReg(), FullDestReg);
2678 // We don't need to legalizeOperands here because for a single operand, src0
2679 // will support any kind of input.
2681 // Move all users of this moved value.
2682 addUsersToMoveToVALUWorklist(FullDestReg, MRI, Worklist);
2685 void SIInstrInfo::splitScalar64BitBinaryOp(
2686 SmallVectorImpl<MachineInstr *> &Worklist,
2688 unsigned Opcode) const {
2689 MachineBasicBlock &MBB = *Inst->getParent();
2690 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
2692 MachineOperand &Dest = Inst->getOperand(0);
2693 MachineOperand &Src0 = Inst->getOperand(1);
2694 MachineOperand &Src1 = Inst->getOperand(2);
2695 DebugLoc DL = Inst->getDebugLoc();
2697 MachineBasicBlock::iterator MII = Inst;
2699 const MCInstrDesc &InstDesc = get(Opcode);
2700 const TargetRegisterClass *Src0RC = Src0.isReg() ?
2701 MRI.getRegClass(Src0.getReg()) :
2702 &AMDGPU::SGPR_32RegClass;
2704 const TargetRegisterClass *Src0SubRC = RI.getSubRegClass(Src0RC, AMDGPU::sub0);
2705 const TargetRegisterClass *Src1RC = Src1.isReg() ?
2706 MRI.getRegClass(Src1.getReg()) :
2707 &AMDGPU::SGPR_32RegClass;
2709 const TargetRegisterClass *Src1SubRC = RI.getSubRegClass(Src1RC, AMDGPU::sub0);
2711 MachineOperand SrcReg0Sub0 = buildExtractSubRegOrImm(MII, MRI, Src0, Src0RC,
2712 AMDGPU::sub0, Src0SubRC);
2713 MachineOperand SrcReg1Sub0 = buildExtractSubRegOrImm(MII, MRI, Src1, Src1RC,
2714 AMDGPU::sub0, Src1SubRC);
2716 const TargetRegisterClass *DestRC = MRI.getRegClass(Dest.getReg());
2717 const TargetRegisterClass *NewDestRC = RI.getEquivalentVGPRClass(DestRC);
2718 const TargetRegisterClass *NewDestSubRC = RI.getSubRegClass(NewDestRC, AMDGPU::sub0);
2720 unsigned DestSub0 = MRI.createVirtualRegister(NewDestSubRC);
2721 MachineInstr *LoHalf = BuildMI(MBB, MII, DL, InstDesc, DestSub0)
2722 .addOperand(SrcReg0Sub0)
2723 .addOperand(SrcReg1Sub0);
2725 MachineOperand SrcReg0Sub1 = buildExtractSubRegOrImm(MII, MRI, Src0, Src0RC,
2726 AMDGPU::sub1, Src0SubRC);
2727 MachineOperand SrcReg1Sub1 = buildExtractSubRegOrImm(MII, MRI, Src1, Src1RC,
2728 AMDGPU::sub1, Src1SubRC);
2730 unsigned DestSub1 = MRI.createVirtualRegister(NewDestSubRC);
2731 MachineInstr *HiHalf = BuildMI(MBB, MII, DL, InstDesc, DestSub1)
2732 .addOperand(SrcReg0Sub1)
2733 .addOperand(SrcReg1Sub1);
2735 unsigned FullDestReg = MRI.createVirtualRegister(NewDestRC);
2736 BuildMI(MBB, MII, DL, get(TargetOpcode::REG_SEQUENCE), FullDestReg)
2738 .addImm(AMDGPU::sub0)
2740 .addImm(AMDGPU::sub1);
2742 MRI.replaceRegWith(Dest.getReg(), FullDestReg);
2744 // Try to legalize the operands in case we need to swap the order to keep it
2746 legalizeOperands(LoHalf);
2747 legalizeOperands(HiHalf);
2749 // Move all users of this moved vlaue.
2750 addUsersToMoveToVALUWorklist(FullDestReg, MRI, Worklist);
2753 void SIInstrInfo::splitScalar64BitBCNT(SmallVectorImpl<MachineInstr *> &Worklist,
2754 MachineInstr *Inst) const {
2755 MachineBasicBlock &MBB = *Inst->getParent();
2756 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
2758 MachineBasicBlock::iterator MII = Inst;
2759 DebugLoc DL = Inst->getDebugLoc();
2761 MachineOperand &Dest = Inst->getOperand(0);
2762 MachineOperand &Src = Inst->getOperand(1);
2764 const MCInstrDesc &InstDesc = get(AMDGPU::V_BCNT_U32_B32_e64);
2765 const TargetRegisterClass *SrcRC = Src.isReg() ?
2766 MRI.getRegClass(Src.getReg()) :
2767 &AMDGPU::SGPR_32RegClass;
2769 unsigned MidReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
2770 unsigned ResultReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
2772 const TargetRegisterClass *SrcSubRC = RI.getSubRegClass(SrcRC, AMDGPU::sub0);
2774 MachineOperand SrcRegSub0 = buildExtractSubRegOrImm(MII, MRI, Src, SrcRC,
2775 AMDGPU::sub0, SrcSubRC);
2776 MachineOperand SrcRegSub1 = buildExtractSubRegOrImm(MII, MRI, Src, SrcRC,
2777 AMDGPU::sub1, SrcSubRC);
2779 BuildMI(MBB, MII, DL, InstDesc, MidReg)
2780 .addOperand(SrcRegSub0)
2783 BuildMI(MBB, MII, DL, InstDesc, ResultReg)
2784 .addOperand(SrcRegSub1)
2787 MRI.replaceRegWith(Dest.getReg(), ResultReg);
2789 // We don't need to legalize operands here. src0 for etiher instruction can be
2790 // an SGPR, and the second input is unused or determined here.
2791 addUsersToMoveToVALUWorklist(ResultReg, MRI, Worklist);
2794 void SIInstrInfo::splitScalar64BitBFE(SmallVectorImpl<MachineInstr *> &Worklist,
2795 MachineInstr *Inst) const {
2796 MachineBasicBlock &MBB = *Inst->getParent();
2797 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
2798 MachineBasicBlock::iterator MII = Inst;
2799 DebugLoc DL = Inst->getDebugLoc();
2801 MachineOperand &Dest = Inst->getOperand(0);
2802 uint32_t Imm = Inst->getOperand(2).getImm();
2803 uint32_t Offset = Imm & 0x3f; // Extract bits [5:0].
2804 uint32_t BitWidth = (Imm & 0x7f0000) >> 16; // Extract bits [22:16].
2808 // Only sext_inreg cases handled.
2809 assert(Inst->getOpcode() == AMDGPU::S_BFE_I64 &&
2814 if (BitWidth < 32) {
2815 unsigned MidRegLo = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
2816 unsigned MidRegHi = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
2817 unsigned ResultReg = MRI.createVirtualRegister(&AMDGPU::VReg_64RegClass);
2819 BuildMI(MBB, MII, DL, get(AMDGPU::V_BFE_I32), MidRegLo)
2820 .addReg(Inst->getOperand(1).getReg(), 0, AMDGPU::sub0)
2824 BuildMI(MBB, MII, DL, get(AMDGPU::V_ASHRREV_I32_e32), MidRegHi)
2828 BuildMI(MBB, MII, DL, get(TargetOpcode::REG_SEQUENCE), ResultReg)
2830 .addImm(AMDGPU::sub0)
2832 .addImm(AMDGPU::sub1);
2834 MRI.replaceRegWith(Dest.getReg(), ResultReg);
2835 addUsersToMoveToVALUWorklist(ResultReg, MRI, Worklist);
2839 MachineOperand &Src = Inst->getOperand(1);
2840 unsigned TmpReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
2841 unsigned ResultReg = MRI.createVirtualRegister(&AMDGPU::VReg_64RegClass);
2843 BuildMI(MBB, MII, DL, get(AMDGPU::V_ASHRREV_I32_e64), TmpReg)
2845 .addReg(Src.getReg(), 0, AMDGPU::sub0);
2847 BuildMI(MBB, MII, DL, get(TargetOpcode::REG_SEQUENCE), ResultReg)
2848 .addReg(Src.getReg(), 0, AMDGPU::sub0)
2849 .addImm(AMDGPU::sub0)
2851 .addImm(AMDGPU::sub1);
2853 MRI.replaceRegWith(Dest.getReg(), ResultReg);
2854 addUsersToMoveToVALUWorklist(ResultReg, MRI, Worklist);
2857 void SIInstrInfo::addUsersToMoveToVALUWorklist(
2859 MachineRegisterInfo &MRI,
2860 SmallVectorImpl<MachineInstr *> &Worklist) const {
2861 for (MachineRegisterInfo::use_iterator I = MRI.use_begin(DstReg),
2862 E = MRI.use_end(); I != E; ++I) {
2863 MachineInstr &UseMI = *I->getParent();
2864 if (!canReadVGPR(UseMI, I.getOperandNo())) {
2865 Worklist.push_back(&UseMI);
2870 const TargetRegisterClass *SIInstrInfo::getDestEquivalentVGPRClass(
2871 const MachineInstr &Inst) const {
2872 const TargetRegisterClass *NewDstRC = getOpRegClass(Inst, 0);
2874 switch (Inst.getOpcode()) {
2875 // For target instructions, getOpRegClass just returns the virtual register
2876 // class associated with the operand, so we need to find an equivalent VGPR
2877 // register class in order to move the instruction to the VALU.
2880 case AMDGPU::REG_SEQUENCE:
2881 case AMDGPU::INSERT_SUBREG:
2882 if (RI.hasVGPRs(NewDstRC))
2885 NewDstRC = RI.getEquivalentVGPRClass(NewDstRC);
2894 // Find the one SGPR operand we are allowed to use.
2895 unsigned SIInstrInfo::findUsedSGPR(const MachineInstr *MI,
2896 int OpIndices[3]) const {
2897 const MCInstrDesc &Desc = MI->getDesc();
2899 // Find the one SGPR operand we are allowed to use.
2901 // First we need to consider the instruction's operand requirements before
2902 // legalizing. Some operands are required to be SGPRs, such as implicit uses
2903 // of VCC, but we are still bound by the constant bus requirement to only use
2906 // If the operand's class is an SGPR, we can never move it.
2908 unsigned SGPRReg = findImplicitSGPRRead(*MI);
2909 if (SGPRReg != AMDGPU::NoRegister)
2912 unsigned UsedSGPRs[3] = { AMDGPU::NoRegister };
2913 const MachineRegisterInfo &MRI = MI->getParent()->getParent()->getRegInfo();
2915 for (unsigned i = 0; i < 3; ++i) {
2916 int Idx = OpIndices[i];
2920 const MachineOperand &MO = MI->getOperand(Idx);
2924 // Is this operand statically required to be an SGPR based on the operand
2926 const TargetRegisterClass *OpRC = RI.getRegClass(Desc.OpInfo[Idx].RegClass);
2927 bool IsRequiredSGPR = RI.isSGPRClass(OpRC);
2931 // If this could be a VGPR or an SGPR, Check the dynamic register class.
2932 unsigned Reg = MO.getReg();
2933 const TargetRegisterClass *RegRC = MRI.getRegClass(Reg);
2934 if (RI.isSGPRClass(RegRC))
2938 // We don't have a required SGPR operand, so we have a bit more freedom in
2939 // selecting operands to move.
2941 // Try to select the most used SGPR. If an SGPR is equal to one of the
2942 // others, we choose that.
2945 // V_FMA_F32 v0, s0, s0, s0 -> No moves
2946 // V_FMA_F32 v0, s0, s1, s0 -> Move s1
2948 // TODO: If some of the operands are 64-bit SGPRs and some 32, we should
2951 if (UsedSGPRs[0] != AMDGPU::NoRegister) {
2952 if (UsedSGPRs[0] == UsedSGPRs[1] || UsedSGPRs[0] == UsedSGPRs[2])
2953 SGPRReg = UsedSGPRs[0];
2956 if (SGPRReg == AMDGPU::NoRegister && UsedSGPRs[1] != AMDGPU::NoRegister) {
2957 if (UsedSGPRs[1] == UsedSGPRs[2])
2958 SGPRReg = UsedSGPRs[1];
2964 MachineInstrBuilder SIInstrInfo::buildIndirectWrite(
2965 MachineBasicBlock *MBB,
2966 MachineBasicBlock::iterator I,
2968 unsigned Address, unsigned OffsetReg) const {
2969 const DebugLoc &DL = MBB->findDebugLoc(I);
2970 unsigned IndirectBaseReg = AMDGPU::VGPR_32RegClass.getRegister(
2971 getIndirectIndexBegin(*MBB->getParent()));
2973 return BuildMI(*MBB, I, DL, get(AMDGPU::SI_INDIRECT_DST_V1))
2974 .addReg(IndirectBaseReg, RegState::Define)
2975 .addOperand(I->getOperand(0))
2976 .addReg(IndirectBaseReg)
2982 MachineInstrBuilder SIInstrInfo::buildIndirectRead(
2983 MachineBasicBlock *MBB,
2984 MachineBasicBlock::iterator I,
2986 unsigned Address, unsigned OffsetReg) const {
2987 const DebugLoc &DL = MBB->findDebugLoc(I);
2988 unsigned IndirectBaseReg = AMDGPU::VGPR_32RegClass.getRegister(
2989 getIndirectIndexBegin(*MBB->getParent()));
2991 return BuildMI(*MBB, I, DL, get(AMDGPU::SI_INDIRECT_SRC_V1))
2992 .addOperand(I->getOperand(0))
2993 .addOperand(I->getOperand(1))
2994 .addReg(IndirectBaseReg)
3000 void SIInstrInfo::reserveIndirectRegisters(BitVector &Reserved,
3001 const MachineFunction &MF) const {
3002 int End = getIndirectIndexEnd(MF);
3003 int Begin = getIndirectIndexBegin(MF);
3009 for (int Index = Begin; Index <= End; ++Index)
3010 Reserved.set(AMDGPU::VGPR_32RegClass.getRegister(Index));
3012 for (int Index = std::max(0, Begin - 1); Index <= End; ++Index)
3013 Reserved.set(AMDGPU::VReg_64RegClass.getRegister(Index));
3015 for (int Index = std::max(0, Begin - 2); Index <= End; ++Index)
3016 Reserved.set(AMDGPU::VReg_96RegClass.getRegister(Index));
3018 for (int Index = std::max(0, Begin - 3); Index <= End; ++Index)
3019 Reserved.set(AMDGPU::VReg_128RegClass.getRegister(Index));
3021 for (int Index = std::max(0, Begin - 7); Index <= End; ++Index)
3022 Reserved.set(AMDGPU::VReg_256RegClass.getRegister(Index));
3024 for (int Index = std::max(0, Begin - 15); Index <= End; ++Index)
3025 Reserved.set(AMDGPU::VReg_512RegClass.getRegister(Index));
3028 MachineOperand *SIInstrInfo::getNamedOperand(MachineInstr &MI,
3029 unsigned OperandName) const {
3030 int Idx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), OperandName);
3034 return &MI.getOperand(Idx);
3037 uint64_t SIInstrInfo::getDefaultRsrcDataFormat() const {
3038 uint64_t RsrcDataFormat = AMDGPU::RSRC_DATA_FORMAT;
3039 if (ST.isAmdHsaOS()) {
3040 RsrcDataFormat |= (1ULL << 56);
3042 if (ST.getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS)
3044 RsrcDataFormat |= (2ULL << 59);
3047 return RsrcDataFormat;
3050 uint64_t SIInstrInfo::getScratchRsrcWords23() const {
3051 uint64_t Rsrc23 = getDefaultRsrcDataFormat() |
3052 AMDGPU::RSRC_TID_ENABLE |
3053 0xffffffff; // Size;
3055 // If TID_ENABLE is set, DATA_FORMAT specifies stride bits [14:17].
3056 // Clear them unless we want a huge stride.
3057 if (ST.getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS)
3058 Rsrc23 &= ~AMDGPU::RSRC_DATA_FORMAT;