1 //===-- SIInstrInfo.cpp - SI Instruction Information ---------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// \brief SI Implementation of TargetInstrInfo.
13 //===----------------------------------------------------------------------===//
16 #include "SIInstrInfo.h"
17 #include "AMDGPUTargetMachine.h"
18 #include "SIDefines.h"
19 #include "SIMachineFunctionInfo.h"
20 #include "llvm/CodeGen/MachineFrameInfo.h"
21 #include "llvm/CodeGen/MachineInstrBuilder.h"
22 #include "llvm/CodeGen/MachineRegisterInfo.h"
23 #include "llvm/IR/Function.h"
24 #include "llvm/CodeGen/RegisterScavenging.h"
25 #include "llvm/MC/MCInstrDesc.h"
26 #include "llvm/Support/Debug.h"
30 SIInstrInfo::SIInstrInfo(const AMDGPUSubtarget &st)
31 : AMDGPUInstrInfo(st), RI() {}
33 //===----------------------------------------------------------------------===//
34 // TargetInstrInfo callbacks
35 //===----------------------------------------------------------------------===//
37 static unsigned getNumOperandsNoGlue(SDNode *Node) {
38 unsigned N = Node->getNumOperands();
39 while (N && Node->getOperand(N - 1).getValueType() == MVT::Glue)
44 static SDValue findChainOperand(SDNode *Load) {
45 SDValue LastOp = Load->getOperand(getNumOperandsNoGlue(Load) - 1);
46 assert(LastOp.getValueType() == MVT::Other && "Chain missing from load node");
50 /// \brief Returns true if both nodes have the same value for the given
51 /// operand \p Op, or if both nodes do not have this operand.
52 static bool nodesHaveSameOperandValue(SDNode *N0, SDNode* N1, unsigned OpName) {
53 unsigned Opc0 = N0->getMachineOpcode();
54 unsigned Opc1 = N1->getMachineOpcode();
56 int Op0Idx = AMDGPU::getNamedOperandIdx(Opc0, OpName);
57 int Op1Idx = AMDGPU::getNamedOperandIdx(Opc1, OpName);
59 if (Op0Idx == -1 && Op1Idx == -1)
63 if ((Op0Idx == -1 && Op1Idx != -1) ||
64 (Op1Idx == -1 && Op0Idx != -1))
67 // getNamedOperandIdx returns the index for the MachineInstr's operands,
68 // which includes the result as the first operand. We are indexing into the
69 // MachineSDNode's operands, so we need to skip the result operand to get
74 return N0->getOperand(Op0Idx) == N1->getOperand(Op1Idx);
77 bool SIInstrInfo::isReallyTriviallyReMaterializable(const MachineInstr *MI,
78 AliasAnalysis *AA) const {
79 // TODO: The generic check fails for VALU instructions that should be
80 // rematerializable due to implicit reads of exec. We really want all of the
81 // generic logic for this except for this.
82 switch (MI->getOpcode()) {
83 case AMDGPU::V_MOV_B32_e32:
84 case AMDGPU::V_MOV_B32_e64:
85 case AMDGPU::V_MOV_B64_PSEUDO:
92 bool SIInstrInfo::areLoadsFromSameBasePtr(SDNode *Load0, SDNode *Load1,
94 int64_t &Offset1) const {
95 if (!Load0->isMachineOpcode() || !Load1->isMachineOpcode())
98 unsigned Opc0 = Load0->getMachineOpcode();
99 unsigned Opc1 = Load1->getMachineOpcode();
101 // Make sure both are actually loads.
102 if (!get(Opc0).mayLoad() || !get(Opc1).mayLoad())
105 if (isDS(Opc0) && isDS(Opc1)) {
107 // FIXME: Handle this case:
108 if (getNumOperandsNoGlue(Load0) != getNumOperandsNoGlue(Load1))
112 if (Load0->getOperand(1) != Load1->getOperand(1))
116 if (findChainOperand(Load0) != findChainOperand(Load1))
119 // Skip read2 / write2 variants for simplicity.
120 // TODO: We should report true if the used offsets are adjacent (excluded
122 if (AMDGPU::getNamedOperandIdx(Opc0, AMDGPU::OpName::data1) != -1 ||
123 AMDGPU::getNamedOperandIdx(Opc1, AMDGPU::OpName::data1) != -1)
126 Offset0 = cast<ConstantSDNode>(Load0->getOperand(2))->getZExtValue();
127 Offset1 = cast<ConstantSDNode>(Load1->getOperand(2))->getZExtValue();
131 if (isSMRD(Opc0) && isSMRD(Opc1)) {
132 assert(getNumOperandsNoGlue(Load0) == getNumOperandsNoGlue(Load1));
135 if (Load0->getOperand(0) != Load1->getOperand(0))
138 const ConstantSDNode *Load0Offset =
139 dyn_cast<ConstantSDNode>(Load0->getOperand(1));
140 const ConstantSDNode *Load1Offset =
141 dyn_cast<ConstantSDNode>(Load1->getOperand(1));
143 if (!Load0Offset || !Load1Offset)
147 if (findChainOperand(Load0) != findChainOperand(Load1))
150 Offset0 = Load0Offset->getZExtValue();
151 Offset1 = Load1Offset->getZExtValue();
155 // MUBUF and MTBUF can access the same addresses.
156 if ((isMUBUF(Opc0) || isMTBUF(Opc0)) && (isMUBUF(Opc1) || isMTBUF(Opc1))) {
158 // MUBUF and MTBUF have vaddr at different indices.
159 if (!nodesHaveSameOperandValue(Load0, Load1, AMDGPU::OpName::soffset) ||
160 findChainOperand(Load0) != findChainOperand(Load1) ||
161 !nodesHaveSameOperandValue(Load0, Load1, AMDGPU::OpName::vaddr) ||
162 !nodesHaveSameOperandValue(Load0, Load1, AMDGPU::OpName::srsrc))
165 int OffIdx0 = AMDGPU::getNamedOperandIdx(Opc0, AMDGPU::OpName::offset);
166 int OffIdx1 = AMDGPU::getNamedOperandIdx(Opc1, AMDGPU::OpName::offset);
168 if (OffIdx0 == -1 || OffIdx1 == -1)
171 // getNamedOperandIdx returns the index for MachineInstrs. Since they
172 // inlcude the output in the operand list, but SDNodes don't, we need to
173 // subtract the index by one.
177 SDValue Off0 = Load0->getOperand(OffIdx0);
178 SDValue Off1 = Load1->getOperand(OffIdx1);
180 // The offset might be a FrameIndexSDNode.
181 if (!isa<ConstantSDNode>(Off0) || !isa<ConstantSDNode>(Off1))
184 Offset0 = cast<ConstantSDNode>(Off0)->getZExtValue();
185 Offset1 = cast<ConstantSDNode>(Off1)->getZExtValue();
192 static bool isStride64(unsigned Opc) {
194 case AMDGPU::DS_READ2ST64_B32:
195 case AMDGPU::DS_READ2ST64_B64:
196 case AMDGPU::DS_WRITE2ST64_B32:
197 case AMDGPU::DS_WRITE2ST64_B64:
204 bool SIInstrInfo::getMemOpBaseRegImmOfs(MachineInstr *LdSt, unsigned &BaseReg,
206 const TargetRegisterInfo *TRI) const {
207 unsigned Opc = LdSt->getOpcode();
210 const MachineOperand *OffsetImm = getNamedOperand(*LdSt,
211 AMDGPU::OpName::offset);
213 // Normal, single offset LDS instruction.
214 const MachineOperand *AddrReg = getNamedOperand(*LdSt,
215 AMDGPU::OpName::addr);
217 BaseReg = AddrReg->getReg();
218 Offset = OffsetImm->getImm();
222 // The 2 offset instructions use offset0 and offset1 instead. We can treat
223 // these as a load with a single offset if the 2 offsets are consecutive. We
224 // will use this for some partially aligned loads.
225 const MachineOperand *Offset0Imm = getNamedOperand(*LdSt,
226 AMDGPU::OpName::offset0);
227 const MachineOperand *Offset1Imm = getNamedOperand(*LdSt,
228 AMDGPU::OpName::offset1);
230 uint8_t Offset0 = Offset0Imm->getImm();
231 uint8_t Offset1 = Offset1Imm->getImm();
233 if (Offset1 > Offset0 && Offset1 - Offset0 == 1) {
234 // Each of these offsets is in element sized units, so we need to convert
235 // to bytes of the individual reads.
239 EltSize = getOpRegClass(*LdSt, 0)->getSize() / 2;
241 assert(LdSt->mayStore());
242 int Data0Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::data0);
243 EltSize = getOpRegClass(*LdSt, Data0Idx)->getSize();
249 const MachineOperand *AddrReg = getNamedOperand(*LdSt,
250 AMDGPU::OpName::addr);
251 BaseReg = AddrReg->getReg();
252 Offset = EltSize * Offset0;
259 if (isMUBUF(*LdSt) || isMTBUF(*LdSt)) {
260 if (AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::soffset) != -1)
263 const MachineOperand *AddrReg = getNamedOperand(*LdSt,
264 AMDGPU::OpName::vaddr);
268 const MachineOperand *OffsetImm = getNamedOperand(*LdSt,
269 AMDGPU::OpName::offset);
270 BaseReg = AddrReg->getReg();
271 Offset = OffsetImm->getImm();
276 const MachineOperand *OffsetImm = getNamedOperand(*LdSt,
277 AMDGPU::OpName::offset);
281 const MachineOperand *SBaseReg = getNamedOperand(*LdSt,
282 AMDGPU::OpName::sbase);
283 BaseReg = SBaseReg->getReg();
284 Offset = OffsetImm->getImm();
291 bool SIInstrInfo::shouldClusterLoads(MachineInstr *FirstLdSt,
292 MachineInstr *SecondLdSt,
293 unsigned NumLoads) const {
294 // TODO: This needs finer tuning
298 if (isDS(*FirstLdSt) && isDS(*SecondLdSt))
301 if (isSMRD(*FirstLdSt) && isSMRD(*SecondLdSt))
304 if ((isMUBUF(*FirstLdSt) || isMTBUF(*FirstLdSt)) &&
305 (isMUBUF(*SecondLdSt) || isMTBUF(*SecondLdSt)))
312 SIInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
313 MachineBasicBlock::iterator MI, DebugLoc DL,
314 unsigned DestReg, unsigned SrcReg,
315 bool KillSrc) const {
317 // If we are trying to copy to or from SCC, there is a bug somewhere else in
318 // the backend. While it may be theoretically possible to do this, it should
319 // never be necessary.
320 assert(DestReg != AMDGPU::SCC && SrcReg != AMDGPU::SCC);
322 static const int16_t Sub0_15[] = {
323 AMDGPU::sub0, AMDGPU::sub1, AMDGPU::sub2, AMDGPU::sub3,
324 AMDGPU::sub4, AMDGPU::sub5, AMDGPU::sub6, AMDGPU::sub7,
325 AMDGPU::sub8, AMDGPU::sub9, AMDGPU::sub10, AMDGPU::sub11,
326 AMDGPU::sub12, AMDGPU::sub13, AMDGPU::sub14, AMDGPU::sub15, 0
329 static const int16_t Sub0_7[] = {
330 AMDGPU::sub0, AMDGPU::sub1, AMDGPU::sub2, AMDGPU::sub3,
331 AMDGPU::sub4, AMDGPU::sub5, AMDGPU::sub6, AMDGPU::sub7, 0
334 static const int16_t Sub0_3[] = {
335 AMDGPU::sub0, AMDGPU::sub1, AMDGPU::sub2, AMDGPU::sub3, 0
338 static const int16_t Sub0_2[] = {
339 AMDGPU::sub0, AMDGPU::sub1, AMDGPU::sub2, 0
342 static const int16_t Sub0_1[] = {
343 AMDGPU::sub0, AMDGPU::sub1, 0
347 const int16_t *SubIndices;
349 if (AMDGPU::SReg_32RegClass.contains(DestReg)) {
350 assert(AMDGPU::SReg_32RegClass.contains(SrcReg));
351 BuildMI(MBB, MI, DL, get(AMDGPU::S_MOV_B32), DestReg)
352 .addReg(SrcReg, getKillRegState(KillSrc));
355 } else if (AMDGPU::SReg_64RegClass.contains(DestReg)) {
356 if (DestReg == AMDGPU::VCC) {
357 if (AMDGPU::SReg_64RegClass.contains(SrcReg)) {
358 BuildMI(MBB, MI, DL, get(AMDGPU::S_MOV_B64), AMDGPU::VCC)
359 .addReg(SrcReg, getKillRegState(KillSrc));
361 // FIXME: Hack until VReg_1 removed.
362 assert(AMDGPU::VGPR_32RegClass.contains(SrcReg));
363 BuildMI(MBB, MI, DL, get(AMDGPU::V_CMP_NE_I32_e32))
365 .addReg(SrcReg, getKillRegState(KillSrc));
371 assert(AMDGPU::SReg_64RegClass.contains(SrcReg));
372 BuildMI(MBB, MI, DL, get(AMDGPU::S_MOV_B64), DestReg)
373 .addReg(SrcReg, getKillRegState(KillSrc));
376 } else if (AMDGPU::SReg_128RegClass.contains(DestReg)) {
377 assert(AMDGPU::SReg_128RegClass.contains(SrcReg));
378 Opcode = AMDGPU::S_MOV_B32;
381 } else if (AMDGPU::SReg_256RegClass.contains(DestReg)) {
382 assert(AMDGPU::SReg_256RegClass.contains(SrcReg));
383 Opcode = AMDGPU::S_MOV_B32;
386 } else if (AMDGPU::SReg_512RegClass.contains(DestReg)) {
387 assert(AMDGPU::SReg_512RegClass.contains(SrcReg));
388 Opcode = AMDGPU::S_MOV_B32;
389 SubIndices = Sub0_15;
391 } else if (AMDGPU::VGPR_32RegClass.contains(DestReg)) {
392 assert(AMDGPU::VGPR_32RegClass.contains(SrcReg) ||
393 AMDGPU::SReg_32RegClass.contains(SrcReg));
394 BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), DestReg)
395 .addReg(SrcReg, getKillRegState(KillSrc));
398 } else if (AMDGPU::VReg_64RegClass.contains(DestReg)) {
399 assert(AMDGPU::VReg_64RegClass.contains(SrcReg) ||
400 AMDGPU::SReg_64RegClass.contains(SrcReg));
401 Opcode = AMDGPU::V_MOV_B32_e32;
404 } else if (AMDGPU::VReg_96RegClass.contains(DestReg)) {
405 assert(AMDGPU::VReg_96RegClass.contains(SrcReg));
406 Opcode = AMDGPU::V_MOV_B32_e32;
409 } else if (AMDGPU::VReg_128RegClass.contains(DestReg)) {
410 assert(AMDGPU::VReg_128RegClass.contains(SrcReg) ||
411 AMDGPU::SReg_128RegClass.contains(SrcReg));
412 Opcode = AMDGPU::V_MOV_B32_e32;
415 } else if (AMDGPU::VReg_256RegClass.contains(DestReg)) {
416 assert(AMDGPU::VReg_256RegClass.contains(SrcReg) ||
417 AMDGPU::SReg_256RegClass.contains(SrcReg));
418 Opcode = AMDGPU::V_MOV_B32_e32;
421 } else if (AMDGPU::VReg_512RegClass.contains(DestReg)) {
422 assert(AMDGPU::VReg_512RegClass.contains(SrcReg) ||
423 AMDGPU::SReg_512RegClass.contains(SrcReg));
424 Opcode = AMDGPU::V_MOV_B32_e32;
425 SubIndices = Sub0_15;
428 llvm_unreachable("Can't copy register!");
431 while (unsigned SubIdx = *SubIndices++) {
432 MachineInstrBuilder Builder = BuildMI(MBB, MI, DL,
433 get(Opcode), RI.getSubReg(DestReg, SubIdx));
435 Builder.addReg(RI.getSubReg(SrcReg, SubIdx), getKillRegState(KillSrc));
438 Builder.addReg(DestReg, RegState::Define | RegState::Implicit);
442 int SIInstrInfo::commuteOpcode(const MachineInstr &MI) const {
443 const unsigned Opcode = MI.getOpcode();
447 // Try to map original to commuted opcode
448 NewOpc = AMDGPU::getCommuteRev(Opcode);
450 // Check if the commuted (REV) opcode exists on the target.
451 return pseudoToMCOpcode(NewOpc) != -1 ? NewOpc : -1;
453 // Try to map commuted to original opcode
454 NewOpc = AMDGPU::getCommuteOrig(Opcode);
456 // Check if the original (non-REV) opcode exists on the target.
457 return pseudoToMCOpcode(NewOpc) != -1 ? NewOpc : -1;
462 unsigned SIInstrInfo::getMovOpcode(const TargetRegisterClass *DstRC) const {
464 if (DstRC->getSize() == 4) {
465 return RI.isSGPRClass(DstRC) ? AMDGPU::S_MOV_B32 : AMDGPU::V_MOV_B32_e32;
466 } else if (DstRC->getSize() == 8 && RI.isSGPRClass(DstRC)) {
467 return AMDGPU::S_MOV_B64;
468 } else if (DstRC->getSize() == 8 && !RI.isSGPRClass(DstRC)) {
469 return AMDGPU::V_MOV_B64_PSEUDO;
474 static unsigned getSGPRSpillSaveOpcode(unsigned Size) {
477 return AMDGPU::SI_SPILL_S32_SAVE;
479 return AMDGPU::SI_SPILL_S64_SAVE;
481 return AMDGPU::SI_SPILL_S128_SAVE;
483 return AMDGPU::SI_SPILL_S256_SAVE;
485 return AMDGPU::SI_SPILL_S512_SAVE;
487 llvm_unreachable("unknown register size");
491 static unsigned getVGPRSpillSaveOpcode(unsigned Size) {
494 return AMDGPU::SI_SPILL_V32_SAVE;
496 return AMDGPU::SI_SPILL_V64_SAVE;
498 return AMDGPU::SI_SPILL_V128_SAVE;
500 return AMDGPU::SI_SPILL_V256_SAVE;
502 return AMDGPU::SI_SPILL_V512_SAVE;
504 llvm_unreachable("unknown register size");
508 void SIInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
509 MachineBasicBlock::iterator MI,
510 unsigned SrcReg, bool isKill,
512 const TargetRegisterClass *RC,
513 const TargetRegisterInfo *TRI) const {
514 MachineFunction *MF = MBB.getParent();
515 SIMachineFunctionInfo *MFI = MF->getInfo<SIMachineFunctionInfo>();
516 MachineFrameInfo *FrameInfo = MF->getFrameInfo();
517 DebugLoc DL = MBB.findDebugLoc(MI);
519 unsigned Size = FrameInfo->getObjectSize(FrameIndex);
520 unsigned Align = FrameInfo->getObjectAlignment(FrameIndex);
521 MachinePointerInfo PtrInfo
522 = MachinePointerInfo::getFixedStack(*MF, FrameIndex);
523 MachineMemOperand *MMO
524 = MF->getMachineMemOperand(PtrInfo, MachineMemOperand::MOStore,
527 if (RI.isSGPRClass(RC)) {
528 MFI->setHasSpilledSGPRs();
530 // We are only allowed to create one new instruction when spilling
531 // registers, so we need to use pseudo instruction for spilling
533 unsigned Opcode = getSGPRSpillSaveOpcode(RC->getSize());
534 BuildMI(MBB, MI, DL, get(Opcode))
535 .addReg(SrcReg) // src
536 .addFrameIndex(FrameIndex) // frame_idx
542 if (!ST.isVGPRSpillingEnabled(MFI)) {
543 LLVMContext &Ctx = MF->getFunction()->getContext();
544 Ctx.emitError("SIInstrInfo::storeRegToStackSlot - Do not know how to"
546 BuildMI(MBB, MI, DL, get(AMDGPU::KILL))
552 assert(RI.hasVGPRs(RC) && "Only VGPR spilling expected");
554 unsigned Opcode = getVGPRSpillSaveOpcode(RC->getSize());
555 MFI->setHasSpilledVGPRs();
556 BuildMI(MBB, MI, DL, get(Opcode))
557 .addReg(SrcReg) // src
558 .addFrameIndex(FrameIndex) // frame_idx
559 .addReg(MFI->getScratchRSrcReg()) // scratch_rsrc
560 .addReg(MFI->getScratchWaveOffsetReg()) // scratch_offset
564 static unsigned getSGPRSpillRestoreOpcode(unsigned Size) {
567 return AMDGPU::SI_SPILL_S32_RESTORE;
569 return AMDGPU::SI_SPILL_S64_RESTORE;
571 return AMDGPU::SI_SPILL_S128_RESTORE;
573 return AMDGPU::SI_SPILL_S256_RESTORE;
575 return AMDGPU::SI_SPILL_S512_RESTORE;
577 llvm_unreachable("unknown register size");
581 static unsigned getVGPRSpillRestoreOpcode(unsigned Size) {
584 return AMDGPU::SI_SPILL_V32_RESTORE;
586 return AMDGPU::SI_SPILL_V64_RESTORE;
588 return AMDGPU::SI_SPILL_V128_RESTORE;
590 return AMDGPU::SI_SPILL_V256_RESTORE;
592 return AMDGPU::SI_SPILL_V512_RESTORE;
594 llvm_unreachable("unknown register size");
598 void SIInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
599 MachineBasicBlock::iterator MI,
600 unsigned DestReg, int FrameIndex,
601 const TargetRegisterClass *RC,
602 const TargetRegisterInfo *TRI) const {
603 MachineFunction *MF = MBB.getParent();
604 const SIMachineFunctionInfo *MFI = MF->getInfo<SIMachineFunctionInfo>();
605 MachineFrameInfo *FrameInfo = MF->getFrameInfo();
606 DebugLoc DL = MBB.findDebugLoc(MI);
607 unsigned Align = FrameInfo->getObjectAlignment(FrameIndex);
608 unsigned Size = FrameInfo->getObjectSize(FrameIndex);
610 MachinePointerInfo PtrInfo
611 = MachinePointerInfo::getFixedStack(*MF, FrameIndex);
613 MachineMemOperand *MMO = MF->getMachineMemOperand(
614 PtrInfo, MachineMemOperand::MOLoad, Size, Align);
616 if (RI.isSGPRClass(RC)) {
617 // FIXME: Maybe this should not include a memoperand because it will be
618 // lowered to non-memory instructions.
619 unsigned Opcode = getSGPRSpillRestoreOpcode(RC->getSize());
620 BuildMI(MBB, MI, DL, get(Opcode), DestReg)
621 .addFrameIndex(FrameIndex) // frame_idx
627 if (!ST.isVGPRSpillingEnabled(MFI)) {
628 LLVMContext &Ctx = MF->getFunction()->getContext();
629 Ctx.emitError("SIInstrInfo::loadRegFromStackSlot - Do not know how to"
630 " restore register");
631 BuildMI(MBB, MI, DL, get(AMDGPU::IMPLICIT_DEF), DestReg);
636 assert(RI.hasVGPRs(RC) && "Only VGPR spilling expected");
638 unsigned Opcode = getVGPRSpillRestoreOpcode(RC->getSize());
639 BuildMI(MBB, MI, DL, get(Opcode), DestReg)
640 .addFrameIndex(FrameIndex) // frame_idx
641 .addReg(MFI->getScratchRSrcReg()) // scratch_rsrc
642 .addReg(MFI->getScratchWaveOffsetReg()) // scratch_offset
646 /// \param @Offset Offset in bytes of the FrameIndex being spilled
647 unsigned SIInstrInfo::calculateLDSSpillAddress(MachineBasicBlock &MBB,
648 MachineBasicBlock::iterator MI,
649 RegScavenger *RS, unsigned TmpReg,
650 unsigned FrameOffset,
651 unsigned Size) const {
652 MachineFunction *MF = MBB.getParent();
653 SIMachineFunctionInfo *MFI = MF->getInfo<SIMachineFunctionInfo>();
654 const AMDGPUSubtarget &ST = MF->getSubtarget<AMDGPUSubtarget>();
655 const SIRegisterInfo *TRI =
656 static_cast<const SIRegisterInfo*>(ST.getRegisterInfo());
657 DebugLoc DL = MBB.findDebugLoc(MI);
658 unsigned WorkGroupSize = MFI->getMaximumWorkGroupSize(*MF);
659 unsigned WavefrontSize = ST.getWavefrontSize();
661 unsigned TIDReg = MFI->getTIDReg();
662 if (!MFI->hasCalculatedTID()) {
663 MachineBasicBlock &Entry = MBB.getParent()->front();
664 MachineBasicBlock::iterator Insert = Entry.front();
665 DebugLoc DL = Insert->getDebugLoc();
667 TIDReg = RI.findUnusedRegister(MF->getRegInfo(), &AMDGPU::VGPR_32RegClass);
668 if (TIDReg == AMDGPU::NoRegister)
672 if (MFI->getShaderType() == ShaderType::COMPUTE &&
673 WorkGroupSize > WavefrontSize) {
676 = TRI->getPreloadedValue(*MF, SIRegisterInfo::WORKGROUP_ID_X);
678 = TRI->getPreloadedValue(*MF, SIRegisterInfo::WORKGROUP_ID_Y);
680 = TRI->getPreloadedValue(*MF, SIRegisterInfo::WORKGROUP_ID_Z);
681 unsigned InputPtrReg =
682 TRI->getPreloadedValue(*MF, SIRegisterInfo::KERNARG_SEGMENT_PTR);
683 for (unsigned Reg : {TIDIGXReg, TIDIGYReg, TIDIGZReg}) {
684 if (!Entry.isLiveIn(Reg))
685 Entry.addLiveIn(Reg);
688 RS->enterBasicBlock(&Entry);
689 // FIXME: Can we scavenge an SReg_64 and access the subregs?
690 unsigned STmp0 = RS->scavengeRegister(&AMDGPU::SGPR_32RegClass, 0);
691 unsigned STmp1 = RS->scavengeRegister(&AMDGPU::SGPR_32RegClass, 0);
692 BuildMI(Entry, Insert, DL, get(AMDGPU::S_LOAD_DWORD_IMM), STmp0)
694 .addImm(SI::KernelInputOffsets::NGROUPS_Z);
695 BuildMI(Entry, Insert, DL, get(AMDGPU::S_LOAD_DWORD_IMM), STmp1)
697 .addImm(SI::KernelInputOffsets::NGROUPS_Y);
699 // NGROUPS.X * NGROUPS.Y
700 BuildMI(Entry, Insert, DL, get(AMDGPU::S_MUL_I32), STmp1)
703 // (NGROUPS.X * NGROUPS.Y) * TIDIG.X
704 BuildMI(Entry, Insert, DL, get(AMDGPU::V_MUL_U32_U24_e32), TIDReg)
707 // NGROUPS.Z * TIDIG.Y + (NGROUPS.X * NGROPUS.Y * TIDIG.X)
708 BuildMI(Entry, Insert, DL, get(AMDGPU::V_MAD_U32_U24), TIDReg)
712 // (NGROUPS.Z * TIDIG.Y + (NGROUPS.X * NGROPUS.Y * TIDIG.X)) + TIDIG.Z
713 BuildMI(Entry, Insert, DL, get(AMDGPU::V_ADD_I32_e32), TIDReg)
718 BuildMI(Entry, Insert, DL, get(AMDGPU::V_MBCNT_LO_U32_B32_e64),
723 BuildMI(Entry, Insert, DL, get(AMDGPU::V_MBCNT_HI_U32_B32_e64),
729 BuildMI(Entry, Insert, DL, get(AMDGPU::V_LSHLREV_B32_e32),
733 MFI->setTIDReg(TIDReg);
736 // Add FrameIndex to LDS offset
737 unsigned LDSOffset = MFI->LDSSize + (FrameOffset * WorkGroupSize);
738 BuildMI(MBB, MI, DL, get(AMDGPU::V_ADD_I32_e32), TmpReg)
745 void SIInstrInfo::insertNOPs(MachineBasicBlock::iterator MI,
754 BuildMI(*MI->getParent(), MI, MI->getDebugLoc(), get(AMDGPU::S_NOP))
759 bool SIInstrInfo::expandPostRAPseudo(MachineBasicBlock::iterator MI) const {
760 MachineBasicBlock &MBB = *MI->getParent();
761 DebugLoc DL = MBB.findDebugLoc(MI);
762 switch (MI->getOpcode()) {
763 default: return AMDGPUInstrInfo::expandPostRAPseudo(MI);
765 case AMDGPU::SGPR_USE:
766 // This is just a placeholder for register allocation.
767 MI->eraseFromParent();
770 case AMDGPU::V_MOV_B64_PSEUDO: {
771 unsigned Dst = MI->getOperand(0).getReg();
772 unsigned DstLo = RI.getSubReg(Dst, AMDGPU::sub0);
773 unsigned DstHi = RI.getSubReg(Dst, AMDGPU::sub1);
775 const MachineOperand &SrcOp = MI->getOperand(1);
776 // FIXME: Will this work for 64-bit floating point immediates?
777 assert(!SrcOp.isFPImm());
779 APInt Imm(64, SrcOp.getImm());
780 BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), DstLo)
781 .addImm(Imm.getLoBits(32).getZExtValue())
782 .addReg(Dst, RegState::Implicit);
783 BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), DstHi)
784 .addImm(Imm.getHiBits(32).getZExtValue())
785 .addReg(Dst, RegState::Implicit);
787 assert(SrcOp.isReg());
788 BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), DstLo)
789 .addReg(RI.getSubReg(SrcOp.getReg(), AMDGPU::sub0))
790 .addReg(Dst, RegState::Implicit);
791 BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), DstHi)
792 .addReg(RI.getSubReg(SrcOp.getReg(), AMDGPU::sub1))
793 .addReg(Dst, RegState::Implicit);
795 MI->eraseFromParent();
799 case AMDGPU::V_CNDMASK_B64_PSEUDO: {
800 unsigned Dst = MI->getOperand(0).getReg();
801 unsigned DstLo = RI.getSubReg(Dst, AMDGPU::sub0);
802 unsigned DstHi = RI.getSubReg(Dst, AMDGPU::sub1);
803 unsigned Src0 = MI->getOperand(1).getReg();
804 unsigned Src1 = MI->getOperand(2).getReg();
805 const MachineOperand &SrcCond = MI->getOperand(3);
807 BuildMI(MBB, MI, DL, get(AMDGPU::V_CNDMASK_B32_e64), DstLo)
808 .addReg(RI.getSubReg(Src0, AMDGPU::sub0))
809 .addReg(RI.getSubReg(Src1, AMDGPU::sub0))
810 .addOperand(SrcCond);
811 BuildMI(MBB, MI, DL, get(AMDGPU::V_CNDMASK_B32_e64), DstHi)
812 .addReg(RI.getSubReg(Src0, AMDGPU::sub1))
813 .addReg(RI.getSubReg(Src1, AMDGPU::sub1))
814 .addOperand(SrcCond);
815 MI->eraseFromParent();
819 case AMDGPU::SI_CONSTDATA_PTR: {
820 const SIRegisterInfo *TRI =
821 static_cast<const SIRegisterInfo *>(ST.getRegisterInfo());
822 MachineFunction &MF = *MBB.getParent();
823 unsigned Reg = MI->getOperand(0).getReg();
824 unsigned RegLo = TRI->getSubReg(Reg, AMDGPU::sub0);
825 unsigned RegHi = TRI->getSubReg(Reg, AMDGPU::sub1);
827 // Create a bundle so these instructions won't be re-ordered by the
828 // post-RA scheduler.
829 MIBundleBuilder Bundler(MBB, MI);
830 Bundler.append(BuildMI(MF, DL, get(AMDGPU::S_GETPC_B64), Reg));
832 // Add 32-bit offset from this instruction to the start of the
834 Bundler.append(BuildMI(MF, DL, get(AMDGPU::S_ADD_U32), RegLo)
836 .addOperand(MI->getOperand(1)));
837 Bundler.append(BuildMI(MF, DL, get(AMDGPU::S_ADDC_U32), RegHi)
841 llvm::finalizeBundle(MBB, Bundler.begin());
843 MI->eraseFromParent();
850 /// Commutes the operands in the given instruction.
851 /// The commutable operands are specified by their indices OpIdx0 and OpIdx1.
853 /// Do not call this method for a non-commutable instruction or for
854 /// non-commutable pair of operand indices OpIdx0 and OpIdx1.
855 /// Even though the instruction is commutable, the method may still
856 /// fail to commute the operands, null pointer is returned in such cases.
857 MachineInstr *SIInstrInfo::commuteInstructionImpl(MachineInstr *MI,
860 unsigned OpIdx1) const {
861 int CommutedOpcode = commuteOpcode(*MI);
862 if (CommutedOpcode == -1)
865 int Src0Idx = AMDGPU::getNamedOperandIdx(MI->getOpcode(),
866 AMDGPU::OpName::src0);
867 MachineOperand &Src0 = MI->getOperand(Src0Idx);
871 int Src1Idx = AMDGPU::getNamedOperandIdx(MI->getOpcode(),
872 AMDGPU::OpName::src1);
874 if ((OpIdx0 != static_cast<unsigned>(Src0Idx) ||
875 OpIdx1 != static_cast<unsigned>(Src1Idx)) &&
876 (OpIdx0 != static_cast<unsigned>(Src1Idx) ||
877 OpIdx1 != static_cast<unsigned>(Src0Idx)))
880 MachineOperand &Src1 = MI->getOperand(Src1Idx);
884 const MCInstrDesc &InstrDesc = MI->getDesc();
885 // For VOP2 instructions, any operand type is valid to use for src0. Make
886 // sure we can use the src1 as src0.
888 // We could be stricter here and only allow commuting if there is a reason
889 // to do so. i.e. if both operands are VGPRs there is no real benefit,
890 // although MachineCSE attempts to find matches by commuting.
891 const MachineRegisterInfo &MRI = MI->getParent()->getParent()->getRegInfo();
892 if (!isLegalRegOperand(MRI, InstrDesc.OpInfo[Src1Idx], Src0))
897 // Allow commuting instructions with Imm operands.
898 if (NewMI || !Src1.isImm() ||
899 (!isVOP2(*MI) && !isVOP3(*MI))) {
902 // Be sure to copy the source modifiers to the right place.
903 if (MachineOperand *Src0Mods
904 = getNamedOperand(*MI, AMDGPU::OpName::src0_modifiers)) {
905 MachineOperand *Src1Mods
906 = getNamedOperand(*MI, AMDGPU::OpName::src1_modifiers);
908 int Src0ModsVal = Src0Mods->getImm();
909 if (!Src1Mods && Src0ModsVal != 0)
912 // XXX - This assert might be a lie. It might be useful to have a neg
913 // modifier with 0.0.
914 int Src1ModsVal = Src1Mods->getImm();
915 assert((Src1ModsVal == 0) && "Not expecting modifiers with immediates");
917 Src1Mods->setImm(Src0ModsVal);
918 Src0Mods->setImm(Src1ModsVal);
921 unsigned Reg = Src0.getReg();
922 unsigned SubReg = Src0.getSubReg();
924 Src0.ChangeToImmediate(Src1.getImm());
926 llvm_unreachable("Should only have immediates");
928 Src1.ChangeToRegister(Reg, false);
929 Src1.setSubReg(SubReg);
931 MI = TargetInstrInfo::commuteInstructionImpl(MI, NewMI, OpIdx0, OpIdx1);
935 MI->setDesc(get(CommutedOpcode));
940 // This needs to be implemented because the source modifiers may be inserted
941 // between the true commutable operands, and the base
942 // TargetInstrInfo::commuteInstruction uses it.
943 bool SIInstrInfo::findCommutedOpIndices(MachineInstr *MI,
945 unsigned &SrcOpIdx1) const {
946 const MCInstrDesc &MCID = MI->getDesc();
947 if (!MCID.isCommutable())
950 unsigned Opc = MI->getOpcode();
951 int Src0Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src0);
955 // FIXME: Workaround TargetInstrInfo::commuteInstruction asserting on
956 // immediate. Also, immediate src0 operand is not handled in
957 // SIInstrInfo::commuteInstruction();
958 if (!MI->getOperand(Src0Idx).isReg())
961 int Src1Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src1);
965 MachineOperand &Src1 = MI->getOperand(Src1Idx);
967 // SIInstrInfo::commuteInstruction() does support commuting the immediate
968 // operand src1 in 2 and 3 operand instructions.
969 if (!isVOP2(MI->getOpcode()) && !isVOP3(MI->getOpcode()))
971 } else if (Src1.isReg()) {
972 // If any source modifiers are set, the generic instruction commuting won't
973 // understand how to copy the source modifiers.
974 if (hasModifiersSet(*MI, AMDGPU::OpName::src0_modifiers) ||
975 hasModifiersSet(*MI, AMDGPU::OpName::src1_modifiers))
980 return fixCommutedOpIndices(SrcOpIdx0, SrcOpIdx1, Src0Idx, Src1Idx);
983 MachineInstr *SIInstrInfo::buildMovInstr(MachineBasicBlock *MBB,
984 MachineBasicBlock::iterator I,
986 unsigned SrcReg) const {
987 return BuildMI(*MBB, I, MBB->findDebugLoc(I), get(AMDGPU::V_MOV_B32_e32),
988 DstReg) .addReg(SrcReg);
991 bool SIInstrInfo::isMov(unsigned Opcode) const {
993 default: return false;
994 case AMDGPU::S_MOV_B32:
995 case AMDGPU::S_MOV_B64:
996 case AMDGPU::V_MOV_B32_e32:
997 case AMDGPU::V_MOV_B32_e64:
1002 static void removeModOperands(MachineInstr &MI) {
1003 unsigned Opc = MI.getOpcode();
1004 int Src0ModIdx = AMDGPU::getNamedOperandIdx(Opc,
1005 AMDGPU::OpName::src0_modifiers);
1006 int Src1ModIdx = AMDGPU::getNamedOperandIdx(Opc,
1007 AMDGPU::OpName::src1_modifiers);
1008 int Src2ModIdx = AMDGPU::getNamedOperandIdx(Opc,
1009 AMDGPU::OpName::src2_modifiers);
1011 MI.RemoveOperand(Src2ModIdx);
1012 MI.RemoveOperand(Src1ModIdx);
1013 MI.RemoveOperand(Src0ModIdx);
1016 bool SIInstrInfo::FoldImmediate(MachineInstr *UseMI, MachineInstr *DefMI,
1017 unsigned Reg, MachineRegisterInfo *MRI) const {
1018 if (!MRI->hasOneNonDBGUse(Reg))
1021 unsigned Opc = UseMI->getOpcode();
1022 if (Opc == AMDGPU::V_MAD_F32 || Opc == AMDGPU::V_MAC_F32_e64) {
1023 // Don't fold if we are using source modifiers. The new VOP2 instructions
1025 if (hasModifiersSet(*UseMI, AMDGPU::OpName::src0_modifiers) ||
1026 hasModifiersSet(*UseMI, AMDGPU::OpName::src1_modifiers) ||
1027 hasModifiersSet(*UseMI, AMDGPU::OpName::src2_modifiers)) {
1031 MachineOperand *Src0 = getNamedOperand(*UseMI, AMDGPU::OpName::src0);
1032 MachineOperand *Src1 = getNamedOperand(*UseMI, AMDGPU::OpName::src1);
1033 MachineOperand *Src2 = getNamedOperand(*UseMI, AMDGPU::OpName::src2);
1035 // Multiplied part is the constant: Use v_madmk_f32
1036 // We should only expect these to be on src0 due to canonicalizations.
1037 if (Src0->isReg() && Src0->getReg() == Reg) {
1038 if (!Src1->isReg() ||
1039 (Src1->isReg() && RI.isSGPRClass(MRI->getRegClass(Src1->getReg()))))
1042 if (!Src2->isReg() ||
1043 (Src2->isReg() && RI.isSGPRClass(MRI->getRegClass(Src2->getReg()))))
1046 // We need to do some weird looking operand shuffling since the madmk
1047 // operands are out of the normal expected order with the multiplied
1048 // constant as the last operand.
1050 // v_mad_f32 src0, src1, src2 -> v_madmk_f32 src0 * src2K + src1
1055 const int64_t Imm = DefMI->getOperand(1).getImm();
1057 // FIXME: This would be a lot easier if we could return a new instruction
1058 // instead of having to modify in place.
1060 // Remove these first since they are at the end.
1061 UseMI->RemoveOperand(AMDGPU::getNamedOperandIdx(Opc,
1062 AMDGPU::OpName::omod));
1063 UseMI->RemoveOperand(AMDGPU::getNamedOperandIdx(Opc,
1064 AMDGPU::OpName::clamp));
1066 unsigned Src1Reg = Src1->getReg();
1067 unsigned Src1SubReg = Src1->getSubReg();
1068 unsigned Src2Reg = Src2->getReg();
1069 unsigned Src2SubReg = Src2->getSubReg();
1070 Src0->setReg(Src1Reg);
1071 Src0->setSubReg(Src1SubReg);
1072 Src0->setIsKill(Src1->isKill());
1074 Src1->setReg(Src2Reg);
1075 Src1->setSubReg(Src2SubReg);
1076 Src1->setIsKill(Src2->isKill());
1078 if (Opc == AMDGPU::V_MAC_F32_e64) {
1079 UseMI->untieRegOperand(
1080 AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src2));
1083 Src2->ChangeToImmediate(Imm);
1085 removeModOperands(*UseMI);
1086 UseMI->setDesc(get(AMDGPU::V_MADMK_F32));
1088 bool DeleteDef = MRI->hasOneNonDBGUse(Reg);
1090 DefMI->eraseFromParent();
1095 // Added part is the constant: Use v_madak_f32
1096 if (Src2->isReg() && Src2->getReg() == Reg) {
1097 // Not allowed to use constant bus for another operand.
1098 // We can however allow an inline immediate as src0.
1099 if (!Src0->isImm() &&
1100 (Src0->isReg() && RI.isSGPRClass(MRI->getRegClass(Src0->getReg()))))
1103 if (!Src1->isReg() ||
1104 (Src1->isReg() && RI.isSGPRClass(MRI->getRegClass(Src1->getReg()))))
1107 const int64_t Imm = DefMI->getOperand(1).getImm();
1109 // FIXME: This would be a lot easier if we could return a new instruction
1110 // instead of having to modify in place.
1112 // Remove these first since they are at the end.
1113 UseMI->RemoveOperand(AMDGPU::getNamedOperandIdx(Opc,
1114 AMDGPU::OpName::omod));
1115 UseMI->RemoveOperand(AMDGPU::getNamedOperandIdx(Opc,
1116 AMDGPU::OpName::clamp));
1118 if (Opc == AMDGPU::V_MAC_F32_e64) {
1119 UseMI->untieRegOperand(
1120 AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src2));
1123 // ChangingToImmediate adds Src2 back to the instruction.
1124 Src2->ChangeToImmediate(Imm);
1126 // These come before src2.
1127 removeModOperands(*UseMI);
1128 UseMI->setDesc(get(AMDGPU::V_MADAK_F32));
1130 bool DeleteDef = MRI->hasOneNonDBGUse(Reg);
1132 DefMI->eraseFromParent();
1141 static bool offsetsDoNotOverlap(int WidthA, int OffsetA,
1142 int WidthB, int OffsetB) {
1143 int LowOffset = OffsetA < OffsetB ? OffsetA : OffsetB;
1144 int HighOffset = OffsetA < OffsetB ? OffsetB : OffsetA;
1145 int LowWidth = (LowOffset == OffsetA) ? WidthA : WidthB;
1146 return LowOffset + LowWidth <= HighOffset;
1149 bool SIInstrInfo::checkInstOffsetsDoNotOverlap(MachineInstr *MIa,
1150 MachineInstr *MIb) const {
1151 unsigned BaseReg0, Offset0;
1152 unsigned BaseReg1, Offset1;
1154 if (getMemOpBaseRegImmOfs(MIa, BaseReg0, Offset0, &RI) &&
1155 getMemOpBaseRegImmOfs(MIb, BaseReg1, Offset1, &RI)) {
1156 assert(MIa->hasOneMemOperand() && MIb->hasOneMemOperand() &&
1157 "read2 / write2 not expected here yet");
1158 unsigned Width0 = (*MIa->memoperands_begin())->getSize();
1159 unsigned Width1 = (*MIb->memoperands_begin())->getSize();
1160 if (BaseReg0 == BaseReg1 &&
1161 offsetsDoNotOverlap(Width0, Offset0, Width1, Offset1)) {
1169 bool SIInstrInfo::areMemAccessesTriviallyDisjoint(MachineInstr *MIa,
1171 AliasAnalysis *AA) const {
1172 assert(MIa && (MIa->mayLoad() || MIa->mayStore()) &&
1173 "MIa must load from or modify a memory location");
1174 assert(MIb && (MIb->mayLoad() || MIb->mayStore()) &&
1175 "MIb must load from or modify a memory location");
1177 if (MIa->hasUnmodeledSideEffects() || MIb->hasUnmodeledSideEffects())
1180 // XXX - Can we relax this between address spaces?
1181 if (MIa->hasOrderedMemoryRef() || MIb->hasOrderedMemoryRef())
1184 // TODO: Should we check the address space from the MachineMemOperand? That
1185 // would allow us to distinguish objects we know don't alias based on the
1186 // underlying address space, even if it was lowered to a different one,
1187 // e.g. private accesses lowered to use MUBUF instructions on a scratch
1191 return checkInstOffsetsDoNotOverlap(MIa, MIb);
1193 return !isFLAT(*MIb);
1196 if (isMUBUF(*MIa) || isMTBUF(*MIa)) {
1197 if (isMUBUF(*MIb) || isMTBUF(*MIb))
1198 return checkInstOffsetsDoNotOverlap(MIa, MIb);
1200 return !isFLAT(*MIb) && !isSMRD(*MIb);
1205 return checkInstOffsetsDoNotOverlap(MIa, MIb);
1207 return !isFLAT(*MIb) && !isMUBUF(*MIa) && !isMTBUF(*MIa);
1212 return checkInstOffsetsDoNotOverlap(MIa, MIb);
1220 MachineInstr *SIInstrInfo::convertToThreeAddress(MachineFunction::iterator &MBB,
1221 MachineBasicBlock::iterator &MI,
1222 LiveVariables *LV) const {
1224 switch (MI->getOpcode()) {
1225 default: return nullptr;
1226 case AMDGPU::V_MAC_F32_e64: break;
1227 case AMDGPU::V_MAC_F32_e32: {
1228 const MachineOperand *Src0 = getNamedOperand(*MI, AMDGPU::OpName::src0);
1229 if (Src0->isImm() && !isInlineConstant(*Src0, 4))
1235 const MachineOperand *Dst = getNamedOperand(*MI, AMDGPU::OpName::dst);
1236 const MachineOperand *Src0 = getNamedOperand(*MI, AMDGPU::OpName::src0);
1237 const MachineOperand *Src1 = getNamedOperand(*MI, AMDGPU::OpName::src1);
1238 const MachineOperand *Src2 = getNamedOperand(*MI, AMDGPU::OpName::src2);
1240 return BuildMI(*MBB, MI, MI->getDebugLoc(), get(AMDGPU::V_MAD_F32))
1242 .addImm(0) // Src0 mods
1244 .addImm(0) // Src1 mods
1246 .addImm(0) // Src mods
1252 bool SIInstrInfo::isInlineConstant(const APInt &Imm) const {
1253 int64_t SVal = Imm.getSExtValue();
1254 if (SVal >= -16 && SVal <= 64)
1257 if (Imm.getBitWidth() == 64) {
1258 uint64_t Val = Imm.getZExtValue();
1259 return (DoubleToBits(0.0) == Val) ||
1260 (DoubleToBits(1.0) == Val) ||
1261 (DoubleToBits(-1.0) == Val) ||
1262 (DoubleToBits(0.5) == Val) ||
1263 (DoubleToBits(-0.5) == Val) ||
1264 (DoubleToBits(2.0) == Val) ||
1265 (DoubleToBits(-2.0) == Val) ||
1266 (DoubleToBits(4.0) == Val) ||
1267 (DoubleToBits(-4.0) == Val);
1270 // The actual type of the operand does not seem to matter as long
1271 // as the bits match one of the inline immediate values. For example:
1273 // -nan has the hexadecimal encoding of 0xfffffffe which is -2 in decimal,
1274 // so it is a legal inline immediate.
1276 // 1065353216 has the hexadecimal encoding 0x3f800000 which is 1.0f in
1277 // floating-point, so it is a legal inline immediate.
1278 uint32_t Val = Imm.getZExtValue();
1280 return (FloatToBits(0.0f) == Val) ||
1281 (FloatToBits(1.0f) == Val) ||
1282 (FloatToBits(-1.0f) == Val) ||
1283 (FloatToBits(0.5f) == Val) ||
1284 (FloatToBits(-0.5f) == Val) ||
1285 (FloatToBits(2.0f) == Val) ||
1286 (FloatToBits(-2.0f) == Val) ||
1287 (FloatToBits(4.0f) == Val) ||
1288 (FloatToBits(-4.0f) == Val);
1291 bool SIInstrInfo::isInlineConstant(const MachineOperand &MO,
1292 unsigned OpSize) const {
1294 // MachineOperand provides no way to tell the true operand size, since it
1295 // only records a 64-bit value. We need to know the size to determine if a
1296 // 32-bit floating point immediate bit pattern is legal for an integer
1297 // immediate. It would be for any 32-bit integer operand, but would not be
1298 // for a 64-bit one.
1300 unsigned BitSize = 8 * OpSize;
1301 return isInlineConstant(APInt(BitSize, MO.getImm(), true));
1307 bool SIInstrInfo::isLiteralConstant(const MachineOperand &MO,
1308 unsigned OpSize) const {
1309 return MO.isImm() && !isInlineConstant(MO, OpSize);
1312 static bool compareMachineOp(const MachineOperand &Op0,
1313 const MachineOperand &Op1) {
1314 if (Op0.getType() != Op1.getType())
1317 switch (Op0.getType()) {
1318 case MachineOperand::MO_Register:
1319 return Op0.getReg() == Op1.getReg();
1320 case MachineOperand::MO_Immediate:
1321 return Op0.getImm() == Op1.getImm();
1323 llvm_unreachable("Didn't expect to be comparing these operand types");
1327 bool SIInstrInfo::isImmOperandLegal(const MachineInstr *MI, unsigned OpNo,
1328 const MachineOperand &MO) const {
1329 const MCOperandInfo &OpInfo = get(MI->getOpcode()).OpInfo[OpNo];
1331 assert(MO.isImm() || MO.isTargetIndex() || MO.isFI());
1333 if (OpInfo.OperandType == MCOI::OPERAND_IMMEDIATE)
1336 if (OpInfo.RegClass < 0)
1339 unsigned OpSize = RI.getRegClass(OpInfo.RegClass)->getSize();
1340 if (isLiteralConstant(MO, OpSize))
1341 return RI.opCanUseLiteralConstant(OpInfo.OperandType);
1343 return RI.opCanUseInlineConstant(OpInfo.OperandType);
1346 bool SIInstrInfo::hasVALU32BitEncoding(unsigned Opcode) const {
1347 int Op32 = AMDGPU::getVOPe32(Opcode);
1351 return pseudoToMCOpcode(Op32) != -1;
1354 bool SIInstrInfo::hasModifiers(unsigned Opcode) const {
1355 // The src0_modifier operand is present on all instructions
1356 // that have modifiers.
1358 return AMDGPU::getNamedOperandIdx(Opcode,
1359 AMDGPU::OpName::src0_modifiers) != -1;
1362 bool SIInstrInfo::hasModifiersSet(const MachineInstr &MI,
1363 unsigned OpName) const {
1364 const MachineOperand *Mods = getNamedOperand(MI, OpName);
1365 return Mods && Mods->getImm();
1368 bool SIInstrInfo::usesConstantBus(const MachineRegisterInfo &MRI,
1369 const MachineOperand &MO,
1370 unsigned OpSize) const {
1371 // Literal constants use the constant bus.
1372 if (isLiteralConstant(MO, OpSize))
1375 if (!MO.isReg() || !MO.isUse())
1378 if (TargetRegisterInfo::isVirtualRegister(MO.getReg()))
1379 return RI.isSGPRClass(MRI.getRegClass(MO.getReg()));
1381 // FLAT_SCR is just an SGPR pair.
1382 if (!MO.isImplicit() && (MO.getReg() == AMDGPU::FLAT_SCR))
1385 // EXEC register uses the constant bus.
1386 if (!MO.isImplicit() && MO.getReg() == AMDGPU::EXEC)
1389 // SGPRs use the constant bus
1390 if (MO.getReg() == AMDGPU::M0 || MO.getReg() == AMDGPU::VCC ||
1391 (!MO.isImplicit() &&
1392 (AMDGPU::SGPR_32RegClass.contains(MO.getReg()) ||
1393 AMDGPU::SGPR_64RegClass.contains(MO.getReg())))) {
1400 static unsigned findImplicitSGPRRead(const MachineInstr &MI) {
1401 for (const MachineOperand &MO : MI.implicit_operands()) {
1402 // We only care about reads.
1406 switch (MO.getReg()) {
1409 case AMDGPU::FLAT_SCR:
1417 return AMDGPU::NoRegister;
1420 bool SIInstrInfo::verifyInstruction(const MachineInstr *MI,
1421 StringRef &ErrInfo) const {
1422 uint16_t Opcode = MI->getOpcode();
1423 const MachineRegisterInfo &MRI = MI->getParent()->getParent()->getRegInfo();
1424 int Src0Idx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src0);
1425 int Src1Idx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src1);
1426 int Src2Idx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src2);
1428 // Make sure the number of operands is correct.
1429 const MCInstrDesc &Desc = get(Opcode);
1430 if (!Desc.isVariadic() &&
1431 Desc.getNumOperands() != MI->getNumExplicitOperands()) {
1432 ErrInfo = "Instruction has wrong number of operands.";
1436 // Make sure the register classes are correct
1437 for (int i = 0, e = Desc.getNumOperands(); i != e; ++i) {
1438 if (MI->getOperand(i).isFPImm()) {
1439 ErrInfo = "FPImm Machine Operands are not supported. ISel should bitcast "
1440 "all fp values to integers.";
1444 int RegClass = Desc.OpInfo[i].RegClass;
1446 switch (Desc.OpInfo[i].OperandType) {
1447 case MCOI::OPERAND_REGISTER:
1448 if (MI->getOperand(i).isImm()) {
1449 ErrInfo = "Illegal immediate value for operand.";
1453 case AMDGPU::OPERAND_REG_IMM32:
1455 case AMDGPU::OPERAND_REG_INLINE_C:
1456 if (isLiteralConstant(MI->getOperand(i),
1457 RI.getRegClass(RegClass)->getSize())) {
1458 ErrInfo = "Illegal immediate value for operand.";
1462 case MCOI::OPERAND_IMMEDIATE:
1463 // Check if this operand is an immediate.
1464 // FrameIndex operands will be replaced by immediates, so they are
1466 if (!MI->getOperand(i).isImm() && !MI->getOperand(i).isFI()) {
1467 ErrInfo = "Expected immediate, but got non-immediate";
1475 if (!MI->getOperand(i).isReg())
1478 if (RegClass != -1) {
1479 unsigned Reg = MI->getOperand(i).getReg();
1480 if (TargetRegisterInfo::isVirtualRegister(Reg))
1483 const TargetRegisterClass *RC = RI.getRegClass(RegClass);
1484 if (!RC->contains(Reg)) {
1485 ErrInfo = "Operand has incorrect register class.";
1493 if (isVOP1(*MI) || isVOP2(*MI) || isVOP3(*MI) || isVOPC(*MI)) {
1494 // Only look at the true operands. Only a real operand can use the constant
1495 // bus, and we don't want to check pseudo-operands like the source modifier
1497 const int OpIndices[] = { Src0Idx, Src1Idx, Src2Idx };
1499 unsigned ConstantBusCount = 0;
1500 unsigned SGPRUsed = findImplicitSGPRRead(*MI);
1501 if (SGPRUsed != AMDGPU::NoRegister)
1504 for (int OpIdx : OpIndices) {
1507 const MachineOperand &MO = MI->getOperand(OpIdx);
1508 if (usesConstantBus(MRI, MO, getOpSize(Opcode, OpIdx))) {
1510 if (MO.getReg() != SGPRUsed)
1512 SGPRUsed = MO.getReg();
1518 if (ConstantBusCount > 1) {
1519 ErrInfo = "VOP* instruction uses the constant bus more than once";
1524 // Verify misc. restrictions on specific instructions.
1525 if (Desc.getOpcode() == AMDGPU::V_DIV_SCALE_F32 ||
1526 Desc.getOpcode() == AMDGPU::V_DIV_SCALE_F64) {
1527 const MachineOperand &Src0 = MI->getOperand(Src0Idx);
1528 const MachineOperand &Src1 = MI->getOperand(Src1Idx);
1529 const MachineOperand &Src2 = MI->getOperand(Src2Idx);
1530 if (Src0.isReg() && Src1.isReg() && Src2.isReg()) {
1531 if (!compareMachineOp(Src0, Src1) &&
1532 !compareMachineOp(Src0, Src2)) {
1533 ErrInfo = "v_div_scale_{f32|f64} require src0 = src1 or src2";
1539 // Make sure we aren't losing exec uses in the td files. This mostly requires
1540 // being careful when using let Uses to try to add other use registers.
1541 if (!isGenericOpcode(Opcode) && !isSALU(Opcode) && !isSMRD(Opcode)) {
1542 const MachineOperand *Exec = MI->findRegisterUseOperand(AMDGPU::EXEC);
1543 if (!Exec || !Exec->isImplicit()) {
1544 ErrInfo = "VALU instruction does not implicitly read exec mask";
1552 unsigned SIInstrInfo::getVALUOp(const MachineInstr &MI) {
1553 switch (MI.getOpcode()) {
1554 default: return AMDGPU::INSTRUCTION_LIST_END;
1555 case AMDGPU::REG_SEQUENCE: return AMDGPU::REG_SEQUENCE;
1556 case AMDGPU::COPY: return AMDGPU::COPY;
1557 case AMDGPU::PHI: return AMDGPU::PHI;
1558 case AMDGPU::INSERT_SUBREG: return AMDGPU::INSERT_SUBREG;
1559 case AMDGPU::S_MOV_B32:
1560 return MI.getOperand(1).isReg() ?
1561 AMDGPU::COPY : AMDGPU::V_MOV_B32_e32;
1562 case AMDGPU::S_ADD_I32:
1563 case AMDGPU::S_ADD_U32: return AMDGPU::V_ADD_I32_e32;
1564 case AMDGPU::S_ADDC_U32: return AMDGPU::V_ADDC_U32_e32;
1565 case AMDGPU::S_SUB_I32:
1566 case AMDGPU::S_SUB_U32: return AMDGPU::V_SUB_I32_e32;
1567 case AMDGPU::S_SUBB_U32: return AMDGPU::V_SUBB_U32_e32;
1568 case AMDGPU::S_MUL_I32: return AMDGPU::V_MUL_LO_I32;
1569 case AMDGPU::S_AND_B32: return AMDGPU::V_AND_B32_e32;
1570 case AMDGPU::S_OR_B32: return AMDGPU::V_OR_B32_e32;
1571 case AMDGPU::S_XOR_B32: return AMDGPU::V_XOR_B32_e32;
1572 case AMDGPU::S_MIN_I32: return AMDGPU::V_MIN_I32_e32;
1573 case AMDGPU::S_MIN_U32: return AMDGPU::V_MIN_U32_e32;
1574 case AMDGPU::S_MAX_I32: return AMDGPU::V_MAX_I32_e32;
1575 case AMDGPU::S_MAX_U32: return AMDGPU::V_MAX_U32_e32;
1576 case AMDGPU::S_ASHR_I32: return AMDGPU::V_ASHR_I32_e32;
1577 case AMDGPU::S_ASHR_I64: return AMDGPU::V_ASHR_I64;
1578 case AMDGPU::S_LSHL_B32: return AMDGPU::V_LSHL_B32_e32;
1579 case AMDGPU::S_LSHL_B64: return AMDGPU::V_LSHL_B64;
1580 case AMDGPU::S_LSHR_B32: return AMDGPU::V_LSHR_B32_e32;
1581 case AMDGPU::S_LSHR_B64: return AMDGPU::V_LSHR_B64;
1582 case AMDGPU::S_SEXT_I32_I8: return AMDGPU::V_BFE_I32;
1583 case AMDGPU::S_SEXT_I32_I16: return AMDGPU::V_BFE_I32;
1584 case AMDGPU::S_BFE_U32: return AMDGPU::V_BFE_U32;
1585 case AMDGPU::S_BFE_I32: return AMDGPU::V_BFE_I32;
1586 case AMDGPU::S_BFM_B32: return AMDGPU::V_BFM_B32_e64;
1587 case AMDGPU::S_BREV_B32: return AMDGPU::V_BFREV_B32_e32;
1588 case AMDGPU::S_NOT_B32: return AMDGPU::V_NOT_B32_e32;
1589 case AMDGPU::S_NOT_B64: return AMDGPU::V_NOT_B32_e32;
1590 case AMDGPU::S_CMP_EQ_I32: return AMDGPU::V_CMP_EQ_I32_e32;
1591 case AMDGPU::S_CMP_LG_I32: return AMDGPU::V_CMP_NE_I32_e32;
1592 case AMDGPU::S_CMP_GT_I32: return AMDGPU::V_CMP_GT_I32_e32;
1593 case AMDGPU::S_CMP_GE_I32: return AMDGPU::V_CMP_GE_I32_e32;
1594 case AMDGPU::S_CMP_LT_I32: return AMDGPU::V_CMP_LT_I32_e32;
1595 case AMDGPU::S_CMP_LE_I32: return AMDGPU::V_CMP_LE_I32_e32;
1596 case AMDGPU::S_LOAD_DWORD_IMM:
1597 case AMDGPU::S_LOAD_DWORD_SGPR:
1598 case AMDGPU::S_LOAD_DWORD_IMM_ci:
1599 return AMDGPU::BUFFER_LOAD_DWORD_ADDR64;
1600 case AMDGPU::S_LOAD_DWORDX2_IMM:
1601 case AMDGPU::S_LOAD_DWORDX2_SGPR:
1602 case AMDGPU::S_LOAD_DWORDX2_IMM_ci:
1603 return AMDGPU::BUFFER_LOAD_DWORDX2_ADDR64;
1604 case AMDGPU::S_LOAD_DWORDX4_IMM:
1605 case AMDGPU::S_LOAD_DWORDX4_SGPR:
1606 case AMDGPU::S_LOAD_DWORDX4_IMM_ci:
1607 return AMDGPU::BUFFER_LOAD_DWORDX4_ADDR64;
1608 case AMDGPU::S_BCNT1_I32_B32: return AMDGPU::V_BCNT_U32_B32_e64;
1609 case AMDGPU::S_FF1_I32_B32: return AMDGPU::V_FFBL_B32_e32;
1610 case AMDGPU::S_FLBIT_I32_B32: return AMDGPU::V_FFBH_U32_e32;
1611 case AMDGPU::S_FLBIT_I32: return AMDGPU::V_FFBH_I32_e64;
1615 bool SIInstrInfo::isSALUOpSupportedOnVALU(const MachineInstr &MI) const {
1616 return getVALUOp(MI) != AMDGPU::INSTRUCTION_LIST_END;
1619 const TargetRegisterClass *SIInstrInfo::getOpRegClass(const MachineInstr &MI,
1620 unsigned OpNo) const {
1621 const MachineRegisterInfo &MRI = MI.getParent()->getParent()->getRegInfo();
1622 const MCInstrDesc &Desc = get(MI.getOpcode());
1623 if (MI.isVariadic() || OpNo >= Desc.getNumOperands() ||
1624 Desc.OpInfo[OpNo].RegClass == -1) {
1625 unsigned Reg = MI.getOperand(OpNo).getReg();
1627 if (TargetRegisterInfo::isVirtualRegister(Reg))
1628 return MRI.getRegClass(Reg);
1629 return RI.getPhysRegClass(Reg);
1632 unsigned RCID = Desc.OpInfo[OpNo].RegClass;
1633 return RI.getRegClass(RCID);
1636 bool SIInstrInfo::canReadVGPR(const MachineInstr &MI, unsigned OpNo) const {
1637 switch (MI.getOpcode()) {
1639 case AMDGPU::REG_SEQUENCE:
1641 case AMDGPU::INSERT_SUBREG:
1642 return RI.hasVGPRs(getOpRegClass(MI, 0));
1644 return RI.hasVGPRs(getOpRegClass(MI, OpNo));
1648 void SIInstrInfo::legalizeOpWithMove(MachineInstr *MI, unsigned OpIdx) const {
1649 MachineBasicBlock::iterator I = MI;
1650 MachineBasicBlock *MBB = MI->getParent();
1651 MachineOperand &MO = MI->getOperand(OpIdx);
1652 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
1653 unsigned RCID = get(MI->getOpcode()).OpInfo[OpIdx].RegClass;
1654 const TargetRegisterClass *RC = RI.getRegClass(RCID);
1655 unsigned Opcode = AMDGPU::V_MOV_B32_e32;
1657 Opcode = AMDGPU::COPY;
1658 else if (RI.isSGPRClass(RC))
1659 Opcode = AMDGPU::S_MOV_B32;
1662 const TargetRegisterClass *VRC = RI.getEquivalentVGPRClass(RC);
1663 if (RI.getCommonSubClass(&AMDGPU::VReg_64RegClass, VRC))
1664 VRC = &AMDGPU::VReg_64RegClass;
1666 VRC = &AMDGPU::VGPR_32RegClass;
1668 unsigned Reg = MRI.createVirtualRegister(VRC);
1669 DebugLoc DL = MBB->findDebugLoc(I);
1670 BuildMI(*MI->getParent(), I, DL, get(Opcode), Reg)
1672 MO.ChangeToRegister(Reg, false);
1675 unsigned SIInstrInfo::buildExtractSubReg(MachineBasicBlock::iterator MI,
1676 MachineRegisterInfo &MRI,
1677 MachineOperand &SuperReg,
1678 const TargetRegisterClass *SuperRC,
1680 const TargetRegisterClass *SubRC)
1682 MachineBasicBlock *MBB = MI->getParent();
1683 DebugLoc DL = MI->getDebugLoc();
1684 unsigned SubReg = MRI.createVirtualRegister(SubRC);
1686 if (SuperReg.getSubReg() == AMDGPU::NoSubRegister) {
1687 BuildMI(*MBB, MI, DL, get(TargetOpcode::COPY), SubReg)
1688 .addReg(SuperReg.getReg(), 0, SubIdx);
1692 // Just in case the super register is itself a sub-register, copy it to a new
1693 // value so we don't need to worry about merging its subreg index with the
1694 // SubIdx passed to this function. The register coalescer should be able to
1695 // eliminate this extra copy.
1696 unsigned NewSuperReg = MRI.createVirtualRegister(SuperRC);
1698 BuildMI(*MBB, MI, DL, get(TargetOpcode::COPY), NewSuperReg)
1699 .addReg(SuperReg.getReg(), 0, SuperReg.getSubReg());
1701 BuildMI(*MBB, MI, DL, get(TargetOpcode::COPY), SubReg)
1702 .addReg(NewSuperReg, 0, SubIdx);
1707 MachineOperand SIInstrInfo::buildExtractSubRegOrImm(
1708 MachineBasicBlock::iterator MII,
1709 MachineRegisterInfo &MRI,
1711 const TargetRegisterClass *SuperRC,
1713 const TargetRegisterClass *SubRC) const {
1715 // XXX - Is there a better way to do this?
1716 if (SubIdx == AMDGPU::sub0)
1717 return MachineOperand::CreateImm(Op.getImm() & 0xFFFFFFFF);
1718 if (SubIdx == AMDGPU::sub1)
1719 return MachineOperand::CreateImm(Op.getImm() >> 32);
1721 llvm_unreachable("Unhandled register index for immediate");
1724 unsigned SubReg = buildExtractSubReg(MII, MRI, Op, SuperRC,
1726 return MachineOperand::CreateReg(SubReg, false);
1729 // Change the order of operands from (0, 1, 2) to (0, 2, 1)
1730 void SIInstrInfo::swapOperands(MachineBasicBlock::iterator Inst) const {
1731 assert(Inst->getNumExplicitOperands() == 3);
1732 MachineOperand Op1 = Inst->getOperand(1);
1733 Inst->RemoveOperand(1);
1734 Inst->addOperand(Op1);
1737 bool SIInstrInfo::isLegalRegOperand(const MachineRegisterInfo &MRI,
1738 const MCOperandInfo &OpInfo,
1739 const MachineOperand &MO) const {
1743 unsigned Reg = MO.getReg();
1744 const TargetRegisterClass *RC =
1745 TargetRegisterInfo::isVirtualRegister(Reg) ?
1746 MRI.getRegClass(Reg) :
1747 RI.getPhysRegClass(Reg);
1749 // In order to be legal, the common sub-class must be equal to the
1750 // class of the current operand. For example:
1752 // v_mov_b32 s0 ; Operand defined as vsrc_32
1753 // ; RI.getCommonSubClass(s0,vsrc_32) = sgpr ; LEGAL
1755 // s_sendmsg 0, s0 ; Operand defined as m0reg
1756 // ; RI.getCommonSubClass(s0,m0reg) = m0reg ; NOT LEGAL
1758 return RI.getCommonSubClass(RC, RI.getRegClass(OpInfo.RegClass)) == RC;
1761 bool SIInstrInfo::isLegalVSrcOperand(const MachineRegisterInfo &MRI,
1762 const MCOperandInfo &OpInfo,
1763 const MachineOperand &MO) const {
1765 return isLegalRegOperand(MRI, OpInfo, MO);
1767 // Handle non-register types that are treated like immediates.
1768 assert(MO.isImm() || MO.isTargetIndex() || MO.isFI());
1772 bool SIInstrInfo::isOperandLegal(const MachineInstr *MI, unsigned OpIdx,
1773 const MachineOperand *MO) const {
1774 const MachineRegisterInfo &MRI = MI->getParent()->getParent()->getRegInfo();
1775 const MCInstrDesc &InstDesc = get(MI->getOpcode());
1776 const MCOperandInfo &OpInfo = InstDesc.OpInfo[OpIdx];
1777 const TargetRegisterClass *DefinedRC =
1778 OpInfo.RegClass != -1 ? RI.getRegClass(OpInfo.RegClass) : nullptr;
1780 MO = &MI->getOperand(OpIdx);
1783 usesConstantBus(MRI, *MO, DefinedRC->getSize())) {
1785 MO->isReg() ? MO->getReg() : (unsigned)AMDGPU::NoRegister;
1786 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1789 const MachineOperand &Op = MI->getOperand(i);
1790 if (Op.isReg() && Op.getReg() != SGPRUsed &&
1791 usesConstantBus(MRI, Op, getOpSize(*MI, i))) {
1799 return isLegalRegOperand(MRI, OpInfo, *MO);
1803 // Handle non-register types that are treated like immediates.
1804 assert(MO->isImm() || MO->isTargetIndex() || MO->isFI());
1807 // This operand expects an immediate.
1811 return isImmOperandLegal(MI, OpIdx, *MO);
1814 void SIInstrInfo::legalizeOperandsVOP2(MachineRegisterInfo &MRI,
1815 MachineInstr *MI) const {
1816 unsigned Opc = MI->getOpcode();
1817 const MCInstrDesc &InstrDesc = get(Opc);
1819 int Src1Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src1);
1820 MachineOperand &Src1 = MI->getOperand(Src1Idx);
1822 // If there is an implicit SGPR use such as VCC use for v_addc_u32/v_subb_u32
1823 // we need to only have one constant bus use.
1825 // Note we do not need to worry about literal constants here. They are
1826 // disabled for the operand type for instructions because they will always
1827 // violate the one constant bus use rule.
1828 bool HasImplicitSGPR = findImplicitSGPRRead(*MI) != AMDGPU::NoRegister;
1829 if (HasImplicitSGPR) {
1830 int Src0Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src0);
1831 MachineOperand &Src0 = MI->getOperand(Src0Idx);
1833 if (Src0.isReg() && RI.isSGPRReg(MRI, Src0.getReg()))
1834 legalizeOpWithMove(MI, Src0Idx);
1837 // VOP2 src0 instructions support all operand types, so we don't need to check
1838 // their legality. If src1 is already legal, we don't need to do anything.
1839 if (isLegalRegOperand(MRI, InstrDesc.OpInfo[Src1Idx], Src1))
1842 // We do not use commuteInstruction here because it is too aggressive and will
1843 // commute if it is possible. We only want to commute here if it improves
1844 // legality. This can be called a fairly large number of times so don't waste
1845 // compile time pointlessly swapping and checking legality again.
1846 if (HasImplicitSGPR || !MI->isCommutable()) {
1847 legalizeOpWithMove(MI, Src1Idx);
1851 int Src0Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src0);
1852 MachineOperand &Src0 = MI->getOperand(Src0Idx);
1854 // If src0 can be used as src1, commuting will make the operands legal.
1855 // Otherwise we have to give up and insert a move.
1857 // TODO: Other immediate-like operand kinds could be commuted if there was a
1858 // MachineOperand::ChangeTo* for them.
1859 if ((!Src1.isImm() && !Src1.isReg()) ||
1860 !isLegalRegOperand(MRI, InstrDesc.OpInfo[Src1Idx], Src0)) {
1861 legalizeOpWithMove(MI, Src1Idx);
1865 int CommutedOpc = commuteOpcode(*MI);
1866 if (CommutedOpc == -1) {
1867 legalizeOpWithMove(MI, Src1Idx);
1871 MI->setDesc(get(CommutedOpc));
1873 unsigned Src0Reg = Src0.getReg();
1874 unsigned Src0SubReg = Src0.getSubReg();
1875 bool Src0Kill = Src0.isKill();
1878 Src0.ChangeToImmediate(Src1.getImm());
1879 else if (Src1.isReg()) {
1880 Src0.ChangeToRegister(Src1.getReg(), false, false, Src1.isKill());
1881 Src0.setSubReg(Src1.getSubReg());
1883 llvm_unreachable("Should only have register or immediate operands");
1885 Src1.ChangeToRegister(Src0Reg, false, false, Src0Kill);
1886 Src1.setSubReg(Src0SubReg);
1889 // Legalize VOP3 operands. Because all operand types are supported for any
1890 // operand, and since literal constants are not allowed and should never be
1891 // seen, we only need to worry about inserting copies if we use multiple SGPR
1893 void SIInstrInfo::legalizeOperandsVOP3(
1894 MachineRegisterInfo &MRI,
1895 MachineInstr *MI) const {
1896 unsigned Opc = MI->getOpcode();
1899 AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src0),
1900 AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src1),
1901 AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src2)
1904 // Find the one SGPR operand we are allowed to use.
1905 unsigned SGPRReg = findUsedSGPR(MI, VOP3Idx);
1907 for (unsigned i = 0; i < 3; ++i) {
1908 int Idx = VOP3Idx[i];
1911 MachineOperand &MO = MI->getOperand(Idx);
1913 // We should never see a VOP3 instruction with an illegal immediate operand.
1917 if (!RI.isSGPRClass(MRI.getRegClass(MO.getReg())))
1918 continue; // VGPRs are legal
1920 if (SGPRReg == AMDGPU::NoRegister || SGPRReg == MO.getReg()) {
1921 SGPRReg = MO.getReg();
1922 // We can use one SGPR in each VOP3 instruction.
1926 // If we make it this far, then the operand is not legal and we must
1928 legalizeOpWithMove(MI, Idx);
1932 void SIInstrInfo::legalizeOperands(MachineInstr *MI) const {
1933 MachineRegisterInfo &MRI = MI->getParent()->getParent()->getRegInfo();
1937 legalizeOperandsVOP2(MRI, MI);
1943 legalizeOperandsVOP3(MRI, MI);
1947 // Legalize REG_SEQUENCE and PHI
1948 // The register class of the operands much be the same type as the register
1949 // class of the output.
1950 if (MI->getOpcode() == AMDGPU::PHI) {
1951 const TargetRegisterClass *RC = nullptr, *SRC = nullptr, *VRC = nullptr;
1952 for (unsigned i = 1, e = MI->getNumOperands(); i != e; i+=2) {
1953 if (!MI->getOperand(i).isReg() ||
1954 !TargetRegisterInfo::isVirtualRegister(MI->getOperand(i).getReg()))
1956 const TargetRegisterClass *OpRC =
1957 MRI.getRegClass(MI->getOperand(i).getReg());
1958 if (RI.hasVGPRs(OpRC)) {
1965 // If any of the operands are VGPR registers, then they all most be
1966 // otherwise we will create illegal VGPR->SGPR copies when legalizing
1968 if (VRC || !RI.isSGPRClass(getOpRegClass(*MI, 0))) {
1971 VRC = RI.getEquivalentVGPRClass(SRC);
1978 // Update all the operands so they have the same type.
1979 for (unsigned I = 1, E = MI->getNumOperands(); I != E; I += 2) {
1980 MachineOperand &Op = MI->getOperand(I);
1981 if (!Op.isReg() || !TargetRegisterInfo::isVirtualRegister(Op.getReg()))
1983 unsigned DstReg = MRI.createVirtualRegister(RC);
1985 // MI is a PHI instruction.
1986 MachineBasicBlock *InsertBB = MI->getOperand(I + 1).getMBB();
1987 MachineBasicBlock::iterator Insert = InsertBB->getFirstTerminator();
1989 BuildMI(*InsertBB, Insert, MI->getDebugLoc(), get(AMDGPU::COPY), DstReg)
1995 // REG_SEQUENCE doesn't really require operand legalization, but if one has a
1996 // VGPR dest type and SGPR sources, insert copies so all operands are
1997 // VGPRs. This seems to help operand folding / the register coalescer.
1998 if (MI->getOpcode() == AMDGPU::REG_SEQUENCE) {
1999 MachineBasicBlock *MBB = MI->getParent();
2000 const TargetRegisterClass *DstRC = getOpRegClass(*MI, 0);
2001 if (RI.hasVGPRs(DstRC)) {
2002 // Update all the operands so they are VGPR register classes. These may
2003 // not be the same register class because REG_SEQUENCE supports mixing
2004 // subregister index types e.g. sub0_sub1 + sub2 + sub3
2005 for (unsigned I = 1, E = MI->getNumOperands(); I != E; I += 2) {
2006 MachineOperand &Op = MI->getOperand(I);
2007 if (!Op.isReg() || !TargetRegisterInfo::isVirtualRegister(Op.getReg()))
2010 const TargetRegisterClass *OpRC = MRI.getRegClass(Op.getReg());
2011 const TargetRegisterClass *VRC = RI.getEquivalentVGPRClass(OpRC);
2015 unsigned DstReg = MRI.createVirtualRegister(VRC);
2017 BuildMI(*MBB, MI, MI->getDebugLoc(), get(AMDGPU::COPY), DstReg)
2028 // Legalize INSERT_SUBREG
2029 // src0 must have the same register class as dst
2030 if (MI->getOpcode() == AMDGPU::INSERT_SUBREG) {
2031 unsigned Dst = MI->getOperand(0).getReg();
2032 unsigned Src0 = MI->getOperand(1).getReg();
2033 const TargetRegisterClass *DstRC = MRI.getRegClass(Dst);
2034 const TargetRegisterClass *Src0RC = MRI.getRegClass(Src0);
2035 if (DstRC != Src0RC) {
2036 MachineBasicBlock &MBB = *MI->getParent();
2037 unsigned NewSrc0 = MRI.createVirtualRegister(DstRC);
2038 BuildMI(MBB, MI, MI->getDebugLoc(), get(AMDGPU::COPY), NewSrc0)
2040 MI->getOperand(1).setReg(NewSrc0);
2045 // Legalize MUBUF* instructions
2046 // FIXME: If we start using the non-addr64 instructions for compute, we
2047 // may need to legalize them here.
2049 AMDGPU::getNamedOperandIdx(MI->getOpcode(), AMDGPU::OpName::srsrc);
2050 if (SRsrcIdx != -1) {
2051 // We have an MUBUF instruction
2052 MachineOperand *SRsrc = &MI->getOperand(SRsrcIdx);
2053 unsigned SRsrcRC = get(MI->getOpcode()).OpInfo[SRsrcIdx].RegClass;
2054 if (RI.getCommonSubClass(MRI.getRegClass(SRsrc->getReg()),
2055 RI.getRegClass(SRsrcRC))) {
2056 // The operands are legal.
2057 // FIXME: We may need to legalize operands besided srsrc.
2061 MachineBasicBlock &MBB = *MI->getParent();
2063 // Extract the ptr from the resource descriptor.
2064 unsigned SRsrcPtr = buildExtractSubReg(MI, MRI, *SRsrc,
2065 &AMDGPU::VReg_128RegClass, AMDGPU::sub0_sub1, &AMDGPU::VReg_64RegClass);
2067 // Create an empty resource descriptor
2068 unsigned Zero64 = MRI.createVirtualRegister(&AMDGPU::SReg_64RegClass);
2069 unsigned SRsrcFormatLo = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
2070 unsigned SRsrcFormatHi = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
2071 unsigned NewSRsrc = MRI.createVirtualRegister(&AMDGPU::SReg_128RegClass);
2072 uint64_t RsrcDataFormat = getDefaultRsrcDataFormat();
2075 BuildMI(MBB, MI, MI->getDebugLoc(), get(AMDGPU::S_MOV_B64),
2079 // SRsrcFormatLo = RSRC_DATA_FORMAT{31-0}
2080 BuildMI(MBB, MI, MI->getDebugLoc(), get(AMDGPU::S_MOV_B32),
2082 .addImm(RsrcDataFormat & 0xFFFFFFFF);
2084 // SRsrcFormatHi = RSRC_DATA_FORMAT{63-32}
2085 BuildMI(MBB, MI, MI->getDebugLoc(), get(AMDGPU::S_MOV_B32),
2087 .addImm(RsrcDataFormat >> 32);
2089 // NewSRsrc = {Zero64, SRsrcFormat}
2090 BuildMI(MBB, MI, MI->getDebugLoc(), get(AMDGPU::REG_SEQUENCE), NewSRsrc)
2092 .addImm(AMDGPU::sub0_sub1)
2093 .addReg(SRsrcFormatLo)
2094 .addImm(AMDGPU::sub2)
2095 .addReg(SRsrcFormatHi)
2096 .addImm(AMDGPU::sub3);
2098 MachineOperand *VAddr = getNamedOperand(*MI, AMDGPU::OpName::vaddr);
2099 unsigned NewVAddr = MRI.createVirtualRegister(&AMDGPU::VReg_64RegClass);
2101 // This is already an ADDR64 instruction so we need to add the pointer
2102 // extracted from the resource descriptor to the current value of VAddr.
2103 unsigned NewVAddrLo = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
2104 unsigned NewVAddrHi = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
2106 // NewVaddrLo = SRsrcPtr:sub0 + VAddr:sub0
2107 DebugLoc DL = MI->getDebugLoc();
2108 BuildMI(MBB, MI, DL, get(AMDGPU::V_ADD_I32_e32), NewVAddrLo)
2109 .addReg(SRsrcPtr, 0, AMDGPU::sub0)
2110 .addReg(VAddr->getReg(), 0, AMDGPU::sub0);
2112 // NewVaddrHi = SRsrcPtr:sub1 + VAddr:sub1
2113 BuildMI(MBB, MI, DL, get(AMDGPU::V_ADDC_U32_e32), NewVAddrHi)
2114 .addReg(SRsrcPtr, 0, AMDGPU::sub1)
2115 .addReg(VAddr->getReg(), 0, AMDGPU::sub1);
2117 // NewVaddr = {NewVaddrHi, NewVaddrLo}
2118 BuildMI(MBB, MI, MI->getDebugLoc(), get(AMDGPU::REG_SEQUENCE), NewVAddr)
2120 .addImm(AMDGPU::sub0)
2122 .addImm(AMDGPU::sub1);
2124 // This instructions is the _OFFSET variant, so we need to convert it to
2126 assert(MBB.getParent()->getSubtarget<AMDGPUSubtarget>().getGeneration()
2127 < AMDGPUSubtarget::VOLCANIC_ISLANDS &&
2128 "FIXME: Need to emit flat atomics here");
2130 MachineOperand *VData = getNamedOperand(*MI, AMDGPU::OpName::vdata);
2131 MachineOperand *Offset = getNamedOperand(*MI, AMDGPU::OpName::offset);
2132 MachineOperand *SOffset = getNamedOperand(*MI, AMDGPU::OpName::soffset);
2133 unsigned Addr64Opcode = AMDGPU::getAddr64Inst(MI->getOpcode());
2135 // Atomics rith return have have an additional tied operand and are
2136 // missing some of the special bits.
2137 MachineOperand *VDataIn = getNamedOperand(*MI, AMDGPU::OpName::vdata_in);
2138 MachineInstr *Addr64;
2141 // Regular buffer load / store.
2142 MachineInstrBuilder MIB
2143 = BuildMI(MBB, MI, MI->getDebugLoc(), get(Addr64Opcode))
2145 .addReg(AMDGPU::NoRegister) // Dummy value for vaddr.
2146 // This will be replaced later
2147 // with the new value of vaddr.
2149 .addOperand(*SOffset)
2150 .addOperand(*Offset);
2152 // Atomics do not have this operand.
2153 if (const MachineOperand *GLC
2154 = getNamedOperand(*MI, AMDGPU::OpName::glc)) {
2155 MIB.addImm(GLC->getImm());
2158 MIB.addImm(getNamedImmOperand(*MI, AMDGPU::OpName::slc));
2160 if (const MachineOperand *TFE
2161 = getNamedOperand(*MI, AMDGPU::OpName::tfe)) {
2162 MIB.addImm(TFE->getImm());
2165 MIB.setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
2168 // Atomics with return.
2169 Addr64 = BuildMI(MBB, MI, MI->getDebugLoc(), get(Addr64Opcode))
2171 .addOperand(*VDataIn)
2172 .addReg(AMDGPU::NoRegister) // Dummy value for vaddr.
2173 // This will be replaced later
2174 // with the new value of vaddr.
2176 .addOperand(*SOffset)
2177 .addOperand(*Offset)
2178 .addImm(getNamedImmOperand(*MI, AMDGPU::OpName::slc))
2179 .setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
2182 MI->removeFromParent();
2185 // NewVaddr = {NewVaddrHi, NewVaddrLo}
2186 BuildMI(MBB, MI, MI->getDebugLoc(), get(AMDGPU::REG_SEQUENCE), NewVAddr)
2187 .addReg(SRsrcPtr, 0, AMDGPU::sub0)
2188 .addImm(AMDGPU::sub0)
2189 .addReg(SRsrcPtr, 0, AMDGPU::sub1)
2190 .addImm(AMDGPU::sub1);
2192 VAddr = getNamedOperand(*MI, AMDGPU::OpName::vaddr);
2193 SRsrc = getNamedOperand(*MI, AMDGPU::OpName::srsrc);
2196 // Update the instruction to use NewVaddr
2197 VAddr->setReg(NewVAddr);
2198 // Update the instruction to use NewSRsrc
2199 SRsrc->setReg(NewSRsrc);
2203 void SIInstrInfo::splitSMRD(MachineInstr *MI,
2204 const TargetRegisterClass *HalfRC,
2205 unsigned HalfImmOp, unsigned HalfSGPROp,
2206 MachineInstr *&Lo, MachineInstr *&Hi) const {
2208 DebugLoc DL = MI->getDebugLoc();
2209 MachineBasicBlock *MBB = MI->getParent();
2210 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
2211 unsigned RegLo = MRI.createVirtualRegister(HalfRC);
2212 unsigned RegHi = MRI.createVirtualRegister(HalfRC);
2213 unsigned HalfSize = HalfRC->getSize();
2214 const MachineOperand *OffOp =
2215 getNamedOperand(*MI, AMDGPU::OpName::offset);
2216 const MachineOperand *SBase = getNamedOperand(*MI, AMDGPU::OpName::sbase);
2218 // The SMRD has an 8-bit offset in dwords on SI and a 20-bit offset in bytes
2221 bool IsKill = SBase->isKill();
2224 MBB->getParent()->getSubtarget<AMDGPUSubtarget>().getGeneration() >=
2225 AMDGPUSubtarget::VOLCANIC_ISLANDS;
2226 unsigned OffScale = isVI ? 1 : 4;
2227 // Handle the _IMM variant
2228 unsigned LoOffset = OffOp->getImm() * OffScale;
2229 unsigned HiOffset = LoOffset + HalfSize;
2230 Lo = BuildMI(*MBB, MI, DL, get(HalfImmOp), RegLo)
2231 // Use addReg instead of addOperand
2232 // to make sure kill flag is cleared.
2233 .addReg(SBase->getReg(), 0, SBase->getSubReg())
2234 .addImm(LoOffset / OffScale);
2236 if (!isUInt<20>(HiOffset) || (!isVI && !isUInt<8>(HiOffset / OffScale))) {
2237 unsigned OffsetSGPR =
2238 MRI.createVirtualRegister(&AMDGPU::SReg_32RegClass);
2239 BuildMI(*MBB, MI, DL, get(AMDGPU::S_MOV_B32), OffsetSGPR)
2240 .addImm(HiOffset); // The offset in register is in bytes.
2241 Hi = BuildMI(*MBB, MI, DL, get(HalfSGPROp), RegHi)
2242 .addReg(SBase->getReg(), getKillRegState(IsKill),
2244 .addReg(OffsetSGPR);
2246 Hi = BuildMI(*MBB, MI, DL, get(HalfImmOp), RegHi)
2247 .addReg(SBase->getReg(), getKillRegState(IsKill),
2249 .addImm(HiOffset / OffScale);
2252 // Handle the _SGPR variant
2253 MachineOperand *SOff = getNamedOperand(*MI, AMDGPU::OpName::soff);
2254 Lo = BuildMI(*MBB, MI, DL, get(HalfSGPROp), RegLo)
2255 .addReg(SBase->getReg(), 0, SBase->getSubReg())
2257 unsigned OffsetSGPR = MRI.createVirtualRegister(&AMDGPU::SReg_32RegClass);
2258 BuildMI(*MBB, MI, DL, get(AMDGPU::S_ADD_I32), OffsetSGPR)
2259 .addReg(SOff->getReg(), 0, SOff->getSubReg())
2261 Hi = BuildMI(*MBB, MI, DL, get(HalfSGPROp), RegHi)
2262 .addReg(SBase->getReg(), getKillRegState(IsKill),
2264 .addReg(OffsetSGPR);
2267 unsigned SubLo, SubHi;
2268 const TargetRegisterClass *NewDstRC;
2271 SubLo = AMDGPU::sub0;
2272 SubHi = AMDGPU::sub1;
2273 NewDstRC = &AMDGPU::VReg_64RegClass;
2276 SubLo = AMDGPU::sub0_sub1;
2277 SubHi = AMDGPU::sub2_sub3;
2278 NewDstRC = &AMDGPU::VReg_128RegClass;
2281 SubLo = AMDGPU::sub0_sub1_sub2_sub3;
2282 SubHi = AMDGPU::sub4_sub5_sub6_sub7;
2283 NewDstRC = &AMDGPU::VReg_256RegClass;
2286 SubLo = AMDGPU::sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7;
2287 SubHi = AMDGPU::sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15;
2288 NewDstRC = &AMDGPU::VReg_512RegClass;
2291 llvm_unreachable("Unhandled HalfSize");
2294 unsigned OldDst = MI->getOperand(0).getReg();
2295 unsigned NewDst = MRI.createVirtualRegister(NewDstRC);
2297 MRI.replaceRegWith(OldDst, NewDst);
2299 BuildMI(*MBB, MI, DL, get(AMDGPU::REG_SEQUENCE), NewDst)
2306 void SIInstrInfo::moveSMRDToVALU(MachineInstr *MI,
2307 MachineRegisterInfo &MRI,
2308 SmallVectorImpl<MachineInstr *> &Worklist) const {
2309 MachineBasicBlock *MBB = MI->getParent();
2310 int DstIdx = AMDGPU::getNamedOperandIdx(MI->getOpcode(), AMDGPU::OpName::dst);
2311 assert(DstIdx != -1);
2312 unsigned DstRCID = get(MI->getOpcode()).OpInfo[DstIdx].RegClass;
2313 switch(RI.getRegClass(DstRCID)->getSize()) {
2317 unsigned NewOpcode = getVALUOp(*MI);
2321 if (MI->getOperand(2).isReg()) {
2322 RegOffset = MI->getOperand(2).getReg();
2325 assert(MI->getOperand(2).isImm());
2326 // SMRD instructions take a dword offsets on SI and byte offset on VI
2327 // and MUBUF instructions always take a byte offset.
2328 ImmOffset = MI->getOperand(2).getImm();
2329 if (MBB->getParent()->getSubtarget<AMDGPUSubtarget>().getGeneration() <=
2330 AMDGPUSubtarget::SEA_ISLANDS)
2332 RegOffset = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
2334 if (isUInt<12>(ImmOffset)) {
2335 BuildMI(*MBB, MI, MI->getDebugLoc(), get(AMDGPU::S_MOV_B32),
2339 BuildMI(*MBB, MI, MI->getDebugLoc(), get(AMDGPU::S_MOV_B32),
2346 unsigned SRsrc = MRI.createVirtualRegister(&AMDGPU::SReg_128RegClass);
2347 unsigned DWord0 = RegOffset;
2348 unsigned DWord1 = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
2349 unsigned DWord2 = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
2350 unsigned DWord3 = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
2351 uint64_t RsrcDataFormat = getDefaultRsrcDataFormat();
2353 BuildMI(*MBB, MI, MI->getDebugLoc(), get(AMDGPU::S_MOV_B32), DWord1)
2355 BuildMI(*MBB, MI, MI->getDebugLoc(), get(AMDGPU::S_MOV_B32), DWord2)
2356 .addImm(RsrcDataFormat & 0xFFFFFFFF);
2357 BuildMI(*MBB, MI, MI->getDebugLoc(), get(AMDGPU::S_MOV_B32), DWord3)
2358 .addImm(RsrcDataFormat >> 32);
2359 BuildMI(*MBB, MI, MI->getDebugLoc(), get(AMDGPU::REG_SEQUENCE), SRsrc)
2361 .addImm(AMDGPU::sub0)
2363 .addImm(AMDGPU::sub1)
2365 .addImm(AMDGPU::sub2)
2367 .addImm(AMDGPU::sub3);
2369 const MCInstrDesc &NewInstDesc = get(NewOpcode);
2370 const TargetRegisterClass *NewDstRC
2371 = RI.getRegClass(NewInstDesc.OpInfo[0].RegClass);
2372 unsigned NewDstReg = MRI.createVirtualRegister(NewDstRC);
2373 unsigned DstReg = MI->getOperand(0).getReg();
2374 MRI.replaceRegWith(DstReg, NewDstReg);
2376 MachineInstr *NewInst =
2377 BuildMI(*MBB, MI, MI->getDebugLoc(), NewInstDesc, NewDstReg)
2378 .addOperand(MI->getOperand(1)) // sbase
2385 .setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
2386 MI->eraseFromParent();
2388 legalizeOperands(NewInst);
2389 addUsersToMoveToVALUWorklist(NewDstReg, MRI, Worklist);
2393 MachineInstr *Lo, *Hi;
2394 splitSMRD(MI, &AMDGPU::SReg_128RegClass, AMDGPU::S_LOAD_DWORDX4_IMM,
2395 AMDGPU::S_LOAD_DWORDX4_SGPR, Lo, Hi);
2396 MI->eraseFromParent();
2397 moveSMRDToVALU(Lo, MRI, Worklist);
2398 moveSMRDToVALU(Hi, MRI, Worklist);
2403 MachineInstr *Lo, *Hi;
2404 splitSMRD(MI, &AMDGPU::SReg_256RegClass, AMDGPU::S_LOAD_DWORDX8_IMM,
2405 AMDGPU::S_LOAD_DWORDX8_SGPR, Lo, Hi);
2406 MI->eraseFromParent();
2407 moveSMRDToVALU(Lo, MRI, Worklist);
2408 moveSMRDToVALU(Hi, MRI, Worklist);
2414 void SIInstrInfo::moveToVALU(MachineInstr &TopInst) const {
2415 SmallVector<MachineInstr *, 128> Worklist;
2416 Worklist.push_back(&TopInst);
2418 while (!Worklist.empty()) {
2419 MachineInstr *Inst = Worklist.pop_back_val();
2420 MachineBasicBlock *MBB = Inst->getParent();
2421 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
2423 unsigned Opcode = Inst->getOpcode();
2424 unsigned NewOpcode = getVALUOp(*Inst);
2426 // Handle some special cases
2429 if (isSMRD(*Inst)) {
2430 moveSMRDToVALU(Inst, MRI, Worklist);
2434 case AMDGPU::S_AND_B64:
2435 splitScalar64BitBinaryOp(Worklist, Inst, AMDGPU::V_AND_B32_e64);
2436 Inst->eraseFromParent();
2439 case AMDGPU::S_OR_B64:
2440 splitScalar64BitBinaryOp(Worklist, Inst, AMDGPU::V_OR_B32_e64);
2441 Inst->eraseFromParent();
2444 case AMDGPU::S_XOR_B64:
2445 splitScalar64BitBinaryOp(Worklist, Inst, AMDGPU::V_XOR_B32_e64);
2446 Inst->eraseFromParent();
2449 case AMDGPU::S_NOT_B64:
2450 splitScalar64BitUnaryOp(Worklist, Inst, AMDGPU::V_NOT_B32_e32);
2451 Inst->eraseFromParent();
2454 case AMDGPU::S_BCNT1_I32_B64:
2455 splitScalar64BitBCNT(Worklist, Inst);
2456 Inst->eraseFromParent();
2459 case AMDGPU::S_BFE_I64: {
2460 splitScalar64BitBFE(Worklist, Inst);
2461 Inst->eraseFromParent();
2465 case AMDGPU::S_LSHL_B32:
2466 if (ST.getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS) {
2467 NewOpcode = AMDGPU::V_LSHLREV_B32_e64;
2471 case AMDGPU::S_ASHR_I32:
2472 if (ST.getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS) {
2473 NewOpcode = AMDGPU::V_ASHRREV_I32_e64;
2477 case AMDGPU::S_LSHR_B32:
2478 if (ST.getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS) {
2479 NewOpcode = AMDGPU::V_LSHRREV_B32_e64;
2483 case AMDGPU::S_LSHL_B64:
2484 if (ST.getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS) {
2485 NewOpcode = AMDGPU::V_LSHLREV_B64;
2489 case AMDGPU::S_ASHR_I64:
2490 if (ST.getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS) {
2491 NewOpcode = AMDGPU::V_ASHRREV_I64;
2495 case AMDGPU::S_LSHR_B64:
2496 if (ST.getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS) {
2497 NewOpcode = AMDGPU::V_LSHRREV_B64;
2502 case AMDGPU::S_ABS_I32:
2503 lowerScalarAbs(Worklist, Inst);
2504 Inst->eraseFromParent();
2507 case AMDGPU::S_BFE_U64:
2508 case AMDGPU::S_BFM_B64:
2509 llvm_unreachable("Moving this op to VALU not implemented");
2512 if (NewOpcode == AMDGPU::INSTRUCTION_LIST_END) {
2513 // We cannot move this instruction to the VALU, so we should try to
2514 // legalize its operands instead.
2515 legalizeOperands(Inst);
2519 // Use the new VALU Opcode.
2520 const MCInstrDesc &NewDesc = get(NewOpcode);
2521 Inst->setDesc(NewDesc);
2523 // Remove any references to SCC. Vector instructions can't read from it, and
2524 // We're just about to add the implicit use / defs of VCC, and we don't want
2526 for (unsigned i = Inst->getNumOperands() - 1; i > 0; --i) {
2527 MachineOperand &Op = Inst->getOperand(i);
2528 if (Op.isReg() && Op.getReg() == AMDGPU::SCC)
2529 Inst->RemoveOperand(i);
2532 if (Opcode == AMDGPU::S_SEXT_I32_I8 || Opcode == AMDGPU::S_SEXT_I32_I16) {
2533 // We are converting these to a BFE, so we need to add the missing
2534 // operands for the size and offset.
2535 unsigned Size = (Opcode == AMDGPU::S_SEXT_I32_I8) ? 8 : 16;
2536 Inst->addOperand(MachineOperand::CreateImm(0));
2537 Inst->addOperand(MachineOperand::CreateImm(Size));
2539 } else if (Opcode == AMDGPU::S_BCNT1_I32_B32) {
2540 // The VALU version adds the second operand to the result, so insert an
2542 Inst->addOperand(MachineOperand::CreateImm(0));
2545 Inst->addImplicitDefUseOperands(*Inst->getParent()->getParent());
2547 if (Opcode == AMDGPU::S_BFE_I32 || Opcode == AMDGPU::S_BFE_U32) {
2548 const MachineOperand &OffsetWidthOp = Inst->getOperand(2);
2549 // If we need to move this to VGPRs, we need to unpack the second operand
2550 // back into the 2 separate ones for bit offset and width.
2551 assert(OffsetWidthOp.isImm() &&
2552 "Scalar BFE is only implemented for constant width and offset");
2553 uint32_t Imm = OffsetWidthOp.getImm();
2555 uint32_t Offset = Imm & 0x3f; // Extract bits [5:0].
2556 uint32_t BitWidth = (Imm & 0x7f0000) >> 16; // Extract bits [22:16].
2557 Inst->RemoveOperand(2); // Remove old immediate.
2558 Inst->addOperand(MachineOperand::CreateImm(Offset));
2559 Inst->addOperand(MachineOperand::CreateImm(BitWidth));
2562 // Update the destination register class.
2563 const TargetRegisterClass *NewDstRC = getDestEquivalentVGPRClass(*Inst);
2567 unsigned DstReg = Inst->getOperand(0).getReg();
2568 unsigned NewDstReg = MRI.createVirtualRegister(NewDstRC);
2569 MRI.replaceRegWith(DstReg, NewDstReg);
2571 // Legalize the operands
2572 legalizeOperands(Inst);
2574 addUsersToMoveToVALUWorklist(NewDstReg, MRI, Worklist);
2578 //===----------------------------------------------------------------------===//
2579 // Indirect addressing callbacks
2580 //===----------------------------------------------------------------------===//
2582 unsigned SIInstrInfo::calculateIndirectAddress(unsigned RegIndex,
2583 unsigned Channel) const {
2584 assert(Channel == 0);
2588 const TargetRegisterClass *SIInstrInfo::getIndirectAddrRegClass() const {
2589 return &AMDGPU::VGPR_32RegClass;
2592 void SIInstrInfo::lowerScalarAbs(SmallVectorImpl<MachineInstr *> &Worklist,
2593 MachineInstr *Inst) const {
2594 MachineBasicBlock &MBB = *Inst->getParent();
2595 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
2596 MachineBasicBlock::iterator MII = Inst;
2597 DebugLoc DL = Inst->getDebugLoc();
2599 MachineOperand &Dest = Inst->getOperand(0);
2600 MachineOperand &Src = Inst->getOperand(1);
2601 unsigned TmpReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
2602 unsigned ResultReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
2604 BuildMI(MBB, MII, DL, get(AMDGPU::V_SUB_I32_e32), TmpReg)
2606 .addReg(Src.getReg());
2608 BuildMI(MBB, MII, DL, get(AMDGPU::V_MAX_I32_e64), ResultReg)
2609 .addReg(Src.getReg())
2612 MRI.replaceRegWith(Dest.getReg(), ResultReg);
2613 addUsersToMoveToVALUWorklist(ResultReg, MRI, Worklist);
2616 void SIInstrInfo::splitScalar64BitUnaryOp(
2617 SmallVectorImpl<MachineInstr *> &Worklist,
2619 unsigned Opcode) const {
2620 MachineBasicBlock &MBB = *Inst->getParent();
2621 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
2623 MachineOperand &Dest = Inst->getOperand(0);
2624 MachineOperand &Src0 = Inst->getOperand(1);
2625 DebugLoc DL = Inst->getDebugLoc();
2627 MachineBasicBlock::iterator MII = Inst;
2629 const MCInstrDesc &InstDesc = get(Opcode);
2630 const TargetRegisterClass *Src0RC = Src0.isReg() ?
2631 MRI.getRegClass(Src0.getReg()) :
2632 &AMDGPU::SGPR_32RegClass;
2634 const TargetRegisterClass *Src0SubRC = RI.getSubRegClass(Src0RC, AMDGPU::sub0);
2636 MachineOperand SrcReg0Sub0 = buildExtractSubRegOrImm(MII, MRI, Src0, Src0RC,
2637 AMDGPU::sub0, Src0SubRC);
2639 const TargetRegisterClass *DestRC = MRI.getRegClass(Dest.getReg());
2640 const TargetRegisterClass *NewDestRC = RI.getEquivalentVGPRClass(DestRC);
2641 const TargetRegisterClass *NewDestSubRC = RI.getSubRegClass(NewDestRC, AMDGPU::sub0);
2643 unsigned DestSub0 = MRI.createVirtualRegister(NewDestSubRC);
2644 BuildMI(MBB, MII, DL, InstDesc, DestSub0)
2645 .addOperand(SrcReg0Sub0);
2647 MachineOperand SrcReg0Sub1 = buildExtractSubRegOrImm(MII, MRI, Src0, Src0RC,
2648 AMDGPU::sub1, Src0SubRC);
2650 unsigned DestSub1 = MRI.createVirtualRegister(NewDestSubRC);
2651 BuildMI(MBB, MII, DL, InstDesc, DestSub1)
2652 .addOperand(SrcReg0Sub1);
2654 unsigned FullDestReg = MRI.createVirtualRegister(NewDestRC);
2655 BuildMI(MBB, MII, DL, get(TargetOpcode::REG_SEQUENCE), FullDestReg)
2657 .addImm(AMDGPU::sub0)
2659 .addImm(AMDGPU::sub1);
2661 MRI.replaceRegWith(Dest.getReg(), FullDestReg);
2663 // We don't need to legalizeOperands here because for a single operand, src0
2664 // will support any kind of input.
2666 // Move all users of this moved value.
2667 addUsersToMoveToVALUWorklist(FullDestReg, MRI, Worklist);
2670 void SIInstrInfo::splitScalar64BitBinaryOp(
2671 SmallVectorImpl<MachineInstr *> &Worklist,
2673 unsigned Opcode) const {
2674 MachineBasicBlock &MBB = *Inst->getParent();
2675 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
2677 MachineOperand &Dest = Inst->getOperand(0);
2678 MachineOperand &Src0 = Inst->getOperand(1);
2679 MachineOperand &Src1 = Inst->getOperand(2);
2680 DebugLoc DL = Inst->getDebugLoc();
2682 MachineBasicBlock::iterator MII = Inst;
2684 const MCInstrDesc &InstDesc = get(Opcode);
2685 const TargetRegisterClass *Src0RC = Src0.isReg() ?
2686 MRI.getRegClass(Src0.getReg()) :
2687 &AMDGPU::SGPR_32RegClass;
2689 const TargetRegisterClass *Src0SubRC = RI.getSubRegClass(Src0RC, AMDGPU::sub0);
2690 const TargetRegisterClass *Src1RC = Src1.isReg() ?
2691 MRI.getRegClass(Src1.getReg()) :
2692 &AMDGPU::SGPR_32RegClass;
2694 const TargetRegisterClass *Src1SubRC = RI.getSubRegClass(Src1RC, AMDGPU::sub0);
2696 MachineOperand SrcReg0Sub0 = buildExtractSubRegOrImm(MII, MRI, Src0, Src0RC,
2697 AMDGPU::sub0, Src0SubRC);
2698 MachineOperand SrcReg1Sub0 = buildExtractSubRegOrImm(MII, MRI, Src1, Src1RC,
2699 AMDGPU::sub0, Src1SubRC);
2701 const TargetRegisterClass *DestRC = MRI.getRegClass(Dest.getReg());
2702 const TargetRegisterClass *NewDestRC = RI.getEquivalentVGPRClass(DestRC);
2703 const TargetRegisterClass *NewDestSubRC = RI.getSubRegClass(NewDestRC, AMDGPU::sub0);
2705 unsigned DestSub0 = MRI.createVirtualRegister(NewDestSubRC);
2706 MachineInstr *LoHalf = BuildMI(MBB, MII, DL, InstDesc, DestSub0)
2707 .addOperand(SrcReg0Sub0)
2708 .addOperand(SrcReg1Sub0);
2710 MachineOperand SrcReg0Sub1 = buildExtractSubRegOrImm(MII, MRI, Src0, Src0RC,
2711 AMDGPU::sub1, Src0SubRC);
2712 MachineOperand SrcReg1Sub1 = buildExtractSubRegOrImm(MII, MRI, Src1, Src1RC,
2713 AMDGPU::sub1, Src1SubRC);
2715 unsigned DestSub1 = MRI.createVirtualRegister(NewDestSubRC);
2716 MachineInstr *HiHalf = BuildMI(MBB, MII, DL, InstDesc, DestSub1)
2717 .addOperand(SrcReg0Sub1)
2718 .addOperand(SrcReg1Sub1);
2720 unsigned FullDestReg = MRI.createVirtualRegister(NewDestRC);
2721 BuildMI(MBB, MII, DL, get(TargetOpcode::REG_SEQUENCE), FullDestReg)
2723 .addImm(AMDGPU::sub0)
2725 .addImm(AMDGPU::sub1);
2727 MRI.replaceRegWith(Dest.getReg(), FullDestReg);
2729 // Try to legalize the operands in case we need to swap the order to keep it
2731 legalizeOperands(LoHalf);
2732 legalizeOperands(HiHalf);
2734 // Move all users of this moved vlaue.
2735 addUsersToMoveToVALUWorklist(FullDestReg, MRI, Worklist);
2738 void SIInstrInfo::splitScalar64BitBCNT(SmallVectorImpl<MachineInstr *> &Worklist,
2739 MachineInstr *Inst) const {
2740 MachineBasicBlock &MBB = *Inst->getParent();
2741 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
2743 MachineBasicBlock::iterator MII = Inst;
2744 DebugLoc DL = Inst->getDebugLoc();
2746 MachineOperand &Dest = Inst->getOperand(0);
2747 MachineOperand &Src = Inst->getOperand(1);
2749 const MCInstrDesc &InstDesc = get(AMDGPU::V_BCNT_U32_B32_e64);
2750 const TargetRegisterClass *SrcRC = Src.isReg() ?
2751 MRI.getRegClass(Src.getReg()) :
2752 &AMDGPU::SGPR_32RegClass;
2754 unsigned MidReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
2755 unsigned ResultReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
2757 const TargetRegisterClass *SrcSubRC = RI.getSubRegClass(SrcRC, AMDGPU::sub0);
2759 MachineOperand SrcRegSub0 = buildExtractSubRegOrImm(MII, MRI, Src, SrcRC,
2760 AMDGPU::sub0, SrcSubRC);
2761 MachineOperand SrcRegSub1 = buildExtractSubRegOrImm(MII, MRI, Src, SrcRC,
2762 AMDGPU::sub1, SrcSubRC);
2764 BuildMI(MBB, MII, DL, InstDesc, MidReg)
2765 .addOperand(SrcRegSub0)
2768 BuildMI(MBB, MII, DL, InstDesc, ResultReg)
2769 .addOperand(SrcRegSub1)
2772 MRI.replaceRegWith(Dest.getReg(), ResultReg);
2774 // We don't need to legalize operands here. src0 for etiher instruction can be
2775 // an SGPR, and the second input is unused or determined here.
2776 addUsersToMoveToVALUWorklist(ResultReg, MRI, Worklist);
2779 void SIInstrInfo::splitScalar64BitBFE(SmallVectorImpl<MachineInstr *> &Worklist,
2780 MachineInstr *Inst) const {
2781 MachineBasicBlock &MBB = *Inst->getParent();
2782 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
2783 MachineBasicBlock::iterator MII = Inst;
2784 DebugLoc DL = Inst->getDebugLoc();
2786 MachineOperand &Dest = Inst->getOperand(0);
2787 uint32_t Imm = Inst->getOperand(2).getImm();
2788 uint32_t Offset = Imm & 0x3f; // Extract bits [5:0].
2789 uint32_t BitWidth = (Imm & 0x7f0000) >> 16; // Extract bits [22:16].
2793 // Only sext_inreg cases handled.
2794 assert(Inst->getOpcode() == AMDGPU::S_BFE_I64 &&
2799 if (BitWidth < 32) {
2800 unsigned MidRegLo = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
2801 unsigned MidRegHi = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
2802 unsigned ResultReg = MRI.createVirtualRegister(&AMDGPU::VReg_64RegClass);
2804 BuildMI(MBB, MII, DL, get(AMDGPU::V_BFE_I32), MidRegLo)
2805 .addReg(Inst->getOperand(1).getReg(), 0, AMDGPU::sub0)
2809 BuildMI(MBB, MII, DL, get(AMDGPU::V_ASHRREV_I32_e32), MidRegHi)
2813 BuildMI(MBB, MII, DL, get(TargetOpcode::REG_SEQUENCE), ResultReg)
2815 .addImm(AMDGPU::sub0)
2817 .addImm(AMDGPU::sub1);
2819 MRI.replaceRegWith(Dest.getReg(), ResultReg);
2820 addUsersToMoveToVALUWorklist(ResultReg, MRI, Worklist);
2824 MachineOperand &Src = Inst->getOperand(1);
2825 unsigned TmpReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
2826 unsigned ResultReg = MRI.createVirtualRegister(&AMDGPU::VReg_64RegClass);
2828 BuildMI(MBB, MII, DL, get(AMDGPU::V_ASHRREV_I32_e64), TmpReg)
2830 .addReg(Src.getReg(), 0, AMDGPU::sub0);
2832 BuildMI(MBB, MII, DL, get(TargetOpcode::REG_SEQUENCE), ResultReg)
2833 .addReg(Src.getReg(), 0, AMDGPU::sub0)
2834 .addImm(AMDGPU::sub0)
2836 .addImm(AMDGPU::sub1);
2838 MRI.replaceRegWith(Dest.getReg(), ResultReg);
2839 addUsersToMoveToVALUWorklist(ResultReg, MRI, Worklist);
2842 void SIInstrInfo::addUsersToMoveToVALUWorklist(
2844 MachineRegisterInfo &MRI,
2845 SmallVectorImpl<MachineInstr *> &Worklist) const {
2846 for (MachineRegisterInfo::use_iterator I = MRI.use_begin(DstReg),
2847 E = MRI.use_end(); I != E; ++I) {
2848 MachineInstr &UseMI = *I->getParent();
2849 if (!canReadVGPR(UseMI, I.getOperandNo())) {
2850 Worklist.push_back(&UseMI);
2855 const TargetRegisterClass *SIInstrInfo::getDestEquivalentVGPRClass(
2856 const MachineInstr &Inst) const {
2857 const TargetRegisterClass *NewDstRC = getOpRegClass(Inst, 0);
2859 switch (Inst.getOpcode()) {
2860 // For target instructions, getOpRegClass just returns the virtual register
2861 // class associated with the operand, so we need to find an equivalent VGPR
2862 // register class in order to move the instruction to the VALU.
2865 case AMDGPU::REG_SEQUENCE:
2866 case AMDGPU::INSERT_SUBREG:
2867 if (RI.hasVGPRs(NewDstRC))
2870 NewDstRC = RI.getEquivalentVGPRClass(NewDstRC);
2879 // Find the one SGPR operand we are allowed to use.
2880 unsigned SIInstrInfo::findUsedSGPR(const MachineInstr *MI,
2881 int OpIndices[3]) const {
2882 const MCInstrDesc &Desc = MI->getDesc();
2884 // Find the one SGPR operand we are allowed to use.
2886 // First we need to consider the instruction's operand requirements before
2887 // legalizing. Some operands are required to be SGPRs, such as implicit uses
2888 // of VCC, but we are still bound by the constant bus requirement to only use
2891 // If the operand's class is an SGPR, we can never move it.
2893 unsigned SGPRReg = findImplicitSGPRRead(*MI);
2894 if (SGPRReg != AMDGPU::NoRegister)
2897 unsigned UsedSGPRs[3] = { AMDGPU::NoRegister };
2898 const MachineRegisterInfo &MRI = MI->getParent()->getParent()->getRegInfo();
2900 for (unsigned i = 0; i < 3; ++i) {
2901 int Idx = OpIndices[i];
2905 const MachineOperand &MO = MI->getOperand(Idx);
2909 // Is this operand statically required to be an SGPR based on the operand
2911 const TargetRegisterClass *OpRC = RI.getRegClass(Desc.OpInfo[Idx].RegClass);
2912 bool IsRequiredSGPR = RI.isSGPRClass(OpRC);
2916 // If this could be a VGPR or an SGPR, Check the dynamic register class.
2917 unsigned Reg = MO.getReg();
2918 const TargetRegisterClass *RegRC = MRI.getRegClass(Reg);
2919 if (RI.isSGPRClass(RegRC))
2923 // We don't have a required SGPR operand, so we have a bit more freedom in
2924 // selecting operands to move.
2926 // Try to select the most used SGPR. If an SGPR is equal to one of the
2927 // others, we choose that.
2930 // V_FMA_F32 v0, s0, s0, s0 -> No moves
2931 // V_FMA_F32 v0, s0, s1, s0 -> Move s1
2933 // TODO: If some of the operands are 64-bit SGPRs and some 32, we should
2936 if (UsedSGPRs[0] != AMDGPU::NoRegister) {
2937 if (UsedSGPRs[0] == UsedSGPRs[1] || UsedSGPRs[0] == UsedSGPRs[2])
2938 SGPRReg = UsedSGPRs[0];
2941 if (SGPRReg == AMDGPU::NoRegister && UsedSGPRs[1] != AMDGPU::NoRegister) {
2942 if (UsedSGPRs[1] == UsedSGPRs[2])
2943 SGPRReg = UsedSGPRs[1];
2949 MachineInstrBuilder SIInstrInfo::buildIndirectWrite(
2950 MachineBasicBlock *MBB,
2951 MachineBasicBlock::iterator I,
2953 unsigned Address, unsigned OffsetReg) const {
2954 const DebugLoc &DL = MBB->findDebugLoc(I);
2955 unsigned IndirectBaseReg = AMDGPU::VGPR_32RegClass.getRegister(
2956 getIndirectIndexBegin(*MBB->getParent()));
2958 return BuildMI(*MBB, I, DL, get(AMDGPU::SI_INDIRECT_DST_V1))
2959 .addReg(IndirectBaseReg, RegState::Define)
2960 .addOperand(I->getOperand(0))
2961 .addReg(IndirectBaseReg)
2967 MachineInstrBuilder SIInstrInfo::buildIndirectRead(
2968 MachineBasicBlock *MBB,
2969 MachineBasicBlock::iterator I,
2971 unsigned Address, unsigned OffsetReg) const {
2972 const DebugLoc &DL = MBB->findDebugLoc(I);
2973 unsigned IndirectBaseReg = AMDGPU::VGPR_32RegClass.getRegister(
2974 getIndirectIndexBegin(*MBB->getParent()));
2976 return BuildMI(*MBB, I, DL, get(AMDGPU::SI_INDIRECT_SRC_V1))
2977 .addOperand(I->getOperand(0))
2978 .addOperand(I->getOperand(1))
2979 .addReg(IndirectBaseReg)
2985 void SIInstrInfo::reserveIndirectRegisters(BitVector &Reserved,
2986 const MachineFunction &MF) const {
2987 int End = getIndirectIndexEnd(MF);
2988 int Begin = getIndirectIndexBegin(MF);
2994 for (int Index = Begin; Index <= End; ++Index)
2995 Reserved.set(AMDGPU::VGPR_32RegClass.getRegister(Index));
2997 for (int Index = std::max(0, Begin - 1); Index <= End; ++Index)
2998 Reserved.set(AMDGPU::VReg_64RegClass.getRegister(Index));
3000 for (int Index = std::max(0, Begin - 2); Index <= End; ++Index)
3001 Reserved.set(AMDGPU::VReg_96RegClass.getRegister(Index));
3003 for (int Index = std::max(0, Begin - 3); Index <= End; ++Index)
3004 Reserved.set(AMDGPU::VReg_128RegClass.getRegister(Index));
3006 for (int Index = std::max(0, Begin - 7); Index <= End; ++Index)
3007 Reserved.set(AMDGPU::VReg_256RegClass.getRegister(Index));
3009 for (int Index = std::max(0, Begin - 15); Index <= End; ++Index)
3010 Reserved.set(AMDGPU::VReg_512RegClass.getRegister(Index));
3013 MachineOperand *SIInstrInfo::getNamedOperand(MachineInstr &MI,
3014 unsigned OperandName) const {
3015 int Idx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), OperandName);
3019 return &MI.getOperand(Idx);
3022 uint64_t SIInstrInfo::getDefaultRsrcDataFormat() const {
3023 uint64_t RsrcDataFormat = AMDGPU::RSRC_DATA_FORMAT;
3024 if (ST.isAmdHsaOS()) {
3025 RsrcDataFormat |= (1ULL << 56);
3027 if (ST.getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS)
3029 RsrcDataFormat |= (2ULL << 59);
3032 return RsrcDataFormat;
3035 uint64_t SIInstrInfo::getScratchRsrcWords23() const {
3036 uint64_t Rsrc23 = getDefaultRsrcDataFormat() |
3037 AMDGPU::RSRC_TID_ENABLE |
3038 0xffffffff; // Size;
3040 // If TID_ENABLE is set, DATA_FORMAT specifies stride bits [14:17].
3041 // Clear them unless we want a huge stride.
3042 if (ST.getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS)
3043 Rsrc23 &= ~AMDGPU::RSRC_DATA_FORMAT;