1 //===-- SIFixSGPRCopies.cpp - Remove potential VGPR => SGPR copies --------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// Copies from VGPR to SGPR registers are illegal and the register coalescer
12 /// will sometimes generate these illegal copies in situations like this:
14 /// Register Class <vsrc> is the union of <vgpr> and <sgpr>
17 /// %vreg0 <sgpr> = SCALAR_INST
18 /// %vreg1 <vsrc> = COPY %vreg0 <sgpr>
20 /// BRANCH %cond BB1, BB2
22 /// %vreg2 <vgpr> = VECTOR_INST
23 /// %vreg3 <vsrc> = COPY %vreg2 <vgpr>
25 /// %vreg4 <vsrc> = PHI %vreg1 <vsrc>, <BB#0>, %vreg3 <vrsc>, <BB#1>
26 /// %vreg5 <vgpr> = VECTOR_INST %vreg4 <vsrc>
29 /// The coalescer will begin at BB0 and eliminate its copy, then the resulting
30 /// code will look like this:
33 /// %vreg0 <sgpr> = SCALAR_INST
35 /// BRANCH %cond BB1, BB2
37 /// %vreg2 <vgpr> = VECTOR_INST
38 /// %vreg3 <vsrc> = COPY %vreg2 <vgpr>
40 /// %vreg4 <sgpr> = PHI %vreg0 <sgpr>, <BB#0>, %vreg3 <vsrc>, <BB#1>
41 /// %vreg5 <vgpr> = VECTOR_INST %vreg4 <sgpr>
43 /// Now that the result of the PHI instruction is an SGPR, the register
44 /// allocator is now forced to constrain the register class of %vreg3 to
45 /// <sgpr> so we end up with final code like this:
48 /// %vreg0 <sgpr> = SCALAR_INST
50 /// BRANCH %cond BB1, BB2
52 /// %vreg2 <vgpr> = VECTOR_INST
53 /// %vreg3 <sgpr> = COPY %vreg2 <vgpr>
55 /// %vreg4 <sgpr> = PHI %vreg0 <sgpr>, <BB#0>, %vreg3 <sgpr>, <BB#1>
56 /// %vreg5 <vgpr> = VECTOR_INST %vreg4 <sgpr>
58 /// Now this code contains an illegal copy from a VGPR to an SGPR.
60 /// In order to avoid this problem, this pass searches for PHI instructions
61 /// which define a <vsrc> register and constrains its definition class to
62 /// <vgpr> if the user of the PHI's definition register is a vector instruction.
63 /// If the PHI's definition class is constrained to <vgpr> then the coalescer
64 /// will be unable to perform the COPY removal from the above example which
65 /// ultimately led to the creation of an illegal COPY.
66 //===----------------------------------------------------------------------===//
69 #include "AMDGPUSubtarget.h"
70 #include "SIInstrInfo.h"
71 #include "llvm/CodeGen/MachineFunctionPass.h"
72 #include "llvm/CodeGen/MachineInstrBuilder.h"
73 #include "llvm/CodeGen/MachineRegisterInfo.h"
74 #include "llvm/Support/Debug.h"
75 #include "llvm/Support/raw_ostream.h"
76 #include "llvm/Target/TargetMachine.h"
80 #define DEBUG_TYPE "sgpr-copies"
84 class SIFixSGPRCopies : public MachineFunctionPass {
88 const TargetRegisterClass *inferRegClassFromUses(const SIRegisterInfo *TRI,
89 const MachineRegisterInfo &MRI,
91 unsigned SubReg) const;
92 const TargetRegisterClass *inferRegClassFromDef(const SIRegisterInfo *TRI,
93 const MachineRegisterInfo &MRI,
95 unsigned SubReg) const;
96 bool isVGPRToSGPRCopy(const MachineInstr &Copy, const SIRegisterInfo *TRI,
97 const MachineRegisterInfo &MRI) const;
100 SIFixSGPRCopies(TargetMachine &tm) : MachineFunctionPass(ID) { }
102 bool runOnMachineFunction(MachineFunction &MF) override;
104 const char *getPassName() const override {
105 return "SI Fix SGPR copies";
108 void getAnalysisUsage(AnalysisUsage &AU) const override {
109 AU.setPreservesCFG();
110 MachineFunctionPass::getAnalysisUsage(AU);
114 } // End anonymous namespace
116 char SIFixSGPRCopies::ID = 0;
118 FunctionPass *llvm::createSIFixSGPRCopiesPass(TargetMachine &tm) {
119 return new SIFixSGPRCopies(tm);
122 static bool hasVGPROperands(const MachineInstr &MI, const SIRegisterInfo *TRI) {
123 const MachineRegisterInfo &MRI = MI.getParent()->getParent()->getRegInfo();
124 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
125 if (!MI.getOperand(i).isReg() ||
126 !TargetRegisterInfo::isVirtualRegister(MI.getOperand(i).getReg()))
129 if (TRI->hasVGPRs(MRI.getRegClass(MI.getOperand(i).getReg())))
135 /// This functions walks the use list of Reg until it finds an Instruction
136 /// that isn't a COPY returns the register class of that instruction.
137 /// \return The register defined by the first non-COPY instruction.
138 const TargetRegisterClass *SIFixSGPRCopies::inferRegClassFromUses(
139 const SIRegisterInfo *TRI,
140 const MachineRegisterInfo &MRI,
142 unsigned SubReg) const {
144 const TargetRegisterClass *RC
145 = TargetRegisterInfo::isVirtualRegister(Reg) ?
146 MRI.getRegClass(Reg) :
147 TRI->getPhysRegClass(Reg);
149 RC = TRI->getSubRegClass(RC, SubReg);
150 for (MachineRegisterInfo::use_instr_iterator
151 I = MRI.use_instr_begin(Reg), E = MRI.use_instr_end(); I != E; ++I) {
152 switch (I->getOpcode()) {
154 RC = TRI->getCommonSubClass(RC, inferRegClassFromUses(TRI, MRI,
155 I->getOperand(0).getReg(),
156 I->getOperand(0).getSubReg()));
164 const TargetRegisterClass *SIFixSGPRCopies::inferRegClassFromDef(
165 const SIRegisterInfo *TRI,
166 const MachineRegisterInfo &MRI,
168 unsigned SubReg) const {
169 if (!TargetRegisterInfo::isVirtualRegister(Reg)) {
170 const TargetRegisterClass *RC = TRI->getPhysRegClass(Reg);
171 return TRI->getSubRegClass(RC, SubReg);
173 MachineInstr *Def = MRI.getVRegDef(Reg);
174 if (Def->getOpcode() != AMDGPU::COPY) {
175 return TRI->getSubRegClass(MRI.getRegClass(Reg), SubReg);
178 return inferRegClassFromDef(TRI, MRI, Def->getOperand(1).getReg(),
179 Def->getOperand(1).getSubReg());
182 bool SIFixSGPRCopies::isVGPRToSGPRCopy(const MachineInstr &Copy,
183 const SIRegisterInfo *TRI,
184 const MachineRegisterInfo &MRI) const {
186 unsigned DstReg = Copy.getOperand(0).getReg();
187 unsigned SrcReg = Copy.getOperand(1).getReg();
188 unsigned SrcSubReg = Copy.getOperand(1).getSubReg();
190 if (!TargetRegisterInfo::isVirtualRegister(DstReg)) {
191 // If the destination register is a physical register there isn't really
192 // much we can do to fix this.
196 const TargetRegisterClass *DstRC = MRI.getRegClass(DstReg);
198 const TargetRegisterClass *SrcRC;
200 if (!TargetRegisterInfo::isVirtualRegister(SrcReg) ||
201 MRI.getRegClass(SrcReg) == &AMDGPU::VReg_1RegClass)
204 SrcRC = TRI->getSubRegClass(MRI.getRegClass(SrcReg), SrcSubReg);
205 return TRI->isSGPRClass(DstRC) && TRI->hasVGPRs(SrcRC);
208 bool SIFixSGPRCopies::runOnMachineFunction(MachineFunction &MF) {
209 MachineRegisterInfo &MRI = MF.getRegInfo();
210 const SIRegisterInfo *TRI =
211 static_cast<const SIRegisterInfo *>(MF.getSubtarget().getRegisterInfo());
212 const SIInstrInfo *TII =
213 static_cast<const SIInstrInfo *>(MF.getSubtarget().getInstrInfo());
214 for (MachineFunction::iterator BI = MF.begin(), BE = MF.end();
217 MachineBasicBlock &MBB = *BI;
218 for (MachineBasicBlock::iterator I = MBB.begin(), E = MBB.end();
220 MachineInstr &MI = *I;
222 switch (MI.getOpcode()) {
226 if (isVGPRToSGPRCopy(MI, TRI, MRI)) {
227 DEBUG(dbgs() << "Fixing VGPR -> SGPR copy: " << MI);
234 DEBUG(dbgs() << "Fixing PHI: " << MI);
236 for (unsigned i = 1; i < MI.getNumOperands(); i += 2) {
237 const MachineOperand &Op = MI.getOperand(i);
238 unsigned Reg = Op.getReg();
239 const TargetRegisterClass *RC
240 = inferRegClassFromDef(TRI, MRI, Reg, Op.getSubReg());
242 MRI.constrainRegClass(Op.getReg(), RC);
244 unsigned Reg = MI.getOperand(0).getReg();
245 const TargetRegisterClass *RC = inferRegClassFromUses(TRI, MRI, Reg,
246 MI.getOperand(0).getSubReg());
247 if (TRI->getCommonSubClass(RC, &AMDGPU::VGPR_32RegClass)) {
248 MRI.constrainRegClass(Reg, &AMDGPU::VGPR_32RegClass);
251 if (!TRI->isSGPRClass(MRI.getRegClass(Reg)))
254 // If a PHI node defines an SGPR and any of its operands are VGPRs,
255 // then we need to move it to the VALU.
257 // Also, if a PHI node defines an SGPR and has all SGPR operands
258 // we must move it to the VALU, because the SGPR operands will
259 // all end up being assigned the same register, which means
260 // there is a potential for a conflict if different threads take
261 // different control flow paths.
269 // sgpr2 = PHI sgpr0, sgpr1
280 // FIXME: This is OK if the branching decision is made based on an
282 bool SGPRBranch = false;
284 // The one exception to this rule is when one of the operands
285 // is defined by a SI_BREAK, SI_IF_BREAK, or SI_ELSE_BREAK
286 // instruction. In this case, there we know the program will
287 // never enter the second block (the loop) without entering
288 // the first block (where the condition is computed), so there
289 // is no chance for values to be over-written.
291 bool HasBreakDef = false;
292 for (unsigned i = 1; i < MI.getNumOperands(); i+=2) {
293 unsigned Reg = MI.getOperand(i).getReg();
294 if (TRI->hasVGPRs(MRI.getRegClass(Reg))) {
298 MachineInstr *DefInstr = MRI.getUniqueVRegDef(Reg);
300 switch(DefInstr->getOpcode()) {
302 case AMDGPU::SI_BREAK:
303 case AMDGPU::SI_IF_BREAK:
304 case AMDGPU::SI_ELSE_BREAK:
305 // If we see a PHI instruction that defines an SGPR, then that PHI
306 // instruction has already been considered and should have
307 // a *_BREAK as an operand.
314 if (!SGPRBranch && !HasBreakDef)
318 case AMDGPU::REG_SEQUENCE: {
319 if (TRI->hasVGPRs(TII->getOpRegClass(MI, 0)) ||
320 !hasVGPROperands(MI, TRI))
323 DEBUG(dbgs() << "Fixing REG_SEQUENCE: " << MI);
328 case AMDGPU::INSERT_SUBREG: {
329 const TargetRegisterClass *DstRC, *Src0RC, *Src1RC;
330 DstRC = MRI.getRegClass(MI.getOperand(0).getReg());
331 Src0RC = MRI.getRegClass(MI.getOperand(1).getReg());
332 Src1RC = MRI.getRegClass(MI.getOperand(2).getReg());
333 if (TRI->isSGPRClass(DstRC) &&
334 (TRI->hasVGPRs(Src0RC) || TRI->hasVGPRs(Src1RC))) {
335 DEBUG(dbgs() << " Fixing INSERT_SUBREG: " << MI);