1 //===-- R600ISelLowering.cpp - R600 DAG Lowering Implementation -----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// \brief Custom DAG lowering for R600
13 //===----------------------------------------------------------------------===//
15 #include "R600ISelLowering.h"
16 #include "AMDGPUFrameLowering.h"
17 #include "AMDGPUIntrinsicInfo.h"
18 #include "AMDGPUSubtarget.h"
19 #include "R600Defines.h"
20 #include "R600InstrInfo.h"
21 #include "R600MachineFunctionInfo.h"
22 #include "llvm/Analysis/ValueTracking.h"
23 #include "llvm/CodeGen/CallingConvLower.h"
24 #include "llvm/CodeGen/MachineFrameInfo.h"
25 #include "llvm/CodeGen/MachineInstrBuilder.h"
26 #include "llvm/CodeGen/MachineRegisterInfo.h"
27 #include "llvm/CodeGen/SelectionDAG.h"
28 #include "llvm/IR/Argument.h"
29 #include "llvm/IR/Function.h"
33 R600TargetLowering::R600TargetLowering(TargetMachine &TM,
34 const AMDGPUSubtarget &STI)
35 : AMDGPUTargetLowering(TM, STI), Gen(STI.getGeneration()) {
36 addRegisterClass(MVT::v4f32, &AMDGPU::R600_Reg128RegClass);
37 addRegisterClass(MVT::f32, &AMDGPU::R600_Reg32RegClass);
38 addRegisterClass(MVT::v4i32, &AMDGPU::R600_Reg128RegClass);
39 addRegisterClass(MVT::i32, &AMDGPU::R600_Reg32RegClass);
40 addRegisterClass(MVT::v2f32, &AMDGPU::R600_Reg64RegClass);
41 addRegisterClass(MVT::v2i32, &AMDGPU::R600_Reg64RegClass);
43 computeRegisterProperties(STI.getRegisterInfo());
45 // Set condition code actions
46 setCondCodeAction(ISD::SETO, MVT::f32, Expand);
47 setCondCodeAction(ISD::SETUO, MVT::f32, Expand);
48 setCondCodeAction(ISD::SETLT, MVT::f32, Expand);
49 setCondCodeAction(ISD::SETLE, MVT::f32, Expand);
50 setCondCodeAction(ISD::SETOLT, MVT::f32, Expand);
51 setCondCodeAction(ISD::SETOLE, MVT::f32, Expand);
52 setCondCodeAction(ISD::SETONE, MVT::f32, Expand);
53 setCondCodeAction(ISD::SETUEQ, MVT::f32, Expand);
54 setCondCodeAction(ISD::SETUGE, MVT::f32, Expand);
55 setCondCodeAction(ISD::SETUGT, MVT::f32, Expand);
56 setCondCodeAction(ISD::SETULT, MVT::f32, Expand);
57 setCondCodeAction(ISD::SETULE, MVT::f32, Expand);
59 setCondCodeAction(ISD::SETLE, MVT::i32, Expand);
60 setCondCodeAction(ISD::SETLT, MVT::i32, Expand);
61 setCondCodeAction(ISD::SETULE, MVT::i32, Expand);
62 setCondCodeAction(ISD::SETULT, MVT::i32, Expand);
64 setOperationAction(ISD::FCOS, MVT::f32, Custom);
65 setOperationAction(ISD::FSIN, MVT::f32, Custom);
67 setOperationAction(ISD::SETCC, MVT::v4i32, Expand);
68 setOperationAction(ISD::SETCC, MVT::v2i32, Expand);
70 setOperationAction(ISD::BR_CC, MVT::i32, Expand);
71 setOperationAction(ISD::BR_CC, MVT::f32, Expand);
72 setOperationAction(ISD::BRCOND, MVT::Other, Custom);
74 setOperationAction(ISD::FSUB, MVT::f32, Expand);
76 setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
77 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
78 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::i1, Custom);
80 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
81 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
83 setOperationAction(ISD::SETCC, MVT::i32, Expand);
84 setOperationAction(ISD::SETCC, MVT::f32, Expand);
85 setOperationAction(ISD::FP_TO_UINT, MVT::i1, Custom);
86 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
87 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Custom);
89 setOperationAction(ISD::SELECT, MVT::i32, Expand);
90 setOperationAction(ISD::SELECT, MVT::f32, Expand);
91 setOperationAction(ISD::SELECT, MVT::v2i32, Expand);
92 setOperationAction(ISD::SELECT, MVT::v4i32, Expand);
95 // TODO: turn these into Legal?
96 if (Subtarget->hasCARRY())
97 setOperationAction(ISD::UADDO, MVT::i32, Custom);
99 if (Subtarget->hasBORROW())
100 setOperationAction(ISD::USUBO, MVT::i32, Custom);
102 // Expand sign extension of vectors
103 if (!Subtarget->hasBFE())
104 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
106 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i1, Expand);
107 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i1, Expand);
109 if (!Subtarget->hasBFE())
110 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand);
111 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i8, Expand);
112 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i8, Expand);
114 if (!Subtarget->hasBFE())
115 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
116 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i16, Expand);
117 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i16, Expand);
119 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
120 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i32, Expand);
121 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i32, Expand);
123 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::Other, Expand);
126 // Legalize loads and stores to the private address space.
127 setOperationAction(ISD::LOAD, MVT::i32, Custom);
128 setOperationAction(ISD::LOAD, MVT::v2i32, Custom);
129 setOperationAction(ISD::LOAD, MVT::v4i32, Custom);
131 // EXTLOAD should be the same as ZEXTLOAD. It is legal for some address
132 // spaces, so it is custom lowered to handle those where it isn't.
133 for (MVT VT : MVT::integer_valuetypes()) {
134 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
135 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i8, Custom);
136 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i16, Custom);
138 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1, Promote);
139 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i8, Custom);
140 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i16, Custom);
142 setLoadExtAction(ISD::EXTLOAD, VT, MVT::i1, Promote);
143 setLoadExtAction(ISD::EXTLOAD, VT, MVT::i8, Custom);
144 setLoadExtAction(ISD::EXTLOAD, VT, MVT::i16, Custom);
147 setOperationAction(ISD::STORE, MVT::i8, Custom);
148 setOperationAction(ISD::STORE, MVT::i32, Custom);
149 setOperationAction(ISD::STORE, MVT::v2i32, Custom);
150 setOperationAction(ISD::STORE, MVT::v4i32, Custom);
151 setTruncStoreAction(MVT::i32, MVT::i8, Custom);
152 setTruncStoreAction(MVT::i32, MVT::i16, Custom);
154 setOperationAction(ISD::LOAD, MVT::i32, Custom);
155 setOperationAction(ISD::LOAD, MVT::v4i32, Custom);
156 setOperationAction(ISD::FrameIndex, MVT::i32, Custom);
158 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i32, Custom);
159 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f32, Custom);
160 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom);
161 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
163 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i32, Custom);
164 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f32, Custom);
165 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
166 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
168 setTargetDAGCombine(ISD::FP_ROUND);
169 setTargetDAGCombine(ISD::FP_TO_SINT);
170 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT);
171 setTargetDAGCombine(ISD::SELECT_CC);
172 setTargetDAGCombine(ISD::INSERT_VECTOR_ELT);
174 // We don't have 64-bit shifts. Thus we need either SHX i64 or SHX_PARTS i32
175 // to be Legal/Custom in order to avoid library calls.
176 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom);
177 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom);
178 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom);
180 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
182 const MVT ScalarIntVTs[] = { MVT::i32, MVT::i64 };
183 for (MVT VT : ScalarIntVTs) {
184 setOperationAction(ISD::ADDC, VT, Expand);
185 setOperationAction(ISD::SUBC, VT, Expand);
186 setOperationAction(ISD::ADDE, VT, Expand);
187 setOperationAction(ISD::SUBE, VT, Expand);
190 setSchedulingPreference(Sched::Source);
193 static inline bool isEOP(MachineBasicBlock::iterator I) {
194 return std::next(I)->getOpcode() == AMDGPU::RETURN;
197 MachineBasicBlock * R600TargetLowering::EmitInstrWithCustomInserter(
198 MachineInstr * MI, MachineBasicBlock * BB) const {
199 MachineFunction * MF = BB->getParent();
200 MachineRegisterInfo &MRI = MF->getRegInfo();
201 MachineBasicBlock::iterator I = *MI;
202 const R600InstrInfo *TII =
203 static_cast<const R600InstrInfo *>(Subtarget->getInstrInfo());
205 switch (MI->getOpcode()) {
207 // Replace LDS_*_RET instruction that don't have any uses with the
208 // equivalent LDS_*_NORET instruction.
209 if (TII->isLDSRetInstr(MI->getOpcode())) {
210 int DstIdx = TII->getOperandIdx(MI->getOpcode(), AMDGPU::OpName::dst);
211 assert(DstIdx != -1);
212 MachineInstrBuilder NewMI;
213 // FIXME: getLDSNoRetOp method only handles LDS_1A1D LDS ops. Add
214 // LDS_1A2D support and remove this special case.
215 if (!MRI.use_empty(MI->getOperand(DstIdx).getReg()) ||
216 MI->getOpcode() == AMDGPU::LDS_CMPST_RET)
219 NewMI = BuildMI(*BB, I, BB->findDebugLoc(I),
220 TII->get(AMDGPU::getLDSNoRetOp(MI->getOpcode())));
221 for (unsigned i = 1, e = MI->getNumOperands(); i < e; ++i) {
222 NewMI.addOperand(MI->getOperand(i));
225 return AMDGPUTargetLowering::EmitInstrWithCustomInserter(MI, BB);
228 case AMDGPU::CLAMP_R600: {
229 MachineInstr *NewMI = TII->buildDefaultInstruction(*BB, I,
231 MI->getOperand(0).getReg(),
232 MI->getOperand(1).getReg());
233 TII->addFlag(NewMI, 0, MO_FLAG_CLAMP);
237 case AMDGPU::FABS_R600: {
238 MachineInstr *NewMI = TII->buildDefaultInstruction(*BB, I,
240 MI->getOperand(0).getReg(),
241 MI->getOperand(1).getReg());
242 TII->addFlag(NewMI, 0, MO_FLAG_ABS);
246 case AMDGPU::FNEG_R600: {
247 MachineInstr *NewMI = TII->buildDefaultInstruction(*BB, I,
249 MI->getOperand(0).getReg(),
250 MI->getOperand(1).getReg());
251 TII->addFlag(NewMI, 0, MO_FLAG_NEG);
255 case AMDGPU::MASK_WRITE: {
256 unsigned maskedRegister = MI->getOperand(0).getReg();
257 assert(TargetRegisterInfo::isVirtualRegister(maskedRegister));
258 MachineInstr * defInstr = MRI.getVRegDef(maskedRegister);
259 TII->addFlag(defInstr, 0, MO_FLAG_MASK);
263 case AMDGPU::MOV_IMM_F32:
264 TII->buildMovImm(*BB, I, MI->getOperand(0).getReg(),
265 MI->getOperand(1).getFPImm()->getValueAPF()
266 .bitcastToAPInt().getZExtValue());
268 case AMDGPU::MOV_IMM_I32:
269 TII->buildMovImm(*BB, I, MI->getOperand(0).getReg(),
270 MI->getOperand(1).getImm());
272 case AMDGPU::CONST_COPY: {
273 MachineInstr *NewMI = TII->buildDefaultInstruction(*BB, MI, AMDGPU::MOV,
274 MI->getOperand(0).getReg(), AMDGPU::ALU_CONST);
275 TII->setImmOperand(NewMI, AMDGPU::OpName::src0_sel,
276 MI->getOperand(1).getImm());
280 case AMDGPU::RAT_WRITE_CACHELESS_32_eg:
281 case AMDGPU::RAT_WRITE_CACHELESS_64_eg:
282 case AMDGPU::RAT_WRITE_CACHELESS_128_eg: {
283 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(MI->getOpcode()))
284 .addOperand(MI->getOperand(0))
285 .addOperand(MI->getOperand(1))
286 .addImm(isEOP(I)); // Set End of program bit
291 unsigned T0 = MRI.createVirtualRegister(&AMDGPU::R600_Reg128RegClass);
292 unsigned T1 = MRI.createVirtualRegister(&AMDGPU::R600_Reg128RegClass);
293 MachineOperand &RID = MI->getOperand(4);
294 MachineOperand &SID = MI->getOperand(5);
295 unsigned TextureId = MI->getOperand(6).getImm();
296 unsigned SrcX = 0, SrcY = 1, SrcZ = 2, SrcW = 3;
297 unsigned CTX = 1, CTY = 1, CTZ = 1, CTW = 1;
309 case 8: // ShadowRect
320 case 11: // Shadow1DArray
324 case 12: // Shadow2DArray
328 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::TEX_SET_GRADIENTS_H), T0)
329 .addOperand(MI->getOperand(3))
347 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::TEX_SET_GRADIENTS_V), T1)
348 .addOperand(MI->getOperand(2))
366 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::TEX_SAMPLE_G))
367 .addOperand(MI->getOperand(0))
368 .addOperand(MI->getOperand(1))
386 .addReg(T0, RegState::Implicit)
387 .addReg(T1, RegState::Implicit);
391 case AMDGPU::TXD_SHADOW: {
392 unsigned T0 = MRI.createVirtualRegister(&AMDGPU::R600_Reg128RegClass);
393 unsigned T1 = MRI.createVirtualRegister(&AMDGPU::R600_Reg128RegClass);
394 MachineOperand &RID = MI->getOperand(4);
395 MachineOperand &SID = MI->getOperand(5);
396 unsigned TextureId = MI->getOperand(6).getImm();
397 unsigned SrcX = 0, SrcY = 1, SrcZ = 2, SrcW = 3;
398 unsigned CTX = 1, CTY = 1, CTZ = 1, CTW = 1;
410 case 8: // ShadowRect
421 case 11: // Shadow1DArray
425 case 12: // Shadow2DArray
430 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::TEX_SET_GRADIENTS_H), T0)
431 .addOperand(MI->getOperand(3))
449 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::TEX_SET_GRADIENTS_V), T1)
450 .addOperand(MI->getOperand(2))
468 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::TEX_SAMPLE_C_G))
469 .addOperand(MI->getOperand(0))
470 .addOperand(MI->getOperand(1))
488 .addReg(T0, RegState::Implicit)
489 .addReg(T1, RegState::Implicit);
494 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::JUMP))
495 .addOperand(MI->getOperand(0));
498 case AMDGPU::BRANCH_COND_f32: {
499 MachineInstr *NewMI =
500 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::PRED_X),
501 AMDGPU::PREDICATE_BIT)
502 .addOperand(MI->getOperand(1))
503 .addImm(OPCODE_IS_NOT_ZERO)
505 TII->addFlag(NewMI, 0, MO_FLAG_PUSH);
506 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::JUMP_COND))
507 .addOperand(MI->getOperand(0))
508 .addReg(AMDGPU::PREDICATE_BIT, RegState::Kill);
512 case AMDGPU::BRANCH_COND_i32: {
513 MachineInstr *NewMI =
514 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::PRED_X),
515 AMDGPU::PREDICATE_BIT)
516 .addOperand(MI->getOperand(1))
517 .addImm(OPCODE_IS_NOT_ZERO_INT)
519 TII->addFlag(NewMI, 0, MO_FLAG_PUSH);
520 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::JUMP_COND))
521 .addOperand(MI->getOperand(0))
522 .addReg(AMDGPU::PREDICATE_BIT, RegState::Kill);
526 case AMDGPU::EG_ExportSwz:
527 case AMDGPU::R600_ExportSwz: {
528 // Instruction is left unmodified if its not the last one of its type
529 bool isLastInstructionOfItsType = true;
530 unsigned InstExportType = MI->getOperand(1).getImm();
531 for (MachineBasicBlock::iterator NextExportInst = std::next(I),
532 EndBlock = BB->end(); NextExportInst != EndBlock;
533 NextExportInst = std::next(NextExportInst)) {
534 if (NextExportInst->getOpcode() == AMDGPU::EG_ExportSwz ||
535 NextExportInst->getOpcode() == AMDGPU::R600_ExportSwz) {
536 unsigned CurrentInstExportType = NextExportInst->getOperand(1)
538 if (CurrentInstExportType == InstExportType) {
539 isLastInstructionOfItsType = false;
545 if (!EOP && !isLastInstructionOfItsType)
547 unsigned CfInst = (MI->getOpcode() == AMDGPU::EG_ExportSwz)? 84 : 40;
548 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(MI->getOpcode()))
549 .addOperand(MI->getOperand(0))
550 .addOperand(MI->getOperand(1))
551 .addOperand(MI->getOperand(2))
552 .addOperand(MI->getOperand(3))
553 .addOperand(MI->getOperand(4))
554 .addOperand(MI->getOperand(5))
555 .addOperand(MI->getOperand(6))
560 case AMDGPU::RETURN: {
561 // RETURN instructions must have the live-out registers as implicit uses,
562 // otherwise they appear dead.
563 R600MachineFunctionInfo *MFI = MF->getInfo<R600MachineFunctionInfo>();
564 MachineInstrBuilder MIB(*MF, MI);
565 for (unsigned i = 0, e = MFI->LiveOuts.size(); i != e; ++i)
566 MIB.addReg(MFI->LiveOuts[i], RegState::Implicit);
571 MI->eraseFromParent();
575 //===----------------------------------------------------------------------===//
576 // Custom DAG Lowering Operations
577 //===----------------------------------------------------------------------===//
579 SDValue R600TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
580 MachineFunction &MF = DAG.getMachineFunction();
581 R600MachineFunctionInfo *MFI = MF.getInfo<R600MachineFunctionInfo>();
582 switch (Op.getOpcode()) {
583 default: return AMDGPUTargetLowering::LowerOperation(Op, DAG);
584 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
585 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
586 case ISD::SHL_PARTS: return LowerSHLParts(Op, DAG);
588 case ISD::SRL_PARTS: return LowerSRXParts(Op, DAG);
589 case ISD::UADDO: return LowerUADDSUBO(Op, DAG, ISD::ADD, AMDGPUISD::CARRY);
590 case ISD::USUBO: return LowerUADDSUBO(Op, DAG, ISD::SUB, AMDGPUISD::BORROW);
592 case ISD::FSIN: return LowerTrig(Op, DAG);
593 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
594 case ISD::STORE: return LowerSTORE(Op, DAG);
596 SDValue Result = LowerLOAD(Op, DAG);
597 assert((!Result.getNode() ||
598 Result.getNode()->getNumValues() == 2) &&
599 "Load should return a value and a chain");
603 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
604 case ISD::GlobalAddress: return LowerGlobalAddress(MFI, Op, DAG);
605 case ISD::INTRINSIC_VOID: {
606 SDValue Chain = Op.getOperand(0);
607 unsigned IntrinsicID =
608 cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
609 switch (IntrinsicID) {
610 case AMDGPUIntrinsic::AMDGPU_store_output: {
611 int64_t RegIndex = cast<ConstantSDNode>(Op.getOperand(3))->getZExtValue();
612 unsigned Reg = AMDGPU::R600_TReg32RegClass.getRegister(RegIndex);
613 MFI->LiveOuts.push_back(Reg);
614 return DAG.getCopyToReg(Chain, SDLoc(Op), Reg, Op.getOperand(2));
616 case AMDGPUIntrinsic::R600_store_swizzle: {
618 const SDValue Args[8] = {
620 Op.getOperand(2), // Export Value
621 Op.getOperand(3), // ArrayBase
622 Op.getOperand(4), // Type
623 DAG.getConstant(0, DL, MVT::i32), // SWZ_X
624 DAG.getConstant(1, DL, MVT::i32), // SWZ_Y
625 DAG.getConstant(2, DL, MVT::i32), // SWZ_Z
626 DAG.getConstant(3, DL, MVT::i32) // SWZ_W
628 return DAG.getNode(AMDGPUISD::EXPORT, DL, Op.getValueType(), Args);
631 // default for switch(IntrinsicID)
634 // break out of case ISD::INTRINSIC_VOID in switch(Op.getOpcode())
637 case ISD::INTRINSIC_WO_CHAIN: {
638 unsigned IntrinsicID =
639 cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
640 EVT VT = Op.getValueType();
642 switch(IntrinsicID) {
643 default: return AMDGPUTargetLowering::LowerOperation(Op, DAG);
644 case AMDGPUIntrinsic::R600_load_input: {
645 int64_t RegIndex = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
646 unsigned Reg = AMDGPU::R600_TReg32RegClass.getRegister(RegIndex);
647 MachineFunction &MF = DAG.getMachineFunction();
648 MachineRegisterInfo &MRI = MF.getRegInfo();
650 return DAG.getCopyFromReg(DAG.getEntryNode(),
651 SDLoc(DAG.getEntryNode()), Reg, VT);
654 case AMDGPUIntrinsic::R600_interp_input: {
655 int slot = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
656 int ijb = cast<ConstantSDNode>(Op.getOperand(2))->getSExtValue();
657 MachineSDNode *interp;
659 const R600InstrInfo *TII =
660 static_cast<const R600InstrInfo *>(Subtarget->getInstrInfo());
661 interp = DAG.getMachineNode(AMDGPU::INTERP_VEC_LOAD, DL,
662 MVT::v4f32, DAG.getTargetConstant(slot / 4, DL, MVT::i32));
663 return DAG.getTargetExtractSubreg(
664 TII->getRegisterInfo().getSubRegFromChannel(slot % 4),
665 DL, MVT::f32, SDValue(interp, 0));
667 MachineFunction &MF = DAG.getMachineFunction();
668 MachineRegisterInfo &MRI = MF.getRegInfo();
669 unsigned RegisterI = AMDGPU::R600_TReg32RegClass.getRegister(2 * ijb);
670 unsigned RegisterJ = AMDGPU::R600_TReg32RegClass.getRegister(2 * ijb + 1);
671 MRI.addLiveIn(RegisterI);
672 MRI.addLiveIn(RegisterJ);
673 SDValue RegisterINode = DAG.getCopyFromReg(DAG.getEntryNode(),
674 SDLoc(DAG.getEntryNode()), RegisterI, MVT::f32);
675 SDValue RegisterJNode = DAG.getCopyFromReg(DAG.getEntryNode(),
676 SDLoc(DAG.getEntryNode()), RegisterJ, MVT::f32);
679 interp = DAG.getMachineNode(AMDGPU::INTERP_PAIR_XY, DL,
680 MVT::f32, MVT::f32, DAG.getTargetConstant(slot / 4, DL, MVT::i32),
681 RegisterJNode, RegisterINode);
683 interp = DAG.getMachineNode(AMDGPU::INTERP_PAIR_ZW, DL,
684 MVT::f32, MVT::f32, DAG.getTargetConstant(slot / 4, DL, MVT::i32),
685 RegisterJNode, RegisterINode);
686 return SDValue(interp, slot % 2);
688 case AMDGPUIntrinsic::R600_interp_xy:
689 case AMDGPUIntrinsic::R600_interp_zw: {
690 int slot = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
691 MachineSDNode *interp;
692 SDValue RegisterINode = Op.getOperand(2);
693 SDValue RegisterJNode = Op.getOperand(3);
695 if (IntrinsicID == AMDGPUIntrinsic::R600_interp_xy)
696 interp = DAG.getMachineNode(AMDGPU::INTERP_PAIR_XY, DL,
697 MVT::f32, MVT::f32, DAG.getTargetConstant(slot, DL, MVT::i32),
698 RegisterJNode, RegisterINode);
700 interp = DAG.getMachineNode(AMDGPU::INTERP_PAIR_ZW, DL,
701 MVT::f32, MVT::f32, DAG.getTargetConstant(slot, DL, MVT::i32),
702 RegisterJNode, RegisterINode);
703 return DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v2f32,
704 SDValue(interp, 0), SDValue(interp, 1));
706 case AMDGPUIntrinsic::R600_tex:
707 case AMDGPUIntrinsic::R600_texc:
708 case AMDGPUIntrinsic::R600_txl:
709 case AMDGPUIntrinsic::R600_txlc:
710 case AMDGPUIntrinsic::R600_txb:
711 case AMDGPUIntrinsic::R600_txbc:
712 case AMDGPUIntrinsic::R600_txf:
713 case AMDGPUIntrinsic::R600_txq:
714 case AMDGPUIntrinsic::R600_ddx:
715 case AMDGPUIntrinsic::R600_ddy:
716 case AMDGPUIntrinsic::R600_ldptr: {
718 switch (IntrinsicID) {
719 case AMDGPUIntrinsic::R600_tex:
722 case AMDGPUIntrinsic::R600_texc:
725 case AMDGPUIntrinsic::R600_txl:
728 case AMDGPUIntrinsic::R600_txlc:
731 case AMDGPUIntrinsic::R600_txb:
734 case AMDGPUIntrinsic::R600_txbc:
737 case AMDGPUIntrinsic::R600_txf:
740 case AMDGPUIntrinsic::R600_txq:
743 case AMDGPUIntrinsic::R600_ddx:
746 case AMDGPUIntrinsic::R600_ddy:
749 case AMDGPUIntrinsic::R600_ldptr:
753 llvm_unreachable("Unknow Texture Operation");
756 SDValue TexArgs[19] = {
757 DAG.getConstant(TextureOp, DL, MVT::i32),
759 DAG.getConstant(0, DL, MVT::i32),
760 DAG.getConstant(1, DL, MVT::i32),
761 DAG.getConstant(2, DL, MVT::i32),
762 DAG.getConstant(3, DL, MVT::i32),
766 DAG.getConstant(0, DL, MVT::i32),
767 DAG.getConstant(1, DL, MVT::i32),
768 DAG.getConstant(2, DL, MVT::i32),
769 DAG.getConstant(3, DL, MVT::i32),
777 return DAG.getNode(AMDGPUISD::TEXTURE_FETCH, DL, MVT::v4f32, TexArgs);
779 case AMDGPUIntrinsic::AMDGPU_dp4: {
781 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(1),
782 DAG.getConstant(0, DL, MVT::i32)),
783 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(2),
784 DAG.getConstant(0, DL, MVT::i32)),
785 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(1),
786 DAG.getConstant(1, DL, MVT::i32)),
787 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(2),
788 DAG.getConstant(1, DL, MVT::i32)),
789 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(1),
790 DAG.getConstant(2, DL, MVT::i32)),
791 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(2),
792 DAG.getConstant(2, DL, MVT::i32)),
793 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(1),
794 DAG.getConstant(3, DL, MVT::i32)),
795 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(2),
796 DAG.getConstant(3, DL, MVT::i32))
798 return DAG.getNode(AMDGPUISD::DOT4, DL, MVT::f32, Args);
801 case Intrinsic::r600_read_ngroups_x:
802 return LowerImplicitParameter(DAG, VT, DL, 0);
803 case Intrinsic::r600_read_ngroups_y:
804 return LowerImplicitParameter(DAG, VT, DL, 1);
805 case Intrinsic::r600_read_ngroups_z:
806 return LowerImplicitParameter(DAG, VT, DL, 2);
807 case Intrinsic::r600_read_global_size_x:
808 return LowerImplicitParameter(DAG, VT, DL, 3);
809 case Intrinsic::r600_read_global_size_y:
810 return LowerImplicitParameter(DAG, VT, DL, 4);
811 case Intrinsic::r600_read_global_size_z:
812 return LowerImplicitParameter(DAG, VT, DL, 5);
813 case Intrinsic::r600_read_local_size_x:
814 return LowerImplicitParameter(DAG, VT, DL, 6);
815 case Intrinsic::r600_read_local_size_y:
816 return LowerImplicitParameter(DAG, VT, DL, 7);
817 case Intrinsic::r600_read_local_size_z:
818 return LowerImplicitParameter(DAG, VT, DL, 8);
820 case Intrinsic::AMDGPU_read_workdim: {
821 uint32_t ByteOffset = getImplicitParameterOffset(MFI, GRID_DIM);
822 return LowerImplicitParameter(DAG, VT, DL, ByteOffset / 4);
825 case Intrinsic::r600_read_tgid_x:
826 return CreateLiveInRegister(DAG, &AMDGPU::R600_TReg32RegClass,
828 case Intrinsic::r600_read_tgid_y:
829 return CreateLiveInRegister(DAG, &AMDGPU::R600_TReg32RegClass,
831 case Intrinsic::r600_read_tgid_z:
832 return CreateLiveInRegister(DAG, &AMDGPU::R600_TReg32RegClass,
834 case Intrinsic::r600_read_tidig_x:
835 return CreateLiveInRegister(DAG, &AMDGPU::R600_TReg32RegClass,
837 case Intrinsic::r600_read_tidig_y:
838 return CreateLiveInRegister(DAG, &AMDGPU::R600_TReg32RegClass,
840 case Intrinsic::r600_read_tidig_z:
841 return CreateLiveInRegister(DAG, &AMDGPU::R600_TReg32RegClass,
843 case Intrinsic::AMDGPU_rsq:
844 // XXX - I'm assuming SI's RSQ_LEGACY matches R600's behavior.
845 return DAG.getNode(AMDGPUISD::RSQ_LEGACY, DL, VT, Op.getOperand(1));
847 case AMDGPUIntrinsic::AMDGPU_fract:
848 case AMDGPUIntrinsic::AMDIL_fraction: // Legacy name.
849 return DAG.getNode(AMDGPUISD::FRACT, DL, VT, Op.getOperand(1));
851 // break out of case ISD::INTRINSIC_WO_CHAIN in switch(Op.getOpcode())
854 } // end switch(Op.getOpcode())
858 void R600TargetLowering::ReplaceNodeResults(SDNode *N,
859 SmallVectorImpl<SDValue> &Results,
860 SelectionDAG &DAG) const {
861 switch (N->getOpcode()) {
863 AMDGPUTargetLowering::ReplaceNodeResults(N, Results, DAG);
865 case ISD::FP_TO_UINT:
866 if (N->getValueType(0) == MVT::i1) {
867 Results.push_back(LowerFPTOUINT(N->getOperand(0), DAG));
870 // Fall-through. Since we don't care about out of bounds values
871 // we can use FP_TO_SINT for uints too. The DAGLegalizer code for uint
872 // considers some extra cases which are not necessary here.
873 case ISD::FP_TO_SINT: {
875 if (expandFP_TO_SINT(N, Result, DAG))
876 Results.push_back(Result);
880 SDValue Op = SDValue(N, 1);
881 SDValue RES = LowerSDIVREM(Op, DAG);
882 Results.push_back(RES);
883 Results.push_back(RES.getValue(1));
887 SDValue Op = SDValue(N, 0);
888 LowerUDIVREM64(Op, DAG, Results);
894 SDValue R600TargetLowering::vectorToVerticalVector(SelectionDAG &DAG,
895 SDValue Vector) const {
898 EVT VecVT = Vector.getValueType();
899 EVT EltVT = VecVT.getVectorElementType();
900 SmallVector<SDValue, 8> Args;
902 for (unsigned i = 0, e = VecVT.getVectorNumElements();
904 Args.push_back(DAG.getNode(
905 ISD::EXTRACT_VECTOR_ELT, DL, EltVT, Vector,
906 DAG.getConstant(i, DL, getVectorIdxTy(DAG.getDataLayout()))));
909 return DAG.getNode(AMDGPUISD::BUILD_VERTICAL_VECTOR, DL, VecVT, Args);
912 SDValue R600TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
913 SelectionDAG &DAG) const {
916 SDValue Vector = Op.getOperand(0);
917 SDValue Index = Op.getOperand(1);
919 if (isa<ConstantSDNode>(Index) ||
920 Vector.getOpcode() == AMDGPUISD::BUILD_VERTICAL_VECTOR)
923 Vector = vectorToVerticalVector(DAG, Vector);
924 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, Op.getValueType(),
928 SDValue R600TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op,
929 SelectionDAG &DAG) const {
931 SDValue Vector = Op.getOperand(0);
932 SDValue Value = Op.getOperand(1);
933 SDValue Index = Op.getOperand(2);
935 if (isa<ConstantSDNode>(Index) ||
936 Vector.getOpcode() == AMDGPUISD::BUILD_VERTICAL_VECTOR)
939 Vector = vectorToVerticalVector(DAG, Vector);
940 SDValue Insert = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, Op.getValueType(),
941 Vector, Value, Index);
942 return vectorToVerticalVector(DAG, Insert);
945 SDValue R600TargetLowering::LowerTrig(SDValue Op, SelectionDAG &DAG) const {
946 // On hw >= R700, COS/SIN input must be between -1. and 1.
947 // Thus we lower them to TRIG ( FRACT ( x / 2Pi + 0.5) - 0.5)
948 EVT VT = Op.getValueType();
949 SDValue Arg = Op.getOperand(0);
952 // TODO: Should this propagate fast-math-flags?
953 SDValue FractPart = DAG.getNode(AMDGPUISD::FRACT, DL, VT,
954 DAG.getNode(ISD::FADD, DL, VT,
955 DAG.getNode(ISD::FMUL, DL, VT, Arg,
956 DAG.getConstantFP(0.15915494309, DL, MVT::f32)),
957 DAG.getConstantFP(0.5, DL, MVT::f32)));
959 switch (Op.getOpcode()) {
961 TrigNode = AMDGPUISD::COS_HW;
964 TrigNode = AMDGPUISD::SIN_HW;
967 llvm_unreachable("Wrong trig opcode");
969 SDValue TrigVal = DAG.getNode(TrigNode, DL, VT,
970 DAG.getNode(ISD::FADD, DL, VT, FractPart,
971 DAG.getConstantFP(-0.5, DL, MVT::f32)));
972 if (Gen >= AMDGPUSubtarget::R700)
974 // On R600 hw, COS/SIN input must be between -Pi and Pi.
975 return DAG.getNode(ISD::FMUL, DL, VT, TrigVal,
976 DAG.getConstantFP(3.14159265359, DL, MVT::f32));
979 SDValue R600TargetLowering::LowerSHLParts(SDValue Op, SelectionDAG &DAG) const {
981 EVT VT = Op.getValueType();
983 SDValue Lo = Op.getOperand(0);
984 SDValue Hi = Op.getOperand(1);
985 SDValue Shift = Op.getOperand(2);
986 SDValue Zero = DAG.getConstant(0, DL, VT);
987 SDValue One = DAG.getConstant(1, DL, VT);
989 SDValue Width = DAG.getConstant(VT.getSizeInBits(), DL, VT);
990 SDValue Width1 = DAG.getConstant(VT.getSizeInBits() - 1, DL, VT);
991 SDValue BigShift = DAG.getNode(ISD::SUB, DL, VT, Shift, Width);
992 SDValue CompShift = DAG.getNode(ISD::SUB, DL, VT, Width1, Shift);
994 // The dance around Width1 is necessary for 0 special case.
995 // Without it the CompShift might be 32, producing incorrect results in
996 // Overflow. So we do the shift in two steps, the alternative is to
997 // add a conditional to filter the special case.
999 SDValue Overflow = DAG.getNode(ISD::SRL, DL, VT, Lo, CompShift);
1000 Overflow = DAG.getNode(ISD::SRL, DL, VT, Overflow, One);
1002 SDValue HiSmall = DAG.getNode(ISD::SHL, DL, VT, Hi, Shift);
1003 HiSmall = DAG.getNode(ISD::OR, DL, VT, HiSmall, Overflow);
1004 SDValue LoSmall = DAG.getNode(ISD::SHL, DL, VT, Lo, Shift);
1006 SDValue HiBig = DAG.getNode(ISD::SHL, DL, VT, Lo, BigShift);
1007 SDValue LoBig = Zero;
1009 Hi = DAG.getSelectCC(DL, Shift, Width, HiSmall, HiBig, ISD::SETULT);
1010 Lo = DAG.getSelectCC(DL, Shift, Width, LoSmall, LoBig, ISD::SETULT);
1012 return DAG.getNode(ISD::MERGE_VALUES, DL, DAG.getVTList(VT,VT), Lo, Hi);
1015 SDValue R600TargetLowering::LowerSRXParts(SDValue Op, SelectionDAG &DAG) const {
1017 EVT VT = Op.getValueType();
1019 SDValue Lo = Op.getOperand(0);
1020 SDValue Hi = Op.getOperand(1);
1021 SDValue Shift = Op.getOperand(2);
1022 SDValue Zero = DAG.getConstant(0, DL, VT);
1023 SDValue One = DAG.getConstant(1, DL, VT);
1025 const bool SRA = Op.getOpcode() == ISD::SRA_PARTS;
1027 SDValue Width = DAG.getConstant(VT.getSizeInBits(), DL, VT);
1028 SDValue Width1 = DAG.getConstant(VT.getSizeInBits() - 1, DL, VT);
1029 SDValue BigShift = DAG.getNode(ISD::SUB, DL, VT, Shift, Width);
1030 SDValue CompShift = DAG.getNode(ISD::SUB, DL, VT, Width1, Shift);
1032 // The dance around Width1 is necessary for 0 special case.
1033 // Without it the CompShift might be 32, producing incorrect results in
1034 // Overflow. So we do the shift in two steps, the alternative is to
1035 // add a conditional to filter the special case.
1037 SDValue Overflow = DAG.getNode(ISD::SHL, DL, VT, Hi, CompShift);
1038 Overflow = DAG.getNode(ISD::SHL, DL, VT, Overflow, One);
1040 SDValue HiSmall = DAG.getNode(SRA ? ISD::SRA : ISD::SRL, DL, VT, Hi, Shift);
1041 SDValue LoSmall = DAG.getNode(ISD::SRL, DL, VT, Lo, Shift);
1042 LoSmall = DAG.getNode(ISD::OR, DL, VT, LoSmall, Overflow);
1044 SDValue LoBig = DAG.getNode(SRA ? ISD::SRA : ISD::SRL, DL, VT, Hi, BigShift);
1045 SDValue HiBig = SRA ? DAG.getNode(ISD::SRA, DL, VT, Hi, Width1) : Zero;
1047 Hi = DAG.getSelectCC(DL, Shift, Width, HiSmall, HiBig, ISD::SETULT);
1048 Lo = DAG.getSelectCC(DL, Shift, Width, LoSmall, LoBig, ISD::SETULT);
1050 return DAG.getNode(ISD::MERGE_VALUES, DL, DAG.getVTList(VT,VT), Lo, Hi);
1053 SDValue R600TargetLowering::LowerUADDSUBO(SDValue Op, SelectionDAG &DAG,
1054 unsigned mainop, unsigned ovf) const {
1056 EVT VT = Op.getValueType();
1058 SDValue Lo = Op.getOperand(0);
1059 SDValue Hi = Op.getOperand(1);
1061 SDValue OVF = DAG.getNode(ovf, DL, VT, Lo, Hi);
1063 OVF = DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, VT, OVF,
1064 DAG.getValueType(MVT::i1));
1066 SDValue Res = DAG.getNode(mainop, DL, VT, Lo, Hi);
1068 return DAG.getNode(ISD::MERGE_VALUES, DL, DAG.getVTList(VT, VT), Res, OVF);
1071 SDValue R600TargetLowering::LowerFPTOUINT(SDValue Op, SelectionDAG &DAG) const {
1077 Op, DAG.getConstantFP(0.0f, DL, MVT::f32),
1078 DAG.getCondCode(ISD::SETNE)
1082 SDValue R600TargetLowering::LowerImplicitParameter(SelectionDAG &DAG, EVT VT,
1084 unsigned DwordOffset) const {
1085 unsigned ByteOffset = DwordOffset * 4;
1086 PointerType * PtrType = PointerType::get(VT.getTypeForEVT(*DAG.getContext()),
1087 AMDGPUAS::CONSTANT_BUFFER_0);
1089 // We shouldn't be using an offset wider than 16-bits for implicit parameters.
1090 assert(isInt<16>(ByteOffset));
1092 return DAG.getLoad(VT, DL, DAG.getEntryNode(),
1093 DAG.getConstant(ByteOffset, DL, MVT::i32), // PTR
1094 MachinePointerInfo(ConstantPointerNull::get(PtrType)),
1095 false, false, false, 0);
1098 bool R600TargetLowering::isZero(SDValue Op) const {
1099 if(ConstantSDNode *Cst = dyn_cast<ConstantSDNode>(Op)) {
1100 return Cst->isNullValue();
1101 } else if(ConstantFPSDNode *CstFP = dyn_cast<ConstantFPSDNode>(Op)){
1102 return CstFP->isZero();
1108 SDValue R600TargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
1110 EVT VT = Op.getValueType();
1112 SDValue LHS = Op.getOperand(0);
1113 SDValue RHS = Op.getOperand(1);
1114 SDValue True = Op.getOperand(2);
1115 SDValue False = Op.getOperand(3);
1116 SDValue CC = Op.getOperand(4);
1119 if (VT == MVT::f32) {
1120 DAGCombinerInfo DCI(DAG, AfterLegalizeVectorOps, true, nullptr);
1121 SDValue MinMax = CombineFMinMaxLegacy(DL, VT, LHS, RHS, True, False, CC, DCI);
1126 // LHS and RHS are guaranteed to be the same value type
1127 EVT CompareVT = LHS.getValueType();
1129 // Check if we can lower this to a native operation.
1131 // Try to lower to a SET* instruction:
1133 // SET* can match the following patterns:
1135 // select_cc f32, f32, -1, 0, cc_supported
1136 // select_cc f32, f32, 1.0f, 0.0f, cc_supported
1137 // select_cc i32, i32, -1, 0, cc_supported
1140 // Move hardware True/False values to the correct operand.
1141 ISD::CondCode CCOpcode = cast<CondCodeSDNode>(CC)->get();
1142 ISD::CondCode InverseCC =
1143 ISD::getSetCCInverse(CCOpcode, CompareVT == MVT::i32);
1144 if (isHWTrueValue(False) && isHWFalseValue(True)) {
1145 if (isCondCodeLegal(InverseCC, CompareVT.getSimpleVT())) {
1146 std::swap(False, True);
1147 CC = DAG.getCondCode(InverseCC);
1149 ISD::CondCode SwapInvCC = ISD::getSetCCSwappedOperands(InverseCC);
1150 if (isCondCodeLegal(SwapInvCC, CompareVT.getSimpleVT())) {
1151 std::swap(False, True);
1152 std::swap(LHS, RHS);
1153 CC = DAG.getCondCode(SwapInvCC);
1158 if (isHWTrueValue(True) && isHWFalseValue(False) &&
1159 (CompareVT == VT || VT == MVT::i32)) {
1160 // This can be matched by a SET* instruction.
1161 return DAG.getNode(ISD::SELECT_CC, DL, VT, LHS, RHS, True, False, CC);
1164 // Try to lower to a CND* instruction:
1166 // CND* can match the following patterns:
1168 // select_cc f32, 0.0, f32, f32, cc_supported
1169 // select_cc f32, 0.0, i32, i32, cc_supported
1170 // select_cc i32, 0, f32, f32, cc_supported
1171 // select_cc i32, 0, i32, i32, cc_supported
1174 // Try to move the zero value to the RHS
1176 ISD::CondCode CCOpcode = cast<CondCodeSDNode>(CC)->get();
1177 // Try swapping the operands
1178 ISD::CondCode CCSwapped = ISD::getSetCCSwappedOperands(CCOpcode);
1179 if (isCondCodeLegal(CCSwapped, CompareVT.getSimpleVT())) {
1180 std::swap(LHS, RHS);
1181 CC = DAG.getCondCode(CCSwapped);
1183 // Try inverting the conditon and then swapping the operands
1184 ISD::CondCode CCInv = ISD::getSetCCInverse(CCOpcode, CompareVT.isInteger());
1185 CCSwapped = ISD::getSetCCSwappedOperands(CCInv);
1186 if (isCondCodeLegal(CCSwapped, CompareVT.getSimpleVT())) {
1187 std::swap(True, False);
1188 std::swap(LHS, RHS);
1189 CC = DAG.getCondCode(CCSwapped);
1196 ISD::CondCode CCOpcode = cast<CondCodeSDNode>(CC)->get();
1197 if (CompareVT != VT) {
1198 // Bitcast True / False to the correct types. This will end up being
1199 // a nop, but it allows us to define only a single pattern in the
1200 // .TD files for each CND* instruction rather than having to have
1201 // one pattern for integer True/False and one for fp True/False
1202 True = DAG.getNode(ISD::BITCAST, DL, CompareVT, True);
1203 False = DAG.getNode(ISD::BITCAST, DL, CompareVT, False);
1210 CCOpcode = ISD::getSetCCInverse(CCOpcode, CompareVT == MVT::i32);
1218 SDValue SelectNode = DAG.getNode(ISD::SELECT_CC, DL, CompareVT,
1221 DAG.getCondCode(CCOpcode));
1222 return DAG.getNode(ISD::BITCAST, DL, VT, SelectNode);
1225 // If we make it this for it means we have no native instructions to handle
1226 // this SELECT_CC, so we must lower it.
1227 SDValue HWTrue, HWFalse;
1229 if (CompareVT == MVT::f32) {
1230 HWTrue = DAG.getConstantFP(1.0f, DL, CompareVT);
1231 HWFalse = DAG.getConstantFP(0.0f, DL, CompareVT);
1232 } else if (CompareVT == MVT::i32) {
1233 HWTrue = DAG.getConstant(-1, DL, CompareVT);
1234 HWFalse = DAG.getConstant(0, DL, CompareVT);
1237 llvm_unreachable("Unhandled value type in LowerSELECT_CC");
1240 // Lower this unsupported SELECT_CC into a combination of two supported
1241 // SELECT_CC operations.
1242 SDValue Cond = DAG.getNode(ISD::SELECT_CC, DL, CompareVT, LHS, RHS, HWTrue, HWFalse, CC);
1244 return DAG.getNode(ISD::SELECT_CC, DL, VT,
1247 DAG.getCondCode(ISD::SETNE));
1250 /// LLVM generates byte-addressed pointers. For indirect addressing, we need to
1251 /// convert these pointers to a register index. Each register holds
1252 /// 16 bytes, (4 x 32bit sub-register), but we need to take into account the
1253 /// \p StackWidth, which tells us how many of the 4 sub-registrers will be used
1254 /// for indirect addressing.
1255 SDValue R600TargetLowering::stackPtrToRegIndex(SDValue Ptr,
1256 unsigned StackWidth,
1257 SelectionDAG &DAG) const {
1259 switch(StackWidth) {
1269 default: llvm_unreachable("Invalid stack width");
1273 return DAG.getNode(ISD::SRL, DL, Ptr.getValueType(), Ptr,
1274 DAG.getConstant(SRLPad, DL, MVT::i32));
1277 void R600TargetLowering::getStackAddress(unsigned StackWidth,
1280 unsigned &PtrIncr) const {
1281 switch (StackWidth) {
1292 Channel = ElemIdx % 2;
1306 SDValue R600TargetLowering::LowerSTORE(SDValue Op, SelectionDAG &DAG) const {
1308 StoreSDNode *StoreNode = cast<StoreSDNode>(Op);
1309 SDValue Chain = Op.getOperand(0);
1310 SDValue Value = Op.getOperand(1);
1311 SDValue Ptr = Op.getOperand(2);
1313 SDValue Result = AMDGPUTargetLowering::LowerSTORE(Op, DAG);
1314 if (Result.getNode()) {
1318 if (StoreNode->getAddressSpace() == AMDGPUAS::GLOBAL_ADDRESS) {
1319 if (StoreNode->isTruncatingStore()) {
1320 EVT VT = Value.getValueType();
1321 assert(VT.bitsLE(MVT::i32));
1322 EVT MemVT = StoreNode->getMemoryVT();
1323 SDValue MaskConstant;
1324 if (MemVT == MVT::i8) {
1325 MaskConstant = DAG.getConstant(0xFF, DL, MVT::i32);
1327 assert(MemVT == MVT::i16);
1328 MaskConstant = DAG.getConstant(0xFFFF, DL, MVT::i32);
1330 SDValue DWordAddr = DAG.getNode(ISD::SRL, DL, VT, Ptr,
1331 DAG.getConstant(2, DL, MVT::i32));
1332 SDValue ByteIndex = DAG.getNode(ISD::AND, DL, Ptr.getValueType(), Ptr,
1333 DAG.getConstant(0x00000003, DL, VT));
1334 SDValue TruncValue = DAG.getNode(ISD::AND, DL, VT, Value, MaskConstant);
1335 SDValue Shift = DAG.getNode(ISD::SHL, DL, VT, ByteIndex,
1336 DAG.getConstant(3, DL, VT));
1337 SDValue ShiftedValue = DAG.getNode(ISD::SHL, DL, VT, TruncValue, Shift);
1338 SDValue Mask = DAG.getNode(ISD::SHL, DL, VT, MaskConstant, Shift);
1339 // XXX: If we add a 64-bit ZW register class, then we could use a 2 x i32
1343 DAG.getConstant(0, DL, MVT::i32),
1344 DAG.getConstant(0, DL, MVT::i32),
1347 SDValue Input = DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v4i32, Src);
1348 SDValue Args[3] = { Chain, Input, DWordAddr };
1349 return DAG.getMemIntrinsicNode(AMDGPUISD::STORE_MSKOR, DL,
1350 Op->getVTList(), Args, MemVT,
1351 StoreNode->getMemOperand());
1352 } else if (Ptr->getOpcode() != AMDGPUISD::DWORDADDR &&
1353 Value.getValueType().bitsGE(MVT::i32)) {
1354 // Convert pointer from byte address to dword address.
1355 Ptr = DAG.getNode(AMDGPUISD::DWORDADDR, DL, Ptr.getValueType(),
1356 DAG.getNode(ISD::SRL, DL, Ptr.getValueType(),
1357 Ptr, DAG.getConstant(2, DL, MVT::i32)));
1359 if (StoreNode->isTruncatingStore() || StoreNode->isIndexed()) {
1360 llvm_unreachable("Truncated and indexed stores not supported yet");
1362 Chain = DAG.getStore(Chain, DL, Value, Ptr, StoreNode->getMemOperand());
1368 EVT ValueVT = Value.getValueType();
1370 if (StoreNode->getAddressSpace() != AMDGPUAS::PRIVATE_ADDRESS) {
1374 SDValue Ret = AMDGPUTargetLowering::LowerSTORE(Op, DAG);
1375 if (Ret.getNode()) {
1378 // Lowering for indirect addressing
1380 const MachineFunction &MF = DAG.getMachineFunction();
1381 const AMDGPUFrameLowering *TFL =
1382 static_cast<const AMDGPUFrameLowering *>(Subtarget->getFrameLowering());
1383 unsigned StackWidth = TFL->getStackWidth(MF);
1385 Ptr = stackPtrToRegIndex(Ptr, StackWidth, DAG);
1387 if (ValueVT.isVector()) {
1388 unsigned NumElemVT = ValueVT.getVectorNumElements();
1389 EVT ElemVT = ValueVT.getVectorElementType();
1390 SmallVector<SDValue, 4> Stores(NumElemVT);
1392 assert(NumElemVT >= StackWidth && "Stack width cannot be greater than "
1393 "vector width in load");
1395 for (unsigned i = 0; i < NumElemVT; ++i) {
1396 unsigned Channel, PtrIncr;
1397 getStackAddress(StackWidth, i, Channel, PtrIncr);
1398 Ptr = DAG.getNode(ISD::ADD, DL, MVT::i32, Ptr,
1399 DAG.getConstant(PtrIncr, DL, MVT::i32));
1400 SDValue Elem = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, ElemVT,
1401 Value, DAG.getConstant(i, DL, MVT::i32));
1403 Stores[i] = DAG.getNode(AMDGPUISD::REGISTER_STORE, DL, MVT::Other,
1405 DAG.getTargetConstant(Channel, DL, MVT::i32));
1407 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Stores);
1409 if (ValueVT == MVT::i8) {
1410 Value = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, Value);
1412 Chain = DAG.getNode(AMDGPUISD::REGISTER_STORE, DL, MVT::Other, Chain, Value, Ptr,
1413 DAG.getTargetConstant(0, DL, MVT::i32)); // Channel
1419 // return (512 + (kc_bank << 12)
1421 ConstantAddressBlock(unsigned AddressSpace) {
1422 switch (AddressSpace) {
1423 case AMDGPUAS::CONSTANT_BUFFER_0:
1425 case AMDGPUAS::CONSTANT_BUFFER_1:
1427 case AMDGPUAS::CONSTANT_BUFFER_2:
1428 return 512 + 4096 * 2;
1429 case AMDGPUAS::CONSTANT_BUFFER_3:
1430 return 512 + 4096 * 3;
1431 case AMDGPUAS::CONSTANT_BUFFER_4:
1432 return 512 + 4096 * 4;
1433 case AMDGPUAS::CONSTANT_BUFFER_5:
1434 return 512 + 4096 * 5;
1435 case AMDGPUAS::CONSTANT_BUFFER_6:
1436 return 512 + 4096 * 6;
1437 case AMDGPUAS::CONSTANT_BUFFER_7:
1438 return 512 + 4096 * 7;
1439 case AMDGPUAS::CONSTANT_BUFFER_8:
1440 return 512 + 4096 * 8;
1441 case AMDGPUAS::CONSTANT_BUFFER_9:
1442 return 512 + 4096 * 9;
1443 case AMDGPUAS::CONSTANT_BUFFER_10:
1444 return 512 + 4096 * 10;
1445 case AMDGPUAS::CONSTANT_BUFFER_11:
1446 return 512 + 4096 * 11;
1447 case AMDGPUAS::CONSTANT_BUFFER_12:
1448 return 512 + 4096 * 12;
1449 case AMDGPUAS::CONSTANT_BUFFER_13:
1450 return 512 + 4096 * 13;
1451 case AMDGPUAS::CONSTANT_BUFFER_14:
1452 return 512 + 4096 * 14;
1453 case AMDGPUAS::CONSTANT_BUFFER_15:
1454 return 512 + 4096 * 15;
1460 SDValue R600TargetLowering::LowerLOAD(SDValue Op, SelectionDAG &DAG) const
1462 EVT VT = Op.getValueType();
1464 LoadSDNode *LoadNode = cast<LoadSDNode>(Op);
1465 SDValue Chain = Op.getOperand(0);
1466 SDValue Ptr = Op.getOperand(1);
1467 SDValue LoweredLoad;
1469 if (SDValue Ret = AMDGPUTargetLowering::LowerLOAD(Op, DAG))
1472 // Lower loads constant address space global variable loads
1473 if (LoadNode->getAddressSpace() == AMDGPUAS::CONSTANT_ADDRESS &&
1474 isa<GlobalVariable>(GetUnderlyingObject(
1475 LoadNode->getMemOperand()->getValue(), DAG.getDataLayout()))) {
1477 SDValue Ptr = DAG.getZExtOrTrunc(
1478 LoadNode->getBasePtr(), DL,
1479 getPointerTy(DAG.getDataLayout(), AMDGPUAS::PRIVATE_ADDRESS));
1480 Ptr = DAG.getNode(ISD::SRL, DL, MVT::i32, Ptr,
1481 DAG.getConstant(2, DL, MVT::i32));
1482 return DAG.getNode(AMDGPUISD::REGISTER_LOAD, DL, Op->getVTList(),
1483 LoadNode->getChain(), Ptr,
1484 DAG.getTargetConstant(0, DL, MVT::i32),
1488 if (LoadNode->getAddressSpace() == AMDGPUAS::LOCAL_ADDRESS && VT.isVector()) {
1489 SDValue MergedValues[2] = {
1490 ScalarizeVectorLoad(Op, DAG),
1493 return DAG.getMergeValues(MergedValues, DL);
1496 int ConstantBlock = ConstantAddressBlock(LoadNode->getAddressSpace());
1497 if (ConstantBlock > -1 &&
1498 ((LoadNode->getExtensionType() == ISD::NON_EXTLOAD) ||
1499 (LoadNode->getExtensionType() == ISD::ZEXTLOAD))) {
1501 if (isa<ConstantExpr>(LoadNode->getMemOperand()->getValue()) ||
1502 isa<Constant>(LoadNode->getMemOperand()->getValue()) ||
1503 isa<ConstantSDNode>(Ptr)) {
1505 for (unsigned i = 0; i < 4; i++) {
1506 // We want Const position encoded with the following formula :
1507 // (((512 + (kc_bank << 12) + const_index) << 2) + chan)
1508 // const_index is Ptr computed by llvm using an alignment of 16.
1509 // Thus we add (((512 + (kc_bank << 12)) + chan ) * 4 here and
1510 // then div by 4 at the ISel step
1511 SDValue NewPtr = DAG.getNode(ISD::ADD, DL, Ptr.getValueType(), Ptr,
1512 DAG.getConstant(4 * i + ConstantBlock * 16, DL, MVT::i32));
1513 Slots[i] = DAG.getNode(AMDGPUISD::CONST_ADDRESS, DL, MVT::i32, NewPtr);
1515 EVT NewVT = MVT::v4i32;
1516 unsigned NumElements = 4;
1517 if (VT.isVector()) {
1519 NumElements = VT.getVectorNumElements();
1521 Result = DAG.getNode(ISD::BUILD_VECTOR, DL, NewVT,
1522 makeArrayRef(Slots, NumElements));
1524 // non-constant ptr can't be folded, keeps it as a v4f32 load
1525 Result = DAG.getNode(AMDGPUISD::CONST_ADDRESS, DL, MVT::v4i32,
1526 DAG.getNode(ISD::SRL, DL, MVT::i32, Ptr,
1527 DAG.getConstant(4, DL, MVT::i32)),
1528 DAG.getConstant(LoadNode->getAddressSpace() -
1529 AMDGPUAS::CONSTANT_BUFFER_0, DL, MVT::i32)
1533 if (!VT.isVector()) {
1534 Result = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::i32, Result,
1535 DAG.getConstant(0, DL, MVT::i32));
1538 SDValue MergedValues[2] = {
1542 return DAG.getMergeValues(MergedValues, DL);
1545 // For most operations returning SDValue() will result in the node being
1546 // expanded by the DAG Legalizer. This is not the case for ISD::LOAD, so we
1547 // need to manually expand loads that may be legal in some address spaces and
1548 // illegal in others. SEXT loads from CONSTANT_BUFFER_0 are supported for
1549 // compute shaders, since the data is sign extended when it is uploaded to the
1550 // buffer. However SEXT loads from other address spaces are not supported, so
1551 // we need to expand them here.
1552 if (LoadNode->getExtensionType() == ISD::SEXTLOAD) {
1553 EVT MemVT = LoadNode->getMemoryVT();
1554 assert(!MemVT.isVector() && (MemVT == MVT::i16 || MemVT == MVT::i8));
1555 SDValue NewLoad = DAG.getExtLoad(ISD::EXTLOAD, DL, VT, Chain, Ptr,
1556 LoadNode->getPointerInfo(), MemVT,
1557 LoadNode->isVolatile(),
1558 LoadNode->isNonTemporal(),
1559 LoadNode->isInvariant(),
1560 LoadNode->getAlignment());
1561 SDValue Res = DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, VT, NewLoad,
1562 DAG.getValueType(MemVT));
1564 SDValue MergedValues[2] = { Res, Chain };
1565 return DAG.getMergeValues(MergedValues, DL);
1568 if (LoadNode->getAddressSpace() != AMDGPUAS::PRIVATE_ADDRESS) {
1572 // Lowering for indirect addressing
1573 const MachineFunction &MF = DAG.getMachineFunction();
1574 const AMDGPUFrameLowering *TFL =
1575 static_cast<const AMDGPUFrameLowering *>(Subtarget->getFrameLowering());
1576 unsigned StackWidth = TFL->getStackWidth(MF);
1578 Ptr = stackPtrToRegIndex(Ptr, StackWidth, DAG);
1580 if (VT.isVector()) {
1581 unsigned NumElemVT = VT.getVectorNumElements();
1582 EVT ElemVT = VT.getVectorElementType();
1585 assert(NumElemVT >= StackWidth && "Stack width cannot be greater than "
1586 "vector width in load");
1588 for (unsigned i = 0; i < NumElemVT; ++i) {
1589 unsigned Channel, PtrIncr;
1590 getStackAddress(StackWidth, i, Channel, PtrIncr);
1591 Ptr = DAG.getNode(ISD::ADD, DL, MVT::i32, Ptr,
1592 DAG.getConstant(PtrIncr, DL, MVT::i32));
1593 Loads[i] = DAG.getNode(AMDGPUISD::REGISTER_LOAD, DL, ElemVT,
1595 DAG.getTargetConstant(Channel, DL, MVT::i32),
1598 for (unsigned i = NumElemVT; i < 4; ++i) {
1599 Loads[i] = DAG.getUNDEF(ElemVT);
1601 EVT TargetVT = EVT::getVectorVT(*DAG.getContext(), ElemVT, 4);
1602 LoweredLoad = DAG.getNode(ISD::BUILD_VECTOR, DL, TargetVT, Loads);
1604 LoweredLoad = DAG.getNode(AMDGPUISD::REGISTER_LOAD, DL, VT,
1606 DAG.getTargetConstant(0, DL, MVT::i32), // Channel
1615 return DAG.getMergeValues(Ops, DL);
1618 SDValue R600TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
1619 SDValue Chain = Op.getOperand(0);
1620 SDValue Cond = Op.getOperand(1);
1621 SDValue Jump = Op.getOperand(2);
1623 return DAG.getNode(AMDGPUISD::BRANCH_COND, SDLoc(Op), Op.getValueType(),
1627 /// XXX Only kernel functions are supported, so we can assume for now that
1628 /// every function is a kernel function, but in the future we should use
1629 /// separate calling conventions for kernel and non-kernel functions.
1630 SDValue R600TargetLowering::LowerFormalArguments(
1632 CallingConv::ID CallConv,
1634 const SmallVectorImpl<ISD::InputArg> &Ins,
1635 SDLoc DL, SelectionDAG &DAG,
1636 SmallVectorImpl<SDValue> &InVals) const {
1637 SmallVector<CCValAssign, 16> ArgLocs;
1638 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
1640 MachineFunction &MF = DAG.getMachineFunction();
1641 R600MachineFunctionInfo *MFI = MF.getInfo<R600MachineFunctionInfo>();
1643 SmallVector<ISD::InputArg, 8> LocalIns;
1645 getOriginalFunctionArgs(DAG, MF.getFunction(), Ins, LocalIns);
1647 AnalyzeFormalArguments(CCInfo, LocalIns);
1649 for (unsigned i = 0, e = Ins.size(); i < e; ++i) {
1650 CCValAssign &VA = ArgLocs[i];
1651 const ISD::InputArg &In = Ins[i];
1653 EVT MemVT = VA.getLocVT();
1654 if (!VT.isVector() && MemVT.isVector()) {
1655 // Get load source type if scalarized.
1656 MemVT = MemVT.getVectorElementType();
1659 if (MFI->getShaderType() != ShaderType::COMPUTE) {
1660 unsigned Reg = MF.addLiveIn(VA.getLocReg(), &AMDGPU::R600_Reg128RegClass);
1661 SDValue Register = DAG.getCopyFromReg(Chain, DL, Reg, VT);
1662 InVals.push_back(Register);
1666 PointerType *PtrTy = PointerType::get(VT.getTypeForEVT(*DAG.getContext()),
1667 AMDGPUAS::CONSTANT_BUFFER_0);
1669 // i64 isn't a legal type, so the register type used ends up as i32, which
1670 // isn't expected here. It attempts to create this sextload, but it ends up
1671 // being invalid. Somehow this seems to work with i64 arguments, but breaks
1674 // The first 36 bytes of the input buffer contains information about
1675 // thread group and global sizes.
1676 ISD::LoadExtType Ext = ISD::NON_EXTLOAD;
1677 if (MemVT.getScalarSizeInBits() != VT.getScalarSizeInBits()) {
1678 // FIXME: This should really check the extload type, but the handling of
1679 // extload vector parameters seems to be broken.
1681 // Ext = In.Flags.isSExt() ? ISD::SEXTLOAD : ISD::ZEXTLOAD;
1682 Ext = ISD::SEXTLOAD;
1685 // Compute the offset from the value.
1686 // XXX - I think PartOffset should give you this, but it seems to give the
1687 // size of the register which isn't useful.
1689 unsigned ValBase = ArgLocs[In.getOrigArgIndex()].getLocMemOffset();
1690 unsigned PartOffset = VA.getLocMemOffset();
1691 unsigned Offset = 36 + VA.getLocMemOffset();
1693 MachinePointerInfo PtrInfo(UndefValue::get(PtrTy), PartOffset - ValBase);
1694 SDValue Arg = DAG.getLoad(ISD::UNINDEXED, Ext, VT, DL, Chain,
1695 DAG.getConstant(Offset, DL, MVT::i32),
1696 DAG.getUNDEF(MVT::i32),
1698 MemVT, false, true, true, 4);
1700 // 4 is the preferred alignment for the CONSTANT memory space.
1701 InVals.push_back(Arg);
1702 MFI->ABIArgOffset = Offset + MemVT.getStoreSize();
1707 EVT R600TargetLowering::getSetCCResultType(const DataLayout &DL, LLVMContext &,
1711 return VT.changeVectorElementTypeToInteger();
1714 static SDValue CompactSwizzlableVector(
1715 SelectionDAG &DAG, SDValue VectorEntry,
1716 DenseMap<unsigned, unsigned> &RemapSwizzle) {
1717 assert(VectorEntry.getOpcode() == ISD::BUILD_VECTOR);
1718 assert(RemapSwizzle.empty());
1719 SDValue NewBldVec[4] = {
1720 VectorEntry.getOperand(0),
1721 VectorEntry.getOperand(1),
1722 VectorEntry.getOperand(2),
1723 VectorEntry.getOperand(3)
1726 for (unsigned i = 0; i < 4; i++) {
1727 if (NewBldVec[i].getOpcode() == ISD::UNDEF)
1728 // We mask write here to teach later passes that the ith element of this
1729 // vector is undef. Thus we can use it to reduce 128 bits reg usage,
1730 // break false dependencies and additionnaly make assembly easier to read.
1731 RemapSwizzle[i] = 7; // SEL_MASK_WRITE
1732 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(NewBldVec[i])) {
1734 RemapSwizzle[i] = 4; // SEL_0
1735 NewBldVec[i] = DAG.getUNDEF(MVT::f32);
1736 } else if (C->isExactlyValue(1.0)) {
1737 RemapSwizzle[i] = 5; // SEL_1
1738 NewBldVec[i] = DAG.getUNDEF(MVT::f32);
1742 if (NewBldVec[i].getOpcode() == ISD::UNDEF)
1744 for (unsigned j = 0; j < i; j++) {
1745 if (NewBldVec[i] == NewBldVec[j]) {
1746 NewBldVec[i] = DAG.getUNDEF(NewBldVec[i].getValueType());
1747 RemapSwizzle[i] = j;
1753 return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(VectorEntry),
1754 VectorEntry.getValueType(), NewBldVec);
1757 static SDValue ReorganizeVector(SelectionDAG &DAG, SDValue VectorEntry,
1758 DenseMap<unsigned, unsigned> &RemapSwizzle) {
1759 assert(VectorEntry.getOpcode() == ISD::BUILD_VECTOR);
1760 assert(RemapSwizzle.empty());
1761 SDValue NewBldVec[4] = {
1762 VectorEntry.getOperand(0),
1763 VectorEntry.getOperand(1),
1764 VectorEntry.getOperand(2),
1765 VectorEntry.getOperand(3)
1767 bool isUnmovable[4] = { false, false, false, false };
1768 for (unsigned i = 0; i < 4; i++) {
1769 RemapSwizzle[i] = i;
1770 if (NewBldVec[i].getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
1771 unsigned Idx = dyn_cast<ConstantSDNode>(NewBldVec[i].getOperand(1))
1774 isUnmovable[Idx] = true;
1778 for (unsigned i = 0; i < 4; i++) {
1779 if (NewBldVec[i].getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
1780 unsigned Idx = dyn_cast<ConstantSDNode>(NewBldVec[i].getOperand(1))
1782 if (isUnmovable[Idx])
1785 std::swap(NewBldVec[Idx], NewBldVec[i]);
1786 std::swap(RemapSwizzle[i], RemapSwizzle[Idx]);
1791 return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(VectorEntry),
1792 VectorEntry.getValueType(), NewBldVec);
1796 SDValue R600TargetLowering::OptimizeSwizzle(SDValue BuildVector,
1797 SDValue Swz[4], SelectionDAG &DAG,
1799 assert(BuildVector.getOpcode() == ISD::BUILD_VECTOR);
1800 // Old -> New swizzle values
1801 DenseMap<unsigned, unsigned> SwizzleRemap;
1803 BuildVector = CompactSwizzlableVector(DAG, BuildVector, SwizzleRemap);
1804 for (unsigned i = 0; i < 4; i++) {
1805 unsigned Idx = cast<ConstantSDNode>(Swz[i])->getZExtValue();
1806 if (SwizzleRemap.find(Idx) != SwizzleRemap.end())
1807 Swz[i] = DAG.getConstant(SwizzleRemap[Idx], DL, MVT::i32);
1810 SwizzleRemap.clear();
1811 BuildVector = ReorganizeVector(DAG, BuildVector, SwizzleRemap);
1812 for (unsigned i = 0; i < 4; i++) {
1813 unsigned Idx = cast<ConstantSDNode>(Swz[i])->getZExtValue();
1814 if (SwizzleRemap.find(Idx) != SwizzleRemap.end())
1815 Swz[i] = DAG.getConstant(SwizzleRemap[Idx], DL, MVT::i32);
1822 //===----------------------------------------------------------------------===//
1823 // Custom DAG Optimizations
1824 //===----------------------------------------------------------------------===//
1826 SDValue R600TargetLowering::PerformDAGCombine(SDNode *N,
1827 DAGCombinerInfo &DCI) const {
1828 SelectionDAG &DAG = DCI.DAG;
1830 switch (N->getOpcode()) {
1831 default: return AMDGPUTargetLowering::PerformDAGCombine(N, DCI);
1832 // (f32 fp_round (f64 uint_to_fp a)) -> (f32 uint_to_fp a)
1833 case ISD::FP_ROUND: {
1834 SDValue Arg = N->getOperand(0);
1835 if (Arg.getOpcode() == ISD::UINT_TO_FP && Arg.getValueType() == MVT::f64) {
1836 return DAG.getNode(ISD::UINT_TO_FP, SDLoc(N), N->getValueType(0),
1842 // (i32 fp_to_sint (fneg (select_cc f32, f32, 1.0, 0.0 cc))) ->
1843 // (i32 select_cc f32, f32, -1, 0 cc)
1845 // Mesa's GLSL frontend generates the above pattern a lot and we can lower
1846 // this to one of the SET*_DX10 instructions.
1847 case ISD::FP_TO_SINT: {
1848 SDValue FNeg = N->getOperand(0);
1849 if (FNeg.getOpcode() != ISD::FNEG) {
1852 SDValue SelectCC = FNeg.getOperand(0);
1853 if (SelectCC.getOpcode() != ISD::SELECT_CC ||
1854 SelectCC.getOperand(0).getValueType() != MVT::f32 || // LHS
1855 SelectCC.getOperand(2).getValueType() != MVT::f32 || // True
1856 !isHWTrueValue(SelectCC.getOperand(2)) ||
1857 !isHWFalseValue(SelectCC.getOperand(3))) {
1862 return DAG.getNode(ISD::SELECT_CC, dl, N->getValueType(0),
1863 SelectCC.getOperand(0), // LHS
1864 SelectCC.getOperand(1), // RHS
1865 DAG.getConstant(-1, dl, MVT::i32), // True
1866 DAG.getConstant(0, dl, MVT::i32), // False
1867 SelectCC.getOperand(4)); // CC
1872 // insert_vector_elt (build_vector elt0, ... , eltN), NewEltIdx, idx
1873 // => build_vector elt0, ... , NewEltIdx, ... , eltN
1874 case ISD::INSERT_VECTOR_ELT: {
1875 SDValue InVec = N->getOperand(0);
1876 SDValue InVal = N->getOperand(1);
1877 SDValue EltNo = N->getOperand(2);
1880 // If the inserted element is an UNDEF, just use the input vector.
1881 if (InVal.getOpcode() == ISD::UNDEF)
1884 EVT VT = InVec.getValueType();
1886 // If we can't generate a legal BUILD_VECTOR, exit
1887 if (!isOperationLegal(ISD::BUILD_VECTOR, VT))
1890 // Check that we know which element is being inserted
1891 if (!isa<ConstantSDNode>(EltNo))
1893 unsigned Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
1895 // Check that the operand is a BUILD_VECTOR (or UNDEF, which can essentially
1896 // be converted to a BUILD_VECTOR). Fill in the Ops vector with the
1898 SmallVector<SDValue, 8> Ops;
1899 if (InVec.getOpcode() == ISD::BUILD_VECTOR) {
1900 Ops.append(InVec.getNode()->op_begin(),
1901 InVec.getNode()->op_end());
1902 } else if (InVec.getOpcode() == ISD::UNDEF) {
1903 unsigned NElts = VT.getVectorNumElements();
1904 Ops.append(NElts, DAG.getUNDEF(InVal.getValueType()));
1909 // Insert the element
1910 if (Elt < Ops.size()) {
1911 // All the operands of BUILD_VECTOR must have the same type;
1912 // we enforce that here.
1913 EVT OpVT = Ops[0].getValueType();
1914 if (InVal.getValueType() != OpVT)
1915 InVal = OpVT.bitsGT(InVal.getValueType()) ?
1916 DAG.getNode(ISD::ANY_EXTEND, dl, OpVT, InVal) :
1917 DAG.getNode(ISD::TRUNCATE, dl, OpVT, InVal);
1921 // Return the new vector
1922 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
1925 // Extract_vec (Build_vector) generated by custom lowering
1926 // also needs to be customly combined
1927 case ISD::EXTRACT_VECTOR_ELT: {
1928 SDValue Arg = N->getOperand(0);
1929 if (Arg.getOpcode() == ISD::BUILD_VECTOR) {
1930 if (ConstantSDNode *Const = dyn_cast<ConstantSDNode>(N->getOperand(1))) {
1931 unsigned Element = Const->getZExtValue();
1932 return Arg->getOperand(Element);
1935 if (Arg.getOpcode() == ISD::BITCAST &&
1936 Arg.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) {
1937 if (ConstantSDNode *Const = dyn_cast<ConstantSDNode>(N->getOperand(1))) {
1938 unsigned Element = Const->getZExtValue();
1939 return DAG.getNode(ISD::BITCAST, SDLoc(N), N->getVTList(),
1940 Arg->getOperand(0).getOperand(Element));
1946 case ISD::SELECT_CC: {
1947 // Try common optimizations
1948 SDValue Ret = AMDGPUTargetLowering::PerformDAGCombine(N, DCI);
1952 // fold selectcc (selectcc x, y, a, b, cc), b, a, b, seteq ->
1953 // selectcc x, y, a, b, inv(cc)
1955 // fold selectcc (selectcc x, y, a, b, cc), b, a, b, setne ->
1956 // selectcc x, y, a, b, cc
1957 SDValue LHS = N->getOperand(0);
1958 if (LHS.getOpcode() != ISD::SELECT_CC) {
1962 SDValue RHS = N->getOperand(1);
1963 SDValue True = N->getOperand(2);
1964 SDValue False = N->getOperand(3);
1965 ISD::CondCode NCC = cast<CondCodeSDNode>(N->getOperand(4))->get();
1967 if (LHS.getOperand(2).getNode() != True.getNode() ||
1968 LHS.getOperand(3).getNode() != False.getNode() ||
1969 RHS.getNode() != False.getNode()) {
1974 default: return SDValue();
1975 case ISD::SETNE: return LHS;
1977 ISD::CondCode LHSCC = cast<CondCodeSDNode>(LHS.getOperand(4))->get();
1978 LHSCC = ISD::getSetCCInverse(LHSCC,
1979 LHS.getOperand(0).getValueType().isInteger());
1980 if (DCI.isBeforeLegalizeOps() ||
1981 isCondCodeLegal(LHSCC, LHS.getOperand(0).getSimpleValueType()))
1982 return DAG.getSelectCC(SDLoc(N),
1994 case AMDGPUISD::EXPORT: {
1995 SDValue Arg = N->getOperand(1);
1996 if (Arg.getOpcode() != ISD::BUILD_VECTOR)
1999 SDValue NewArgs[8] = {
2000 N->getOperand(0), // Chain
2002 N->getOperand(2), // ArrayBase
2003 N->getOperand(3), // Type
2004 N->getOperand(4), // SWZ_X
2005 N->getOperand(5), // SWZ_Y
2006 N->getOperand(6), // SWZ_Z
2007 N->getOperand(7) // SWZ_W
2010 NewArgs[1] = OptimizeSwizzle(N->getOperand(1), &NewArgs[4], DAG, DL);
2011 return DAG.getNode(AMDGPUISD::EXPORT, DL, N->getVTList(), NewArgs);
2013 case AMDGPUISD::TEXTURE_FETCH: {
2014 SDValue Arg = N->getOperand(1);
2015 if (Arg.getOpcode() != ISD::BUILD_VECTOR)
2018 SDValue NewArgs[19] = {
2040 NewArgs[1] = OptimizeSwizzle(N->getOperand(1), &NewArgs[2], DAG, DL);
2041 return DAG.getNode(AMDGPUISD::TEXTURE_FETCH, DL, N->getVTList(), NewArgs);
2045 return AMDGPUTargetLowering::PerformDAGCombine(N, DCI);
2049 FoldOperand(SDNode *ParentNode, unsigned SrcIdx, SDValue &Src, SDValue &Neg,
2050 SDValue &Abs, SDValue &Sel, SDValue &Imm, SelectionDAG &DAG) {
2051 const R600InstrInfo *TII =
2052 static_cast<const R600InstrInfo *>(DAG.getSubtarget().getInstrInfo());
2053 if (!Src.isMachineOpcode())
2055 switch (Src.getMachineOpcode()) {
2056 case AMDGPU::FNEG_R600:
2059 Src = Src.getOperand(0);
2060 Neg = DAG.getTargetConstant(1, SDLoc(ParentNode), MVT::i32);
2062 case AMDGPU::FABS_R600:
2065 Src = Src.getOperand(0);
2066 Abs = DAG.getTargetConstant(1, SDLoc(ParentNode), MVT::i32);
2068 case AMDGPU::CONST_COPY: {
2069 unsigned Opcode = ParentNode->getMachineOpcode();
2070 bool HasDst = TII->getOperandIdx(Opcode, AMDGPU::OpName::dst) > -1;
2075 SDValue CstOffset = Src.getOperand(0);
2076 if (ParentNode->getValueType(0).isVector())
2079 // Gather constants values
2080 int SrcIndices[] = {
2081 TII->getOperandIdx(Opcode, AMDGPU::OpName::src0),
2082 TII->getOperandIdx(Opcode, AMDGPU::OpName::src1),
2083 TII->getOperandIdx(Opcode, AMDGPU::OpName::src2),
2084 TII->getOperandIdx(Opcode, AMDGPU::OpName::src0_X),
2085 TII->getOperandIdx(Opcode, AMDGPU::OpName::src0_Y),
2086 TII->getOperandIdx(Opcode, AMDGPU::OpName::src0_Z),
2087 TII->getOperandIdx(Opcode, AMDGPU::OpName::src0_W),
2088 TII->getOperandIdx(Opcode, AMDGPU::OpName::src1_X),
2089 TII->getOperandIdx(Opcode, AMDGPU::OpName::src1_Y),
2090 TII->getOperandIdx(Opcode, AMDGPU::OpName::src1_Z),
2091 TII->getOperandIdx(Opcode, AMDGPU::OpName::src1_W)
2093 std::vector<unsigned> Consts;
2094 for (int OtherSrcIdx : SrcIndices) {
2095 int OtherSelIdx = TII->getSelIdx(Opcode, OtherSrcIdx);
2096 if (OtherSrcIdx < 0 || OtherSelIdx < 0)
2102 if (RegisterSDNode *Reg =
2103 dyn_cast<RegisterSDNode>(ParentNode->getOperand(OtherSrcIdx))) {
2104 if (Reg->getReg() == AMDGPU::ALU_CONST) {
2106 = cast<ConstantSDNode>(ParentNode->getOperand(OtherSelIdx));
2107 Consts.push_back(Cst->getZExtValue());
2112 ConstantSDNode *Cst = cast<ConstantSDNode>(CstOffset);
2113 Consts.push_back(Cst->getZExtValue());
2114 if (!TII->fitsConstReadLimitations(Consts)) {
2119 Src = DAG.getRegister(AMDGPU::ALU_CONST, MVT::f32);
2122 case AMDGPU::MOV_IMM_I32:
2123 case AMDGPU::MOV_IMM_F32: {
2124 unsigned ImmReg = AMDGPU::ALU_LITERAL_X;
2125 uint64_t ImmValue = 0;
2128 if (Src.getMachineOpcode() == AMDGPU::MOV_IMM_F32) {
2129 ConstantFPSDNode *FPC = dyn_cast<ConstantFPSDNode>(Src.getOperand(0));
2130 float FloatValue = FPC->getValueAPF().convertToFloat();
2131 if (FloatValue == 0.0) {
2132 ImmReg = AMDGPU::ZERO;
2133 } else if (FloatValue == 0.5) {
2134 ImmReg = AMDGPU::HALF;
2135 } else if (FloatValue == 1.0) {
2136 ImmReg = AMDGPU::ONE;
2138 ImmValue = FPC->getValueAPF().bitcastToAPInt().getZExtValue();
2141 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Src.getOperand(0));
2142 uint64_t Value = C->getZExtValue();
2144 ImmReg = AMDGPU::ZERO;
2145 } else if (Value == 1) {
2146 ImmReg = AMDGPU::ONE_INT;
2152 // Check that we aren't already using an immediate.
2153 // XXX: It's possible for an instruction to have more than one
2154 // immediate operand, but this is not supported yet.
2155 if (ImmReg == AMDGPU::ALU_LITERAL_X) {
2158 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Imm);
2160 if (C->getZExtValue())
2162 Imm = DAG.getTargetConstant(ImmValue, SDLoc(ParentNode), MVT::i32);
2164 Src = DAG.getRegister(ImmReg, MVT::i32);
2173 /// \brief Fold the instructions after selecting them
2174 SDNode *R600TargetLowering::PostISelFolding(MachineSDNode *Node,
2175 SelectionDAG &DAG) const {
2176 const R600InstrInfo *TII =
2177 static_cast<const R600InstrInfo *>(DAG.getSubtarget().getInstrInfo());
2178 if (!Node->isMachineOpcode())
2180 unsigned Opcode = Node->getMachineOpcode();
2183 std::vector<SDValue> Ops(Node->op_begin(), Node->op_end());
2185 if (Opcode == AMDGPU::DOT_4) {
2186 int OperandIdx[] = {
2187 TII->getOperandIdx(Opcode, AMDGPU::OpName::src0_X),
2188 TII->getOperandIdx(Opcode, AMDGPU::OpName::src0_Y),
2189 TII->getOperandIdx(Opcode, AMDGPU::OpName::src0_Z),
2190 TII->getOperandIdx(Opcode, AMDGPU::OpName::src0_W),
2191 TII->getOperandIdx(Opcode, AMDGPU::OpName::src1_X),
2192 TII->getOperandIdx(Opcode, AMDGPU::OpName::src1_Y),
2193 TII->getOperandIdx(Opcode, AMDGPU::OpName::src1_Z),
2194 TII->getOperandIdx(Opcode, AMDGPU::OpName::src1_W)
2197 TII->getOperandIdx(Opcode, AMDGPU::OpName::src0_neg_X),
2198 TII->getOperandIdx(Opcode, AMDGPU::OpName::src0_neg_Y),
2199 TII->getOperandIdx(Opcode, AMDGPU::OpName::src0_neg_Z),
2200 TII->getOperandIdx(Opcode, AMDGPU::OpName::src0_neg_W),
2201 TII->getOperandIdx(Opcode, AMDGPU::OpName::src1_neg_X),
2202 TII->getOperandIdx(Opcode, AMDGPU::OpName::src1_neg_Y),
2203 TII->getOperandIdx(Opcode, AMDGPU::OpName::src1_neg_Z),
2204 TII->getOperandIdx(Opcode, AMDGPU::OpName::src1_neg_W)
2207 TII->getOperandIdx(Opcode, AMDGPU::OpName::src0_abs_X),
2208 TII->getOperandIdx(Opcode, AMDGPU::OpName::src0_abs_Y),
2209 TII->getOperandIdx(Opcode, AMDGPU::OpName::src0_abs_Z),
2210 TII->getOperandIdx(Opcode, AMDGPU::OpName::src0_abs_W),
2211 TII->getOperandIdx(Opcode, AMDGPU::OpName::src1_abs_X),
2212 TII->getOperandIdx(Opcode, AMDGPU::OpName::src1_abs_Y),
2213 TII->getOperandIdx(Opcode, AMDGPU::OpName::src1_abs_Z),
2214 TII->getOperandIdx(Opcode, AMDGPU::OpName::src1_abs_W)
2216 for (unsigned i = 0; i < 8; i++) {
2217 if (OperandIdx[i] < 0)
2219 SDValue &Src = Ops[OperandIdx[i] - 1];
2220 SDValue &Neg = Ops[NegIdx[i] - 1];
2221 SDValue &Abs = Ops[AbsIdx[i] - 1];
2222 bool HasDst = TII->getOperandIdx(Opcode, AMDGPU::OpName::dst) > -1;
2223 int SelIdx = TII->getSelIdx(Opcode, OperandIdx[i]);
2226 SDValue &Sel = (SelIdx > -1) ? Ops[SelIdx] : FakeOp;
2227 if (FoldOperand(Node, i, Src, Neg, Abs, Sel, FakeOp, DAG))
2228 return DAG.getMachineNode(Opcode, SDLoc(Node), Node->getVTList(), Ops);
2230 } else if (Opcode == AMDGPU::REG_SEQUENCE) {
2231 for (unsigned i = 1, e = Node->getNumOperands(); i < e; i += 2) {
2232 SDValue &Src = Ops[i];
2233 if (FoldOperand(Node, i, Src, FakeOp, FakeOp, FakeOp, FakeOp, DAG))
2234 return DAG.getMachineNode(Opcode, SDLoc(Node), Node->getVTList(), Ops);
2236 } else if (Opcode == AMDGPU::CLAMP_R600) {
2237 SDValue Src = Node->getOperand(0);
2238 if (!Src.isMachineOpcode() ||
2239 !TII->hasInstrModifiers(Src.getMachineOpcode()))
2241 int ClampIdx = TII->getOperandIdx(Src.getMachineOpcode(),
2242 AMDGPU::OpName::clamp);
2246 std::vector<SDValue> Ops(Src->op_begin(), Src->op_end());
2247 Ops[ClampIdx - 1] = DAG.getTargetConstant(1, DL, MVT::i32);
2248 return DAG.getMachineNode(Src.getMachineOpcode(), DL,
2249 Node->getVTList(), Ops);
2251 if (!TII->hasInstrModifiers(Opcode))
2253 int OperandIdx[] = {
2254 TII->getOperandIdx(Opcode, AMDGPU::OpName::src0),
2255 TII->getOperandIdx(Opcode, AMDGPU::OpName::src1),
2256 TII->getOperandIdx(Opcode, AMDGPU::OpName::src2)
2259 TII->getOperandIdx(Opcode, AMDGPU::OpName::src0_neg),
2260 TII->getOperandIdx(Opcode, AMDGPU::OpName::src1_neg),
2261 TII->getOperandIdx(Opcode, AMDGPU::OpName::src2_neg)
2264 TII->getOperandIdx(Opcode, AMDGPU::OpName::src0_abs),
2265 TII->getOperandIdx(Opcode, AMDGPU::OpName::src1_abs),
2268 for (unsigned i = 0; i < 3; i++) {
2269 if (OperandIdx[i] < 0)
2271 SDValue &Src = Ops[OperandIdx[i] - 1];
2272 SDValue &Neg = Ops[NegIdx[i] - 1];
2274 SDValue &Abs = (AbsIdx[i] > -1) ? Ops[AbsIdx[i] - 1] : FakeAbs;
2275 bool HasDst = TII->getOperandIdx(Opcode, AMDGPU::OpName::dst) > -1;
2276 int SelIdx = TII->getSelIdx(Opcode, OperandIdx[i]);
2277 int ImmIdx = TII->getOperandIdx(Opcode, AMDGPU::OpName::literal);
2282 SDValue &Sel = (SelIdx > -1) ? Ops[SelIdx] : FakeOp;
2283 SDValue &Imm = Ops[ImmIdx];
2284 if (FoldOperand(Node, i, Src, Neg, Abs, Sel, Imm, DAG))
2285 return DAG.getMachineNode(Opcode, SDLoc(Node), Node->getVTList(), Ops);