1 //===- R600MCCodeEmitter.cpp - Code Emitter for R600->Cayman GPU families -===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
12 /// \brief The R600 code emitter produces machine code that can be executed
13 /// directly on the GPU device.
15 //===----------------------------------------------------------------------===//
17 #include "R600Defines.h"
18 #include "MCTargetDesc/AMDGPUMCCodeEmitter.h"
19 #include "MCTargetDesc/AMDGPUMCTargetDesc.h"
20 #include "llvm/MC/MCCodeEmitter.h"
21 #include "llvm/MC/MCContext.h"
22 #include "llvm/MC/MCInst.h"
23 #include "llvm/MC/MCInstrInfo.h"
24 #include "llvm/MC/MCRegisterInfo.h"
25 #include "llvm/MC/MCSubtargetInfo.h"
26 #include "llvm/Support/EndianStream.h"
27 #include "llvm/Support/raw_ostream.h"
33 class R600MCCodeEmitter : public AMDGPUMCCodeEmitter {
34 R600MCCodeEmitter(const R600MCCodeEmitter &) = delete;
35 void operator=(const R600MCCodeEmitter &) = delete;
36 const MCInstrInfo &MCII;
37 const MCRegisterInfo &MRI;
40 R600MCCodeEmitter(const MCInstrInfo &mcii, const MCRegisterInfo &mri)
41 : MCII(mcii), MRI(mri) { }
43 /// \brief Encode the instruction and write it to the OS.
44 void encodeInstruction(const MCInst &MI, raw_ostream &OS,
45 SmallVectorImpl<MCFixup> &Fixups,
46 const MCSubtargetInfo &STI) const override;
48 /// \returns the encoding for an MCOperand.
49 uint64_t getMachineOpValue(const MCInst &MI, const MCOperand &MO,
50 SmallVectorImpl<MCFixup> &Fixups,
51 const MCSubtargetInfo &STI) const override;
54 void EmitByte(unsigned int byte, raw_ostream &OS) const;
56 void Emit(uint32_t value, raw_ostream &OS) const;
57 void Emit(uint64_t value, raw_ostream &OS) const;
59 unsigned getHWRegChan(unsigned reg) const;
60 unsigned getHWReg(unsigned regNo) const;
63 } // End anonymous namespace
82 MCCodeEmitter *llvm::createR600MCCodeEmitter(const MCInstrInfo &MCII,
83 const MCRegisterInfo &MRI,
85 return new R600MCCodeEmitter(MCII, MRI);
88 void R600MCCodeEmitter::encodeInstruction(const MCInst &MI, raw_ostream &OS,
89 SmallVectorImpl<MCFixup> &Fixups,
90 const MCSubtargetInfo &STI) const {
91 const MCInstrDesc &Desc = MCII.get(MI.getOpcode());
92 if (MI.getOpcode() == AMDGPU::RETURN ||
93 MI.getOpcode() == AMDGPU::FETCH_CLAUSE ||
94 MI.getOpcode() == AMDGPU::ALU_CLAUSE ||
95 MI.getOpcode() == AMDGPU::BUNDLE ||
96 MI.getOpcode() == AMDGPU::KILL) {
98 } else if (IS_VTX(Desc)) {
99 uint64_t InstWord01 = getBinaryCodeForInstr(MI, Fixups, STI);
100 uint32_t InstWord2 = MI.getOperand(2).getImm(); // Offset
101 if (!(STI.getFeatureBits()[AMDGPU::FeatureCaymanISA])) {
102 InstWord2 |= 1 << 19; // Mega-Fetch bit
105 Emit(InstWord01, OS);
107 Emit((uint32_t) 0, OS);
108 } else if (IS_TEX(Desc)) {
109 int64_t Sampler = MI.getOperand(14).getImm();
111 int64_t SrcSelect[4] = {
112 MI.getOperand(2).getImm(),
113 MI.getOperand(3).getImm(),
114 MI.getOperand(4).getImm(),
115 MI.getOperand(5).getImm()
117 int64_t Offsets[3] = {
118 MI.getOperand(6).getImm() & 0x1F,
119 MI.getOperand(7).getImm() & 0x1F,
120 MI.getOperand(8).getImm() & 0x1F
123 uint64_t Word01 = getBinaryCodeForInstr(MI, Fixups, STI);
124 uint32_t Word2 = Sampler << 15 | SrcSelect[ELEMENT_X] << 20 |
125 SrcSelect[ELEMENT_Y] << 23 | SrcSelect[ELEMENT_Z] << 26 |
126 SrcSelect[ELEMENT_W] << 29 | Offsets[0] << 0 | Offsets[1] << 5 |
131 Emit((uint32_t) 0, OS);
133 uint64_t Inst = getBinaryCodeForInstr(MI, Fixups, STI);
134 if ((STI.getFeatureBits()[AMDGPU::FeatureR600ALUInst]) &&
135 ((Desc.TSFlags & R600_InstFlag::OP1) ||
136 Desc.TSFlags & R600_InstFlag::OP2)) {
137 uint64_t ISAOpCode = Inst & (0x3FFULL << 39);
138 Inst &= ~(0x3FFULL << 39);
139 Inst |= ISAOpCode << 1;
145 void R600MCCodeEmitter::EmitByte(unsigned int Byte, raw_ostream &OS) const {
146 OS.write((uint8_t) Byte & 0xff);
149 void R600MCCodeEmitter::Emit(uint32_t Value, raw_ostream &OS) const {
150 support::endian::Writer<support::little>(OS).write(Value);
153 void R600MCCodeEmitter::Emit(uint64_t Value, raw_ostream &OS) const {
154 support::endian::Writer<support::little>(OS).write(Value);
157 unsigned R600MCCodeEmitter::getHWRegChan(unsigned reg) const {
158 return MRI.getEncodingValue(reg) >> HW_CHAN_SHIFT;
161 unsigned R600MCCodeEmitter::getHWReg(unsigned RegNo) const {
162 return MRI.getEncodingValue(RegNo) & HW_REG_MASK;
165 uint64_t R600MCCodeEmitter::getMachineOpValue(const MCInst &MI,
167 SmallVectorImpl<MCFixup> &Fixup,
168 const MCSubtargetInfo &STI) const {
170 if (HAS_NATIVE_OPERANDS(MCII.get(MI.getOpcode()).TSFlags))
171 return MRI.getEncodingValue(MO.getReg());
172 return getHWReg(MO.getReg());
179 #include "AMDGPUGenMCCodeEmitter.inc"