1 //===-- AMDGPUMCTargetDesc.cpp - AMDGPU Target Descriptions ---------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// \brief This file provides AMDGPU specific target descriptions.
13 //===----------------------------------------------------------------------===//
15 #include "AMDGPUMCTargetDesc.h"
16 #include "AMDGPUELFStreamer.h"
17 #include "AMDGPUMCAsmInfo.h"
18 #include "AMDGPUTargetStreamer.h"
19 #include "InstPrinter/AMDGPUInstPrinter.h"
20 #include "SIDefines.h"
21 #include "llvm/MC/MCCodeGenInfo.h"
22 #include "llvm/MC/MCContext.h"
23 #include "llvm/MC/MCInstrInfo.h"
24 #include "llvm/MC/MCRegisterInfo.h"
25 #include "llvm/MC/MCStreamer.h"
26 #include "llvm/MC/MCSubtargetInfo.h"
27 #include "llvm/MC/MachineLocation.h"
28 #include "llvm/Support/ErrorHandling.h"
29 #include "llvm/Support/TargetRegistry.h"
33 #define GET_INSTRINFO_MC_DESC
34 #include "AMDGPUGenInstrInfo.inc"
36 #define GET_SUBTARGETINFO_MC_DESC
37 #include "AMDGPUGenSubtargetInfo.inc"
39 #define GET_REGINFO_MC_DESC
40 #include "AMDGPUGenRegisterInfo.inc"
42 static MCInstrInfo *createAMDGPUMCInstrInfo() {
43 MCInstrInfo *X = new MCInstrInfo();
44 InitAMDGPUMCInstrInfo(X);
48 static MCRegisterInfo *createAMDGPUMCRegisterInfo(const Triple &TT) {
49 MCRegisterInfo *X = new MCRegisterInfo();
50 InitAMDGPUMCRegisterInfo(X, 0);
54 static MCSubtargetInfo *
55 createAMDGPUMCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS) {
56 return createAMDGPUMCSubtargetInfoImpl(TT, CPU, FS);
59 static MCCodeGenInfo *createAMDGPUMCCodeGenInfo(const Triple &TT,
62 CodeGenOpt::Level OL) {
63 MCCodeGenInfo *X = new MCCodeGenInfo();
64 X->initMCCodeGenInfo(RM, CM, OL);
68 static MCInstPrinter *createAMDGPUMCInstPrinter(const Triple &T,
69 unsigned SyntaxVariant,
71 const MCInstrInfo &MII,
72 const MCRegisterInfo &MRI) {
73 return new AMDGPUInstPrinter(MAI, MII, MRI);
76 static MCTargetStreamer *createAMDGPUAsmTargetStreamer(MCStreamer &S,
77 formatted_raw_ostream &OS,
78 MCInstPrinter *InstPrint,
80 return new AMDGPUTargetAsmStreamer(S, OS);
83 static MCTargetStreamer * createAMDGPUObjectTargetStreamer(
85 const MCSubtargetInfo &STI) {
86 return new AMDGPUTargetELFStreamer(S);
89 static MCStreamer *createMCStreamer(const Triple &T, MCContext &Context,
90 MCAsmBackend &MAB, raw_pwrite_stream &OS,
91 MCCodeEmitter *Emitter, bool RelaxAll) {
92 if (T.getOS() == Triple::AMDHSA)
93 return createAMDGPUELFStreamer(Context, MAB, OS, Emitter, RelaxAll);
95 return createELFStreamer(Context, MAB, OS, Emitter, RelaxAll);
98 extern "C" void LLVMInitializeAMDGPUTargetMC() {
99 for (Target *T : {&TheAMDGPUTarget, &TheGCNTarget}) {
100 RegisterMCAsmInfo<AMDGPUMCAsmInfo> X(*T);
102 TargetRegistry::RegisterMCCodeGenInfo(*T, createAMDGPUMCCodeGenInfo);
103 TargetRegistry::RegisterMCInstrInfo(*T, createAMDGPUMCInstrInfo);
104 TargetRegistry::RegisterMCRegInfo(*T, createAMDGPUMCRegisterInfo);
105 TargetRegistry::RegisterMCSubtargetInfo(*T, createAMDGPUMCSubtargetInfo);
106 TargetRegistry::RegisterMCInstPrinter(*T, createAMDGPUMCInstPrinter);
107 TargetRegistry::RegisterMCAsmBackend(*T, createAMDGPUAsmBackend);
108 TargetRegistry::RegisterELFStreamer(*T, createMCStreamer);
111 // R600 specific registration
112 TargetRegistry::RegisterMCCodeEmitter(TheAMDGPUTarget,
113 createR600MCCodeEmitter);
115 // GCN specific registration
116 TargetRegistry::RegisterMCCodeEmitter(TheGCNTarget, createSIMCCodeEmitter);
118 TargetRegistry::RegisterAsmTargetStreamer(TheGCNTarget,
119 createAMDGPUAsmTargetStreamer);
120 TargetRegistry::RegisterObjectTargetStreamer(TheGCNTarget,
121 createAMDGPUObjectTargetStreamer);