1 //===-- AMDGPUMCTargetDesc.cpp - AMDGPU Target Descriptions ---------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// \brief This file provides AMDGPU specific target descriptions.
13 //===----------------------------------------------------------------------===//
15 #include "AMDGPUMCTargetDesc.h"
16 #include "AMDGPUMCAsmInfo.h"
17 #include "AMDGPUTargetStreamer.h"
18 #include "InstPrinter/AMDGPUInstPrinter.h"
19 #include "SIDefines.h"
20 #include "llvm/MC/MCCodeGenInfo.h"
21 #include "llvm/MC/MCContext.h"
22 #include "llvm/MC/MCInstrInfo.h"
23 #include "llvm/MC/MCRegisterInfo.h"
24 #include "llvm/MC/MCStreamer.h"
25 #include "llvm/MC/MCSubtargetInfo.h"
26 #include "llvm/MC/MachineLocation.h"
27 #include "llvm/Support/ErrorHandling.h"
28 #include "llvm/Support/TargetRegistry.h"
32 #define GET_INSTRINFO_MC_DESC
33 #include "AMDGPUGenInstrInfo.inc"
35 #define GET_SUBTARGETINFO_MC_DESC
36 #include "AMDGPUGenSubtargetInfo.inc"
38 #define GET_REGINFO_MC_DESC
39 #include "AMDGPUGenRegisterInfo.inc"
41 static MCInstrInfo *createAMDGPUMCInstrInfo() {
42 MCInstrInfo *X = new MCInstrInfo();
43 InitAMDGPUMCInstrInfo(X);
47 static MCRegisterInfo *createAMDGPUMCRegisterInfo(const Triple &TT) {
48 MCRegisterInfo *X = new MCRegisterInfo();
49 InitAMDGPUMCRegisterInfo(X, 0);
53 static MCSubtargetInfo *
54 createAMDGPUMCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS) {
55 return createAMDGPUMCSubtargetInfoImpl(TT, CPU, FS);
58 static MCCodeGenInfo *createAMDGPUMCCodeGenInfo(const Triple &TT,
61 CodeGenOpt::Level OL) {
62 MCCodeGenInfo *X = new MCCodeGenInfo();
63 X->initMCCodeGenInfo(RM, CM, OL);
67 static MCInstPrinter *createAMDGPUMCInstPrinter(const Triple &T,
68 unsigned SyntaxVariant,
70 const MCInstrInfo &MII,
71 const MCRegisterInfo &MRI) {
72 return new AMDGPUInstPrinter(MAI, MII, MRI);
75 static MCTargetStreamer *createAMDGPUAsmTargetStreamer(MCStreamer &S,
76 formatted_raw_ostream &OS,
77 MCInstPrinter *InstPrint,
79 return new AMDGPUTargetAsmStreamer(S, OS);
82 static MCTargetStreamer * createAMDGPUObjectTargetStreamer(
84 const MCSubtargetInfo &STI) {
85 return new AMDGPUTargetELFStreamer(S);
88 extern "C" void LLVMInitializeAMDGPUTargetMC() {
89 for (Target *T : {&TheAMDGPUTarget, &TheGCNTarget}) {
90 RegisterMCAsmInfo<AMDGPUMCAsmInfo> X(*T);
92 TargetRegistry::RegisterMCCodeGenInfo(*T, createAMDGPUMCCodeGenInfo);
93 TargetRegistry::RegisterMCInstrInfo(*T, createAMDGPUMCInstrInfo);
94 TargetRegistry::RegisterMCRegInfo(*T, createAMDGPUMCRegisterInfo);
95 TargetRegistry::RegisterMCSubtargetInfo(*T, createAMDGPUMCSubtargetInfo);
96 TargetRegistry::RegisterMCInstPrinter(*T, createAMDGPUMCInstPrinter);
97 TargetRegistry::RegisterMCAsmBackend(*T, createAMDGPUAsmBackend);
100 // R600 specific registration
101 TargetRegistry::RegisterMCCodeEmitter(TheAMDGPUTarget,
102 createR600MCCodeEmitter);
104 // GCN specific registration
105 TargetRegistry::RegisterMCCodeEmitter(TheGCNTarget, createSIMCCodeEmitter);
107 TargetRegistry::RegisterAsmTargetStreamer(TheGCNTarget,
108 createAMDGPUAsmTargetStreamer);
109 TargetRegistry::RegisterObjectTargetStreamer(TheGCNTarget,
110 createAMDGPUObjectTargetStreamer);