1 set(LLVM_TARGET_DEFINITIONS AMDGPU.td)
3 tablegen(LLVM AMDGPUGenRegisterInfo.inc -gen-register-info)
4 tablegen(LLVM AMDGPUGenInstrInfo.inc -gen-instr-info)
5 tablegen(LLVM AMDGPUGenDAGISel.inc -gen-dag-isel)
6 tablegen(LLVM AMDGPUGenCallingConv.inc -gen-callingconv)
7 tablegen(LLVM AMDGPUGenSubtargetInfo.inc -gen-subtarget)
8 tablegen(LLVM AMDGPUGenIntrinsics.inc -gen-tgt-intrinsic)
9 tablegen(LLVM AMDGPUGenMCCodeEmitter.inc -gen-emitter)
10 tablegen(LLVM AMDGPUGenDFAPacketizer.inc -gen-dfa-packetizer)
11 tablegen(LLVM AMDGPUGenAsmWriter.inc -gen-asm-writer)
12 tablegen(LLVM AMDGPUGenAsmMatcher.inc -gen-asm-matcher)
13 add_public_tablegen_target(AMDGPUCommonTableGen)
15 add_llvm_target(AMDGPUCodeGen
16 AMDILCFGStructurizer.cpp
17 AMDGPUAlwaysInlinePass.cpp
19 AMDGPUDiagnosticInfoUnsupported.cpp
20 AMDGPUFrameLowering.cpp
21 AMDGPUHSATargetObjectFile.cpp
22 AMDGPUIntrinsicInfo.cpp
23 AMDGPUISelDAGToDAG.cpp
25 AMDGPUMachineFunction.cpp
26 AMDGPUOpenCLImageTypeLoweringPass.cpp
28 AMDGPUTargetMachine.cpp
29 AMDGPUTargetTransformInfo.cpp
30 AMDGPUISelLowering.cpp
32 AMDGPUPromoteAlloca.cpp
33 AMDGPURegisterInfo.cpp
34 R600ClauseMergePass.cpp
35 R600ControlFlowFinalizer.cpp
36 R600EmitClauseMarkers.cpp
37 R600ExpandSpecialInstrs.cpp
40 R600MachineFunctionInfo.cpp
41 R600MachineScheduler.cpp
42 R600OptimizeVectorRegisters.cpp
45 R600TextureIntrinsicsReplacer.cpp
46 SIAnnotateControlFlow.cpp
47 SIFixControlFlowLiveIntervals.cpp
49 SIFixSGPRLiveRanges.cpp
54 SILoadStoreOptimizer.cpp
55 SILowerControlFlow.cpp
57 SIMachineFunctionInfo.cpp
58 SIPrepareScratchRegs.cpp
60 SIShrinkInstructions.cpp
64 add_subdirectory(AsmParser)
65 add_subdirectory(InstPrinter)
66 add_subdirectory(TargetInfo)
67 add_subdirectory(MCTargetDesc)
68 add_subdirectory(Utils)