1 //===-- CIInstructions.td - CI Instruction Defintions ---------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
9 // Instruction definitions for CI and newer.
10 //===----------------------------------------------------------------------===//
11 // Remaining instructions:
14 // S_CBRANCH_CDBGSYS_OR_USER
15 // S_CBRANCH_CDBGSYS_AND_USER
17 // DS_GWS_SEMA_RELEASE_ALL
19 // DS_CNDXCHG32_RTN_B64
22 // DS_CONDXCHG32_RTN_B128
25 // BUFFER_LOAD_DWORDX3
26 // BUFFER_STORE_DWORDX3
29 def isCIVI : Predicate <
30 "Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS || "
31 "Subtarget->getGeneration() == AMDGPUSubtarget::VOLCANIC_ISLANDS"
32 >, AssemblerPredicate<"FeatureCIInsts">;
34 def HasFlatAddressSpace : Predicate<"Subtarget->hasFlatAddressSpace()">;
36 //===----------------------------------------------------------------------===//
38 //===----------------------------------------------------------------------===//
40 let SubtargetPredicate = isCIVI in {
42 let SchedRW = [WriteDoubleAdd] in {
43 defm V_TRUNC_F64 : VOP1Inst <vop1<0x17>, "v_trunc_f64",
46 defm V_CEIL_F64 : VOP1Inst <vop1<0x18>, "v_ceil_f64",
49 defm V_FLOOR_F64 : VOP1Inst <vop1<0x1A>, "v_floor_f64",
52 defm V_RNDNE_F64 : VOP1Inst <vop1<0x19>, "v_rndne_f64",
55 } // End SchedRW = [WriteDoubleAdd]
57 let SchedRW = [WriteQuarterRate32] in {
58 defm V_LOG_LEGACY_F32 : VOP1Inst <vop1<0x45, 0x4c>, "v_log_legacy_f32",
61 defm V_EXP_LEGACY_F32 : VOP1Inst <vop1<0x46, 0x4b>, "v_exp_legacy_f32",
64 } // End SchedRW = [WriteQuarterRate32]
66 //===----------------------------------------------------------------------===//
68 //===----------------------------------------------------------------------===//
70 defm V_QSAD_PK_U16_U8 : VOP3Inst <vop3<0x173>, "v_qsad_pk_u16_u8",
73 defm V_MQSAD_U16_U8 : VOP3Inst <vop3<0x172>, "v_mqsad_u16_u8",
76 defm V_MQSAD_U32_U8 : VOP3Inst <vop3<0x175>, "v_mqsad_u32_u8",
80 let isCommutable = 1 in {
81 defm V_MAD_U64_U32 : VOP3Inst <vop3<0x176>, "v_mad_u64_u32",
85 // XXX - Does this set VCC?
86 defm V_MAD_I64_I32 : VOP3Inst <vop3<0x177>, "v_mad_i64_i32",
89 } // End isCommutable = 1
92 //===----------------------------------------------------------------------===//
94 //===----------------------------------------------------------------------===//
95 defm DS_WRAP_RTN_F32 : DS_1A1D_RET <0x34, "ds_wrap_rtn_f32", VGPR_32, "ds_wrap_f32">;
97 // DS_CONDXCHG32_RTN_B64
98 // DS_CONDXCHG32_RTN_B128
100 //===----------------------------------------------------------------------===//
102 //===----------------------------------------------------------------------===//
104 defm S_DCACHE_INV_VOL : SMRD_Inval <smrd<0x1d, 0x22>,
105 "s_dcache_inv_vol", int_amdgcn_s_dcache_inv_vol>;
107 //===----------------------------------------------------------------------===//
108 // MUBUF Instructions
109 //===----------------------------------------------------------------------===//
111 defm BUFFER_WBINVL1_VOL : MUBUF_Invalidate <mubuf<0x70, 0x3f>,
112 "buffer_wbinvl1_vol", int_amdgcn_buffer_wbinvl1_vol
115 //===----------------------------------------------------------------------===//
117 //===----------------------------------------------------------------------===//
119 defm FLAT_LOAD_UBYTE : FLAT_Load_Helper <
120 flat<0x8, 0x10>, "flat_load_ubyte", VGPR_32
122 defm FLAT_LOAD_SBYTE : FLAT_Load_Helper <
123 flat<0x9, 0x11>, "flat_load_sbyte", VGPR_32
125 defm FLAT_LOAD_USHORT : FLAT_Load_Helper <
126 flat<0xa, 0x12>, "flat_load_ushort", VGPR_32
128 defm FLAT_LOAD_SSHORT : FLAT_Load_Helper <
129 flat<0xb, 0x13>, "flat_load_sshort", VGPR_32>
131 defm FLAT_LOAD_DWORD : FLAT_Load_Helper <
132 flat<0xc, 0x14>, "flat_load_dword", VGPR_32
134 defm FLAT_LOAD_DWORDX2 : FLAT_Load_Helper <
135 flat<0xd, 0x15>, "flat_load_dwordx2", VReg_64
137 defm FLAT_LOAD_DWORDX4 : FLAT_Load_Helper <
138 flat<0xe, 0x17>, "flat_load_dwordx4", VReg_128
140 defm FLAT_LOAD_DWORDX3 : FLAT_Load_Helper <
141 flat<0xf, 0x16>, "flat_load_dwordx3", VReg_96
143 defm FLAT_STORE_BYTE : FLAT_Store_Helper <
144 flat<0x18>, "flat_store_byte", VGPR_32
146 defm FLAT_STORE_SHORT : FLAT_Store_Helper <
147 flat <0x1a>, "flat_store_short", VGPR_32
149 defm FLAT_STORE_DWORD : FLAT_Store_Helper <
150 flat<0x1c>, "flat_store_dword", VGPR_32
152 defm FLAT_STORE_DWORDX2 : FLAT_Store_Helper <
153 flat<0x1d>, "flat_store_dwordx2", VReg_64
155 defm FLAT_STORE_DWORDX4 : FLAT_Store_Helper <
156 flat<0x1e, 0x1f>, "flat_store_dwordx4", VReg_128
158 defm FLAT_STORE_DWORDX3 : FLAT_Store_Helper <
159 flat<0x1f, 0x1e>, "flat_store_dwordx3", VReg_96
161 defm FLAT_ATOMIC_SWAP : FLAT_ATOMIC <
162 flat<0x30, 0x40>, "flat_atomic_swap", VGPR_32
164 defm FLAT_ATOMIC_CMPSWAP : FLAT_ATOMIC <
165 flat<0x31, 0x41>, "flat_atomic_cmpswap", VGPR_32, VReg_64
167 defm FLAT_ATOMIC_ADD : FLAT_ATOMIC <
168 flat<0x32, 0x42>, "flat_atomic_add", VGPR_32
170 defm FLAT_ATOMIC_SUB : FLAT_ATOMIC <
171 flat<0x33, 0x43>, "flat_atomic_sub", VGPR_32
173 defm FLAT_ATOMIC_SMIN : FLAT_ATOMIC <
174 flat<0x35, 0x44>, "flat_atomic_smin", VGPR_32
176 defm FLAT_ATOMIC_UMIN : FLAT_ATOMIC <
177 flat<0x36, 0x45>, "flat_atomic_umin", VGPR_32
179 defm FLAT_ATOMIC_SMAX : FLAT_ATOMIC <
180 flat<0x37, 0x46>, "flat_atomic_smax", VGPR_32
182 defm FLAT_ATOMIC_UMAX : FLAT_ATOMIC <
183 flat<0x38, 0x47>, "flat_atomic_umax", VGPR_32
185 defm FLAT_ATOMIC_AND : FLAT_ATOMIC <
186 flat<0x39, 0x48>, "flat_atomic_and", VGPR_32
188 defm FLAT_ATOMIC_OR : FLAT_ATOMIC <
189 flat<0x3a, 0x49>, "flat_atomic_or", VGPR_32
191 defm FLAT_ATOMIC_XOR : FLAT_ATOMIC <
192 flat<0x3b, 0x4a>, "flat_atomic_xor", VGPR_32
194 defm FLAT_ATOMIC_INC : FLAT_ATOMIC <
195 flat<0x3c, 0x4b>, "flat_atomic_inc", VGPR_32
197 defm FLAT_ATOMIC_DEC : FLAT_ATOMIC <
198 flat<0x3d, 0x4c>, "flat_atomic_dec", VGPR_32
200 defm FLAT_ATOMIC_SWAP_X2 : FLAT_ATOMIC <
201 flat<0x50, 0x60>, "flat_atomic_swap_x2", VReg_64
203 defm FLAT_ATOMIC_CMPSWAP_X2 : FLAT_ATOMIC <
204 flat<0x51, 0x61>, "flat_atomic_cmpswap_x2", VReg_64, VReg_128
206 defm FLAT_ATOMIC_ADD_X2 : FLAT_ATOMIC <
207 flat<0x52, 0x62>, "flat_atomic_add_x2", VReg_64
209 defm FLAT_ATOMIC_SUB_X2 : FLAT_ATOMIC <
210 flat<0x53, 0x63>, "flat_atomic_sub_x2", VReg_64
212 defm FLAT_ATOMIC_SMIN_X2 : FLAT_ATOMIC <
213 flat<0x55, 0x64>, "flat_atomic_smin_x2", VReg_64
215 defm FLAT_ATOMIC_UMIN_X2 : FLAT_ATOMIC <
216 flat<0x56, 0x65>, "flat_atomic_umin_x2", VReg_64
218 defm FLAT_ATOMIC_SMAX_X2 : FLAT_ATOMIC <
219 flat<0x57, 0x66>, "flat_atomic_smax_x2", VReg_64
221 defm FLAT_ATOMIC_UMAX_X2 : FLAT_ATOMIC <
222 flat<0x58, 0x67>, "flat_atomic_umax_x2", VReg_64
224 defm FLAT_ATOMIC_AND_X2 : FLAT_ATOMIC <
225 flat<0x59, 0x68>, "flat_atomic_and_x2", VReg_64
227 defm FLAT_ATOMIC_OR_X2 : FLAT_ATOMIC <
228 flat<0x5a, 0x69>, "flat_atomic_or_x2", VReg_64
230 defm FLAT_ATOMIC_XOR_X2 : FLAT_ATOMIC <
231 flat<0x5b, 0x6a>, "flat_atomic_xor_x2", VReg_64
233 defm FLAT_ATOMIC_INC_X2 : FLAT_ATOMIC <
234 flat<0x5c, 0x6b>, "flat_atomic_inc_x2", VReg_64
236 defm FLAT_ATOMIC_DEC_X2 : FLAT_ATOMIC <
237 flat<0x5d, 0x6c>, "flat_atomic_dec_x2", VReg_64
240 } // End SubtargetPredicate = isCIVI
242 // CI Only flat instructions
244 let SubtargetPredicate = isCI, VIAssemblerPredicate = DisableInst in {
246 defm FLAT_ATOMIC_FCMPSWAP : FLAT_ATOMIC <
247 flat<0x3e>, "flat_atomic_fcmpswap", VGPR_32, VReg_64
249 defm FLAT_ATOMIC_FMIN : FLAT_ATOMIC <
250 flat<0x3f>, "flat_atomic_fmin", VGPR_32
252 defm FLAT_ATOMIC_FMAX : FLAT_ATOMIC <
253 flat<0x40>, "flat_atomic_fmax", VGPR_32
255 defm FLAT_ATOMIC_FCMPSWAP_X2 : FLAT_ATOMIC <
256 flat<0x5e>, "flat_atomic_fcmpswap_x2", VReg_64, VReg_128
258 defm FLAT_ATOMIC_FMIN_X2 : FLAT_ATOMIC <
259 flat<0x5f>, "flat_atomic_fmin_x2", VReg_64
261 defm FLAT_ATOMIC_FMAX_X2 : FLAT_ATOMIC <
262 flat<0x60>, "flat_atomic_fmax_x2", VReg_64
265 } // End let SubtargetPredicate = isCI, VIAssemblerPredicate = DisableInst
267 let Predicates = [isCI] in {
269 // Convert (x - floor(x)) to fract(x)
271 (f32 (fsub (f32 (VOP3Mods f32:$x, i32:$mods)),
272 (f32 (ffloor (f32 (VOP3Mods f32:$x, i32:$mods)))))),
273 (V_FRACT_F32_e64 $mods, $x, DSTCLAMP.NONE, DSTOMOD.NONE)
276 // Convert (x + (-floor(x))) to fract(x)
278 (f64 (fadd (f64 (VOP3Mods f64:$x, i32:$mods)),
279 (f64 (fneg (f64 (ffloor (f64 (VOP3Mods f64:$x, i32:$mods)))))))),
280 (V_FRACT_F64_e64 $mods, $x, DSTCLAMP.NONE, DSTOMOD.NONE)
283 } // End Predicates = [isCI]
286 //===----------------------------------------------------------------------===//
288 //===----------------------------------------------------------------------===//
290 let Predicates = [isCIVI] in {
292 // Patterns for global loads with no offset
293 class FlatLoadPat <FLAT inst, SDPatternOperator node, ValueType vt> : Pat <
294 (vt (node i64:$addr)),
295 (inst $addr, 0, 0, 0)
298 def : FlatLoadPat <FLAT_LOAD_UBYTE, flat_az_extloadi8, i32>;
299 def : FlatLoadPat <FLAT_LOAD_SBYTE, flat_sextloadi8, i32>;
300 def : FlatLoadPat <FLAT_LOAD_USHORT, flat_az_extloadi16, i32>;
301 def : FlatLoadPat <FLAT_LOAD_SSHORT, flat_sextloadi16, i32>;
302 def : FlatLoadPat <FLAT_LOAD_DWORD, flat_load, i32>;
303 def : FlatLoadPat <FLAT_LOAD_DWORDX2, flat_load, v2i32>;
304 def : FlatLoadPat <FLAT_LOAD_DWORDX4, flat_load, v4i32>;
306 class FlatStorePat <FLAT inst, SDPatternOperator node, ValueType vt> : Pat <
307 (node vt:$data, i64:$addr),
308 (inst $data, $addr, 0, 0, 0)
311 def : FlatStorePat <FLAT_STORE_BYTE, flat_truncstorei8, i32>;
312 def : FlatStorePat <FLAT_STORE_SHORT, flat_truncstorei16, i32>;
313 def : FlatStorePat <FLAT_STORE_DWORD, flat_store, i32>;
314 def : FlatStorePat <FLAT_STORE_DWORDX2, flat_store, v2i32>;
315 def : FlatStorePat <FLAT_STORE_DWORDX4, flat_store, v4i32>;
317 class FlatAtomicPat <FLAT inst, SDPatternOperator node, ValueType vt> : Pat <
318 (vt (node i64:$addr, vt:$data)),
319 (inst $addr, $data, 0, 0)
322 def : FlatAtomicPat <FLAT_ATOMIC_ADD_RTN, atomic_add_global, i32>;
323 def : FlatAtomicPat <FLAT_ATOMIC_AND_RTN, atomic_and_global, i32>;
324 def : FlatAtomicPat <FLAT_ATOMIC_SUB_RTN, atomic_sub_global, i32>;
325 def : FlatAtomicPat <FLAT_ATOMIC_SMAX_RTN, atomic_max_global, i32>;
326 def : FlatAtomicPat <FLAT_ATOMIC_UMAX_RTN, atomic_umax_global, i32>;
327 def : FlatAtomicPat <FLAT_ATOMIC_SMIN_RTN, atomic_min_global, i32>;
328 def : FlatAtomicPat <FLAT_ATOMIC_UMIN_RTN, atomic_umin_global, i32>;
329 def : FlatAtomicPat <FLAT_ATOMIC_OR_RTN, atomic_or_global, i32>;
330 def : FlatAtomicPat <FLAT_ATOMIC_SWAP_RTN, atomic_swap_global, i32>;
331 def : FlatAtomicPat <FLAT_ATOMIC_XOR_RTN, atomic_xor_global, i32>;
333 } // End Predicates = [isCIVI]