1 //===-- AMDGPUTargetMachine.h - AMDGPU TargetMachine Interface --*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// \brief The AMDGPU TargetMachine interface definition for hw codgen targets.
13 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_LIB_TARGET_R600_AMDGPUTARGETMACHINE_H
16 #define LLVM_LIB_TARGET_R600_AMDGPUTARGETMACHINE_H
18 #include "AMDGPUFrameLowering.h"
19 #include "AMDGPUInstrInfo.h"
20 #include "AMDGPUIntrinsicInfo.h"
21 #include "AMDGPUSubtarget.h"
22 #include "R600ISelLowering.h"
23 #include "llvm/IR/DataLayout.h"
27 //===----------------------------------------------------------------------===//
28 // AMDGPU Target Machine (R600+)
29 //===----------------------------------------------------------------------===//
31 class AMDGPUTargetMachine : public LLVMTargetMachine {
35 std::unique_ptr<TargetLoweringObjectFile> TLOF;
36 AMDGPUSubtarget Subtarget;
37 AMDGPUIntrinsicInfo IntrinsicInfo;
40 AMDGPUTargetMachine(const Target &T, const Triple &TT, StringRef FS,
41 StringRef CPU, TargetOptions Options, Reloc::Model RM,
42 CodeModel::Model CM, CodeGenOpt::Level OL);
43 ~AMDGPUTargetMachine();
45 const AMDGPUSubtarget *getSubtargetImpl() const { return &Subtarget; }
46 const AMDGPUSubtarget *getSubtargetImpl(const Function &) const override {
49 const AMDGPUIntrinsicInfo *getIntrinsicInfo() const override {
50 return &IntrinsicInfo;
52 TargetIRAnalysis getTargetIRAnalysis() override;
54 TargetLoweringObjectFile *getObjFileLowering() const override {
59 //===----------------------------------------------------------------------===//
60 // R600 Target Machine (R600 -> Cayman)
61 //===----------------------------------------------------------------------===//
63 class R600TargetMachine : public AMDGPUTargetMachine {
66 R600TargetMachine(const Target &T, const Triple &TT, StringRef FS,
67 StringRef CPU, TargetOptions Options, Reloc::Model RM,
68 CodeModel::Model CM, CodeGenOpt::Level OL);
70 TargetPassConfig *createPassConfig(PassManagerBase &PM) override;
73 //===----------------------------------------------------------------------===//
74 // GCN Target Machine (SI+)
75 //===----------------------------------------------------------------------===//
77 class GCNTargetMachine : public AMDGPUTargetMachine {
80 GCNTargetMachine(const Target &T, const Triple &TT, StringRef FS,
81 StringRef CPU, TargetOptions Options, Reloc::Model RM,
82 CodeModel::Model CM, CodeGenOpt::Level OL);
84 TargetPassConfig *createPassConfig(PassManagerBase &PM) override;
87 } // End namespace llvm