1 //=====-- AMDGPUSubtarget.h - Define Subtarget for AMDGPU ------*- C++ -*-====//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //==-----------------------------------------------------------------------===//
11 /// \brief AMDGPU specific subclass of TargetSubtarget.
13 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPUSUBTARGET_H
16 #define LLVM_LIB_TARGET_AMDGPU_AMDGPUSUBTARGET_H
18 #include "AMDGPUFrameLowering.h"
19 #include "AMDGPUInstrInfo.h"
20 #include "AMDGPUIntrinsicInfo.h"
21 #include "AMDKernelCodeT.h"
22 #include "AMDGPUSubtarget.h"
23 #include "R600ISelLowering.h"
24 #include "SIFrameLowering.h"
25 #include "Utils/AMDGPUBaseInfo.h"
26 #include "llvm/ADT/StringExtras.h"
27 #include "llvm/ADT/StringRef.h"
28 #include "llvm/Target/TargetSubtargetInfo.h"
30 #define GET_SUBTARGETINFO_HEADER
31 #include "AMDGPUGenSubtargetInfo.inc"
35 class SIMachineFunctionInfo;
37 class AMDGPUSubtarget : public AMDGPUGenSubtargetInfo {
51 FIXED_SGPR_COUNT_FOR_INIT_BUG = 80
68 short TexVTXClauseSize;
75 bool FlatAddressSpace;
76 bool EnableIRStructurizer;
77 bool EnablePromoteAlloca;
79 bool EnableLoadStoreOpt;
80 bool EnableUnsafeDSOffsetFolding;
81 unsigned WavefrontSize;
84 bool EnableVGPRSpilling;
93 bool EnableHugeScratchBuffer;
95 std::unique_ptr<AMDGPUFrameLowering> FrameLowering;
96 std::unique_ptr<AMDGPUTargetLowering> TLInfo;
97 std::unique_ptr<AMDGPUInstrInfo> InstrInfo;
98 InstrItineraryData InstrItins;
102 AMDGPUSubtarget(const Triple &TT, StringRef CPU, StringRef FS,
104 AMDGPUSubtarget &initializeSubtargetDependencies(const Triple &TT,
105 StringRef GPU, StringRef FS);
107 const AMDGPUFrameLowering *getFrameLowering() const override {
108 return FrameLowering.get();
110 const AMDGPUInstrInfo *getInstrInfo() const override {
111 return InstrInfo.get();
113 const AMDGPURegisterInfo *getRegisterInfo() const override {
114 return &InstrInfo->getRegisterInfo();
116 AMDGPUTargetLowering *getTargetLowering() const override {
119 const InstrItineraryData *getInstrItineraryData() const override {
123 void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
125 bool is64bit() const {
129 bool hasVertexCache() const {
130 return HasVertexCache;
133 short getTexVTXClauseSize() const {
134 return TexVTXClauseSize;
137 Generation getGeneration() const {
141 bool hasHWFP64() const {
145 bool hasCaymanISA() const {
149 bool hasFP32Denormals() const {
150 return FP32Denormals;
153 bool hasFP64Denormals() const {
154 return FP64Denormals;
157 bool hasFastFMAF32() const {
161 bool hasFlatAddressSpace() const {
162 return FlatAddressSpace;
165 bool hasBFE() const {
166 return (getGeneration() >= EVERGREEN);
169 bool hasBFI() const {
170 return (getGeneration() >= EVERGREEN);
173 bool hasBFM() const {
177 bool hasBCNT(unsigned Size) const {
179 return (getGeneration() >= EVERGREEN);
182 return (getGeneration() >= SOUTHERN_ISLANDS);
187 bool hasMulU24() const {
188 return (getGeneration() >= EVERGREEN);
191 bool hasMulI24() const {
192 return (getGeneration() >= SOUTHERN_ISLANDS ||
196 bool hasFFBL() const {
197 return (getGeneration() >= EVERGREEN);
200 bool hasFFBH() const {
201 return (getGeneration() >= EVERGREEN);
204 bool hasCARRY() const {
205 return (getGeneration() >= EVERGREEN);
208 bool hasBORROW() const {
209 return (getGeneration() >= EVERGREEN);
212 bool IsIRStructurizerEnabled() const {
213 return EnableIRStructurizer;
216 bool isPromoteAllocaEnabled() const {
217 return EnablePromoteAlloca;
220 bool isIfCvtEnabled() const {
224 bool loadStoreOptEnabled() const {
225 return EnableLoadStoreOpt;
228 bool unsafeDSOffsetFoldingEnabled() const {
229 return EnableUnsafeDSOffsetFolding;
232 unsigned getWavefrontSize() const {
233 return WavefrontSize;
236 unsigned getStackEntrySize() const;
238 bool hasCFAluBug() const {
239 assert(getGeneration() <= NORTHERN_ISLANDS);
243 int getLocalMemorySize() const {
244 return LocalMemorySize;
247 bool hasSGPRInitBug() const {
251 int getLDSBankCount() const {
255 unsigned getAmdKernelCodeChipID() const;
257 AMDGPU::IsaVersion getIsaVersion() const;
259 bool enableMachineScheduler() const override {
263 void overrideSchedPolicy(MachineSchedPolicy &Policy,
264 MachineInstr *begin, MachineInstr *end,
265 unsigned NumRegionInstrs) const override;
267 // Helper functions to simplify if statements
268 bool isTargetELF() const {
272 StringRef getDeviceName() const {
276 bool enableHugeScratchBuffer() const {
277 return EnableHugeScratchBuffer;
280 bool dumpCode() const {
283 bool r600ALUEncoding() const {
286 bool isAmdHsaOS() const {
287 return TargetTriple.getOS() == Triple::AMDHSA;
289 bool isVGPRSpillingEnabled(const SIMachineFunctionInfo *MFI) const;
291 unsigned getMaxWavesPerCU() const {
292 if (getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
295 // FIXME: Not sure what this is for other subtagets.
296 llvm_unreachable("do not know max waves per CU for this subtarget.");
299 bool enableSubRegLiveness() const override {
303 /// \brief Returns the offset in bytes from the start of the input buffer
304 /// of the first explicit kernel argument.
305 unsigned getExplicitKernelArgOffset() const {
306 return isAmdHsaOS() ? 0 : 36;
311 } // End namespace llvm