1 //===-- AMDGPUSubtarget.cpp - AMDGPU Subtarget Information ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// \brief Implements the AMDGPU specific subclass of TargetSubtarget.
13 //===----------------------------------------------------------------------===//
15 #include "AMDGPUSubtarget.h"
16 #include "R600ISelLowering.h"
17 #include "R600InstrInfo.h"
18 #include "R600MachineScheduler.h"
19 #include "SIISelLowering.h"
20 #include "SIInstrInfo.h"
21 #include "SIMachineFunctionInfo.h"
22 #include "llvm/ADT/SmallString.h"
23 #include "llvm/CodeGen/MachineScheduler.h"
27 #define DEBUG_TYPE "amdgpu-subtarget"
29 #define GET_SUBTARGETINFO_ENUM
30 #define GET_SUBTARGETINFO_TARGET_DESC
31 #define GET_SUBTARGETINFO_CTOR
32 #include "AMDGPUGenSubtargetInfo.inc"
35 AMDGPUSubtarget::initializeSubtargetDependencies(const Triple &TT,
36 StringRef GPU, StringRef FS) {
37 // Determine default and user-specified characteristics
38 // On SI+, we want FP64 denormals to be on by default. FP32 denormals can be
39 // enabled, but some instructions do not respect them and they run at the
40 // double precision rate, so don't enable by default.
42 // We want to be able to turn these off, but making this a subtarget feature
43 // for SI has the unhelpful behavior that it unsets everything else if you
46 SmallString<256> FullFS("+promote-alloca,+fp64-denormals,");
49 if (GPU == "" && TT.getArch() == Triple::amdgcn)
52 ParseSubtargetFeatures(GPU, FullFS);
54 // FIXME: I don't think think Evergreen has any useful support for
55 // denormals, but should be checked. Should we issue a warning somewhere
56 // if someone tries to enable these?
57 if (getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS) {
58 FP32Denormals = false;
59 FP64Denormals = false;
64 AMDGPUSubtarget::AMDGPUSubtarget(const Triple &TT, StringRef GPU, StringRef FS,
66 : AMDGPUGenSubtargetInfo(TT, GPU, FS), DevName(GPU), Is64bit(false),
67 DumpCode(false), R600ALUInst(false), HasVertexCache(false),
68 TexVTXClauseSize(0), Gen(AMDGPUSubtarget::R600), FP64(false),
69 FP64Denormals(false), FP32Denormals(false), FastFMAF32(false),
70 CaymanISA(false), FlatAddressSpace(false), EnableIRStructurizer(true),
71 EnablePromoteAlloca(false), EnableIfCvt(true), EnableLoadStoreOpt(false),
72 EnableUnsafeDSOffsetFolding(false),
73 WavefrontSize(0), CFALUBug(false), LocalMemorySize(0),
74 EnableVGPRSpilling(false), SGPRInitBug(false), IsGCN(false),
75 GCN1Encoding(false), GCN3Encoding(false), CIInsts(false), LDSBankCount(0),
76 IsaVersion(ISAVersion0_0_0), EnableHugeScratchBuffer(false),
77 FrameLowering(nullptr),
78 InstrItins(getInstrItineraryForCPU(GPU)), TargetTriple(TT) {
80 initializeSubtargetDependencies(TT, GPU, FS);
82 const unsigned MaxStackAlign = 64 * 16; // Maximum stack alignment (long16)
84 if (getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS) {
85 InstrInfo.reset(new R600InstrInfo(*this));
86 TLInfo.reset(new R600TargetLowering(TM, *this));
88 // FIXME: Should have R600 specific FrameLowering
89 FrameLowering.reset(new AMDGPUFrameLowering(
90 TargetFrameLowering::StackGrowsUp,
94 InstrInfo.reset(new SIInstrInfo(*this));
95 TLInfo.reset(new SITargetLowering(TM, *this));
96 FrameLowering.reset(new SIFrameLowering(
97 TargetFrameLowering::StackGrowsUp,
103 unsigned AMDGPUSubtarget::getStackEntrySize() const {
104 assert(getGeneration() <= NORTHERN_ISLANDS);
105 switch(getWavefrontSize()) {
109 return hasCaymanISA() ? 4 : 8;
113 llvm_unreachable("Illegal wavefront size.");
117 unsigned AMDGPUSubtarget::getAmdKernelCodeChipID() const {
118 switch(getGeneration()) {
119 default: llvm_unreachable("ChipID unknown");
120 case SEA_ISLANDS: return 12;
124 AMDGPU::IsaVersion AMDGPUSubtarget::getIsaVersion() const {
125 return AMDGPU::getIsaVersion(getFeatureBits());
128 bool AMDGPUSubtarget::isVGPRSpillingEnabled(
129 const SIMachineFunctionInfo *MFI) const {
130 return MFI->getShaderType() == ShaderType::COMPUTE || EnableVGPRSpilling;
133 void AMDGPUSubtarget::overrideSchedPolicy(MachineSchedPolicy &Policy,
136 unsigned NumRegionInstrs) const {
137 if (getGeneration() >= SOUTHERN_ISLANDS) {
139 // Track register pressure so the scheduler can try to decrease
140 // pressure once register usage is above the threshold defined by
141 // SIRegisterInfo::getRegPressureSetLimit()
142 Policy.ShouldTrackPressure = true;
144 // Enabling both top down and bottom up scheduling seems to give us less
145 // register spills than just using one of these approaches on its own.
146 Policy.OnlyTopDown = false;
147 Policy.OnlyBottomUp = false;