1 //===-- AMDGPUISelLowering.cpp - AMDGPU Common DAG lowering functions -----===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// \brief This is the parent TargetLowering class for hardware code gen
14 //===----------------------------------------------------------------------===//
16 #include "AMDGPUISelLowering.h"
18 #include "AMDGPUFrameLowering.h"
19 #include "AMDGPUIntrinsicInfo.h"
20 #include "AMDGPURegisterInfo.h"
21 #include "AMDGPUSubtarget.h"
22 #include "R600MachineFunctionInfo.h"
23 #include "SIMachineFunctionInfo.h"
24 #include "llvm/CodeGen/CallingConvLower.h"
25 #include "llvm/CodeGen/MachineFunction.h"
26 #include "llvm/CodeGen/MachineRegisterInfo.h"
27 #include "llvm/CodeGen/SelectionDAG.h"
28 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
29 #include "llvm/IR/DataLayout.h"
30 #include "llvm/IR/DiagnosticInfo.h"
31 #include "llvm/IR/DiagnosticPrinter.h"
37 /// Diagnostic information for unimplemented or unsupported feature reporting.
38 class DiagnosticInfoUnsupported : public DiagnosticInfo {
40 const Twine &Description;
45 static int getKindID() {
47 KindID = llvm::getNextAvailablePluginDiagnosticKind();
52 DiagnosticInfoUnsupported(const Function &Fn, const Twine &Desc,
53 DiagnosticSeverity Severity = DS_Error)
54 : DiagnosticInfo(getKindID(), Severity),
58 const Function &getFunction() const { return Fn; }
59 const Twine &getDescription() const { return Description; }
61 void print(DiagnosticPrinter &DP) const override {
62 DP << "unsupported " << getDescription() << " in " << Fn.getName();
65 static bool classof(const DiagnosticInfo *DI) {
66 return DI->getKind() == getKindID();
70 int DiagnosticInfoUnsupported::KindID = 0;
74 static bool allocateStack(unsigned ValNo, MVT ValVT, MVT LocVT,
75 CCValAssign::LocInfo LocInfo,
76 ISD::ArgFlagsTy ArgFlags, CCState &State) {
77 unsigned Offset = State.AllocateStack(ValVT.getStoreSize(),
78 ArgFlags.getOrigAlign());
79 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
84 #include "AMDGPUGenCallingConv.inc"
86 // Find a larger type to do a load / store of a vector with.
87 EVT AMDGPUTargetLowering::getEquivalentMemType(LLVMContext &Ctx, EVT VT) {
88 unsigned StoreSize = VT.getStoreSizeInBits();
90 return EVT::getIntegerVT(Ctx, StoreSize);
92 assert(StoreSize % 32 == 0 && "Store size not a multiple of 32");
93 return EVT::getVectorVT(Ctx, MVT::i32, StoreSize / 32);
96 // Type for a vector that will be loaded to.
97 EVT AMDGPUTargetLowering::getEquivalentLoadRegType(LLVMContext &Ctx, EVT VT) {
98 unsigned StoreSize = VT.getStoreSizeInBits();
100 return EVT::getIntegerVT(Ctx, 32);
102 return EVT::getVectorVT(Ctx, MVT::i32, StoreSize / 32);
105 AMDGPUTargetLowering::AMDGPUTargetLowering(TargetMachine &TM,
106 const AMDGPUSubtarget &STI)
107 : TargetLowering(TM), Subtarget(&STI) {
108 setOperationAction(ISD::Constant, MVT::i32, Legal);
109 setOperationAction(ISD::Constant, MVT::i64, Legal);
110 setOperationAction(ISD::ConstantFP, MVT::f32, Legal);
111 setOperationAction(ISD::ConstantFP, MVT::f64, Legal);
113 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
114 setOperationAction(ISD::BRIND, MVT::Other, Expand);
116 // We need to custom lower some of the intrinsics
117 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
119 // Library functions. These default to Expand, but we have instructions
121 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
122 setOperationAction(ISD::FEXP2, MVT::f32, Legal);
123 setOperationAction(ISD::FPOW, MVT::f32, Legal);
124 setOperationAction(ISD::FLOG2, MVT::f32, Legal);
125 setOperationAction(ISD::FABS, MVT::f32, Legal);
126 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
127 setOperationAction(ISD::FRINT, MVT::f32, Legal);
128 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
129 setOperationAction(ISD::FMINNUM, MVT::f32, Legal);
130 setOperationAction(ISD::FMAXNUM, MVT::f32, Legal);
132 setOperationAction(ISD::FROUND, MVT::f32, Custom);
133 setOperationAction(ISD::FROUND, MVT::f64, Custom);
135 setOperationAction(ISD::FREM, MVT::f32, Custom);
136 setOperationAction(ISD::FREM, MVT::f64, Custom);
138 // v_mad_f32 does not support denormals according to some sources.
139 if (!Subtarget->hasFP32Denormals())
140 setOperationAction(ISD::FMAD, MVT::f32, Legal);
142 // Expand to fneg + fadd.
143 setOperationAction(ISD::FSUB, MVT::f64, Expand);
145 // Lower floating point store/load to integer store/load to reduce the number
146 // of patterns in tablegen.
147 setOperationAction(ISD::STORE, MVT::f32, Promote);
148 AddPromotedToType(ISD::STORE, MVT::f32, MVT::i32);
150 setOperationAction(ISD::STORE, MVT::v2f32, Promote);
151 AddPromotedToType(ISD::STORE, MVT::v2f32, MVT::v2i32);
153 setOperationAction(ISD::STORE, MVT::v4f32, Promote);
154 AddPromotedToType(ISD::STORE, MVT::v4f32, MVT::v4i32);
156 setOperationAction(ISD::STORE, MVT::v8f32, Promote);
157 AddPromotedToType(ISD::STORE, MVT::v8f32, MVT::v8i32);
159 setOperationAction(ISD::STORE, MVT::v16f32, Promote);
160 AddPromotedToType(ISD::STORE, MVT::v16f32, MVT::v16i32);
162 setOperationAction(ISD::STORE, MVT::f64, Promote);
163 AddPromotedToType(ISD::STORE, MVT::f64, MVT::i64);
165 setOperationAction(ISD::STORE, MVT::v2f64, Promote);
166 AddPromotedToType(ISD::STORE, MVT::v2f64, MVT::v2i64);
168 // Custom lowering of vector stores is required for local address space
170 setOperationAction(ISD::STORE, MVT::v4i32, Custom);
172 setTruncStoreAction(MVT::v2i32, MVT::v2i16, Custom);
173 setTruncStoreAction(MVT::v2i32, MVT::v2i8, Custom);
174 setTruncStoreAction(MVT::v4i32, MVT::v4i8, Custom);
176 // XXX: This can be change to Custom, once ExpandVectorStores can
177 // handle 64-bit stores.
178 setTruncStoreAction(MVT::v4i32, MVT::v4i16, Expand);
180 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
181 setTruncStoreAction(MVT::i64, MVT::i8, Expand);
182 setTruncStoreAction(MVT::i64, MVT::i1, Expand);
183 setTruncStoreAction(MVT::v2i64, MVT::v2i1, Expand);
184 setTruncStoreAction(MVT::v4i64, MVT::v4i1, Expand);
187 setOperationAction(ISD::LOAD, MVT::f32, Promote);
188 AddPromotedToType(ISD::LOAD, MVT::f32, MVT::i32);
190 setOperationAction(ISD::LOAD, MVT::v2f32, Promote);
191 AddPromotedToType(ISD::LOAD, MVT::v2f32, MVT::v2i32);
193 setOperationAction(ISD::LOAD, MVT::v4f32, Promote);
194 AddPromotedToType(ISD::LOAD, MVT::v4f32, MVT::v4i32);
196 setOperationAction(ISD::LOAD, MVT::v8f32, Promote);
197 AddPromotedToType(ISD::LOAD, MVT::v8f32, MVT::v8i32);
199 setOperationAction(ISD::LOAD, MVT::v16f32, Promote);
200 AddPromotedToType(ISD::LOAD, MVT::v16f32, MVT::v16i32);
202 setOperationAction(ISD::LOAD, MVT::f64, Promote);
203 AddPromotedToType(ISD::LOAD, MVT::f64, MVT::i64);
205 setOperationAction(ISD::LOAD, MVT::v2f64, Promote);
206 AddPromotedToType(ISD::LOAD, MVT::v2f64, MVT::v2i64);
208 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i32, Custom);
209 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4f32, Custom);
210 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i32, Custom);
211 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8f32, Custom);
212 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v2f32, Custom);
213 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v2i32, Custom);
214 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v4f32, Custom);
215 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v4i32, Custom);
216 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v8f32, Custom);
217 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v8i32, Custom);
219 // There are no 64-bit extloads. These should be done as a 32-bit extload and
220 // an extension to 64-bit.
221 for (MVT VT : MVT::integer_valuetypes()) {
222 setLoadExtAction(ISD::EXTLOAD, MVT::i64, VT, Expand);
223 setLoadExtAction(ISD::SEXTLOAD, MVT::i64, VT, Expand);
224 setLoadExtAction(ISD::ZEXTLOAD, MVT::i64, VT, Expand);
227 for (MVT VT : MVT::integer_vector_valuetypes()) {
228 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2i8, Expand);
229 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v2i8, Expand);
230 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::v2i8, Expand);
231 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v4i8, Expand);
232 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v4i8, Expand);
233 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::v4i8, Expand);
234 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2i16, Expand);
235 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v2i16, Expand);
236 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::v2i16, Expand);
237 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v4i16, Expand);
238 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v4i16, Expand);
239 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::v4i16, Expand);
242 setOperationAction(ISD::BR_CC, MVT::i1, Expand);
244 if (Subtarget->getGeneration() < AMDGPUSubtarget::SEA_ISLANDS) {
245 setOperationAction(ISD::FCEIL, MVT::f64, Custom);
246 setOperationAction(ISD::FTRUNC, MVT::f64, Custom);
247 setOperationAction(ISD::FRINT, MVT::f64, Custom);
248 setOperationAction(ISD::FFLOOR, MVT::f64, Custom);
251 if (!Subtarget->hasBFI()) {
252 // fcopysign can be done in a single instruction with BFI.
253 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
254 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
257 setOperationAction(ISD::FP16_TO_FP, MVT::f64, Expand);
259 setLoadExtAction(ISD::EXTLOAD, MVT::f32, MVT::f16, Expand);
260 setLoadExtAction(ISD::EXTLOAD, MVT::v2f32, MVT::v2f16, Expand);
261 setLoadExtAction(ISD::EXTLOAD, MVT::v4f32, MVT::v4f16, Expand);
262 setLoadExtAction(ISD::EXTLOAD, MVT::v8f32, MVT::v8f16, Expand);
264 setLoadExtAction(ISD::EXTLOAD, MVT::f64, MVT::f16, Expand);
265 setLoadExtAction(ISD::EXTLOAD, MVT::v2f64, MVT::v2f16, Expand);
266 setLoadExtAction(ISD::EXTLOAD, MVT::v4f64, MVT::v4f16, Expand);
267 setLoadExtAction(ISD::EXTLOAD, MVT::v8f64, MVT::v8f16, Expand);
269 setTruncStoreAction(MVT::f32, MVT::f16, Expand);
270 setTruncStoreAction(MVT::v2f32, MVT::v2f16, Expand);
271 setTruncStoreAction(MVT::v4f32, MVT::v4f16, Expand);
272 setTruncStoreAction(MVT::v8f32, MVT::v8f16, Expand);
274 setTruncStoreAction(MVT::f64, MVT::f16, Expand);
275 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
277 const MVT ScalarIntVTs[] = { MVT::i32, MVT::i64 };
278 for (MVT VT : ScalarIntVTs) {
279 setOperationAction(ISD::SREM, VT, Expand);
280 setOperationAction(ISD::SDIV, VT, Expand);
282 // GPU does not have divrem function for signed or unsigned.
283 setOperationAction(ISD::SDIVREM, VT, Custom);
284 setOperationAction(ISD::UDIVREM, VT, Custom);
286 // GPU does not have [S|U]MUL_LOHI functions as a single instruction.
287 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
288 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
290 setOperationAction(ISD::BSWAP, VT, Expand);
291 setOperationAction(ISD::CTTZ, VT, Expand);
292 setOperationAction(ISD::CTLZ, VT, Expand);
295 if (!Subtarget->hasBCNT(32))
296 setOperationAction(ISD::CTPOP, MVT::i32, Expand);
298 if (!Subtarget->hasBCNT(64))
299 setOperationAction(ISD::CTPOP, MVT::i64, Expand);
301 // The hardware supports 32-bit ROTR, but not ROTL.
302 setOperationAction(ISD::ROTL, MVT::i32, Expand);
303 setOperationAction(ISD::ROTL, MVT::i64, Expand);
304 setOperationAction(ISD::ROTR, MVT::i64, Expand);
306 setOperationAction(ISD::MUL, MVT::i64, Expand);
307 setOperationAction(ISD::MULHU, MVT::i64, Expand);
308 setOperationAction(ISD::MULHS, MVT::i64, Expand);
309 setOperationAction(ISD::UDIV, MVT::i32, Expand);
310 setOperationAction(ISD::UREM, MVT::i32, Expand);
311 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Custom);
312 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
313 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
314 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Custom);
315 setOperationAction(ISD::SELECT_CC, MVT::i64, Expand);
317 setOperationAction(ISD::SMIN, MVT::i32, Legal);
318 setOperationAction(ISD::UMIN, MVT::i32, Legal);
319 setOperationAction(ISD::SMAX, MVT::i32, Legal);
320 setOperationAction(ISD::UMAX, MVT::i32, Legal);
322 if (!Subtarget->hasFFBH())
323 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, Expand);
325 if (!Subtarget->hasFFBL())
326 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32, Expand);
328 static const MVT::SimpleValueType VectorIntTypes[] = {
329 MVT::v2i32, MVT::v4i32
332 for (MVT VT : VectorIntTypes) {
333 // Expand the following operations for the current type by default.
334 setOperationAction(ISD::ADD, VT, Expand);
335 setOperationAction(ISD::AND, VT, Expand);
336 setOperationAction(ISD::FP_TO_SINT, VT, Expand);
337 setOperationAction(ISD::FP_TO_UINT, VT, Expand);
338 setOperationAction(ISD::MUL, VT, Expand);
339 setOperationAction(ISD::OR, VT, Expand);
340 setOperationAction(ISD::SHL, VT, Expand);
341 setOperationAction(ISD::SRA, VT, Expand);
342 setOperationAction(ISD::SRL, VT, Expand);
343 setOperationAction(ISD::ROTL, VT, Expand);
344 setOperationAction(ISD::ROTR, VT, Expand);
345 setOperationAction(ISD::SUB, VT, Expand);
346 setOperationAction(ISD::SINT_TO_FP, VT, Expand);
347 setOperationAction(ISD::UINT_TO_FP, VT, Expand);
348 setOperationAction(ISD::SDIV, VT, Expand);
349 setOperationAction(ISD::UDIV, VT, Expand);
350 setOperationAction(ISD::SREM, VT, Expand);
351 setOperationAction(ISD::UREM, VT, Expand);
352 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
353 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
354 setOperationAction(ISD::SDIVREM, VT, Custom);
355 setOperationAction(ISD::UDIVREM, VT, Custom);
356 setOperationAction(ISD::ADDC, VT, Expand);
357 setOperationAction(ISD::SUBC, VT, Expand);
358 setOperationAction(ISD::ADDE, VT, Expand);
359 setOperationAction(ISD::SUBE, VT, Expand);
360 setOperationAction(ISD::SELECT, VT, Expand);
361 setOperationAction(ISD::VSELECT, VT, Expand);
362 setOperationAction(ISD::SELECT_CC, VT, Expand);
363 setOperationAction(ISD::XOR, VT, Expand);
364 setOperationAction(ISD::BSWAP, VT, Expand);
365 setOperationAction(ISD::CTPOP, VT, Expand);
366 setOperationAction(ISD::CTTZ, VT, Expand);
367 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand);
368 setOperationAction(ISD::CTLZ, VT, Expand);
369 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand);
370 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Expand);
373 static const MVT::SimpleValueType FloatVectorTypes[] = {
374 MVT::v2f32, MVT::v4f32
377 for (MVT VT : FloatVectorTypes) {
378 setOperationAction(ISD::FABS, VT, Expand);
379 setOperationAction(ISD::FMINNUM, VT, Expand);
380 setOperationAction(ISD::FMAXNUM, VT, Expand);
381 setOperationAction(ISD::FADD, VT, Expand);
382 setOperationAction(ISD::FCEIL, VT, Expand);
383 setOperationAction(ISD::FCOS, VT, Expand);
384 setOperationAction(ISD::FDIV, VT, Expand);
385 setOperationAction(ISD::FEXP2, VT, Expand);
386 setOperationAction(ISD::FLOG2, VT, Expand);
387 setOperationAction(ISD::FREM, VT, Expand);
388 setOperationAction(ISD::FPOW, VT, Expand);
389 setOperationAction(ISD::FFLOOR, VT, Expand);
390 setOperationAction(ISD::FTRUNC, VT, Expand);
391 setOperationAction(ISD::FMUL, VT, Expand);
392 setOperationAction(ISD::FMA, VT, Expand);
393 setOperationAction(ISD::FRINT, VT, Expand);
394 setOperationAction(ISD::FNEARBYINT, VT, Expand);
395 setOperationAction(ISD::FSQRT, VT, Expand);
396 setOperationAction(ISD::FSIN, VT, Expand);
397 setOperationAction(ISD::FSUB, VT, Expand);
398 setOperationAction(ISD::FNEG, VT, Expand);
399 setOperationAction(ISD::SELECT, VT, Expand);
400 setOperationAction(ISD::VSELECT, VT, Expand);
401 setOperationAction(ISD::SELECT_CC, VT, Expand);
402 setOperationAction(ISD::FCOPYSIGN, VT, Expand);
403 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Expand);
406 setOperationAction(ISD::FNEARBYINT, MVT::f32, Custom);
407 setOperationAction(ISD::FNEARBYINT, MVT::f64, Custom);
409 setTargetDAGCombine(ISD::SHL);
410 setTargetDAGCombine(ISD::MUL);
411 setTargetDAGCombine(ISD::SELECT);
412 setTargetDAGCombine(ISD::SELECT_CC);
413 setTargetDAGCombine(ISD::STORE);
415 setTargetDAGCombine(ISD::FADD);
416 setTargetDAGCombine(ISD::FSUB);
418 setBooleanContents(ZeroOrNegativeOneBooleanContent);
419 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
421 setSchedulingPreference(Sched::RegPressure);
422 setJumpIsExpensive(true);
424 // SI at least has hardware support for floating point exceptions, but no way
425 // of using or handling them is implemented. They are also optional in OpenCL
427 setHasFloatingPointExceptions(false);
429 setSelectIsExpensive(false);
430 PredictableSelectIsExpensive = false;
432 setFsqrtIsCheap(true);
434 // FIXME: Need to really handle these.
435 MaxStoresPerMemcpy = 4096;
436 MaxStoresPerMemmove = 4096;
437 MaxStoresPerMemset = 4096;
440 //===----------------------------------------------------------------------===//
441 // Target Information
442 //===----------------------------------------------------------------------===//
444 MVT AMDGPUTargetLowering::getVectorIdxTy(const DataLayout &) const {
448 bool AMDGPUTargetLowering::isSelectSupported(SelectSupportKind SelType) const {
452 // The backend supports 32 and 64 bit floating point immediates.
453 // FIXME: Why are we reporting vectors of FP immediates as legal?
454 bool AMDGPUTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
455 EVT ScalarVT = VT.getScalarType();
456 return (ScalarVT == MVT::f32 || ScalarVT == MVT::f64);
459 // We don't want to shrink f64 / f32 constants.
460 bool AMDGPUTargetLowering::ShouldShrinkFPConstant(EVT VT) const {
461 EVT ScalarVT = VT.getScalarType();
462 return (ScalarVT != MVT::f32 && ScalarVT != MVT::f64);
465 bool AMDGPUTargetLowering::shouldReduceLoadWidth(SDNode *N,
469 unsigned NewSize = NewVT.getStoreSizeInBits();
471 // If we are reducing to a 32-bit load, this is always better.
475 EVT OldVT = N->getValueType(0);
476 unsigned OldSize = OldVT.getStoreSizeInBits();
478 // Don't produce extloads from sub 32-bit types. SI doesn't have scalar
479 // extloads, so doing one requires using a buffer_load. In cases where we
480 // still couldn't use a scalar load, using the wider load shouldn't really
483 // If the old size already had to be an extload, there's no harm in continuing
484 // to reduce the width.
485 return (OldSize < 32);
488 bool AMDGPUTargetLowering::isLoadBitCastBeneficial(EVT LoadTy,
490 if (LoadTy.getSizeInBits() != CastTy.getSizeInBits())
493 unsigned LScalarSize = LoadTy.getScalarType().getSizeInBits();
494 unsigned CastScalarSize = CastTy.getScalarType().getSizeInBits();
496 return ((LScalarSize <= CastScalarSize) ||
497 (CastScalarSize >= 32) ||
501 // SI+ has instructions for cttz / ctlz for 32-bit values. This is probably also
502 // profitable with the expansion for 64-bit since it's generally good to
504 // FIXME: These should really have the size as a parameter.
505 bool AMDGPUTargetLowering::isCheapToSpeculateCttz() const {
509 bool AMDGPUTargetLowering::isCheapToSpeculateCtlz() const {
513 //===---------------------------------------------------------------------===//
515 //===---------------------------------------------------------------------===//
517 bool AMDGPUTargetLowering::isFAbsFree(EVT VT) const {
518 assert(VT.isFloatingPoint());
519 return VT == MVT::f32 || VT == MVT::f64;
522 bool AMDGPUTargetLowering::isFNegFree(EVT VT) const {
523 assert(VT.isFloatingPoint());
524 return VT == MVT::f32 || VT == MVT::f64;
527 bool AMDGPUTargetLowering:: storeOfVectorConstantIsCheap(EVT MemVT,
533 bool AMDGPUTargetLowering::isTruncateFree(EVT Source, EVT Dest) const {
534 // Truncate is just accessing a subregister.
535 return Dest.bitsLT(Source) && (Dest.getSizeInBits() % 32 == 0);
538 bool AMDGPUTargetLowering::isTruncateFree(Type *Source, Type *Dest) const {
539 // Truncate is just accessing a subregister.
540 return Dest->getPrimitiveSizeInBits() < Source->getPrimitiveSizeInBits() &&
541 (Dest->getPrimitiveSizeInBits() % 32 == 0);
544 bool AMDGPUTargetLowering::isZExtFree(Type *Src, Type *Dest) const {
545 unsigned SrcSize = Src->getScalarSizeInBits();
546 unsigned DestSize = Dest->getScalarSizeInBits();
548 return SrcSize == 32 && DestSize == 64;
551 bool AMDGPUTargetLowering::isZExtFree(EVT Src, EVT Dest) const {
552 // Any register load of a 64-bit value really requires 2 32-bit moves. For all
553 // practical purposes, the extra mov 0 to load a 64-bit is free. As used,
554 // this will enable reducing 64-bit operations the 32-bit, which is always
556 return Src == MVT::i32 && Dest == MVT::i64;
559 bool AMDGPUTargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
560 return isZExtFree(Val.getValueType(), VT2);
563 bool AMDGPUTargetLowering::isNarrowingProfitable(EVT SrcVT, EVT DestVT) const {
564 // There aren't really 64-bit registers, but pairs of 32-bit ones and only a
565 // limited number of native 64-bit operations. Shrinking an operation to fit
566 // in a single 32-bit register should always be helpful. As currently used,
567 // this is much less general than the name suggests, and is only used in
568 // places trying to reduce the sizes of loads. Shrinking loads to < 32-bits is
569 // not profitable, and may actually be harmful.
570 return SrcVT.getSizeInBits() > 32 && DestVT.getSizeInBits() == 32;
573 //===---------------------------------------------------------------------===//
574 // TargetLowering Callbacks
575 //===---------------------------------------------------------------------===//
577 void AMDGPUTargetLowering::AnalyzeFormalArguments(CCState &State,
578 const SmallVectorImpl<ISD::InputArg> &Ins) const {
580 State.AnalyzeFormalArguments(Ins, CC_AMDGPU);
583 SDValue AMDGPUTargetLowering::LowerReturn(
585 CallingConv::ID CallConv,
587 const SmallVectorImpl<ISD::OutputArg> &Outs,
588 const SmallVectorImpl<SDValue> &OutVals,
589 SDLoc DL, SelectionDAG &DAG) const {
590 return DAG.getNode(AMDGPUISD::RET_FLAG, DL, MVT::Other, Chain);
593 //===---------------------------------------------------------------------===//
594 // Target specific lowering
595 //===---------------------------------------------------------------------===//
597 SDValue AMDGPUTargetLowering::LowerCall(CallLoweringInfo &CLI,
598 SmallVectorImpl<SDValue> &InVals) const {
599 SDValue Callee = CLI.Callee;
600 SelectionDAG &DAG = CLI.DAG;
602 const Function &Fn = *DAG.getMachineFunction().getFunction();
604 StringRef FuncName("<unknown>");
606 if (const ExternalSymbolSDNode *G = dyn_cast<ExternalSymbolSDNode>(Callee))
607 FuncName = G->getSymbol();
608 else if (const GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
609 FuncName = G->getGlobal()->getName();
611 DiagnosticInfoUnsupported NoCalls(Fn, "call to function " + FuncName);
612 DAG.getContext()->diagnose(NoCalls);
616 SDValue AMDGPUTargetLowering::LowerOperation(SDValue Op,
617 SelectionDAG &DAG) const {
618 switch (Op.getOpcode()) {
620 Op.getNode()->dump();
621 llvm_unreachable("Custom lowering code for this"
622 "instruction is not implemented yet!");
624 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op, DAG);
625 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
626 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op, DAG);
627 case ISD::FrameIndex: return LowerFrameIndex(Op, DAG);
628 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
629 case ISD::UDIVREM: return LowerUDIVREM(Op, DAG);
630 case ISD::SDIVREM: return LowerSDIVREM(Op, DAG);
631 case ISD::FREM: return LowerFREM(Op, DAG);
632 case ISD::FCEIL: return LowerFCEIL(Op, DAG);
633 case ISD::FTRUNC: return LowerFTRUNC(Op, DAG);
634 case ISD::FRINT: return LowerFRINT(Op, DAG);
635 case ISD::FNEARBYINT: return LowerFNEARBYINT(Op, DAG);
636 case ISD::FROUND: return LowerFROUND(Op, DAG);
637 case ISD::FFLOOR: return LowerFFLOOR(Op, DAG);
638 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
639 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
640 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
641 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG);
646 void AMDGPUTargetLowering::ReplaceNodeResults(SDNode *N,
647 SmallVectorImpl<SDValue> &Results,
648 SelectionDAG &DAG) const {
649 switch (N->getOpcode()) {
650 case ISD::SIGN_EXTEND_INREG:
651 // Different parts of legalization seem to interpret which type of
652 // sign_extend_inreg is the one to check for custom lowering. The extended
653 // from type is what really matters, but some places check for custom
654 // lowering of the result type. This results in trying to use
655 // ReplaceNodeResults to sext_in_reg to an illegal type, so we'll just do
656 // nothing here and let the illegal result integer be handled normally.
659 SDNode *Node = LowerLOAD(SDValue(N, 0), DAG).getNode();
663 Results.push_back(SDValue(Node, 0));
664 Results.push_back(SDValue(Node, 1));
665 // XXX: LLVM seems not to replace Chain Value inside CustomWidenLowerNode
667 DAG.ReplaceAllUsesOfValueWith(SDValue(N,1), SDValue(Node, 1));
671 SDValue Lowered = LowerSTORE(SDValue(N, 0), DAG);
672 if (Lowered.getNode())
673 Results.push_back(Lowered);
681 // FIXME: This implements accesses to initialized globals in the constant
682 // address space by copying them to private and accessing that. It does not
683 // properly handle illegal types or vectors. The private vector loads are not
684 // scalarized, and the illegal scalars hit an assertion. This technique will not
685 // work well with large initializers, and this should eventually be
686 // removed. Initialized globals should be placed into a data section that the
687 // runtime will load into a buffer before the kernel is executed. Uses of the
688 // global need to be replaced with a pointer loaded from an implicit kernel
689 // argument into this buffer holding the copy of the data, which will remove the
690 // need for any of this.
691 SDValue AMDGPUTargetLowering::LowerConstantInitializer(const Constant* Init,
692 const GlobalValue *GV,
693 const SDValue &InitPtr,
695 SelectionDAG &DAG) const {
696 const DataLayout &TD = DAG.getDataLayout();
698 Type *InitTy = Init->getType();
700 if (const ConstantInt *CI = dyn_cast<ConstantInt>(Init)) {
701 EVT VT = EVT::getEVT(InitTy);
702 PointerType *PtrTy = PointerType::get(InitTy, AMDGPUAS::PRIVATE_ADDRESS);
703 return DAG.getStore(Chain, DL, DAG.getConstant(*CI, DL, VT), InitPtr,
704 MachinePointerInfo(UndefValue::get(PtrTy)), false,
705 false, TD.getPrefTypeAlignment(InitTy));
708 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(Init)) {
709 EVT VT = EVT::getEVT(CFP->getType());
710 PointerType *PtrTy = PointerType::get(CFP->getType(), 0);
711 return DAG.getStore(Chain, DL, DAG.getConstantFP(*CFP, DL, VT), InitPtr,
712 MachinePointerInfo(UndefValue::get(PtrTy)), false,
713 false, TD.getPrefTypeAlignment(CFP->getType()));
716 if (StructType *ST = dyn_cast<StructType>(InitTy)) {
717 const StructLayout *SL = TD.getStructLayout(ST);
719 EVT PtrVT = InitPtr.getValueType();
720 SmallVector<SDValue, 8> Chains;
722 for (unsigned I = 0, N = ST->getNumElements(); I != N; ++I) {
723 SDValue Offset = DAG.getConstant(SL->getElementOffset(I), DL, PtrVT);
724 SDValue Ptr = DAG.getNode(ISD::ADD, DL, PtrVT, InitPtr, Offset);
726 Constant *Elt = Init->getAggregateElement(I);
727 Chains.push_back(LowerConstantInitializer(Elt, GV, Ptr, Chain, DAG));
730 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Chains);
733 if (SequentialType *SeqTy = dyn_cast<SequentialType>(InitTy)) {
734 EVT PtrVT = InitPtr.getValueType();
736 unsigned NumElements;
737 if (ArrayType *AT = dyn_cast<ArrayType>(SeqTy))
738 NumElements = AT->getNumElements();
739 else if (VectorType *VT = dyn_cast<VectorType>(SeqTy))
740 NumElements = VT->getNumElements();
742 llvm_unreachable("Unexpected type");
744 unsigned EltSize = TD.getTypeAllocSize(SeqTy->getElementType());
745 SmallVector<SDValue, 8> Chains;
746 for (unsigned i = 0; i < NumElements; ++i) {
747 SDValue Offset = DAG.getConstant(i * EltSize, DL, PtrVT);
748 SDValue Ptr = DAG.getNode(ISD::ADD, DL, PtrVT, InitPtr, Offset);
750 Constant *Elt = Init->getAggregateElement(i);
751 Chains.push_back(LowerConstantInitializer(Elt, GV, Ptr, Chain, DAG));
754 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Chains);
757 if (isa<UndefValue>(Init)) {
758 EVT VT = EVT::getEVT(InitTy);
759 PointerType *PtrTy = PointerType::get(InitTy, AMDGPUAS::PRIVATE_ADDRESS);
760 return DAG.getStore(Chain, DL, DAG.getUNDEF(VT), InitPtr,
761 MachinePointerInfo(UndefValue::get(PtrTy)), false,
762 false, TD.getPrefTypeAlignment(InitTy));
766 llvm_unreachable("Unhandled constant initializer");
769 static bool hasDefinedInitializer(const GlobalValue *GV) {
770 const GlobalVariable *GVar = dyn_cast<GlobalVariable>(GV);
771 if (!GVar || !GVar->hasInitializer())
774 if (isa<UndefValue>(GVar->getInitializer()))
780 SDValue AMDGPUTargetLowering::LowerGlobalAddress(AMDGPUMachineFunction* MFI,
782 SelectionDAG &DAG) const {
784 const DataLayout &DL = DAG.getDataLayout();
785 GlobalAddressSDNode *G = cast<GlobalAddressSDNode>(Op);
786 const GlobalValue *GV = G->getGlobal();
788 switch (G->getAddressSpace()) {
789 case AMDGPUAS::LOCAL_ADDRESS: {
790 // XXX: What does the value of G->getOffset() mean?
791 assert(G->getOffset() == 0 &&
792 "Do not know what to do with an non-zero offset");
794 // TODO: We could emit code to handle the initialization somewhere.
795 if (hasDefinedInitializer(GV))
799 if (MFI->LocalMemoryObjects.count(GV) == 0) {
800 uint64_t Size = DL.getTypeAllocSize(GV->getType()->getElementType());
801 Offset = MFI->LDSSize;
802 MFI->LocalMemoryObjects[GV] = Offset;
803 // XXX: Account for alignment?
804 MFI->LDSSize += Size;
806 Offset = MFI->LocalMemoryObjects[GV];
809 return DAG.getConstant(Offset, SDLoc(Op),
810 getPointerTy(DL, AMDGPUAS::LOCAL_ADDRESS));
812 case AMDGPUAS::CONSTANT_ADDRESS: {
813 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo();
814 Type *EltType = GV->getType()->getElementType();
815 unsigned Size = DL.getTypeAllocSize(EltType);
816 unsigned Alignment = DL.getPrefTypeAlignment(EltType);
818 MVT PrivPtrVT = getPointerTy(DL, AMDGPUAS::PRIVATE_ADDRESS);
819 MVT ConstPtrVT = getPointerTy(DL, AMDGPUAS::CONSTANT_ADDRESS);
821 int FI = FrameInfo->CreateStackObject(Size, Alignment, false);
822 SDValue InitPtr = DAG.getFrameIndex(FI, PrivPtrVT);
824 const GlobalVariable *Var = cast<GlobalVariable>(GV);
825 if (!Var->hasInitializer()) {
826 // This has no use, but bugpoint will hit it.
827 return DAG.getZExtOrTrunc(InitPtr, SDLoc(Op), ConstPtrVT);
830 const Constant *Init = Var->getInitializer();
831 SmallVector<SDNode*, 8> WorkList;
833 for (SDNode::use_iterator I = DAG.getEntryNode()->use_begin(),
834 E = DAG.getEntryNode()->use_end(); I != E; ++I) {
835 if (I->getOpcode() != AMDGPUISD::REGISTER_LOAD && I->getOpcode() != ISD::LOAD)
837 WorkList.push_back(*I);
839 SDValue Chain = LowerConstantInitializer(Init, GV, InitPtr, DAG.getEntryNode(), DAG);
840 for (SmallVector<SDNode*, 8>::iterator I = WorkList.begin(),
841 E = WorkList.end(); I != E; ++I) {
842 SmallVector<SDValue, 8> Ops;
843 Ops.push_back(Chain);
844 for (unsigned i = 1; i < (*I)->getNumOperands(); ++i) {
845 Ops.push_back((*I)->getOperand(i));
847 DAG.UpdateNodeOperands(*I, Ops);
849 return DAG.getZExtOrTrunc(InitPtr, SDLoc(Op), ConstPtrVT);
853 const Function &Fn = *DAG.getMachineFunction().getFunction();
854 DiagnosticInfoUnsupported BadInit(Fn,
855 "initializer for address space");
856 DAG.getContext()->diagnose(BadInit);
860 SDValue AMDGPUTargetLowering::LowerCONCAT_VECTORS(SDValue Op,
861 SelectionDAG &DAG) const {
862 SmallVector<SDValue, 8> Args;
864 for (const SDUse &U : Op->ops())
865 DAG.ExtractVectorElements(U.get(), Args);
867 return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(Op), Op.getValueType(), Args);
870 SDValue AMDGPUTargetLowering::LowerEXTRACT_SUBVECTOR(SDValue Op,
871 SelectionDAG &DAG) const {
873 SmallVector<SDValue, 8> Args;
874 unsigned Start = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
875 EVT VT = Op.getValueType();
876 DAG.ExtractVectorElements(Op.getOperand(0), Args, Start,
877 VT.getVectorNumElements());
879 return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(Op), Op.getValueType(), Args);
882 SDValue AMDGPUTargetLowering::LowerFrameIndex(SDValue Op,
883 SelectionDAG &DAG) const {
885 MachineFunction &MF = DAG.getMachineFunction();
886 const AMDGPUFrameLowering *TFL = Subtarget->getFrameLowering();
888 FrameIndexSDNode *FIN = cast<FrameIndexSDNode>(Op);
890 unsigned FrameIndex = FIN->getIndex();
891 unsigned IgnoredFrameReg;
893 TFL->getFrameIndexReference(MF, FrameIndex, IgnoredFrameReg);
894 return DAG.getConstant(Offset * 4 * TFL->getStackWidth(MF), SDLoc(Op),
898 SDValue AMDGPUTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
899 SelectionDAG &DAG) const {
900 unsigned IntrinsicID = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
902 EVT VT = Op.getValueType();
904 switch (IntrinsicID) {
906 case AMDGPUIntrinsic::AMDGPU_abs:
907 case AMDGPUIntrinsic::AMDIL_abs: // Legacy name.
908 return LowerIntrinsicIABS(Op, DAG);
909 case AMDGPUIntrinsic::AMDGPU_lrp:
910 return LowerIntrinsicLRP(Op, DAG);
912 case AMDGPUIntrinsic::AMDGPU_clamp:
913 case AMDGPUIntrinsic::AMDIL_clamp: // Legacy name.
914 return DAG.getNode(AMDGPUISD::CLAMP, DL, VT,
915 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
917 case Intrinsic::AMDGPU_div_scale: {
918 // 3rd parameter required to be a constant.
919 const ConstantSDNode *Param = dyn_cast<ConstantSDNode>(Op.getOperand(3));
921 return DAG.getUNDEF(VT);
923 // Translate to the operands expected by the machine instruction. The
924 // first parameter must be the same as the first instruction.
925 SDValue Numerator = Op.getOperand(1);
926 SDValue Denominator = Op.getOperand(2);
928 // Note this order is opposite of the machine instruction's operations,
929 // which is s0.f = Quotient, s1.f = Denominator, s2.f = Numerator. The
930 // intrinsic has the numerator as the first operand to match a normal
931 // division operation.
933 SDValue Src0 = Param->isAllOnesValue() ? Numerator : Denominator;
935 return DAG.getNode(AMDGPUISD::DIV_SCALE, DL, Op->getVTList(), Src0,
936 Denominator, Numerator);
939 case Intrinsic::AMDGPU_div_fmas:
940 return DAG.getNode(AMDGPUISD::DIV_FMAS, DL, VT,
941 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3),
944 case Intrinsic::AMDGPU_div_fixup:
945 return DAG.getNode(AMDGPUISD::DIV_FIXUP, DL, VT,
946 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
948 case Intrinsic::AMDGPU_trig_preop:
949 return DAG.getNode(AMDGPUISD::TRIG_PREOP, DL, VT,
950 Op.getOperand(1), Op.getOperand(2));
952 case Intrinsic::AMDGPU_rcp:
953 return DAG.getNode(AMDGPUISD::RCP, DL, VT, Op.getOperand(1));
955 case Intrinsic::AMDGPU_rsq:
956 return DAG.getNode(AMDGPUISD::RSQ, DL, VT, Op.getOperand(1));
958 case AMDGPUIntrinsic::AMDGPU_legacy_rsq:
959 return DAG.getNode(AMDGPUISD::RSQ_LEGACY, DL, VT, Op.getOperand(1));
961 case Intrinsic::AMDGPU_rsq_clamped:
962 if (Subtarget->getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS) {
963 Type *Type = VT.getTypeForEVT(*DAG.getContext());
964 APFloat Max = APFloat::getLargest(Type->getFltSemantics());
965 APFloat Min = APFloat::getLargest(Type->getFltSemantics(), true);
967 SDValue Rsq = DAG.getNode(AMDGPUISD::RSQ, DL, VT, Op.getOperand(1));
968 SDValue Tmp = DAG.getNode(ISD::FMINNUM, DL, VT, Rsq,
969 DAG.getConstantFP(Max, DL, VT));
970 return DAG.getNode(ISD::FMAXNUM, DL, VT, Tmp,
971 DAG.getConstantFP(Min, DL, VT));
973 return DAG.getNode(AMDGPUISD::RSQ_CLAMPED, DL, VT, Op.getOperand(1));
976 case Intrinsic::AMDGPU_ldexp:
977 return DAG.getNode(AMDGPUISD::LDEXP, DL, VT, Op.getOperand(1),
980 case AMDGPUIntrinsic::AMDGPU_imax:
981 return DAG.getNode(ISD::SMAX, DL, VT, Op.getOperand(1),
983 case AMDGPUIntrinsic::AMDGPU_umax:
984 return DAG.getNode(ISD::UMAX, DL, VT, Op.getOperand(1),
986 case AMDGPUIntrinsic::AMDGPU_imin:
987 return DAG.getNode(ISD::SMIN, DL, VT, Op.getOperand(1),
989 case AMDGPUIntrinsic::AMDGPU_umin:
990 return DAG.getNode(ISD::UMIN, DL, VT, Op.getOperand(1),
993 case AMDGPUIntrinsic::AMDGPU_umul24:
994 return DAG.getNode(AMDGPUISD::MUL_U24, DL, VT,
995 Op.getOperand(1), Op.getOperand(2));
997 case AMDGPUIntrinsic::AMDGPU_imul24:
998 return DAG.getNode(AMDGPUISD::MUL_I24, DL, VT,
999 Op.getOperand(1), Op.getOperand(2));
1001 case AMDGPUIntrinsic::AMDGPU_umad24:
1002 return DAG.getNode(AMDGPUISD::MAD_U24, DL, VT,
1003 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
1005 case AMDGPUIntrinsic::AMDGPU_imad24:
1006 return DAG.getNode(AMDGPUISD::MAD_I24, DL, VT,
1007 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
1009 case AMDGPUIntrinsic::AMDGPU_cvt_f32_ubyte0:
1010 return DAG.getNode(AMDGPUISD::CVT_F32_UBYTE0, DL, VT, Op.getOperand(1));
1012 case AMDGPUIntrinsic::AMDGPU_cvt_f32_ubyte1:
1013 return DAG.getNode(AMDGPUISD::CVT_F32_UBYTE1, DL, VT, Op.getOperand(1));
1015 case AMDGPUIntrinsic::AMDGPU_cvt_f32_ubyte2:
1016 return DAG.getNode(AMDGPUISD::CVT_F32_UBYTE2, DL, VT, Op.getOperand(1));
1018 case AMDGPUIntrinsic::AMDGPU_cvt_f32_ubyte3:
1019 return DAG.getNode(AMDGPUISD::CVT_F32_UBYTE3, DL, VT, Op.getOperand(1));
1021 case AMDGPUIntrinsic::AMDGPU_bfe_i32:
1022 return DAG.getNode(AMDGPUISD::BFE_I32, DL, VT,
1027 case AMDGPUIntrinsic::AMDGPU_bfe_u32:
1028 return DAG.getNode(AMDGPUISD::BFE_U32, DL, VT,
1033 case AMDGPUIntrinsic::AMDGPU_bfi:
1034 return DAG.getNode(AMDGPUISD::BFI, DL, VT,
1039 case AMDGPUIntrinsic::AMDGPU_bfm:
1040 return DAG.getNode(AMDGPUISD::BFM, DL, VT,
1044 case AMDGPUIntrinsic::AMDGPU_brev:
1045 return DAG.getNode(AMDGPUISD::BREV, DL, VT, Op.getOperand(1));
1047 case Intrinsic::AMDGPU_class:
1048 return DAG.getNode(AMDGPUISD::FP_CLASS, DL, VT,
1049 Op.getOperand(1), Op.getOperand(2));
1051 case AMDGPUIntrinsic::AMDIL_exp: // Legacy name.
1052 return DAG.getNode(ISD::FEXP2, DL, VT, Op.getOperand(1));
1054 case AMDGPUIntrinsic::AMDIL_round_nearest: // Legacy name.
1055 return DAG.getNode(ISD::FRINT, DL, VT, Op.getOperand(1));
1056 case AMDGPUIntrinsic::AMDGPU_trunc: // Legacy name.
1057 return DAG.getNode(ISD::FTRUNC, DL, VT, Op.getOperand(1));
1061 ///IABS(a) = SMAX(sub(0, a), a)
1062 SDValue AMDGPUTargetLowering::LowerIntrinsicIABS(SDValue Op,
1063 SelectionDAG &DAG) const {
1065 EVT VT = Op.getValueType();
1066 SDValue Neg = DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, DL, VT),
1069 return DAG.getNode(ISD::SMAX, DL, VT, Neg, Op.getOperand(1));
1072 /// Linear Interpolation
1073 /// LRP(a, b, c) = muladd(a, b, (1 - a) * c)
1074 SDValue AMDGPUTargetLowering::LowerIntrinsicLRP(SDValue Op,
1075 SelectionDAG &DAG) const {
1077 EVT VT = Op.getValueType();
1078 SDValue OneSubA = DAG.getNode(ISD::FSUB, DL, VT,
1079 DAG.getConstantFP(1.0f, DL, MVT::f32),
1081 SDValue OneSubAC = DAG.getNode(ISD::FMUL, DL, VT, OneSubA,
1083 return DAG.getNode(ISD::FADD, DL, VT,
1084 DAG.getNode(ISD::FMUL, DL, VT, Op.getOperand(1), Op.getOperand(2)),
1088 /// \brief Generate Min/Max node
1089 SDValue AMDGPUTargetLowering::CombineFMinMaxLegacy(SDLoc DL,
1096 DAGCombinerInfo &DCI) const {
1097 if (Subtarget->getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS)
1100 if (!(LHS == True && RHS == False) && !(LHS == False && RHS == True))
1103 SelectionDAG &DAG = DCI.DAG;
1104 ISD::CondCode CCOpcode = cast<CondCodeSDNode>(CC)->get();
1113 case ISD::SETFALSE2:
1122 return DAG.getNode(AMDGPUISD::FMIN_LEGACY, DL, VT, RHS, LHS);
1123 return DAG.getNode(AMDGPUISD::FMAX_LEGACY, DL, VT, LHS, RHS);
1129 // Ordered. Assume ordered for undefined.
1131 // Only do this after legalization to avoid interfering with other combines
1132 // which might occur.
1133 if (DCI.getDAGCombineLevel() < AfterLegalizeDAG &&
1134 !DCI.isCalledByLegalizer())
1137 // We need to permute the operands to get the correct NaN behavior. The
1138 // selected operand is the second one based on the failing compare with NaN,
1139 // so permute it based on the compare type the hardware uses.
1141 return DAG.getNode(AMDGPUISD::FMIN_LEGACY, DL, VT, LHS, RHS);
1142 return DAG.getNode(AMDGPUISD::FMAX_LEGACY, DL, VT, RHS, LHS);
1147 return DAG.getNode(AMDGPUISD::FMAX_LEGACY, DL, VT, RHS, LHS);
1148 return DAG.getNode(AMDGPUISD::FMIN_LEGACY, DL, VT, LHS, RHS);
1154 if (DCI.getDAGCombineLevel() < AfterLegalizeDAG &&
1155 !DCI.isCalledByLegalizer())
1159 return DAG.getNode(AMDGPUISD::FMAX_LEGACY, DL, VT, LHS, RHS);
1160 return DAG.getNode(AMDGPUISD::FMIN_LEGACY, DL, VT, RHS, LHS);
1162 case ISD::SETCC_INVALID:
1163 llvm_unreachable("Invalid setcc condcode!");
1168 SDValue AMDGPUTargetLowering::ScalarizeVectorLoad(const SDValue Op,
1169 SelectionDAG &DAG) const {
1170 LoadSDNode *Load = cast<LoadSDNode>(Op);
1171 EVT MemVT = Load->getMemoryVT();
1172 EVT MemEltVT = MemVT.getVectorElementType();
1174 EVT LoadVT = Op.getValueType();
1175 EVT EltVT = LoadVT.getVectorElementType();
1176 EVT PtrVT = Load->getBasePtr().getValueType();
1178 unsigned NumElts = Load->getMemoryVT().getVectorNumElements();
1179 SmallVector<SDValue, 8> Loads;
1180 SmallVector<SDValue, 8> Chains;
1183 unsigned MemEltSize = MemEltVT.getStoreSize();
1184 MachinePointerInfo SrcValue(Load->getMemOperand()->getValue());
1186 for (unsigned i = 0; i < NumElts; ++i) {
1187 SDValue Ptr = DAG.getNode(ISD::ADD, SL, PtrVT, Load->getBasePtr(),
1188 DAG.getConstant(i * MemEltSize, SL, PtrVT));
1191 = DAG.getExtLoad(Load->getExtensionType(), SL, EltVT,
1192 Load->getChain(), Ptr,
1193 SrcValue.getWithOffset(i * MemEltSize),
1194 MemEltVT, Load->isVolatile(), Load->isNonTemporal(),
1195 Load->isInvariant(), Load->getAlignment());
1196 Loads.push_back(NewLoad.getValue(0));
1197 Chains.push_back(NewLoad.getValue(1));
1201 DAG.getNode(ISD::BUILD_VECTOR, SL, LoadVT, Loads),
1202 DAG.getNode(ISD::TokenFactor, SL, MVT::Other, Chains)
1205 return DAG.getMergeValues(Ops, SL);
1208 SDValue AMDGPUTargetLowering::SplitVectorLoad(const SDValue Op,
1209 SelectionDAG &DAG) const {
1210 EVT VT = Op.getValueType();
1212 // If this is a 2 element vector, we really want to scalarize and not create
1213 // weird 1 element vectors.
1214 if (VT.getVectorNumElements() == 2)
1215 return ScalarizeVectorLoad(Op, DAG);
1217 LoadSDNode *Load = cast<LoadSDNode>(Op);
1218 SDValue BasePtr = Load->getBasePtr();
1219 EVT PtrVT = BasePtr.getValueType();
1220 EVT MemVT = Load->getMemoryVT();
1222 MachinePointerInfo SrcValue(Load->getMemOperand()->getValue());
1225 EVT LoMemVT, HiMemVT;
1228 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(VT);
1229 std::tie(LoMemVT, HiMemVT) = DAG.GetSplitDestVTs(MemVT);
1230 std::tie(Lo, Hi) = DAG.SplitVector(Op, SL, LoVT, HiVT);
1232 = DAG.getExtLoad(Load->getExtensionType(), SL, LoVT,
1233 Load->getChain(), BasePtr,
1235 LoMemVT, Load->isVolatile(), Load->isNonTemporal(),
1236 Load->isInvariant(), Load->getAlignment());
1238 SDValue HiPtr = DAG.getNode(ISD::ADD, SL, PtrVT, BasePtr,
1239 DAG.getConstant(LoMemVT.getStoreSize(), SL,
1243 = DAG.getExtLoad(Load->getExtensionType(), SL, HiVT,
1244 Load->getChain(), HiPtr,
1245 SrcValue.getWithOffset(LoMemVT.getStoreSize()),
1246 HiMemVT, Load->isVolatile(), Load->isNonTemporal(),
1247 Load->isInvariant(), Load->getAlignment());
1250 DAG.getNode(ISD::CONCAT_VECTORS, SL, VT, LoLoad, HiLoad),
1251 DAG.getNode(ISD::TokenFactor, SL, MVT::Other,
1252 LoLoad.getValue(1), HiLoad.getValue(1))
1255 return DAG.getMergeValues(Ops, SL);
1258 SDValue AMDGPUTargetLowering::MergeVectorStore(const SDValue &Op,
1259 SelectionDAG &DAG) const {
1260 StoreSDNode *Store = cast<StoreSDNode>(Op);
1261 EVT MemVT = Store->getMemoryVT();
1262 unsigned MemBits = MemVT.getSizeInBits();
1264 // Byte stores are really expensive, so if possible, try to pack 32-bit vector
1265 // truncating store into an i32 store.
1266 // XXX: We could also handle optimize other vector bitwidths.
1267 if (!MemVT.isVector() || MemBits > 32) {
1272 SDValue Value = Store->getValue();
1273 EVT VT = Value.getValueType();
1274 EVT ElemVT = VT.getVectorElementType();
1275 SDValue Ptr = Store->getBasePtr();
1276 EVT MemEltVT = MemVT.getVectorElementType();
1277 unsigned MemEltBits = MemEltVT.getSizeInBits();
1278 unsigned MemNumElements = MemVT.getVectorNumElements();
1279 unsigned PackedSize = MemVT.getStoreSizeInBits();
1280 SDValue Mask = DAG.getConstant((1 << MemEltBits) - 1, DL, MVT::i32);
1282 assert(Value.getValueType().getScalarSizeInBits() >= 32);
1284 SDValue PackedValue;
1285 for (unsigned i = 0; i < MemNumElements; ++i) {
1286 SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, ElemVT, Value,
1287 DAG.getConstant(i, DL, MVT::i32));
1288 Elt = DAG.getZExtOrTrunc(Elt, DL, MVT::i32);
1289 Elt = DAG.getNode(ISD::AND, DL, MVT::i32, Elt, Mask); // getZeroExtendInReg
1291 SDValue Shift = DAG.getConstant(MemEltBits * i, DL, MVT::i32);
1292 Elt = DAG.getNode(ISD::SHL, DL, MVT::i32, Elt, Shift);
1297 PackedValue = DAG.getNode(ISD::OR, DL, MVT::i32, PackedValue, Elt);
1301 if (PackedSize < 32) {
1302 EVT PackedVT = EVT::getIntegerVT(*DAG.getContext(), PackedSize);
1303 return DAG.getTruncStore(Store->getChain(), DL, PackedValue, Ptr,
1304 Store->getMemOperand()->getPointerInfo(),
1306 Store->isNonTemporal(), Store->isVolatile(),
1307 Store->getAlignment());
1310 return DAG.getStore(Store->getChain(), DL, PackedValue, Ptr,
1311 Store->getMemOperand()->getPointerInfo(),
1312 Store->isVolatile(), Store->isNonTemporal(),
1313 Store->getAlignment());
1316 SDValue AMDGPUTargetLowering::ScalarizeVectorStore(SDValue Op,
1317 SelectionDAG &DAG) const {
1318 StoreSDNode *Store = cast<StoreSDNode>(Op);
1319 EVT MemEltVT = Store->getMemoryVT().getVectorElementType();
1320 EVT EltVT = Store->getValue().getValueType().getVectorElementType();
1321 EVT PtrVT = Store->getBasePtr().getValueType();
1322 unsigned NumElts = Store->getMemoryVT().getVectorNumElements();
1325 SmallVector<SDValue, 8> Chains;
1327 unsigned EltSize = MemEltVT.getStoreSize();
1328 MachinePointerInfo SrcValue(Store->getMemOperand()->getValue());
1330 for (unsigned i = 0, e = NumElts; i != e; ++i) {
1331 SDValue Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, EltVT,
1333 DAG.getConstant(i, SL, MVT::i32));
1335 SDValue Offset = DAG.getConstant(i * MemEltVT.getStoreSize(), SL, PtrVT);
1336 SDValue Ptr = DAG.getNode(ISD::ADD, SL, PtrVT, Store->getBasePtr(), Offset);
1338 DAG.getTruncStore(Store->getChain(), SL, Val, Ptr,
1339 SrcValue.getWithOffset(i * EltSize),
1340 MemEltVT, Store->isNonTemporal(), Store->isVolatile(),
1341 Store->getAlignment());
1342 Chains.push_back(NewStore);
1345 return DAG.getNode(ISD::TokenFactor, SL, MVT::Other, Chains);
1348 SDValue AMDGPUTargetLowering::SplitVectorStore(SDValue Op,
1349 SelectionDAG &DAG) const {
1350 StoreSDNode *Store = cast<StoreSDNode>(Op);
1351 SDValue Val = Store->getValue();
1352 EVT VT = Val.getValueType();
1354 // If this is a 2 element vector, we really want to scalarize and not create
1355 // weird 1 element vectors.
1356 if (VT.getVectorNumElements() == 2)
1357 return ScalarizeVectorStore(Op, DAG);
1359 EVT MemVT = Store->getMemoryVT();
1360 SDValue Chain = Store->getChain();
1361 SDValue BasePtr = Store->getBasePtr();
1365 EVT LoMemVT, HiMemVT;
1368 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(VT);
1369 std::tie(LoMemVT, HiMemVT) = DAG.GetSplitDestVTs(MemVT);
1370 std::tie(Lo, Hi) = DAG.SplitVector(Val, SL, LoVT, HiVT);
1372 EVT PtrVT = BasePtr.getValueType();
1373 SDValue HiPtr = DAG.getNode(ISD::ADD, SL, PtrVT, BasePtr,
1374 DAG.getConstant(LoMemVT.getStoreSize(), SL,
1377 MachinePointerInfo SrcValue(Store->getMemOperand()->getValue());
1379 = DAG.getTruncStore(Chain, SL, Lo,
1383 Store->isNonTemporal(),
1384 Store->isVolatile(),
1385 Store->getAlignment());
1387 = DAG.getTruncStore(Chain, SL, Hi,
1389 SrcValue.getWithOffset(LoMemVT.getStoreSize()),
1391 Store->isNonTemporal(),
1392 Store->isVolatile(),
1393 Store->getAlignment());
1395 return DAG.getNode(ISD::TokenFactor, SL, MVT::Other, LoStore, HiStore);
1399 SDValue AMDGPUTargetLowering::LowerLOAD(SDValue Op, SelectionDAG &DAG) const {
1401 LoadSDNode *Load = cast<LoadSDNode>(Op);
1402 ISD::LoadExtType ExtType = Load->getExtensionType();
1403 EVT VT = Op.getValueType();
1404 EVT MemVT = Load->getMemoryVT();
1406 if (ExtType == ISD::NON_EXTLOAD && VT.getSizeInBits() < 32) {
1407 assert(VT == MVT::i1 && "Only i1 non-extloads expected");
1408 // FIXME: Copied from PPC
1409 // First, load into 32 bits, then truncate to 1 bit.
1411 SDValue Chain = Load->getChain();
1412 SDValue BasePtr = Load->getBasePtr();
1413 MachineMemOperand *MMO = Load->getMemOperand();
1415 SDValue NewLD = DAG.getExtLoad(ISD::EXTLOAD, DL, MVT::i32, Chain,
1416 BasePtr, MVT::i8, MMO);
1419 DAG.getNode(ISD::TRUNCATE, DL, VT, NewLD),
1423 return DAG.getMergeValues(Ops, DL);
1426 if (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS ||
1427 Load->getAddressSpace() != AMDGPUAS::PRIVATE_ADDRESS ||
1428 ExtType == ISD::NON_EXTLOAD || Load->getMemoryVT().bitsGE(MVT::i32))
1431 // <SI && AS=PRIVATE && EXTLOAD && size < 32bit,
1432 // register (2-)byte extract.
1434 // Get Register holding the target.
1435 SDValue Ptr = DAG.getNode(ISD::SRL, DL, MVT::i32, Load->getBasePtr(),
1436 DAG.getConstant(2, DL, MVT::i32));
1437 // Load the Register.
1438 SDValue Ret = DAG.getNode(AMDGPUISD::REGISTER_LOAD, DL, Op.getValueType(),
1439 Load->getChain(), Ptr,
1440 DAG.getTargetConstant(0, DL, MVT::i32),
1443 // Get offset within the register.
1444 SDValue ByteIdx = DAG.getNode(ISD::AND, DL, MVT::i32,
1446 DAG.getConstant(0x3, DL, MVT::i32));
1448 // Bit offset of target byte (byteIdx * 8).
1449 SDValue ShiftAmt = DAG.getNode(ISD::SHL, DL, MVT::i32, ByteIdx,
1450 DAG.getConstant(3, DL, MVT::i32));
1452 // Shift to the right.
1453 Ret = DAG.getNode(ISD::SRL, DL, MVT::i32, Ret, ShiftAmt);
1455 // Eliminate the upper bits by setting them to ...
1456 EVT MemEltVT = MemVT.getScalarType();
1459 if (ExtType == ISD::SEXTLOAD) {
1460 SDValue MemEltVTNode = DAG.getValueType(MemEltVT);
1463 DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, MVT::i32, Ret, MemEltVTNode),
1467 return DAG.getMergeValues(Ops, DL);
1472 DAG.getZeroExtendInReg(Ret, DL, MemEltVT),
1476 return DAG.getMergeValues(Ops, DL);
1479 SDValue AMDGPUTargetLowering::LowerSTORE(SDValue Op, SelectionDAG &DAG) const {
1481 SDValue Result = AMDGPUTargetLowering::MergeVectorStore(Op, DAG);
1482 if (Result.getNode()) {
1486 StoreSDNode *Store = cast<StoreSDNode>(Op);
1487 SDValue Chain = Store->getChain();
1488 if ((Store->getAddressSpace() == AMDGPUAS::LOCAL_ADDRESS ||
1489 Store->getAddressSpace() == AMDGPUAS::PRIVATE_ADDRESS) &&
1490 Store->getValue().getValueType().isVector()) {
1491 return ScalarizeVectorStore(Op, DAG);
1494 EVT MemVT = Store->getMemoryVT();
1495 if (Store->getAddressSpace() == AMDGPUAS::PRIVATE_ADDRESS &&
1496 MemVT.bitsLT(MVT::i32)) {
1498 if (Store->getMemoryVT() == MVT::i8) {
1500 } else if (Store->getMemoryVT() == MVT::i16) {
1503 SDValue BasePtr = Store->getBasePtr();
1504 SDValue Ptr = DAG.getNode(ISD::SRL, DL, MVT::i32, BasePtr,
1505 DAG.getConstant(2, DL, MVT::i32));
1506 SDValue Dst = DAG.getNode(AMDGPUISD::REGISTER_LOAD, DL, MVT::i32,
1508 DAG.getTargetConstant(0, DL, MVT::i32));
1510 SDValue ByteIdx = DAG.getNode(ISD::AND, DL, MVT::i32, BasePtr,
1511 DAG.getConstant(0x3, DL, MVT::i32));
1513 SDValue ShiftAmt = DAG.getNode(ISD::SHL, DL, MVT::i32, ByteIdx,
1514 DAG.getConstant(3, DL, MVT::i32));
1516 SDValue SExtValue = DAG.getNode(ISD::SIGN_EXTEND, DL, MVT::i32,
1519 SDValue MaskedValue = DAG.getZeroExtendInReg(SExtValue, DL, MemVT);
1521 SDValue ShiftedValue = DAG.getNode(ISD::SHL, DL, MVT::i32,
1522 MaskedValue, ShiftAmt);
1524 SDValue DstMask = DAG.getNode(ISD::SHL, DL, MVT::i32,
1525 DAG.getConstant(Mask, DL, MVT::i32),
1527 DstMask = DAG.getNode(ISD::XOR, DL, MVT::i32, DstMask,
1528 DAG.getConstant(0xffffffff, DL, MVT::i32));
1529 Dst = DAG.getNode(ISD::AND, DL, MVT::i32, Dst, DstMask);
1531 SDValue Value = DAG.getNode(ISD::OR, DL, MVT::i32, Dst, ShiftedValue);
1532 return DAG.getNode(AMDGPUISD::REGISTER_STORE, DL, MVT::Other,
1534 DAG.getTargetConstant(0, DL, MVT::i32));
1539 // This is a shortcut for integer division because we have fast i32<->f32
1540 // conversions, and fast f32 reciprocal instructions. The fractional part of a
1541 // float is enough to accurately represent up to a 24-bit integer.
1542 SDValue AMDGPUTargetLowering::LowerDIVREM24(SDValue Op, SelectionDAG &DAG, bool sign) const {
1544 EVT VT = Op.getValueType();
1545 SDValue LHS = Op.getOperand(0);
1546 SDValue RHS = Op.getOperand(1);
1547 MVT IntVT = MVT::i32;
1548 MVT FltVT = MVT::f32;
1550 ISD::NodeType ToFp = sign ? ISD::SINT_TO_FP : ISD::UINT_TO_FP;
1551 ISD::NodeType ToInt = sign ? ISD::FP_TO_SINT : ISD::FP_TO_UINT;
1553 if (VT.isVector()) {
1554 unsigned NElts = VT.getVectorNumElements();
1555 IntVT = MVT::getVectorVT(MVT::i32, NElts);
1556 FltVT = MVT::getVectorVT(MVT::f32, NElts);
1559 unsigned BitSize = VT.getScalarType().getSizeInBits();
1561 SDValue jq = DAG.getConstant(1, DL, IntVT);
1564 // char|short jq = ia ^ ib;
1565 jq = DAG.getNode(ISD::XOR, DL, VT, LHS, RHS);
1567 // jq = jq >> (bitsize - 2)
1568 jq = DAG.getNode(ISD::SRA, DL, VT, jq,
1569 DAG.getConstant(BitSize - 2, DL, VT));
1572 jq = DAG.getNode(ISD::OR, DL, VT, jq, DAG.getConstant(1, DL, VT));
1575 jq = DAG.getSExtOrTrunc(jq, DL, IntVT);
1578 // int ia = (int)LHS;
1580 DAG.getSExtOrTrunc(LHS, DL, IntVT) : DAG.getZExtOrTrunc(LHS, DL, IntVT);
1582 // int ib, (int)RHS;
1584 DAG.getSExtOrTrunc(RHS, DL, IntVT) : DAG.getZExtOrTrunc(RHS, DL, IntVT);
1586 // float fa = (float)ia;
1587 SDValue fa = DAG.getNode(ToFp, DL, FltVT, ia);
1589 // float fb = (float)ib;
1590 SDValue fb = DAG.getNode(ToFp, DL, FltVT, ib);
1592 // float fq = native_divide(fa, fb);
1593 SDValue fq = DAG.getNode(ISD::FMUL, DL, FltVT,
1594 fa, DAG.getNode(AMDGPUISD::RCP, DL, FltVT, fb));
1597 fq = DAG.getNode(ISD::FTRUNC, DL, FltVT, fq);
1599 // float fqneg = -fq;
1600 SDValue fqneg = DAG.getNode(ISD::FNEG, DL, FltVT, fq);
1602 // float fr = mad(fqneg, fb, fa);
1603 SDValue fr = DAG.getNode(ISD::FADD, DL, FltVT,
1604 DAG.getNode(ISD::FMUL, DL, FltVT, fqneg, fb), fa);
1606 // int iq = (int)fq;
1607 SDValue iq = DAG.getNode(ToInt, DL, IntVT, fq);
1610 fr = DAG.getNode(ISD::FABS, DL, FltVT, fr);
1613 fb = DAG.getNode(ISD::FABS, DL, FltVT, fb);
1615 EVT SetCCVT = getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT);
1617 // int cv = fr >= fb;
1618 SDValue cv = DAG.getSetCC(DL, SetCCVT, fr, fb, ISD::SETOGE);
1620 // jq = (cv ? jq : 0);
1621 jq = DAG.getNode(ISD::SELECT, DL, VT, cv, jq, DAG.getConstant(0, DL, VT));
1623 // dst = trunc/extend to legal type
1624 iq = sign ? DAG.getSExtOrTrunc(iq, DL, VT) : DAG.getZExtOrTrunc(iq, DL, VT);
1627 SDValue Div = DAG.getNode(ISD::ADD, DL, VT, iq, jq);
1629 // Rem needs compensation, it's easier to recompute it
1630 SDValue Rem = DAG.getNode(ISD::MUL, DL, VT, Div, RHS);
1631 Rem = DAG.getNode(ISD::SUB, DL, VT, LHS, Rem);
1637 return DAG.getMergeValues(Res, DL);
1640 void AMDGPUTargetLowering::LowerUDIVREM64(SDValue Op,
1642 SmallVectorImpl<SDValue> &Results) const {
1643 assert(Op.getValueType() == MVT::i64);
1646 EVT VT = Op.getValueType();
1647 EVT HalfVT = VT.getHalfSizedIntegerVT(*DAG.getContext());
1649 SDValue one = DAG.getConstant(1, DL, HalfVT);
1650 SDValue zero = DAG.getConstant(0, DL, HalfVT);
1653 SDValue LHS = Op.getOperand(0);
1654 SDValue LHS_Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, LHS, zero);
1655 SDValue LHS_Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, LHS, one);
1657 SDValue RHS = Op.getOperand(1);
1658 SDValue RHS_Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, RHS, zero);
1659 SDValue RHS_Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, RHS, one);
1661 if (VT == MVT::i64 &&
1662 DAG.MaskedValueIsZero(RHS, APInt::getHighBitsSet(64, 32)) &&
1663 DAG.MaskedValueIsZero(LHS, APInt::getHighBitsSet(64, 32))) {
1665 SDValue Res = DAG.getNode(ISD::UDIVREM, DL, DAG.getVTList(HalfVT, HalfVT),
1668 SDValue DIV = DAG.getNode(ISD::BUILD_PAIR, DL, VT, Res.getValue(0), zero);
1669 SDValue REM = DAG.getNode(ISD::BUILD_PAIR, DL, VT, Res.getValue(1), zero);
1670 Results.push_back(DIV);
1671 Results.push_back(REM);
1675 // Get Speculative values
1676 SDValue DIV_Part = DAG.getNode(ISD::UDIV, DL, HalfVT, LHS_Hi, RHS_Lo);
1677 SDValue REM_Part = DAG.getNode(ISD::UREM, DL, HalfVT, LHS_Hi, RHS_Lo);
1679 SDValue REM_Lo = DAG.getSelectCC(DL, RHS_Hi, zero, REM_Part, LHS_Hi, ISD::SETEQ);
1680 SDValue REM = DAG.getNode(ISD::BUILD_PAIR, DL, VT, REM_Lo, zero);
1682 SDValue DIV_Hi = DAG.getSelectCC(DL, RHS_Hi, zero, DIV_Part, zero, ISD::SETEQ);
1683 SDValue DIV_Lo = zero;
1685 const unsigned halfBitWidth = HalfVT.getSizeInBits();
1687 for (unsigned i = 0; i < halfBitWidth; ++i) {
1688 const unsigned bitPos = halfBitWidth - i - 1;
1689 SDValue POS = DAG.getConstant(bitPos, DL, HalfVT);
1690 // Get value of high bit
1691 SDValue HBit = DAG.getNode(ISD::SRL, DL, HalfVT, LHS_Lo, POS);
1692 HBit = DAG.getNode(ISD::AND, DL, HalfVT, HBit, one);
1693 HBit = DAG.getNode(ISD::ZERO_EXTEND, DL, VT, HBit);
1696 REM = DAG.getNode(ISD::SHL, DL, VT, REM, DAG.getConstant(1, DL, VT));
1698 REM = DAG.getNode(ISD::OR, DL, VT, REM, HBit);
1700 SDValue BIT = DAG.getConstant(1 << bitPos, DL, HalfVT);
1701 SDValue realBIT = DAG.getSelectCC(DL, REM, RHS, BIT, zero, ISD::SETUGE);
1703 DIV_Lo = DAG.getNode(ISD::OR, DL, HalfVT, DIV_Lo, realBIT);
1706 SDValue REM_sub = DAG.getNode(ISD::SUB, DL, VT, REM, RHS);
1707 REM = DAG.getSelectCC(DL, REM, RHS, REM_sub, REM, ISD::SETUGE);
1710 SDValue DIV = DAG.getNode(ISD::BUILD_PAIR, DL, VT, DIV_Lo, DIV_Hi);
1711 Results.push_back(DIV);
1712 Results.push_back(REM);
1715 SDValue AMDGPUTargetLowering::LowerUDIVREM(SDValue Op,
1716 SelectionDAG &DAG) const {
1718 EVT VT = Op.getValueType();
1720 if (VT == MVT::i64) {
1721 SmallVector<SDValue, 2> Results;
1722 LowerUDIVREM64(Op, DAG, Results);
1723 return DAG.getMergeValues(Results, DL);
1726 SDValue Num = Op.getOperand(0);
1727 SDValue Den = Op.getOperand(1);
1729 if (VT == MVT::i32) {
1730 if (DAG.MaskedValueIsZero(Num, APInt::getHighBitsSet(32, 8)) &&
1731 DAG.MaskedValueIsZero(Den, APInt::getHighBitsSet(32, 8))) {
1732 // TODO: We technically could do this for i64, but shouldn't that just be
1733 // handled by something generally reducing 64-bit division on 32-bit
1734 // values to 32-bit?
1735 return LowerDIVREM24(Op, DAG, false);
1739 // RCP = URECIP(Den) = 2^32 / Den + e
1740 // e is rounding error.
1741 SDValue RCP = DAG.getNode(AMDGPUISD::URECIP, DL, VT, Den);
1743 // RCP_LO = mul(RCP, Den) */
1744 SDValue RCP_LO = DAG.getNode(ISD::MUL, DL, VT, RCP, Den);
1746 // RCP_HI = mulhu (RCP, Den) */
1747 SDValue RCP_HI = DAG.getNode(ISD::MULHU, DL, VT, RCP, Den);
1749 // NEG_RCP_LO = -RCP_LO
1750 SDValue NEG_RCP_LO = DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, DL, VT),
1753 // ABS_RCP_LO = (RCP_HI == 0 ? NEG_RCP_LO : RCP_LO)
1754 SDValue ABS_RCP_LO = DAG.getSelectCC(DL, RCP_HI, DAG.getConstant(0, DL, VT),
1757 // Calculate the rounding error from the URECIP instruction
1758 // E = mulhu(ABS_RCP_LO, RCP)
1759 SDValue E = DAG.getNode(ISD::MULHU, DL, VT, ABS_RCP_LO, RCP);
1761 // RCP_A_E = RCP + E
1762 SDValue RCP_A_E = DAG.getNode(ISD::ADD, DL, VT, RCP, E);
1764 // RCP_S_E = RCP - E
1765 SDValue RCP_S_E = DAG.getNode(ISD::SUB, DL, VT, RCP, E);
1767 // Tmp0 = (RCP_HI == 0 ? RCP_A_E : RCP_SUB_E)
1768 SDValue Tmp0 = DAG.getSelectCC(DL, RCP_HI, DAG.getConstant(0, DL, VT),
1771 // Quotient = mulhu(Tmp0, Num)
1772 SDValue Quotient = DAG.getNode(ISD::MULHU, DL, VT, Tmp0, Num);
1774 // Num_S_Remainder = Quotient * Den
1775 SDValue Num_S_Remainder = DAG.getNode(ISD::MUL, DL, VT, Quotient, Den);
1777 // Remainder = Num - Num_S_Remainder
1778 SDValue Remainder = DAG.getNode(ISD::SUB, DL, VT, Num, Num_S_Remainder);
1780 // Remainder_GE_Den = (Remainder >= Den ? -1 : 0)
1781 SDValue Remainder_GE_Den = DAG.getSelectCC(DL, Remainder, Den,
1782 DAG.getConstant(-1, DL, VT),
1783 DAG.getConstant(0, DL, VT),
1785 // Remainder_GE_Zero = (Num >= Num_S_Remainder ? -1 : 0)
1786 SDValue Remainder_GE_Zero = DAG.getSelectCC(DL, Num,
1788 DAG.getConstant(-1, DL, VT),
1789 DAG.getConstant(0, DL, VT),
1791 // Tmp1 = Remainder_GE_Den & Remainder_GE_Zero
1792 SDValue Tmp1 = DAG.getNode(ISD::AND, DL, VT, Remainder_GE_Den,
1795 // Calculate Division result:
1797 // Quotient_A_One = Quotient + 1
1798 SDValue Quotient_A_One = DAG.getNode(ISD::ADD, DL, VT, Quotient,
1799 DAG.getConstant(1, DL, VT));
1801 // Quotient_S_One = Quotient - 1
1802 SDValue Quotient_S_One = DAG.getNode(ISD::SUB, DL, VT, Quotient,
1803 DAG.getConstant(1, DL, VT));
1805 // Div = (Tmp1 == 0 ? Quotient : Quotient_A_One)
1806 SDValue Div = DAG.getSelectCC(DL, Tmp1, DAG.getConstant(0, DL, VT),
1807 Quotient, Quotient_A_One, ISD::SETEQ);
1809 // Div = (Remainder_GE_Zero == 0 ? Quotient_S_One : Div)
1810 Div = DAG.getSelectCC(DL, Remainder_GE_Zero, DAG.getConstant(0, DL, VT),
1811 Quotient_S_One, Div, ISD::SETEQ);
1813 // Calculate Rem result:
1815 // Remainder_S_Den = Remainder - Den
1816 SDValue Remainder_S_Den = DAG.getNode(ISD::SUB, DL, VT, Remainder, Den);
1818 // Remainder_A_Den = Remainder + Den
1819 SDValue Remainder_A_Den = DAG.getNode(ISD::ADD, DL, VT, Remainder, Den);
1821 // Rem = (Tmp1 == 0 ? Remainder : Remainder_S_Den)
1822 SDValue Rem = DAG.getSelectCC(DL, Tmp1, DAG.getConstant(0, DL, VT),
1823 Remainder, Remainder_S_Den, ISD::SETEQ);
1825 // Rem = (Remainder_GE_Zero == 0 ? Remainder_A_Den : Rem)
1826 Rem = DAG.getSelectCC(DL, Remainder_GE_Zero, DAG.getConstant(0, DL, VT),
1827 Remainder_A_Den, Rem, ISD::SETEQ);
1832 return DAG.getMergeValues(Ops, DL);
1835 SDValue AMDGPUTargetLowering::LowerSDIVREM(SDValue Op,
1836 SelectionDAG &DAG) const {
1838 EVT VT = Op.getValueType();
1840 SDValue LHS = Op.getOperand(0);
1841 SDValue RHS = Op.getOperand(1);
1843 SDValue Zero = DAG.getConstant(0, DL, VT);
1844 SDValue NegOne = DAG.getConstant(-1, DL, VT);
1846 if (VT == MVT::i32 &&
1847 DAG.ComputeNumSignBits(LHS) > 8 &&
1848 DAG.ComputeNumSignBits(RHS) > 8) {
1849 return LowerDIVREM24(Op, DAG, true);
1851 if (VT == MVT::i64 &&
1852 DAG.ComputeNumSignBits(LHS) > 32 &&
1853 DAG.ComputeNumSignBits(RHS) > 32) {
1854 EVT HalfVT = VT.getHalfSizedIntegerVT(*DAG.getContext());
1857 SDValue LHS_Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, LHS, Zero);
1858 SDValue RHS_Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, RHS, Zero);
1859 SDValue DIVREM = DAG.getNode(ISD::SDIVREM, DL, DAG.getVTList(HalfVT, HalfVT),
1862 DAG.getNode(ISD::SIGN_EXTEND, DL, VT, DIVREM.getValue(0)),
1863 DAG.getNode(ISD::SIGN_EXTEND, DL, VT, DIVREM.getValue(1))
1865 return DAG.getMergeValues(Res, DL);
1868 SDValue LHSign = DAG.getSelectCC(DL, LHS, Zero, NegOne, Zero, ISD::SETLT);
1869 SDValue RHSign = DAG.getSelectCC(DL, RHS, Zero, NegOne, Zero, ISD::SETLT);
1870 SDValue DSign = DAG.getNode(ISD::XOR, DL, VT, LHSign, RHSign);
1871 SDValue RSign = LHSign; // Remainder sign is the same as LHS
1873 LHS = DAG.getNode(ISD::ADD, DL, VT, LHS, LHSign);
1874 RHS = DAG.getNode(ISD::ADD, DL, VT, RHS, RHSign);
1876 LHS = DAG.getNode(ISD::XOR, DL, VT, LHS, LHSign);
1877 RHS = DAG.getNode(ISD::XOR, DL, VT, RHS, RHSign);
1879 SDValue Div = DAG.getNode(ISD::UDIVREM, DL, DAG.getVTList(VT, VT), LHS, RHS);
1880 SDValue Rem = Div.getValue(1);
1882 Div = DAG.getNode(ISD::XOR, DL, VT, Div, DSign);
1883 Rem = DAG.getNode(ISD::XOR, DL, VT, Rem, RSign);
1885 Div = DAG.getNode(ISD::SUB, DL, VT, Div, DSign);
1886 Rem = DAG.getNode(ISD::SUB, DL, VT, Rem, RSign);
1892 return DAG.getMergeValues(Res, DL);
1895 // (frem x, y) -> (fsub x, (fmul (ftrunc (fdiv x, y)), y))
1896 SDValue AMDGPUTargetLowering::LowerFREM(SDValue Op, SelectionDAG &DAG) const {
1898 EVT VT = Op.getValueType();
1899 SDValue X = Op.getOperand(0);
1900 SDValue Y = Op.getOperand(1);
1902 SDValue Div = DAG.getNode(ISD::FDIV, SL, VT, X, Y);
1903 SDValue Floor = DAG.getNode(ISD::FTRUNC, SL, VT, Div);
1904 SDValue Mul = DAG.getNode(ISD::FMUL, SL, VT, Floor, Y);
1906 return DAG.getNode(ISD::FSUB, SL, VT, X, Mul);
1909 SDValue AMDGPUTargetLowering::LowerFCEIL(SDValue Op, SelectionDAG &DAG) const {
1911 SDValue Src = Op.getOperand(0);
1913 // result = trunc(src)
1914 // if (src > 0.0 && src != result)
1917 SDValue Trunc = DAG.getNode(ISD::FTRUNC, SL, MVT::f64, Src);
1919 const SDValue Zero = DAG.getConstantFP(0.0, SL, MVT::f64);
1920 const SDValue One = DAG.getConstantFP(1.0, SL, MVT::f64);
1923 getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), MVT::f64);
1925 SDValue Lt0 = DAG.getSetCC(SL, SetCCVT, Src, Zero, ISD::SETOGT);
1926 SDValue NeTrunc = DAG.getSetCC(SL, SetCCVT, Src, Trunc, ISD::SETONE);
1927 SDValue And = DAG.getNode(ISD::AND, SL, SetCCVT, Lt0, NeTrunc);
1929 SDValue Add = DAG.getNode(ISD::SELECT, SL, MVT::f64, And, One, Zero);
1930 return DAG.getNode(ISD::FADD, SL, MVT::f64, Trunc, Add);
1933 static SDValue extractF64Exponent(SDValue Hi, SDLoc SL, SelectionDAG &DAG) {
1934 const unsigned FractBits = 52;
1935 const unsigned ExpBits = 11;
1937 SDValue ExpPart = DAG.getNode(AMDGPUISD::BFE_U32, SL, MVT::i32,
1939 DAG.getConstant(FractBits - 32, SL, MVT::i32),
1940 DAG.getConstant(ExpBits, SL, MVT::i32));
1941 SDValue Exp = DAG.getNode(ISD::SUB, SL, MVT::i32, ExpPart,
1942 DAG.getConstant(1023, SL, MVT::i32));
1947 SDValue AMDGPUTargetLowering::LowerFTRUNC(SDValue Op, SelectionDAG &DAG) const {
1949 SDValue Src = Op.getOperand(0);
1951 assert(Op.getValueType() == MVT::f64);
1953 const SDValue Zero = DAG.getConstant(0, SL, MVT::i32);
1954 const SDValue One = DAG.getConstant(1, SL, MVT::i32);
1956 SDValue VecSrc = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, Src);
1958 // Extract the upper half, since this is where we will find the sign and
1960 SDValue Hi = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, VecSrc, One);
1962 SDValue Exp = extractF64Exponent(Hi, SL, DAG);
1964 const unsigned FractBits = 52;
1966 // Extract the sign bit.
1967 const SDValue SignBitMask = DAG.getConstant(UINT32_C(1) << 31, SL, MVT::i32);
1968 SDValue SignBit = DAG.getNode(ISD::AND, SL, MVT::i32, Hi, SignBitMask);
1970 // Extend back to to 64-bits.
1971 SDValue SignBit64 = DAG.getNode(ISD::BUILD_VECTOR, SL, MVT::v2i32,
1973 SignBit64 = DAG.getNode(ISD::BITCAST, SL, MVT::i64, SignBit64);
1975 SDValue BcInt = DAG.getNode(ISD::BITCAST, SL, MVT::i64, Src);
1976 const SDValue FractMask
1977 = DAG.getConstant((UINT64_C(1) << FractBits) - 1, SL, MVT::i64);
1979 SDValue Shr = DAG.getNode(ISD::SRA, SL, MVT::i64, FractMask, Exp);
1980 SDValue Not = DAG.getNOT(SL, Shr, MVT::i64);
1981 SDValue Tmp0 = DAG.getNode(ISD::AND, SL, MVT::i64, BcInt, Not);
1984 getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), MVT::i32);
1986 const SDValue FiftyOne = DAG.getConstant(FractBits - 1, SL, MVT::i32);
1988 SDValue ExpLt0 = DAG.getSetCC(SL, SetCCVT, Exp, Zero, ISD::SETLT);
1989 SDValue ExpGt51 = DAG.getSetCC(SL, SetCCVT, Exp, FiftyOne, ISD::SETGT);
1991 SDValue Tmp1 = DAG.getNode(ISD::SELECT, SL, MVT::i64, ExpLt0, SignBit64, Tmp0);
1992 SDValue Tmp2 = DAG.getNode(ISD::SELECT, SL, MVT::i64, ExpGt51, BcInt, Tmp1);
1994 return DAG.getNode(ISD::BITCAST, SL, MVT::f64, Tmp2);
1997 SDValue AMDGPUTargetLowering::LowerFRINT(SDValue Op, SelectionDAG &DAG) const {
1999 SDValue Src = Op.getOperand(0);
2001 assert(Op.getValueType() == MVT::f64);
2003 APFloat C1Val(APFloat::IEEEdouble, "0x1.0p+52");
2004 SDValue C1 = DAG.getConstantFP(C1Val, SL, MVT::f64);
2005 SDValue CopySign = DAG.getNode(ISD::FCOPYSIGN, SL, MVT::f64, C1, Src);
2007 SDValue Tmp1 = DAG.getNode(ISD::FADD, SL, MVT::f64, Src, CopySign);
2008 SDValue Tmp2 = DAG.getNode(ISD::FSUB, SL, MVT::f64, Tmp1, CopySign);
2010 SDValue Fabs = DAG.getNode(ISD::FABS, SL, MVT::f64, Src);
2012 APFloat C2Val(APFloat::IEEEdouble, "0x1.fffffffffffffp+51");
2013 SDValue C2 = DAG.getConstantFP(C2Val, SL, MVT::f64);
2016 getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), MVT::f64);
2017 SDValue Cond = DAG.getSetCC(SL, SetCCVT, Fabs, C2, ISD::SETOGT);
2019 return DAG.getSelect(SL, MVT::f64, Cond, Src, Tmp2);
2022 SDValue AMDGPUTargetLowering::LowerFNEARBYINT(SDValue Op, SelectionDAG &DAG) const {
2023 // FNEARBYINT and FRINT are the same, except in their handling of FP
2024 // exceptions. Those aren't really meaningful for us, and OpenCL only has
2025 // rint, so just treat them as equivalent.
2026 return DAG.getNode(ISD::FRINT, SDLoc(Op), Op.getValueType(), Op.getOperand(0));
2029 // XXX - May require not supporting f32 denormals?
2030 SDValue AMDGPUTargetLowering::LowerFROUND32(SDValue Op, SelectionDAG &DAG) const {
2032 SDValue X = Op.getOperand(0);
2034 SDValue T = DAG.getNode(ISD::FTRUNC, SL, MVT::f32, X);
2036 SDValue Diff = DAG.getNode(ISD::FSUB, SL, MVT::f32, X, T);
2038 SDValue AbsDiff = DAG.getNode(ISD::FABS, SL, MVT::f32, Diff);
2040 const SDValue Zero = DAG.getConstantFP(0.0, SL, MVT::f32);
2041 const SDValue One = DAG.getConstantFP(1.0, SL, MVT::f32);
2042 const SDValue Half = DAG.getConstantFP(0.5, SL, MVT::f32);
2044 SDValue SignOne = DAG.getNode(ISD::FCOPYSIGN, SL, MVT::f32, One, X);
2047 getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), MVT::f32);
2049 SDValue Cmp = DAG.getSetCC(SL, SetCCVT, AbsDiff, Half, ISD::SETOGE);
2051 SDValue Sel = DAG.getNode(ISD::SELECT, SL, MVT::f32, Cmp, SignOne, Zero);
2053 return DAG.getNode(ISD::FADD, SL, MVT::f32, T, Sel);
2056 SDValue AMDGPUTargetLowering::LowerFROUND64(SDValue Op, SelectionDAG &DAG) const {
2058 SDValue X = Op.getOperand(0);
2060 SDValue L = DAG.getNode(ISD::BITCAST, SL, MVT::i64, X);
2062 const SDValue Zero = DAG.getConstant(0, SL, MVT::i32);
2063 const SDValue One = DAG.getConstant(1, SL, MVT::i32);
2064 const SDValue NegOne = DAG.getConstant(-1, SL, MVT::i32);
2065 const SDValue FiftyOne = DAG.getConstant(51, SL, MVT::i32);
2067 getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), MVT::i32);
2069 SDValue BC = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, X);
2071 SDValue Hi = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, BC, One);
2073 SDValue Exp = extractF64Exponent(Hi, SL, DAG);
2075 const SDValue Mask = DAG.getConstant(INT64_C(0x000fffffffffffff), SL,
2078 SDValue M = DAG.getNode(ISD::SRA, SL, MVT::i64, Mask, Exp);
2079 SDValue D = DAG.getNode(ISD::SRA, SL, MVT::i64,
2080 DAG.getConstant(INT64_C(0x0008000000000000), SL,
2084 SDValue Tmp0 = DAG.getNode(ISD::AND, SL, MVT::i64, L, M);
2085 SDValue Tmp1 = DAG.getSetCC(SL, SetCCVT,
2086 DAG.getConstant(0, SL, MVT::i64), Tmp0,
2089 SDValue Tmp2 = DAG.getNode(ISD::SELECT, SL, MVT::i64, Tmp1,
2090 D, DAG.getConstant(0, SL, MVT::i64));
2091 SDValue K = DAG.getNode(ISD::ADD, SL, MVT::i64, L, Tmp2);
2093 K = DAG.getNode(ISD::AND, SL, MVT::i64, K, DAG.getNOT(SL, M, MVT::i64));
2094 K = DAG.getNode(ISD::BITCAST, SL, MVT::f64, K);
2096 SDValue ExpLt0 = DAG.getSetCC(SL, SetCCVT, Exp, Zero, ISD::SETLT);
2097 SDValue ExpGt51 = DAG.getSetCC(SL, SetCCVT, Exp, FiftyOne, ISD::SETGT);
2098 SDValue ExpEqNegOne = DAG.getSetCC(SL, SetCCVT, NegOne, Exp, ISD::SETEQ);
2100 SDValue Mag = DAG.getNode(ISD::SELECT, SL, MVT::f64,
2102 DAG.getConstantFP(1.0, SL, MVT::f64),
2103 DAG.getConstantFP(0.0, SL, MVT::f64));
2105 SDValue S = DAG.getNode(ISD::FCOPYSIGN, SL, MVT::f64, Mag, X);
2107 K = DAG.getNode(ISD::SELECT, SL, MVT::f64, ExpLt0, S, K);
2108 K = DAG.getNode(ISD::SELECT, SL, MVT::f64, ExpGt51, X, K);
2113 SDValue AMDGPUTargetLowering::LowerFROUND(SDValue Op, SelectionDAG &DAG) const {
2114 EVT VT = Op.getValueType();
2117 return LowerFROUND32(Op, DAG);
2120 return LowerFROUND64(Op, DAG);
2122 llvm_unreachable("unhandled type");
2125 SDValue AMDGPUTargetLowering::LowerFFLOOR(SDValue Op, SelectionDAG &DAG) const {
2127 SDValue Src = Op.getOperand(0);
2129 // result = trunc(src);
2130 // if (src < 0.0 && src != result)
2133 SDValue Trunc = DAG.getNode(ISD::FTRUNC, SL, MVT::f64, Src);
2135 const SDValue Zero = DAG.getConstantFP(0.0, SL, MVT::f64);
2136 const SDValue NegOne = DAG.getConstantFP(-1.0, SL, MVT::f64);
2139 getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), MVT::f64);
2141 SDValue Lt0 = DAG.getSetCC(SL, SetCCVT, Src, Zero, ISD::SETOLT);
2142 SDValue NeTrunc = DAG.getSetCC(SL, SetCCVT, Src, Trunc, ISD::SETONE);
2143 SDValue And = DAG.getNode(ISD::AND, SL, SetCCVT, Lt0, NeTrunc);
2145 SDValue Add = DAG.getNode(ISD::SELECT, SL, MVT::f64, And, NegOne, Zero);
2146 return DAG.getNode(ISD::FADD, SL, MVT::f64, Trunc, Add);
2149 SDValue AMDGPUTargetLowering::LowerINT_TO_FP64(SDValue Op, SelectionDAG &DAG,
2150 bool Signed) const {
2152 SDValue Src = Op.getOperand(0);
2154 SDValue BC = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, Src);
2156 SDValue Lo = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, BC,
2157 DAG.getConstant(0, SL, MVT::i32));
2158 SDValue Hi = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, BC,
2159 DAG.getConstant(1, SL, MVT::i32));
2161 SDValue CvtHi = DAG.getNode(Signed ? ISD::SINT_TO_FP : ISD::UINT_TO_FP,
2164 SDValue CvtLo = DAG.getNode(ISD::UINT_TO_FP, SL, MVT::f64, Lo);
2166 SDValue LdExp = DAG.getNode(AMDGPUISD::LDEXP, SL, MVT::f64, CvtHi,
2167 DAG.getConstant(32, SL, MVT::i32));
2169 return DAG.getNode(ISD::FADD, SL, MVT::f64, LdExp, CvtLo);
2172 SDValue AMDGPUTargetLowering::LowerUINT_TO_FP(SDValue Op,
2173 SelectionDAG &DAG) const {
2174 SDValue S0 = Op.getOperand(0);
2175 if (S0.getValueType() != MVT::i64)
2178 EVT DestVT = Op.getValueType();
2179 if (DestVT == MVT::f64)
2180 return LowerINT_TO_FP64(Op, DAG, false);
2182 assert(DestVT == MVT::f32);
2186 // f32 uint_to_fp i64
2187 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, S0,
2188 DAG.getConstant(0, DL, MVT::i32));
2189 SDValue FloatLo = DAG.getNode(ISD::UINT_TO_FP, DL, MVT::f32, Lo);
2190 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, S0,
2191 DAG.getConstant(1, DL, MVT::i32));
2192 SDValue FloatHi = DAG.getNode(ISD::UINT_TO_FP, DL, MVT::f32, Hi);
2193 FloatHi = DAG.getNode(ISD::FMUL, DL, MVT::f32, FloatHi,
2194 DAG.getConstantFP(4294967296.0f, DL, MVT::f32)); // 2^32
2195 return DAG.getNode(ISD::FADD, DL, MVT::f32, FloatLo, FloatHi);
2198 SDValue AMDGPUTargetLowering::LowerSINT_TO_FP(SDValue Op,
2199 SelectionDAG &DAG) const {
2200 SDValue Src = Op.getOperand(0);
2201 if (Src.getValueType() == MVT::i64 && Op.getValueType() == MVT::f64)
2202 return LowerINT_TO_FP64(Op, DAG, true);
2207 SDValue AMDGPUTargetLowering::LowerFP64_TO_INT(SDValue Op, SelectionDAG &DAG,
2208 bool Signed) const {
2211 SDValue Src = Op.getOperand(0);
2213 SDValue Trunc = DAG.getNode(ISD::FTRUNC, SL, MVT::f64, Src);
2215 SDValue K0 = DAG.getConstantFP(BitsToDouble(UINT64_C(0x3df0000000000000)), SL,
2217 SDValue K1 = DAG.getConstantFP(BitsToDouble(UINT64_C(0xc1f0000000000000)), SL,
2220 SDValue Mul = DAG.getNode(ISD::FMUL, SL, MVT::f64, Trunc, K0);
2222 SDValue FloorMul = DAG.getNode(ISD::FFLOOR, SL, MVT::f64, Mul);
2225 SDValue Fma = DAG.getNode(ISD::FMA, SL, MVT::f64, FloorMul, K1, Trunc);
2227 SDValue Hi = DAG.getNode(Signed ? ISD::FP_TO_SINT : ISD::FP_TO_UINT, SL,
2228 MVT::i32, FloorMul);
2229 SDValue Lo = DAG.getNode(ISD::FP_TO_UINT, SL, MVT::i32, Fma);
2231 SDValue Result = DAG.getNode(ISD::BUILD_VECTOR, SL, MVT::v2i32, Lo, Hi);
2233 return DAG.getNode(ISD::BITCAST, SL, MVT::i64, Result);
2236 SDValue AMDGPUTargetLowering::LowerFP_TO_SINT(SDValue Op,
2237 SelectionDAG &DAG) const {
2238 SDValue Src = Op.getOperand(0);
2240 if (Op.getValueType() == MVT::i64 && Src.getValueType() == MVT::f64)
2241 return LowerFP64_TO_INT(Op, DAG, true);
2246 SDValue AMDGPUTargetLowering::LowerFP_TO_UINT(SDValue Op,
2247 SelectionDAG &DAG) const {
2248 SDValue Src = Op.getOperand(0);
2250 if (Op.getValueType() == MVT::i64 && Src.getValueType() == MVT::f64)
2251 return LowerFP64_TO_INT(Op, DAG, false);
2256 SDValue AMDGPUTargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op,
2257 SelectionDAG &DAG) const {
2258 EVT ExtraVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
2259 MVT VT = Op.getSimpleValueType();
2260 MVT ScalarVT = VT.getScalarType();
2265 SDValue Src = Op.getOperand(0);
2268 // TODO: Don't scalarize on Evergreen?
2269 unsigned NElts = VT.getVectorNumElements();
2270 SmallVector<SDValue, 8> Args;
2271 DAG.ExtractVectorElements(Src, Args, 0, NElts);
2273 SDValue VTOp = DAG.getValueType(ExtraVT.getScalarType());
2274 for (unsigned I = 0; I < NElts; ++I)
2275 Args[I] = DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, ScalarVT, Args[I], VTOp);
2277 return DAG.getNode(ISD::BUILD_VECTOR, DL, VT, Args);
2280 //===----------------------------------------------------------------------===//
2281 // Custom DAG optimizations
2282 //===----------------------------------------------------------------------===//
2284 static bool isU24(SDValue Op, SelectionDAG &DAG) {
2285 APInt KnownZero, KnownOne;
2286 EVT VT = Op.getValueType();
2287 DAG.computeKnownBits(Op, KnownZero, KnownOne);
2289 return (VT.getSizeInBits() - KnownZero.countLeadingOnes()) <= 24;
2292 static bool isI24(SDValue Op, SelectionDAG &DAG) {
2293 EVT VT = Op.getValueType();
2295 // In order for this to be a signed 24-bit value, bit 23, must
2297 return VT.getSizeInBits() >= 24 && // Types less than 24-bit should be treated
2298 // as unsigned 24-bit values.
2299 (VT.getSizeInBits() - DAG.ComputeNumSignBits(Op)) < 24;
2302 static void simplifyI24(SDValue Op, TargetLowering::DAGCombinerInfo &DCI) {
2304 SelectionDAG &DAG = DCI.DAG;
2305 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2306 EVT VT = Op.getValueType();
2308 APInt Demanded = APInt::getLowBitsSet(VT.getSizeInBits(), 24);
2309 APInt KnownZero, KnownOne;
2310 TargetLowering::TargetLoweringOpt TLO(DAG, true, true);
2311 if (TLI.SimplifyDemandedBits(Op, Demanded, KnownZero, KnownOne, TLO))
2312 DCI.CommitTargetLoweringOpt(TLO);
2315 template <typename IntTy>
2316 static SDValue constantFoldBFE(SelectionDAG &DAG, IntTy Src0,
2317 uint32_t Offset, uint32_t Width, SDLoc DL) {
2318 if (Width + Offset < 32) {
2319 uint32_t Shl = static_cast<uint32_t>(Src0) << (32 - Offset - Width);
2320 IntTy Result = static_cast<IntTy>(Shl) >> (32 - Width);
2321 return DAG.getConstant(Result, DL, MVT::i32);
2324 return DAG.getConstant(Src0 >> Offset, DL, MVT::i32);
2327 static bool usesAllNormalStores(SDNode *LoadVal) {
2328 for (SDNode::use_iterator I = LoadVal->use_begin(); !I.atEnd(); ++I) {
2329 if (!ISD::isNormalStore(*I))
2336 // If we have a copy of an illegal type, replace it with a load / store of an
2337 // equivalently sized legal type. This avoids intermediate bit pack / unpack
2338 // instructions emitted when handling extloads and truncstores. Ideally we could
2339 // recognize the pack / unpack pattern to eliminate it.
2340 SDValue AMDGPUTargetLowering::performStoreCombine(SDNode *N,
2341 DAGCombinerInfo &DCI) const {
2342 if (!DCI.isBeforeLegalize())
2345 StoreSDNode *SN = cast<StoreSDNode>(N);
2346 SDValue Value = SN->getValue();
2347 EVT VT = Value.getValueType();
2349 if (isTypeLegal(VT) || SN->isVolatile() ||
2350 !ISD::isNormalLoad(Value.getNode()) || VT.getSizeInBits() < 8)
2353 LoadSDNode *LoadVal = cast<LoadSDNode>(Value);
2354 if (LoadVal->isVolatile() || !usesAllNormalStores(LoadVal))
2357 EVT MemVT = LoadVal->getMemoryVT();
2360 SelectionDAG &DAG = DCI.DAG;
2361 EVT LoadVT = getEquivalentMemType(*DAG.getContext(), MemVT);
2363 SDValue NewLoad = DAG.getLoad(ISD::UNINDEXED, ISD::NON_EXTLOAD,
2365 LoadVal->getChain(),
2366 LoadVal->getBasePtr(),
2367 LoadVal->getOffset(),
2369 LoadVal->getMemOperand());
2371 SDValue CastLoad = DAG.getNode(ISD::BITCAST, SL, VT, NewLoad.getValue(0));
2372 DCI.CombineTo(LoadVal, CastLoad, NewLoad.getValue(1), false);
2374 return DAG.getStore(SN->getChain(), SL, NewLoad,
2375 SN->getBasePtr(), SN->getMemOperand());
2378 SDValue AMDGPUTargetLowering::performShlCombine(SDNode *N,
2379 DAGCombinerInfo &DCI) const {
2380 if (N->getValueType(0) != MVT::i64)
2383 // i64 (shl x, 32) -> (build_pair 0, x)
2385 // Doing this with moves theoretically helps MI optimizations that understand
2386 // copies. 2 v_mov_b32_e32 will have the same code size / cycle count as
2387 // v_lshl_b64. In the SALU case, I think this is slightly worse since it
2388 // doubles the code size and I'm unsure about cycle count.
2389 const ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N->getOperand(1));
2390 if (!RHS || RHS->getZExtValue() != 32)
2393 SDValue LHS = N->getOperand(0);
2396 SelectionDAG &DAG = DCI.DAG;
2398 // Extract low 32-bits.
2399 SDValue Lo = DAG.getNode(ISD::TRUNCATE, SL, MVT::i32, LHS);
2401 const SDValue Zero = DAG.getConstant(0, SL, MVT::i32);
2402 return DAG.getNode(ISD::BUILD_PAIR, SL, MVT::i64, Zero, Lo);
2405 SDValue AMDGPUTargetLowering::performMulCombine(SDNode *N,
2406 DAGCombinerInfo &DCI) const {
2407 EVT VT = N->getValueType(0);
2409 if (VT.isVector() || VT.getSizeInBits() > 32)
2412 SelectionDAG &DAG = DCI.DAG;
2415 SDValue N0 = N->getOperand(0);
2416 SDValue N1 = N->getOperand(1);
2419 if (Subtarget->hasMulU24() && isU24(N0, DAG) && isU24(N1, DAG)) {
2420 N0 = DAG.getZExtOrTrunc(N0, DL, MVT::i32);
2421 N1 = DAG.getZExtOrTrunc(N1, DL, MVT::i32);
2422 Mul = DAG.getNode(AMDGPUISD::MUL_U24, DL, MVT::i32, N0, N1);
2423 } else if (Subtarget->hasMulI24() && isI24(N0, DAG) && isI24(N1, DAG)) {
2424 N0 = DAG.getSExtOrTrunc(N0, DL, MVT::i32);
2425 N1 = DAG.getSExtOrTrunc(N1, DL, MVT::i32);
2426 Mul = DAG.getNode(AMDGPUISD::MUL_I24, DL, MVT::i32, N0, N1);
2431 // We need to use sext even for MUL_U24, because MUL_U24 is used
2432 // for signed multiply of 8 and 16-bit types.
2433 return DAG.getSExtOrTrunc(Mul, DL, VT);
2436 SDValue AMDGPUTargetLowering::PerformDAGCombine(SDNode *N,
2437 DAGCombinerInfo &DCI) const {
2438 SelectionDAG &DAG = DCI.DAG;
2441 switch(N->getOpcode()) {
2445 if (DCI.getDAGCombineLevel() < AfterLegalizeDAG)
2448 return performShlCombine(N, DCI);
2451 return performMulCombine(N, DCI);
2452 case AMDGPUISD::MUL_I24:
2453 case AMDGPUISD::MUL_U24: {
2454 SDValue N0 = N->getOperand(0);
2455 SDValue N1 = N->getOperand(1);
2456 simplifyI24(N0, DCI);
2457 simplifyI24(N1, DCI);
2461 SDValue Cond = N->getOperand(0);
2462 if (Cond.getOpcode() == ISD::SETCC && Cond.hasOneUse()) {
2463 EVT VT = N->getValueType(0);
2464 SDValue LHS = Cond.getOperand(0);
2465 SDValue RHS = Cond.getOperand(1);
2466 SDValue CC = Cond.getOperand(2);
2468 SDValue True = N->getOperand(1);
2469 SDValue False = N->getOperand(2);
2472 return CombineFMinMaxLegacy(DL, VT, LHS, RHS, True, False, CC, DCI);
2477 case AMDGPUISD::BFE_I32:
2478 case AMDGPUISD::BFE_U32: {
2479 assert(!N->getValueType(0).isVector() &&
2480 "Vector handling of BFE not implemented");
2481 ConstantSDNode *Width = dyn_cast<ConstantSDNode>(N->getOperand(2));
2485 uint32_t WidthVal = Width->getZExtValue() & 0x1f;
2487 return DAG.getConstant(0, DL, MVT::i32);
2489 ConstantSDNode *Offset = dyn_cast<ConstantSDNode>(N->getOperand(1));
2493 SDValue BitsFrom = N->getOperand(0);
2494 uint32_t OffsetVal = Offset->getZExtValue() & 0x1f;
2496 bool Signed = N->getOpcode() == AMDGPUISD::BFE_I32;
2498 if (OffsetVal == 0) {
2499 // This is already sign / zero extended, so try to fold away extra BFEs.
2500 unsigned SignBits = Signed ? (32 - WidthVal + 1) : (32 - WidthVal);
2502 unsigned OpSignBits = DAG.ComputeNumSignBits(BitsFrom);
2503 if (OpSignBits >= SignBits)
2506 EVT SmallVT = EVT::getIntegerVT(*DAG.getContext(), WidthVal);
2508 // This is a sign_extend_inreg. Replace it to take advantage of existing
2509 // DAG Combines. If not eliminated, we will match back to BFE during
2512 // TODO: The sext_inreg of extended types ends, although we can could
2513 // handle them in a single BFE.
2514 return DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, MVT::i32, BitsFrom,
2515 DAG.getValueType(SmallVT));
2518 return DAG.getZeroExtendInReg(BitsFrom, DL, SmallVT);
2521 if (ConstantSDNode *CVal = dyn_cast<ConstantSDNode>(BitsFrom)) {
2523 return constantFoldBFE<int32_t>(DAG,
2524 CVal->getSExtValue(),
2530 return constantFoldBFE<uint32_t>(DAG,
2531 CVal->getZExtValue(),
2537 if ((OffsetVal + WidthVal) >= 32) {
2538 SDValue ShiftVal = DAG.getConstant(OffsetVal, DL, MVT::i32);
2539 return DAG.getNode(Signed ? ISD::SRA : ISD::SRL, DL, MVT::i32,
2540 BitsFrom, ShiftVal);
2543 if (BitsFrom.hasOneUse()) {
2544 APInt Demanded = APInt::getBitsSet(32,
2546 OffsetVal + WidthVal);
2548 APInt KnownZero, KnownOne;
2549 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
2550 !DCI.isBeforeLegalizeOps());
2551 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2552 if (TLO.ShrinkDemandedConstant(BitsFrom, Demanded) ||
2553 TLI.SimplifyDemandedBits(BitsFrom, Demanded,
2554 KnownZero, KnownOne, TLO)) {
2555 DCI.CommitTargetLoweringOpt(TLO);
2563 return performStoreCombine(N, DCI);
2568 //===----------------------------------------------------------------------===//
2570 //===----------------------------------------------------------------------===//
2572 void AMDGPUTargetLowering::getOriginalFunctionArgs(
2575 const SmallVectorImpl<ISD::InputArg> &Ins,
2576 SmallVectorImpl<ISD::InputArg> &OrigIns) const {
2578 for (unsigned i = 0, e = Ins.size(); i < e; ++i) {
2579 if (Ins[i].ArgVT == Ins[i].VT) {
2580 OrigIns.push_back(Ins[i]);
2585 if (Ins[i].ArgVT.isVector() && !Ins[i].VT.isVector()) {
2586 // Vector has been split into scalars.
2587 VT = Ins[i].ArgVT.getVectorElementType();
2588 } else if (Ins[i].VT.isVector() && Ins[i].ArgVT.isVector() &&
2589 Ins[i].ArgVT.getVectorElementType() !=
2590 Ins[i].VT.getVectorElementType()) {
2591 // Vector elements have been promoted
2594 // Vector has been spilt into smaller vectors.
2598 ISD::InputArg Arg(Ins[i].Flags, VT, VT, Ins[i].Used,
2599 Ins[i].OrigArgIndex, Ins[i].PartOffset);
2600 OrigIns.push_back(Arg);
2604 bool AMDGPUTargetLowering::isHWTrueValue(SDValue Op) const {
2605 if (ConstantFPSDNode * CFP = dyn_cast<ConstantFPSDNode>(Op)) {
2606 return CFP->isExactlyValue(1.0);
2608 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
2609 return C->isAllOnesValue();
2614 bool AMDGPUTargetLowering::isHWFalseValue(SDValue Op) const {
2615 if (ConstantFPSDNode * CFP = dyn_cast<ConstantFPSDNode>(Op)) {
2616 return CFP->getValueAPF().isZero();
2618 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
2619 return C->isNullValue();
2624 SDValue AMDGPUTargetLowering::CreateLiveInRegister(SelectionDAG &DAG,
2625 const TargetRegisterClass *RC,
2626 unsigned Reg, EVT VT) const {
2627 MachineFunction &MF = DAG.getMachineFunction();
2628 MachineRegisterInfo &MRI = MF.getRegInfo();
2629 unsigned VirtualRegister;
2630 if (!MRI.isLiveIn(Reg)) {
2631 VirtualRegister = MRI.createVirtualRegister(RC);
2632 MRI.addLiveIn(Reg, VirtualRegister);
2634 VirtualRegister = MRI.getLiveInVirtReg(Reg);
2636 return DAG.getRegister(VirtualRegister, VT);
2639 uint32_t AMDGPUTargetLowering::getImplicitParameterOffset(
2640 const AMDGPUMachineFunction *MFI, const ImplicitParameter Param) const {
2641 uint64_t ArgOffset = MFI->ABIArgOffset;
2646 return ArgOffset + 4;
2648 llvm_unreachable("unexpected implicit parameter type");
2651 #define NODE_NAME_CASE(node) case AMDGPUISD::node: return #node;
2653 const char* AMDGPUTargetLowering::getTargetNodeName(unsigned Opcode) const {
2654 switch ((AMDGPUISD::NodeType)Opcode) {
2655 case AMDGPUISD::FIRST_NUMBER: break;
2657 NODE_NAME_CASE(CALL);
2658 NODE_NAME_CASE(UMUL);
2659 NODE_NAME_CASE(RET_FLAG);
2660 NODE_NAME_CASE(BRANCH_COND);
2663 NODE_NAME_CASE(DWORDADDR)
2664 NODE_NAME_CASE(FRACT)
2665 NODE_NAME_CASE(CLAMP)
2666 NODE_NAME_CASE(COS_HW)
2667 NODE_NAME_CASE(SIN_HW)
2668 NODE_NAME_CASE(FMAX_LEGACY)
2669 NODE_NAME_CASE(FMIN_LEGACY)
2670 NODE_NAME_CASE(FMAX3)
2671 NODE_NAME_CASE(SMAX3)
2672 NODE_NAME_CASE(UMAX3)
2673 NODE_NAME_CASE(FMIN3)
2674 NODE_NAME_CASE(SMIN3)
2675 NODE_NAME_CASE(UMIN3)
2676 NODE_NAME_CASE(URECIP)
2677 NODE_NAME_CASE(DIV_SCALE)
2678 NODE_NAME_CASE(DIV_FMAS)
2679 NODE_NAME_CASE(DIV_FIXUP)
2680 NODE_NAME_CASE(TRIG_PREOP)
2683 NODE_NAME_CASE(RSQ_LEGACY)
2684 NODE_NAME_CASE(RSQ_CLAMPED)
2685 NODE_NAME_CASE(LDEXP)
2686 NODE_NAME_CASE(FP_CLASS)
2687 NODE_NAME_CASE(DOT4)
2688 NODE_NAME_CASE(CARRY)
2689 NODE_NAME_CASE(BORROW)
2690 NODE_NAME_CASE(BFE_U32)
2691 NODE_NAME_CASE(BFE_I32)
2694 NODE_NAME_CASE(BREV)
2695 NODE_NAME_CASE(MUL_U24)
2696 NODE_NAME_CASE(MUL_I24)
2697 NODE_NAME_CASE(MAD_U24)
2698 NODE_NAME_CASE(MAD_I24)
2699 NODE_NAME_CASE(TEXTURE_FETCH)
2700 NODE_NAME_CASE(EXPORT)
2701 NODE_NAME_CASE(CONST_ADDRESS)
2702 NODE_NAME_CASE(REGISTER_LOAD)
2703 NODE_NAME_CASE(REGISTER_STORE)
2704 NODE_NAME_CASE(LOAD_CONSTANT)
2705 NODE_NAME_CASE(LOAD_INPUT)
2706 NODE_NAME_CASE(SAMPLE)
2707 NODE_NAME_CASE(SAMPLEB)
2708 NODE_NAME_CASE(SAMPLED)
2709 NODE_NAME_CASE(SAMPLEL)
2710 NODE_NAME_CASE(CVT_F32_UBYTE0)
2711 NODE_NAME_CASE(CVT_F32_UBYTE1)
2712 NODE_NAME_CASE(CVT_F32_UBYTE2)
2713 NODE_NAME_CASE(CVT_F32_UBYTE3)
2714 NODE_NAME_CASE(BUILD_VERTICAL_VECTOR)
2715 NODE_NAME_CASE(CONST_DATA_PTR)
2716 case AMDGPUISD::FIRST_MEM_OPCODE_NUMBER: break;
2717 NODE_NAME_CASE(SENDMSG)
2718 NODE_NAME_CASE(INTERP_MOV)
2719 NODE_NAME_CASE(INTERP_P1)
2720 NODE_NAME_CASE(INTERP_P2)
2721 NODE_NAME_CASE(STORE_MSKOR)
2722 NODE_NAME_CASE(TBUFFER_STORE_FORMAT)
2723 case AMDGPUISD::LAST_AMDGPU_ISD_NUMBER: break;
2728 SDValue AMDGPUTargetLowering::getRsqrtEstimate(SDValue Operand,
2729 DAGCombinerInfo &DCI,
2730 unsigned &RefinementSteps,
2731 bool &UseOneConstNR) const {
2732 SelectionDAG &DAG = DCI.DAG;
2733 EVT VT = Operand.getValueType();
2735 if (VT == MVT::f32) {
2736 RefinementSteps = 0;
2737 return DAG.getNode(AMDGPUISD::RSQ, SDLoc(Operand), VT, Operand);
2740 // TODO: There is also f64 rsq instruction, but the documentation is less
2741 // clear on its precision.
2746 SDValue AMDGPUTargetLowering::getRecipEstimate(SDValue Operand,
2747 DAGCombinerInfo &DCI,
2748 unsigned &RefinementSteps) const {
2749 SelectionDAG &DAG = DCI.DAG;
2750 EVT VT = Operand.getValueType();
2752 if (VT == MVT::f32) {
2753 // Reciprocal, < 1 ulp error.
2755 // This reciprocal approximation converges to < 0.5 ulp error with one
2756 // newton rhapson performed with two fused multiple adds (FMAs).
2758 RefinementSteps = 0;
2759 return DAG.getNode(AMDGPUISD::RCP, SDLoc(Operand), VT, Operand);
2762 // TODO: There is also f64 rcp instruction, but the documentation is less
2763 // clear on its precision.
2768 static void computeKnownBitsForMinMax(const SDValue Op0,
2772 const SelectionDAG &DAG,
2774 APInt Op0Zero, Op0One;
2775 APInt Op1Zero, Op1One;
2776 DAG.computeKnownBits(Op0, Op0Zero, Op0One, Depth);
2777 DAG.computeKnownBits(Op1, Op1Zero, Op1One, Depth);
2779 KnownZero = Op0Zero & Op1Zero;
2780 KnownOne = Op0One & Op1One;
2783 void AMDGPUTargetLowering::computeKnownBitsForTargetNode(
2787 const SelectionDAG &DAG,
2788 unsigned Depth) const {
2790 KnownZero = KnownOne = APInt(KnownOne.getBitWidth(), 0); // Don't know anything.
2794 unsigned Opc = Op.getOpcode();
2799 case ISD::INTRINSIC_WO_CHAIN: {
2800 // FIXME: The intrinsic should just use the node.
2801 switch (cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue()) {
2802 case AMDGPUIntrinsic::AMDGPU_imax:
2803 case AMDGPUIntrinsic::AMDGPU_umax:
2804 case AMDGPUIntrinsic::AMDGPU_imin:
2805 case AMDGPUIntrinsic::AMDGPU_umin:
2806 computeKnownBitsForMinMax(Op.getOperand(1), Op.getOperand(2),
2807 KnownZero, KnownOne, DAG, Depth);
2815 case AMDGPUISD::CARRY:
2816 case AMDGPUISD::BORROW: {
2817 KnownZero = APInt::getHighBitsSet(32, 31);
2821 case AMDGPUISD::BFE_I32:
2822 case AMDGPUISD::BFE_U32: {
2823 ConstantSDNode *CWidth = dyn_cast<ConstantSDNode>(Op.getOperand(2));
2827 unsigned BitWidth = 32;
2828 uint32_t Width = CWidth->getZExtValue() & 0x1f;
2830 if (Opc == AMDGPUISD::BFE_U32)
2831 KnownZero = APInt::getHighBitsSet(BitWidth, BitWidth - Width);
2838 unsigned AMDGPUTargetLowering::ComputeNumSignBitsForTargetNode(
2840 const SelectionDAG &DAG,
2841 unsigned Depth) const {
2842 switch (Op.getOpcode()) {
2843 case AMDGPUISD::BFE_I32: {
2844 ConstantSDNode *Width = dyn_cast<ConstantSDNode>(Op.getOperand(2));
2848 unsigned SignBits = 32 - Width->getZExtValue() + 1;
2849 ConstantSDNode *Offset = dyn_cast<ConstantSDNode>(Op.getOperand(1));
2850 if (!Offset || !Offset->isNullValue())
2853 // TODO: Could probably figure something out with non-0 offsets.
2854 unsigned Op0SignBits = DAG.ComputeNumSignBits(Op.getOperand(0), Depth + 1);
2855 return std::max(SignBits, Op0SignBits);
2858 case AMDGPUISD::BFE_U32: {
2859 ConstantSDNode *Width = dyn_cast<ConstantSDNode>(Op.getOperand(2));
2860 return Width ? 32 - (Width->getZExtValue() & 0x1f) : 1;
2863 case AMDGPUISD::CARRY:
2864 case AMDGPUISD::BORROW: