1 //===-- AMDGPUISelLowering.cpp - AMDGPU Common DAG lowering functions -----===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// \brief This is the parent TargetLowering class for hardware code gen
14 //===----------------------------------------------------------------------===//
16 #include "AMDGPUISelLowering.h"
18 #include "AMDGPUDiagnosticInfoUnsupported.h"
19 #include "AMDGPUFrameLowering.h"
20 #include "AMDGPUIntrinsicInfo.h"
21 #include "AMDGPURegisterInfo.h"
22 #include "AMDGPUSubtarget.h"
23 #include "R600MachineFunctionInfo.h"
24 #include "SIMachineFunctionInfo.h"
25 #include "llvm/CodeGen/CallingConvLower.h"
26 #include "llvm/CodeGen/MachineFunction.h"
27 #include "llvm/CodeGen/MachineRegisterInfo.h"
28 #include "llvm/CodeGen/SelectionDAG.h"
29 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
30 #include "llvm/IR/DataLayout.h"
34 static bool allocateStack(unsigned ValNo, MVT ValVT, MVT LocVT,
35 CCValAssign::LocInfo LocInfo,
36 ISD::ArgFlagsTy ArgFlags, CCState &State) {
37 unsigned Offset = State.AllocateStack(ValVT.getStoreSize(),
38 ArgFlags.getOrigAlign());
39 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
44 #include "AMDGPUGenCallingConv.inc"
46 // Find a larger type to do a load / store of a vector with.
47 EVT AMDGPUTargetLowering::getEquivalentMemType(LLVMContext &Ctx, EVT VT) {
48 unsigned StoreSize = VT.getStoreSizeInBits();
50 return EVT::getIntegerVT(Ctx, StoreSize);
52 assert(StoreSize % 32 == 0 && "Store size not a multiple of 32");
53 return EVT::getVectorVT(Ctx, MVT::i32, StoreSize / 32);
56 // Type for a vector that will be loaded to.
57 EVT AMDGPUTargetLowering::getEquivalentLoadRegType(LLVMContext &Ctx, EVT VT) {
58 unsigned StoreSize = VT.getStoreSizeInBits();
60 return EVT::getIntegerVT(Ctx, 32);
62 return EVT::getVectorVT(Ctx, MVT::i32, StoreSize / 32);
65 AMDGPUTargetLowering::AMDGPUTargetLowering(TargetMachine &TM,
66 const AMDGPUSubtarget &STI)
67 : TargetLowering(TM), Subtarget(&STI) {
68 setOperationAction(ISD::Constant, MVT::i32, Legal);
69 setOperationAction(ISD::Constant, MVT::i64, Legal);
70 setOperationAction(ISD::ConstantFP, MVT::f32, Legal);
71 setOperationAction(ISD::ConstantFP, MVT::f64, Legal);
73 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
74 setOperationAction(ISD::BRIND, MVT::Other, Expand);
76 // This is totally unsupported, just custom lower to produce an error.
77 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Custom);
79 // We need to custom lower some of the intrinsics
80 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
82 // Library functions. These default to Expand, but we have instructions
84 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
85 setOperationAction(ISD::FEXP2, MVT::f32, Legal);
86 setOperationAction(ISD::FPOW, MVT::f32, Legal);
87 setOperationAction(ISD::FLOG2, MVT::f32, Legal);
88 setOperationAction(ISD::FABS, MVT::f32, Legal);
89 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
90 setOperationAction(ISD::FRINT, MVT::f32, Legal);
91 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
92 setOperationAction(ISD::FMINNUM, MVT::f32, Legal);
93 setOperationAction(ISD::FMAXNUM, MVT::f32, Legal);
95 setOperationAction(ISD::FROUND, MVT::f32, Custom);
96 setOperationAction(ISD::FROUND, MVT::f64, Custom);
98 setOperationAction(ISD::FREM, MVT::f32, Custom);
99 setOperationAction(ISD::FREM, MVT::f64, Custom);
101 // v_mad_f32 does not support denormals according to some sources.
102 if (!Subtarget->hasFP32Denormals())
103 setOperationAction(ISD::FMAD, MVT::f32, Legal);
105 // Expand to fneg + fadd.
106 setOperationAction(ISD::FSUB, MVT::f64, Expand);
108 // Lower floating point store/load to integer store/load to reduce the number
109 // of patterns in tablegen.
110 setOperationAction(ISD::STORE, MVT::f32, Promote);
111 AddPromotedToType(ISD::STORE, MVT::f32, MVT::i32);
113 setOperationAction(ISD::STORE, MVT::v2f32, Promote);
114 AddPromotedToType(ISD::STORE, MVT::v2f32, MVT::v2i32);
116 setOperationAction(ISD::STORE, MVT::v4f32, Promote);
117 AddPromotedToType(ISD::STORE, MVT::v4f32, MVT::v4i32);
119 setOperationAction(ISD::STORE, MVT::v8f32, Promote);
120 AddPromotedToType(ISD::STORE, MVT::v8f32, MVT::v8i32);
122 setOperationAction(ISD::STORE, MVT::v16f32, Promote);
123 AddPromotedToType(ISD::STORE, MVT::v16f32, MVT::v16i32);
125 setOperationAction(ISD::STORE, MVT::f64, Promote);
126 AddPromotedToType(ISD::STORE, MVT::f64, MVT::i64);
128 setOperationAction(ISD::STORE, MVT::v2f64, Promote);
129 AddPromotedToType(ISD::STORE, MVT::v2f64, MVT::v2i64);
131 // Custom lowering of vector stores is required for local address space
133 setOperationAction(ISD::STORE, MVT::v4i32, Custom);
135 setTruncStoreAction(MVT::v2i32, MVT::v2i16, Custom);
136 setTruncStoreAction(MVT::v2i32, MVT::v2i8, Custom);
137 setTruncStoreAction(MVT::v4i32, MVT::v4i8, Custom);
139 // XXX: This can be change to Custom, once ExpandVectorStores can
140 // handle 64-bit stores.
141 setTruncStoreAction(MVT::v4i32, MVT::v4i16, Expand);
143 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
144 setTruncStoreAction(MVT::i64, MVT::i8, Expand);
145 setTruncStoreAction(MVT::i64, MVT::i1, Expand);
146 setTruncStoreAction(MVT::v2i64, MVT::v2i1, Expand);
147 setTruncStoreAction(MVT::v4i64, MVT::v4i1, Expand);
150 setOperationAction(ISD::LOAD, MVT::f32, Promote);
151 AddPromotedToType(ISD::LOAD, MVT::f32, MVT::i32);
153 setOperationAction(ISD::LOAD, MVT::v2f32, Promote);
154 AddPromotedToType(ISD::LOAD, MVT::v2f32, MVT::v2i32);
156 setOperationAction(ISD::LOAD, MVT::v4f32, Promote);
157 AddPromotedToType(ISD::LOAD, MVT::v4f32, MVT::v4i32);
159 setOperationAction(ISD::LOAD, MVT::v8f32, Promote);
160 AddPromotedToType(ISD::LOAD, MVT::v8f32, MVT::v8i32);
162 setOperationAction(ISD::LOAD, MVT::v16f32, Promote);
163 AddPromotedToType(ISD::LOAD, MVT::v16f32, MVT::v16i32);
165 setOperationAction(ISD::LOAD, MVT::f64, Promote);
166 AddPromotedToType(ISD::LOAD, MVT::f64, MVT::i64);
168 setOperationAction(ISD::LOAD, MVT::v2f64, Promote);
169 AddPromotedToType(ISD::LOAD, MVT::v2f64, MVT::v2i64);
171 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i32, Custom);
172 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4f32, Custom);
173 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i32, Custom);
174 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8f32, Custom);
175 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v2f32, Custom);
176 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v2i32, Custom);
177 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v4f32, Custom);
178 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v4i32, Custom);
179 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v8f32, Custom);
180 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v8i32, Custom);
182 // There are no 64-bit extloads. These should be done as a 32-bit extload and
183 // an extension to 64-bit.
184 for (MVT VT : MVT::integer_valuetypes()) {
185 setLoadExtAction(ISD::EXTLOAD, MVT::i64, VT, Expand);
186 setLoadExtAction(ISD::SEXTLOAD, MVT::i64, VT, Expand);
187 setLoadExtAction(ISD::ZEXTLOAD, MVT::i64, VT, Expand);
190 for (MVT VT : MVT::integer_vector_valuetypes()) {
191 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2i8, Expand);
192 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v2i8, Expand);
193 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::v2i8, Expand);
194 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v4i8, Expand);
195 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v4i8, Expand);
196 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::v4i8, Expand);
197 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2i16, Expand);
198 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v2i16, Expand);
199 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::v2i16, Expand);
200 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v4i16, Expand);
201 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v4i16, Expand);
202 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::v4i16, Expand);
205 setOperationAction(ISD::BR_CC, MVT::i1, Expand);
207 if (Subtarget->getGeneration() < AMDGPUSubtarget::SEA_ISLANDS) {
208 setOperationAction(ISD::FCEIL, MVT::f64, Custom);
209 setOperationAction(ISD::FTRUNC, MVT::f64, Custom);
210 setOperationAction(ISD::FRINT, MVT::f64, Custom);
211 setOperationAction(ISD::FFLOOR, MVT::f64, Custom);
214 if (!Subtarget->hasBFI()) {
215 // fcopysign can be done in a single instruction with BFI.
216 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
217 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
220 setOperationAction(ISD::FP16_TO_FP, MVT::f64, Expand);
222 setLoadExtAction(ISD::EXTLOAD, MVT::f32, MVT::f16, Expand);
223 setLoadExtAction(ISD::EXTLOAD, MVT::v2f32, MVT::v2f16, Expand);
224 setLoadExtAction(ISD::EXTLOAD, MVT::v4f32, MVT::v4f16, Expand);
225 setLoadExtAction(ISD::EXTLOAD, MVT::v8f32, MVT::v8f16, Expand);
227 setLoadExtAction(ISD::EXTLOAD, MVT::f64, MVT::f16, Expand);
228 setLoadExtAction(ISD::EXTLOAD, MVT::v2f64, MVT::v2f16, Expand);
229 setLoadExtAction(ISD::EXTLOAD, MVT::v4f64, MVT::v4f16, Expand);
230 setLoadExtAction(ISD::EXTLOAD, MVT::v8f64, MVT::v8f16, Expand);
232 setTruncStoreAction(MVT::f32, MVT::f16, Expand);
233 setTruncStoreAction(MVT::v2f32, MVT::v2f16, Expand);
234 setTruncStoreAction(MVT::v4f32, MVT::v4f16, Expand);
235 setTruncStoreAction(MVT::v8f32, MVT::v8f16, Expand);
237 setTruncStoreAction(MVT::f64, MVT::f16, Expand);
238 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
240 const MVT ScalarIntVTs[] = { MVT::i32, MVT::i64 };
241 for (MVT VT : ScalarIntVTs) {
242 setOperationAction(ISD::SREM, VT, Expand);
243 setOperationAction(ISD::SDIV, VT, Expand);
245 // GPU does not have divrem function for signed or unsigned.
246 setOperationAction(ISD::SDIVREM, VT, Custom);
247 setOperationAction(ISD::UDIVREM, VT, Custom);
249 // GPU does not have [S|U]MUL_LOHI functions as a single instruction.
250 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
251 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
253 setOperationAction(ISD::BSWAP, VT, Expand);
254 setOperationAction(ISD::CTTZ, VT, Expand);
255 setOperationAction(ISD::CTLZ, VT, Expand);
258 if (!Subtarget->hasBCNT(32))
259 setOperationAction(ISD::CTPOP, MVT::i32, Expand);
261 if (!Subtarget->hasBCNT(64))
262 setOperationAction(ISD::CTPOP, MVT::i64, Expand);
264 // The hardware supports 32-bit ROTR, but not ROTL.
265 setOperationAction(ISD::ROTL, MVT::i32, Expand);
266 setOperationAction(ISD::ROTL, MVT::i64, Expand);
267 setOperationAction(ISD::ROTR, MVT::i64, Expand);
269 setOperationAction(ISD::MUL, MVT::i64, Expand);
270 setOperationAction(ISD::MULHU, MVT::i64, Expand);
271 setOperationAction(ISD::MULHS, MVT::i64, Expand);
272 setOperationAction(ISD::UDIV, MVT::i32, Expand);
273 setOperationAction(ISD::UREM, MVT::i32, Expand);
274 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Custom);
275 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
276 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
277 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Custom);
278 setOperationAction(ISD::SELECT_CC, MVT::i64, Expand);
280 setOperationAction(ISD::SMIN, MVT::i32, Legal);
281 setOperationAction(ISD::UMIN, MVT::i32, Legal);
282 setOperationAction(ISD::SMAX, MVT::i32, Legal);
283 setOperationAction(ISD::UMAX, MVT::i32, Legal);
285 if (!Subtarget->hasFFBH())
286 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, Expand);
288 if (!Subtarget->hasFFBL())
289 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32, Expand);
291 static const MVT::SimpleValueType VectorIntTypes[] = {
292 MVT::v2i32, MVT::v4i32
295 for (MVT VT : VectorIntTypes) {
296 // Expand the following operations for the current type by default.
297 setOperationAction(ISD::ADD, VT, Expand);
298 setOperationAction(ISD::AND, VT, Expand);
299 setOperationAction(ISD::FP_TO_SINT, VT, Expand);
300 setOperationAction(ISD::FP_TO_UINT, VT, Expand);
301 setOperationAction(ISD::MUL, VT, Expand);
302 setOperationAction(ISD::OR, VT, Expand);
303 setOperationAction(ISD::SHL, VT, Expand);
304 setOperationAction(ISD::SRA, VT, Expand);
305 setOperationAction(ISD::SRL, VT, Expand);
306 setOperationAction(ISD::ROTL, VT, Expand);
307 setOperationAction(ISD::ROTR, VT, Expand);
308 setOperationAction(ISD::SUB, VT, Expand);
309 setOperationAction(ISD::SINT_TO_FP, VT, Expand);
310 setOperationAction(ISD::UINT_TO_FP, VT, Expand);
311 setOperationAction(ISD::SDIV, VT, Expand);
312 setOperationAction(ISD::UDIV, VT, Expand);
313 setOperationAction(ISD::SREM, VT, Expand);
314 setOperationAction(ISD::UREM, VT, Expand);
315 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
316 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
317 setOperationAction(ISD::SDIVREM, VT, Custom);
318 setOperationAction(ISD::UDIVREM, VT, Expand);
319 setOperationAction(ISD::ADDC, VT, Expand);
320 setOperationAction(ISD::SUBC, VT, Expand);
321 setOperationAction(ISD::ADDE, VT, Expand);
322 setOperationAction(ISD::SUBE, VT, Expand);
323 setOperationAction(ISD::SELECT, VT, Expand);
324 setOperationAction(ISD::VSELECT, VT, Expand);
325 setOperationAction(ISD::SELECT_CC, VT, Expand);
326 setOperationAction(ISD::XOR, VT, Expand);
327 setOperationAction(ISD::BSWAP, VT, Expand);
328 setOperationAction(ISD::CTPOP, VT, Expand);
329 setOperationAction(ISD::CTTZ, VT, Expand);
330 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand);
331 setOperationAction(ISD::CTLZ, VT, Expand);
332 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand);
333 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Expand);
336 static const MVT::SimpleValueType FloatVectorTypes[] = {
337 MVT::v2f32, MVT::v4f32
340 for (MVT VT : FloatVectorTypes) {
341 setOperationAction(ISD::FABS, VT, Expand);
342 setOperationAction(ISD::FMINNUM, VT, Expand);
343 setOperationAction(ISD::FMAXNUM, VT, Expand);
344 setOperationAction(ISD::FADD, VT, Expand);
345 setOperationAction(ISD::FCEIL, VT, Expand);
346 setOperationAction(ISD::FCOS, VT, Expand);
347 setOperationAction(ISD::FDIV, VT, Expand);
348 setOperationAction(ISD::FEXP2, VT, Expand);
349 setOperationAction(ISD::FLOG2, VT, Expand);
350 setOperationAction(ISD::FREM, VT, Expand);
351 setOperationAction(ISD::FPOW, VT, Expand);
352 setOperationAction(ISD::FFLOOR, VT, Expand);
353 setOperationAction(ISD::FTRUNC, VT, Expand);
354 setOperationAction(ISD::FMUL, VT, Expand);
355 setOperationAction(ISD::FMA, VT, Expand);
356 setOperationAction(ISD::FRINT, VT, Expand);
357 setOperationAction(ISD::FNEARBYINT, VT, Expand);
358 setOperationAction(ISD::FSQRT, VT, Expand);
359 setOperationAction(ISD::FSIN, VT, Expand);
360 setOperationAction(ISD::FSUB, VT, Expand);
361 setOperationAction(ISD::FNEG, VT, Expand);
362 setOperationAction(ISD::SELECT, VT, Expand);
363 setOperationAction(ISD::VSELECT, VT, Expand);
364 setOperationAction(ISD::SELECT_CC, VT, Expand);
365 setOperationAction(ISD::FCOPYSIGN, VT, Expand);
366 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Expand);
369 setOperationAction(ISD::FNEARBYINT, MVT::f32, Custom);
370 setOperationAction(ISD::FNEARBYINT, MVT::f64, Custom);
372 setTargetDAGCombine(ISD::SHL);
373 setTargetDAGCombine(ISD::MUL);
374 setTargetDAGCombine(ISD::SELECT);
375 setTargetDAGCombine(ISD::SELECT_CC);
376 setTargetDAGCombine(ISD::STORE);
378 setTargetDAGCombine(ISD::FADD);
379 setTargetDAGCombine(ISD::FSUB);
381 setBooleanContents(ZeroOrNegativeOneBooleanContent);
382 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
384 setSchedulingPreference(Sched::RegPressure);
385 setJumpIsExpensive(true);
387 // SI at least has hardware support for floating point exceptions, but no way
388 // of using or handling them is implemented. They are also optional in OpenCL
390 setHasFloatingPointExceptions(false);
392 setSelectIsExpensive(false);
393 PredictableSelectIsExpensive = false;
395 setFsqrtIsCheap(true);
397 // We want to find all load dependencies for long chains of stores to enable
398 // merging into very wide vectors. The problem is with vectors with > 4
399 // elements. MergeConsecutiveStores will attempt to merge these because x8/x16
400 // vectors are a legal type, even though we have to split the loads
401 // usually. When we can more precisely specify load legality per address
402 // space, we should be able to make FindBetterChain/MergeConsecutiveStores
403 // smarter so that they can figure out what to do in 2 iterations without all
404 // N > 4 stores on the same chain.
405 GatherAllAliasesMaxDepth = 16;
407 // FIXME: Need to really handle these.
408 MaxStoresPerMemcpy = 4096;
409 MaxStoresPerMemmove = 4096;
410 MaxStoresPerMemset = 4096;
413 //===----------------------------------------------------------------------===//
414 // Target Information
415 //===----------------------------------------------------------------------===//
417 MVT AMDGPUTargetLowering::getVectorIdxTy(const DataLayout &) const {
421 bool AMDGPUTargetLowering::isSelectSupported(SelectSupportKind SelType) const {
425 // The backend supports 32 and 64 bit floating point immediates.
426 // FIXME: Why are we reporting vectors of FP immediates as legal?
427 bool AMDGPUTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
428 EVT ScalarVT = VT.getScalarType();
429 return (ScalarVT == MVT::f32 || ScalarVT == MVT::f64);
432 // We don't want to shrink f64 / f32 constants.
433 bool AMDGPUTargetLowering::ShouldShrinkFPConstant(EVT VT) const {
434 EVT ScalarVT = VT.getScalarType();
435 return (ScalarVT != MVT::f32 && ScalarVT != MVT::f64);
438 bool AMDGPUTargetLowering::shouldReduceLoadWidth(SDNode *N,
442 unsigned NewSize = NewVT.getStoreSizeInBits();
444 // If we are reducing to a 32-bit load, this is always better.
448 EVT OldVT = N->getValueType(0);
449 unsigned OldSize = OldVT.getStoreSizeInBits();
451 // Don't produce extloads from sub 32-bit types. SI doesn't have scalar
452 // extloads, so doing one requires using a buffer_load. In cases where we
453 // still couldn't use a scalar load, using the wider load shouldn't really
456 // If the old size already had to be an extload, there's no harm in continuing
457 // to reduce the width.
458 return (OldSize < 32);
461 bool AMDGPUTargetLowering::isLoadBitCastBeneficial(EVT LoadTy,
463 if (LoadTy.getSizeInBits() != CastTy.getSizeInBits())
466 unsigned LScalarSize = LoadTy.getScalarType().getSizeInBits();
467 unsigned CastScalarSize = CastTy.getScalarType().getSizeInBits();
469 return ((LScalarSize <= CastScalarSize) ||
470 (CastScalarSize >= 32) ||
474 // SI+ has instructions for cttz / ctlz for 32-bit values. This is probably also
475 // profitable with the expansion for 64-bit since it's generally good to
477 // FIXME: These should really have the size as a parameter.
478 bool AMDGPUTargetLowering::isCheapToSpeculateCttz() const {
482 bool AMDGPUTargetLowering::isCheapToSpeculateCtlz() const {
486 //===---------------------------------------------------------------------===//
488 //===---------------------------------------------------------------------===//
490 bool AMDGPUTargetLowering::isFAbsFree(EVT VT) const {
491 assert(VT.isFloatingPoint());
492 return VT == MVT::f32 || VT == MVT::f64;
495 bool AMDGPUTargetLowering::isFNegFree(EVT VT) const {
496 assert(VT.isFloatingPoint());
497 return VT == MVT::f32 || VT == MVT::f64;
500 bool AMDGPUTargetLowering:: storeOfVectorConstantIsCheap(EVT MemVT,
506 bool AMDGPUTargetLowering::aggressivelyPreferBuildVectorSources(EVT VecVT) const {
507 // There are few operations which truly have vector input operands. Any vector
508 // operation is going to involve operations on each component, and a
509 // build_vector will be a copy per element, so it always makes sense to use a
510 // build_vector input in place of the extracted element to avoid a copy into a
513 // We should probably only do this if all users are extracts only, but this
514 // should be the common case.
518 bool AMDGPUTargetLowering::isTruncateFree(EVT Source, EVT Dest) const {
519 // Truncate is just accessing a subregister.
520 return Dest.bitsLT(Source) && (Dest.getSizeInBits() % 32 == 0);
523 bool AMDGPUTargetLowering::isTruncateFree(Type *Source, Type *Dest) const {
524 // Truncate is just accessing a subregister.
525 return Dest->getPrimitiveSizeInBits() < Source->getPrimitiveSizeInBits() &&
526 (Dest->getPrimitiveSizeInBits() % 32 == 0);
529 bool AMDGPUTargetLowering::isZExtFree(Type *Src, Type *Dest) const {
530 unsigned SrcSize = Src->getScalarSizeInBits();
531 unsigned DestSize = Dest->getScalarSizeInBits();
533 return SrcSize == 32 && DestSize == 64;
536 bool AMDGPUTargetLowering::isZExtFree(EVT Src, EVT Dest) const {
537 // Any register load of a 64-bit value really requires 2 32-bit moves. For all
538 // practical purposes, the extra mov 0 to load a 64-bit is free. As used,
539 // this will enable reducing 64-bit operations the 32-bit, which is always
541 return Src == MVT::i32 && Dest == MVT::i64;
544 bool AMDGPUTargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
545 return isZExtFree(Val.getValueType(), VT2);
548 bool AMDGPUTargetLowering::isNarrowingProfitable(EVT SrcVT, EVT DestVT) const {
549 // There aren't really 64-bit registers, but pairs of 32-bit ones and only a
550 // limited number of native 64-bit operations. Shrinking an operation to fit
551 // in a single 32-bit register should always be helpful. As currently used,
552 // this is much less general than the name suggests, and is only used in
553 // places trying to reduce the sizes of loads. Shrinking loads to < 32-bits is
554 // not profitable, and may actually be harmful.
555 return SrcVT.getSizeInBits() > 32 && DestVT.getSizeInBits() == 32;
558 //===---------------------------------------------------------------------===//
559 // TargetLowering Callbacks
560 //===---------------------------------------------------------------------===//
562 void AMDGPUTargetLowering::AnalyzeFormalArguments(CCState &State,
563 const SmallVectorImpl<ISD::InputArg> &Ins) const {
565 State.AnalyzeFormalArguments(Ins, CC_AMDGPU);
568 SDValue AMDGPUTargetLowering::LowerReturn(
570 CallingConv::ID CallConv,
572 const SmallVectorImpl<ISD::OutputArg> &Outs,
573 const SmallVectorImpl<SDValue> &OutVals,
574 SDLoc DL, SelectionDAG &DAG) const {
575 return DAG.getNode(AMDGPUISD::RET_FLAG, DL, MVT::Other, Chain);
578 //===---------------------------------------------------------------------===//
579 // Target specific lowering
580 //===---------------------------------------------------------------------===//
582 SDValue AMDGPUTargetLowering::LowerCall(CallLoweringInfo &CLI,
583 SmallVectorImpl<SDValue> &InVals) const {
584 SDValue Callee = CLI.Callee;
585 SelectionDAG &DAG = CLI.DAG;
587 const Function &Fn = *DAG.getMachineFunction().getFunction();
589 StringRef FuncName("<unknown>");
591 if (const ExternalSymbolSDNode *G = dyn_cast<ExternalSymbolSDNode>(Callee))
592 FuncName = G->getSymbol();
593 else if (const GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
594 FuncName = G->getGlobal()->getName();
596 DiagnosticInfoUnsupported NoCalls(Fn, "call to function " + FuncName);
597 DAG.getContext()->diagnose(NoCalls);
601 SDValue AMDGPUTargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
602 SelectionDAG &DAG) const {
603 const Function &Fn = *DAG.getMachineFunction().getFunction();
605 DiagnosticInfoUnsupported NoDynamicAlloca(Fn, "dynamic alloca");
606 DAG.getContext()->diagnose(NoDynamicAlloca);
610 SDValue AMDGPUTargetLowering::LowerOperation(SDValue Op,
611 SelectionDAG &DAG) const {
612 switch (Op.getOpcode()) {
614 Op.getNode()->dump();
615 llvm_unreachable("Custom lowering code for this"
616 "instruction is not implemented yet!");
618 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op, DAG);
619 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
620 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op, DAG);
621 case ISD::FrameIndex: return LowerFrameIndex(Op, DAG);
622 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
623 case ISD::UDIVREM: return LowerUDIVREM(Op, DAG);
624 case ISD::SDIVREM: return LowerSDIVREM(Op, DAG);
625 case ISD::FREM: return LowerFREM(Op, DAG);
626 case ISD::FCEIL: return LowerFCEIL(Op, DAG);
627 case ISD::FTRUNC: return LowerFTRUNC(Op, DAG);
628 case ISD::FRINT: return LowerFRINT(Op, DAG);
629 case ISD::FNEARBYINT: return LowerFNEARBYINT(Op, DAG);
630 case ISD::FROUND: return LowerFROUND(Op, DAG);
631 case ISD::FFLOOR: return LowerFFLOOR(Op, DAG);
632 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
633 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
634 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
635 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG);
636 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
641 void AMDGPUTargetLowering::ReplaceNodeResults(SDNode *N,
642 SmallVectorImpl<SDValue> &Results,
643 SelectionDAG &DAG) const {
644 switch (N->getOpcode()) {
645 case ISD::SIGN_EXTEND_INREG:
646 // Different parts of legalization seem to interpret which type of
647 // sign_extend_inreg is the one to check for custom lowering. The extended
648 // from type is what really matters, but some places check for custom
649 // lowering of the result type. This results in trying to use
650 // ReplaceNodeResults to sext_in_reg to an illegal type, so we'll just do
651 // nothing here and let the illegal result integer be handled normally.
654 SDNode *Node = LowerLOAD(SDValue(N, 0), DAG).getNode();
658 Results.push_back(SDValue(Node, 0));
659 Results.push_back(SDValue(Node, 1));
660 // XXX: LLVM seems not to replace Chain Value inside CustomWidenLowerNode
662 DAG.ReplaceAllUsesOfValueWith(SDValue(N,1), SDValue(Node, 1));
666 SDValue Lowered = LowerSTORE(SDValue(N, 0), DAG);
667 if (Lowered.getNode())
668 Results.push_back(Lowered);
676 // FIXME: This implements accesses to initialized globals in the constant
677 // address space by copying them to private and accessing that. It does not
678 // properly handle illegal types or vectors. The private vector loads are not
679 // scalarized, and the illegal scalars hit an assertion. This technique will not
680 // work well with large initializers, and this should eventually be
681 // removed. Initialized globals should be placed into a data section that the
682 // runtime will load into a buffer before the kernel is executed. Uses of the
683 // global need to be replaced with a pointer loaded from an implicit kernel
684 // argument into this buffer holding the copy of the data, which will remove the
685 // need for any of this.
686 SDValue AMDGPUTargetLowering::LowerConstantInitializer(const Constant* Init,
687 const GlobalValue *GV,
688 const SDValue &InitPtr,
690 SelectionDAG &DAG) const {
691 const DataLayout &TD = DAG.getDataLayout();
693 Type *InitTy = Init->getType();
695 if (const ConstantInt *CI = dyn_cast<ConstantInt>(Init)) {
696 EVT VT = EVT::getEVT(InitTy);
697 PointerType *PtrTy = PointerType::get(InitTy, AMDGPUAS::PRIVATE_ADDRESS);
698 return DAG.getStore(Chain, DL, DAG.getConstant(*CI, DL, VT), InitPtr,
699 MachinePointerInfo(UndefValue::get(PtrTy)), false,
700 false, TD.getPrefTypeAlignment(InitTy));
703 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(Init)) {
704 EVT VT = EVT::getEVT(CFP->getType());
705 PointerType *PtrTy = PointerType::get(CFP->getType(), 0);
706 return DAG.getStore(Chain, DL, DAG.getConstantFP(*CFP, DL, VT), InitPtr,
707 MachinePointerInfo(UndefValue::get(PtrTy)), false,
708 false, TD.getPrefTypeAlignment(CFP->getType()));
711 if (StructType *ST = dyn_cast<StructType>(InitTy)) {
712 const StructLayout *SL = TD.getStructLayout(ST);
714 EVT PtrVT = InitPtr.getValueType();
715 SmallVector<SDValue, 8> Chains;
717 for (unsigned I = 0, N = ST->getNumElements(); I != N; ++I) {
718 SDValue Offset = DAG.getConstant(SL->getElementOffset(I), DL, PtrVT);
719 SDValue Ptr = DAG.getNode(ISD::ADD, DL, PtrVT, InitPtr, Offset);
721 Constant *Elt = Init->getAggregateElement(I);
722 Chains.push_back(LowerConstantInitializer(Elt, GV, Ptr, Chain, DAG));
725 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Chains);
728 if (SequentialType *SeqTy = dyn_cast<SequentialType>(InitTy)) {
729 EVT PtrVT = InitPtr.getValueType();
731 unsigned NumElements;
732 if (ArrayType *AT = dyn_cast<ArrayType>(SeqTy))
733 NumElements = AT->getNumElements();
734 else if (VectorType *VT = dyn_cast<VectorType>(SeqTy))
735 NumElements = VT->getNumElements();
737 llvm_unreachable("Unexpected type");
739 unsigned EltSize = TD.getTypeAllocSize(SeqTy->getElementType());
740 SmallVector<SDValue, 8> Chains;
741 for (unsigned i = 0; i < NumElements; ++i) {
742 SDValue Offset = DAG.getConstant(i * EltSize, DL, PtrVT);
743 SDValue Ptr = DAG.getNode(ISD::ADD, DL, PtrVT, InitPtr, Offset);
745 Constant *Elt = Init->getAggregateElement(i);
746 Chains.push_back(LowerConstantInitializer(Elt, GV, Ptr, Chain, DAG));
749 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Chains);
752 if (isa<UndefValue>(Init)) {
753 EVT VT = EVT::getEVT(InitTy);
754 PointerType *PtrTy = PointerType::get(InitTy, AMDGPUAS::PRIVATE_ADDRESS);
755 return DAG.getStore(Chain, DL, DAG.getUNDEF(VT), InitPtr,
756 MachinePointerInfo(UndefValue::get(PtrTy)), false,
757 false, TD.getPrefTypeAlignment(InitTy));
761 llvm_unreachable("Unhandled constant initializer");
764 static bool hasDefinedInitializer(const GlobalValue *GV) {
765 const GlobalVariable *GVar = dyn_cast<GlobalVariable>(GV);
766 if (!GVar || !GVar->hasInitializer())
769 if (isa<UndefValue>(GVar->getInitializer()))
775 SDValue AMDGPUTargetLowering::LowerGlobalAddress(AMDGPUMachineFunction* MFI,
777 SelectionDAG &DAG) const {
779 const DataLayout &DL = DAG.getDataLayout();
780 GlobalAddressSDNode *G = cast<GlobalAddressSDNode>(Op);
781 const GlobalValue *GV = G->getGlobal();
783 switch (G->getAddressSpace()) {
784 case AMDGPUAS::LOCAL_ADDRESS: {
785 // XXX: What does the value of G->getOffset() mean?
786 assert(G->getOffset() == 0 &&
787 "Do not know what to do with an non-zero offset");
789 // TODO: We could emit code to handle the initialization somewhere.
790 if (hasDefinedInitializer(GV))
794 if (MFI->LocalMemoryObjects.count(GV) == 0) {
795 uint64_t Size = DL.getTypeAllocSize(GV->getType()->getElementType());
796 Offset = MFI->LDSSize;
797 MFI->LocalMemoryObjects[GV] = Offset;
798 // XXX: Account for alignment?
799 MFI->LDSSize += Size;
801 Offset = MFI->LocalMemoryObjects[GV];
804 return DAG.getConstant(Offset, SDLoc(Op),
805 getPointerTy(DL, AMDGPUAS::LOCAL_ADDRESS));
807 case AMDGPUAS::CONSTANT_ADDRESS: {
808 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo();
809 Type *EltType = GV->getType()->getElementType();
810 unsigned Size = DL.getTypeAllocSize(EltType);
811 unsigned Alignment = DL.getPrefTypeAlignment(EltType);
813 MVT PrivPtrVT = getPointerTy(DL, AMDGPUAS::PRIVATE_ADDRESS);
814 MVT ConstPtrVT = getPointerTy(DL, AMDGPUAS::CONSTANT_ADDRESS);
816 int FI = FrameInfo->CreateStackObject(Size, Alignment, false);
817 SDValue InitPtr = DAG.getFrameIndex(FI, PrivPtrVT);
819 const GlobalVariable *Var = cast<GlobalVariable>(GV);
820 if (!Var->hasInitializer()) {
821 // This has no use, but bugpoint will hit it.
822 return DAG.getZExtOrTrunc(InitPtr, SDLoc(Op), ConstPtrVT);
825 const Constant *Init = Var->getInitializer();
826 SmallVector<SDNode*, 8> WorkList;
828 for (SDNode::use_iterator I = DAG.getEntryNode()->use_begin(),
829 E = DAG.getEntryNode()->use_end(); I != E; ++I) {
830 if (I->getOpcode() != AMDGPUISD::REGISTER_LOAD && I->getOpcode() != ISD::LOAD)
832 WorkList.push_back(*I);
834 SDValue Chain = LowerConstantInitializer(Init, GV, InitPtr, DAG.getEntryNode(), DAG);
835 for (SmallVector<SDNode*, 8>::iterator I = WorkList.begin(),
836 E = WorkList.end(); I != E; ++I) {
837 SmallVector<SDValue, 8> Ops;
838 Ops.push_back(Chain);
839 for (unsigned i = 1; i < (*I)->getNumOperands(); ++i) {
840 Ops.push_back((*I)->getOperand(i));
842 DAG.UpdateNodeOperands(*I, Ops);
844 return DAG.getZExtOrTrunc(InitPtr, SDLoc(Op), ConstPtrVT);
848 const Function &Fn = *DAG.getMachineFunction().getFunction();
849 DiagnosticInfoUnsupported BadInit(Fn,
850 "initializer for address space");
851 DAG.getContext()->diagnose(BadInit);
855 SDValue AMDGPUTargetLowering::LowerCONCAT_VECTORS(SDValue Op,
856 SelectionDAG &DAG) const {
857 SmallVector<SDValue, 8> Args;
859 for (const SDUse &U : Op->ops())
860 DAG.ExtractVectorElements(U.get(), Args);
862 return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(Op), Op.getValueType(), Args);
865 SDValue AMDGPUTargetLowering::LowerEXTRACT_SUBVECTOR(SDValue Op,
866 SelectionDAG &DAG) const {
868 SmallVector<SDValue, 8> Args;
869 unsigned Start = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
870 EVT VT = Op.getValueType();
871 DAG.ExtractVectorElements(Op.getOperand(0), Args, Start,
872 VT.getVectorNumElements());
874 return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(Op), Op.getValueType(), Args);
877 SDValue AMDGPUTargetLowering::LowerFrameIndex(SDValue Op,
878 SelectionDAG &DAG) const {
880 MachineFunction &MF = DAG.getMachineFunction();
881 const AMDGPUFrameLowering *TFL = Subtarget->getFrameLowering();
883 FrameIndexSDNode *FIN = cast<FrameIndexSDNode>(Op);
885 unsigned FrameIndex = FIN->getIndex();
886 unsigned IgnoredFrameReg;
888 TFL->getFrameIndexReference(MF, FrameIndex, IgnoredFrameReg);
889 return DAG.getConstant(Offset * 4 * TFL->getStackWidth(MF), SDLoc(Op),
893 SDValue AMDGPUTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
894 SelectionDAG &DAG) const {
895 unsigned IntrinsicID = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
897 EVT VT = Op.getValueType();
899 switch (IntrinsicID) {
901 case AMDGPUIntrinsic::AMDGPU_abs:
902 case AMDGPUIntrinsic::AMDIL_abs: // Legacy name.
903 return LowerIntrinsicIABS(Op, DAG);
904 case AMDGPUIntrinsic::AMDGPU_lrp:
905 return LowerIntrinsicLRP(Op, DAG);
907 case AMDGPUIntrinsic::AMDGPU_clamp:
908 case AMDGPUIntrinsic::AMDIL_clamp: // Legacy name.
909 return DAG.getNode(AMDGPUISD::CLAMP, DL, VT,
910 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
912 case Intrinsic::AMDGPU_div_scale: {
913 // 3rd parameter required to be a constant.
914 const ConstantSDNode *Param = dyn_cast<ConstantSDNode>(Op.getOperand(3));
916 return DAG.getUNDEF(VT);
918 // Translate to the operands expected by the machine instruction. The
919 // first parameter must be the same as the first instruction.
920 SDValue Numerator = Op.getOperand(1);
921 SDValue Denominator = Op.getOperand(2);
923 // Note this order is opposite of the machine instruction's operations,
924 // which is s0.f = Quotient, s1.f = Denominator, s2.f = Numerator. The
925 // intrinsic has the numerator as the first operand to match a normal
926 // division operation.
928 SDValue Src0 = Param->isAllOnesValue() ? Numerator : Denominator;
930 return DAG.getNode(AMDGPUISD::DIV_SCALE, DL, Op->getVTList(), Src0,
931 Denominator, Numerator);
934 case Intrinsic::AMDGPU_div_fmas:
935 return DAG.getNode(AMDGPUISD::DIV_FMAS, DL, VT,
936 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3),
939 case Intrinsic::AMDGPU_div_fixup:
940 return DAG.getNode(AMDGPUISD::DIV_FIXUP, DL, VT,
941 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
943 case Intrinsic::AMDGPU_trig_preop:
944 return DAG.getNode(AMDGPUISD::TRIG_PREOP, DL, VT,
945 Op.getOperand(1), Op.getOperand(2));
947 case Intrinsic::AMDGPU_rcp:
948 return DAG.getNode(AMDGPUISD::RCP, DL, VT, Op.getOperand(1));
950 case Intrinsic::AMDGPU_rsq:
951 return DAG.getNode(AMDGPUISD::RSQ, DL, VT, Op.getOperand(1));
953 case AMDGPUIntrinsic::AMDGPU_legacy_rsq:
954 return DAG.getNode(AMDGPUISD::RSQ_LEGACY, DL, VT, Op.getOperand(1));
956 case Intrinsic::AMDGPU_rsq_clamped:
957 if (Subtarget->getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS) {
958 Type *Type = VT.getTypeForEVT(*DAG.getContext());
959 APFloat Max = APFloat::getLargest(Type->getFltSemantics());
960 APFloat Min = APFloat::getLargest(Type->getFltSemantics(), true);
962 SDValue Rsq = DAG.getNode(AMDGPUISD::RSQ, DL, VT, Op.getOperand(1));
963 SDValue Tmp = DAG.getNode(ISD::FMINNUM, DL, VT, Rsq,
964 DAG.getConstantFP(Max, DL, VT));
965 return DAG.getNode(ISD::FMAXNUM, DL, VT, Tmp,
966 DAG.getConstantFP(Min, DL, VT));
968 return DAG.getNode(AMDGPUISD::RSQ_CLAMPED, DL, VT, Op.getOperand(1));
971 case Intrinsic::AMDGPU_ldexp:
972 return DAG.getNode(AMDGPUISD::LDEXP, DL, VT, Op.getOperand(1),
975 case AMDGPUIntrinsic::AMDGPU_imax:
976 return DAG.getNode(ISD::SMAX, DL, VT, Op.getOperand(1),
978 case AMDGPUIntrinsic::AMDGPU_umax:
979 return DAG.getNode(ISD::UMAX, DL, VT, Op.getOperand(1),
981 case AMDGPUIntrinsic::AMDGPU_imin:
982 return DAG.getNode(ISD::SMIN, DL, VT, Op.getOperand(1),
984 case AMDGPUIntrinsic::AMDGPU_umin:
985 return DAG.getNode(ISD::UMIN, DL, VT, Op.getOperand(1),
988 case AMDGPUIntrinsic::AMDGPU_umul24:
989 return DAG.getNode(AMDGPUISD::MUL_U24, DL, VT,
990 Op.getOperand(1), Op.getOperand(2));
992 case AMDGPUIntrinsic::AMDGPU_imul24:
993 return DAG.getNode(AMDGPUISD::MUL_I24, DL, VT,
994 Op.getOperand(1), Op.getOperand(2));
996 case AMDGPUIntrinsic::AMDGPU_umad24:
997 return DAG.getNode(AMDGPUISD::MAD_U24, DL, VT,
998 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
1000 case AMDGPUIntrinsic::AMDGPU_imad24:
1001 return DAG.getNode(AMDGPUISD::MAD_I24, DL, VT,
1002 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
1004 case AMDGPUIntrinsic::AMDGPU_cvt_f32_ubyte0:
1005 return DAG.getNode(AMDGPUISD::CVT_F32_UBYTE0, DL, VT, Op.getOperand(1));
1007 case AMDGPUIntrinsic::AMDGPU_cvt_f32_ubyte1:
1008 return DAG.getNode(AMDGPUISD::CVT_F32_UBYTE1, DL, VT, Op.getOperand(1));
1010 case AMDGPUIntrinsic::AMDGPU_cvt_f32_ubyte2:
1011 return DAG.getNode(AMDGPUISD::CVT_F32_UBYTE2, DL, VT, Op.getOperand(1));
1013 case AMDGPUIntrinsic::AMDGPU_cvt_f32_ubyte3:
1014 return DAG.getNode(AMDGPUISD::CVT_F32_UBYTE3, DL, VT, Op.getOperand(1));
1016 case AMDGPUIntrinsic::AMDGPU_bfe_i32:
1017 return DAG.getNode(AMDGPUISD::BFE_I32, DL, VT,
1022 case AMDGPUIntrinsic::AMDGPU_bfe_u32:
1023 return DAG.getNode(AMDGPUISD::BFE_U32, DL, VT,
1028 case AMDGPUIntrinsic::AMDGPU_bfi:
1029 return DAG.getNode(AMDGPUISD::BFI, DL, VT,
1034 case AMDGPUIntrinsic::AMDGPU_bfm:
1035 return DAG.getNode(AMDGPUISD::BFM, DL, VT,
1039 case AMDGPUIntrinsic::AMDGPU_brev:
1040 return DAG.getNode(AMDGPUISD::BREV, DL, VT, Op.getOperand(1));
1042 case Intrinsic::AMDGPU_class:
1043 return DAG.getNode(AMDGPUISD::FP_CLASS, DL, VT,
1044 Op.getOperand(1), Op.getOperand(2));
1046 case AMDGPUIntrinsic::AMDIL_exp: // Legacy name.
1047 return DAG.getNode(ISD::FEXP2, DL, VT, Op.getOperand(1));
1049 case AMDGPUIntrinsic::AMDIL_round_nearest: // Legacy name.
1050 return DAG.getNode(ISD::FRINT, DL, VT, Op.getOperand(1));
1051 case AMDGPUIntrinsic::AMDGPU_trunc: // Legacy name.
1052 return DAG.getNode(ISD::FTRUNC, DL, VT, Op.getOperand(1));
1056 ///IABS(a) = SMAX(sub(0, a), a)
1057 SDValue AMDGPUTargetLowering::LowerIntrinsicIABS(SDValue Op,
1058 SelectionDAG &DAG) const {
1060 EVT VT = Op.getValueType();
1061 SDValue Neg = DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, DL, VT),
1064 return DAG.getNode(ISD::SMAX, DL, VT, Neg, Op.getOperand(1));
1067 /// Linear Interpolation
1068 /// LRP(a, b, c) = muladd(a, b, (1 - a) * c)
1069 SDValue AMDGPUTargetLowering::LowerIntrinsicLRP(SDValue Op,
1070 SelectionDAG &DAG) const {
1072 EVT VT = Op.getValueType();
1073 // TODO: Should this propagate fast-math-flags?
1074 SDValue OneSubA = DAG.getNode(ISD::FSUB, DL, VT,
1075 DAG.getConstantFP(1.0f, DL, MVT::f32),
1077 SDValue OneSubAC = DAG.getNode(ISD::FMUL, DL, VT, OneSubA,
1079 return DAG.getNode(ISD::FADD, DL, VT,
1080 DAG.getNode(ISD::FMUL, DL, VT, Op.getOperand(1), Op.getOperand(2)),
1084 /// \brief Generate Min/Max node
1085 SDValue AMDGPUTargetLowering::CombineFMinMaxLegacy(SDLoc DL,
1092 DAGCombinerInfo &DCI) const {
1093 if (Subtarget->getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS)
1096 if (!(LHS == True && RHS == False) && !(LHS == False && RHS == True))
1099 SelectionDAG &DAG = DCI.DAG;
1100 ISD::CondCode CCOpcode = cast<CondCodeSDNode>(CC)->get();
1109 case ISD::SETFALSE2:
1118 return DAG.getNode(AMDGPUISD::FMIN_LEGACY, DL, VT, RHS, LHS);
1119 return DAG.getNode(AMDGPUISD::FMAX_LEGACY, DL, VT, LHS, RHS);
1125 // Ordered. Assume ordered for undefined.
1127 // Only do this after legalization to avoid interfering with other combines
1128 // which might occur.
1129 if (DCI.getDAGCombineLevel() < AfterLegalizeDAG &&
1130 !DCI.isCalledByLegalizer())
1133 // We need to permute the operands to get the correct NaN behavior. The
1134 // selected operand is the second one based on the failing compare with NaN,
1135 // so permute it based on the compare type the hardware uses.
1137 return DAG.getNode(AMDGPUISD::FMIN_LEGACY, DL, VT, LHS, RHS);
1138 return DAG.getNode(AMDGPUISD::FMAX_LEGACY, DL, VT, RHS, LHS);
1143 return DAG.getNode(AMDGPUISD::FMAX_LEGACY, DL, VT, RHS, LHS);
1144 return DAG.getNode(AMDGPUISD::FMIN_LEGACY, DL, VT, LHS, RHS);
1150 if (DCI.getDAGCombineLevel() < AfterLegalizeDAG &&
1151 !DCI.isCalledByLegalizer())
1155 return DAG.getNode(AMDGPUISD::FMAX_LEGACY, DL, VT, LHS, RHS);
1156 return DAG.getNode(AMDGPUISD::FMIN_LEGACY, DL, VT, RHS, LHS);
1158 case ISD::SETCC_INVALID:
1159 llvm_unreachable("Invalid setcc condcode!");
1164 SDValue AMDGPUTargetLowering::ScalarizeVectorLoad(const SDValue Op,
1165 SelectionDAG &DAG) const {
1166 LoadSDNode *Load = cast<LoadSDNode>(Op);
1167 EVT MemVT = Load->getMemoryVT();
1168 EVT MemEltVT = MemVT.getVectorElementType();
1170 EVT LoadVT = Op.getValueType();
1171 EVT EltVT = LoadVT.getVectorElementType();
1172 EVT PtrVT = Load->getBasePtr().getValueType();
1174 unsigned NumElts = Load->getMemoryVT().getVectorNumElements();
1175 SmallVector<SDValue, 8> Loads;
1176 SmallVector<SDValue, 8> Chains;
1179 unsigned MemEltSize = MemEltVT.getStoreSize();
1180 MachinePointerInfo SrcValue(Load->getMemOperand()->getValue());
1182 for (unsigned i = 0; i < NumElts; ++i) {
1183 SDValue Ptr = DAG.getNode(ISD::ADD, SL, PtrVT, Load->getBasePtr(),
1184 DAG.getConstant(i * MemEltSize, SL, PtrVT));
1187 = DAG.getExtLoad(Load->getExtensionType(), SL, EltVT,
1188 Load->getChain(), Ptr,
1189 SrcValue.getWithOffset(i * MemEltSize),
1190 MemEltVT, Load->isVolatile(), Load->isNonTemporal(),
1191 Load->isInvariant(), Load->getAlignment());
1192 Loads.push_back(NewLoad.getValue(0));
1193 Chains.push_back(NewLoad.getValue(1));
1197 DAG.getNode(ISD::BUILD_VECTOR, SL, LoadVT, Loads),
1198 DAG.getNode(ISD::TokenFactor, SL, MVT::Other, Chains)
1201 return DAG.getMergeValues(Ops, SL);
1204 SDValue AMDGPUTargetLowering::SplitVectorLoad(const SDValue Op,
1205 SelectionDAG &DAG) const {
1206 EVT VT = Op.getValueType();
1208 // If this is a 2 element vector, we really want to scalarize and not create
1209 // weird 1 element vectors.
1210 if (VT.getVectorNumElements() == 2)
1211 return ScalarizeVectorLoad(Op, DAG);
1213 LoadSDNode *Load = cast<LoadSDNode>(Op);
1214 SDValue BasePtr = Load->getBasePtr();
1215 EVT PtrVT = BasePtr.getValueType();
1216 EVT MemVT = Load->getMemoryVT();
1218 MachinePointerInfo SrcValue(Load->getMemOperand()->getValue());
1221 EVT LoMemVT, HiMemVT;
1224 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(VT);
1225 std::tie(LoMemVT, HiMemVT) = DAG.GetSplitDestVTs(MemVT);
1226 std::tie(Lo, Hi) = DAG.SplitVector(Op, SL, LoVT, HiVT);
1228 = DAG.getExtLoad(Load->getExtensionType(), SL, LoVT,
1229 Load->getChain(), BasePtr,
1231 LoMemVT, Load->isVolatile(), Load->isNonTemporal(),
1232 Load->isInvariant(), Load->getAlignment());
1234 SDValue HiPtr = DAG.getNode(ISD::ADD, SL, PtrVT, BasePtr,
1235 DAG.getConstant(LoMemVT.getStoreSize(), SL,
1239 = DAG.getExtLoad(Load->getExtensionType(), SL, HiVT,
1240 Load->getChain(), HiPtr,
1241 SrcValue.getWithOffset(LoMemVT.getStoreSize()),
1242 HiMemVT, Load->isVolatile(), Load->isNonTemporal(),
1243 Load->isInvariant(), Load->getAlignment());
1246 DAG.getNode(ISD::CONCAT_VECTORS, SL, VT, LoLoad, HiLoad),
1247 DAG.getNode(ISD::TokenFactor, SL, MVT::Other,
1248 LoLoad.getValue(1), HiLoad.getValue(1))
1251 return DAG.getMergeValues(Ops, SL);
1254 SDValue AMDGPUTargetLowering::MergeVectorStore(const SDValue &Op,
1255 SelectionDAG &DAG) const {
1256 StoreSDNode *Store = cast<StoreSDNode>(Op);
1257 EVT MemVT = Store->getMemoryVT();
1258 unsigned MemBits = MemVT.getSizeInBits();
1260 // Byte stores are really expensive, so if possible, try to pack 32-bit vector
1261 // truncating store into an i32 store.
1262 // XXX: We could also handle optimize other vector bitwidths.
1263 if (!MemVT.isVector() || MemBits > 32) {
1268 SDValue Value = Store->getValue();
1269 EVT VT = Value.getValueType();
1270 EVT ElemVT = VT.getVectorElementType();
1271 SDValue Ptr = Store->getBasePtr();
1272 EVT MemEltVT = MemVT.getVectorElementType();
1273 unsigned MemEltBits = MemEltVT.getSizeInBits();
1274 unsigned MemNumElements = MemVT.getVectorNumElements();
1275 unsigned PackedSize = MemVT.getStoreSizeInBits();
1276 SDValue Mask = DAG.getConstant((1 << MemEltBits) - 1, DL, MVT::i32);
1278 assert(Value.getValueType().getScalarSizeInBits() >= 32);
1280 SDValue PackedValue;
1281 for (unsigned i = 0; i < MemNumElements; ++i) {
1282 SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, ElemVT, Value,
1283 DAG.getConstant(i, DL, MVT::i32));
1284 Elt = DAG.getZExtOrTrunc(Elt, DL, MVT::i32);
1285 Elt = DAG.getNode(ISD::AND, DL, MVT::i32, Elt, Mask); // getZeroExtendInReg
1287 SDValue Shift = DAG.getConstant(MemEltBits * i, DL, MVT::i32);
1288 Elt = DAG.getNode(ISD::SHL, DL, MVT::i32, Elt, Shift);
1293 PackedValue = DAG.getNode(ISD::OR, DL, MVT::i32, PackedValue, Elt);
1297 if (PackedSize < 32) {
1298 EVT PackedVT = EVT::getIntegerVT(*DAG.getContext(), PackedSize);
1299 return DAG.getTruncStore(Store->getChain(), DL, PackedValue, Ptr,
1300 Store->getMemOperand()->getPointerInfo(),
1302 Store->isNonTemporal(), Store->isVolatile(),
1303 Store->getAlignment());
1306 return DAG.getStore(Store->getChain(), DL, PackedValue, Ptr,
1307 Store->getMemOperand()->getPointerInfo(),
1308 Store->isVolatile(), Store->isNonTemporal(),
1309 Store->getAlignment());
1312 SDValue AMDGPUTargetLowering::ScalarizeVectorStore(SDValue Op,
1313 SelectionDAG &DAG) const {
1314 StoreSDNode *Store = cast<StoreSDNode>(Op);
1315 EVT MemEltVT = Store->getMemoryVT().getVectorElementType();
1316 EVT EltVT = Store->getValue().getValueType().getVectorElementType();
1317 EVT PtrVT = Store->getBasePtr().getValueType();
1318 unsigned NumElts = Store->getMemoryVT().getVectorNumElements();
1321 SmallVector<SDValue, 8> Chains;
1323 unsigned EltSize = MemEltVT.getStoreSize();
1324 MachinePointerInfo SrcValue(Store->getMemOperand()->getValue());
1326 for (unsigned i = 0, e = NumElts; i != e; ++i) {
1327 SDValue Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, EltVT,
1329 DAG.getConstant(i, SL, MVT::i32));
1331 SDValue Offset = DAG.getConstant(i * MemEltVT.getStoreSize(), SL, PtrVT);
1332 SDValue Ptr = DAG.getNode(ISD::ADD, SL, PtrVT, Store->getBasePtr(), Offset);
1334 DAG.getTruncStore(Store->getChain(), SL, Val, Ptr,
1335 SrcValue.getWithOffset(i * EltSize),
1336 MemEltVT, Store->isNonTemporal(), Store->isVolatile(),
1337 Store->getAlignment());
1338 Chains.push_back(NewStore);
1341 return DAG.getNode(ISD::TokenFactor, SL, MVT::Other, Chains);
1344 SDValue AMDGPUTargetLowering::SplitVectorStore(SDValue Op,
1345 SelectionDAG &DAG) const {
1346 StoreSDNode *Store = cast<StoreSDNode>(Op);
1347 SDValue Val = Store->getValue();
1348 EVT VT = Val.getValueType();
1350 // If this is a 2 element vector, we really want to scalarize and not create
1351 // weird 1 element vectors.
1352 if (VT.getVectorNumElements() == 2)
1353 return ScalarizeVectorStore(Op, DAG);
1355 EVT MemVT = Store->getMemoryVT();
1356 SDValue Chain = Store->getChain();
1357 SDValue BasePtr = Store->getBasePtr();
1361 EVT LoMemVT, HiMemVT;
1364 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(VT);
1365 std::tie(LoMemVT, HiMemVT) = DAG.GetSplitDestVTs(MemVT);
1366 std::tie(Lo, Hi) = DAG.SplitVector(Val, SL, LoVT, HiVT);
1368 EVT PtrVT = BasePtr.getValueType();
1369 SDValue HiPtr = DAG.getNode(ISD::ADD, SL, PtrVT, BasePtr,
1370 DAG.getConstant(LoMemVT.getStoreSize(), SL,
1373 MachinePointerInfo SrcValue(Store->getMemOperand()->getValue());
1375 = DAG.getTruncStore(Chain, SL, Lo,
1379 Store->isNonTemporal(),
1380 Store->isVolatile(),
1381 Store->getAlignment());
1383 = DAG.getTruncStore(Chain, SL, Hi,
1385 SrcValue.getWithOffset(LoMemVT.getStoreSize()),
1387 Store->isNonTemporal(),
1388 Store->isVolatile(),
1389 Store->getAlignment());
1391 return DAG.getNode(ISD::TokenFactor, SL, MVT::Other, LoStore, HiStore);
1395 SDValue AMDGPUTargetLowering::LowerLOAD(SDValue Op, SelectionDAG &DAG) const {
1397 LoadSDNode *Load = cast<LoadSDNode>(Op);
1398 ISD::LoadExtType ExtType = Load->getExtensionType();
1399 EVT VT = Op.getValueType();
1400 EVT MemVT = Load->getMemoryVT();
1402 if (ExtType == ISD::NON_EXTLOAD && VT.getSizeInBits() < 32) {
1403 assert(VT == MVT::i1 && "Only i1 non-extloads expected");
1404 // FIXME: Copied from PPC
1405 // First, load into 32 bits, then truncate to 1 bit.
1407 SDValue Chain = Load->getChain();
1408 SDValue BasePtr = Load->getBasePtr();
1409 MachineMemOperand *MMO = Load->getMemOperand();
1411 SDValue NewLD = DAG.getExtLoad(ISD::EXTLOAD, DL, MVT::i32, Chain,
1412 BasePtr, MVT::i8, MMO);
1415 DAG.getNode(ISD::TRUNCATE, DL, VT, NewLD),
1419 return DAG.getMergeValues(Ops, DL);
1422 if (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS ||
1423 Load->getAddressSpace() != AMDGPUAS::PRIVATE_ADDRESS ||
1424 ExtType == ISD::NON_EXTLOAD || Load->getMemoryVT().bitsGE(MVT::i32))
1427 // <SI && AS=PRIVATE && EXTLOAD && size < 32bit,
1428 // register (2-)byte extract.
1430 // Get Register holding the target.
1431 SDValue Ptr = DAG.getNode(ISD::SRL, DL, MVT::i32, Load->getBasePtr(),
1432 DAG.getConstant(2, DL, MVT::i32));
1433 // Load the Register.
1434 SDValue Ret = DAG.getNode(AMDGPUISD::REGISTER_LOAD, DL, Op.getValueType(),
1435 Load->getChain(), Ptr,
1436 DAG.getTargetConstant(0, DL, MVT::i32),
1439 // Get offset within the register.
1440 SDValue ByteIdx = DAG.getNode(ISD::AND, DL, MVT::i32,
1442 DAG.getConstant(0x3, DL, MVT::i32));
1444 // Bit offset of target byte (byteIdx * 8).
1445 SDValue ShiftAmt = DAG.getNode(ISD::SHL, DL, MVT::i32, ByteIdx,
1446 DAG.getConstant(3, DL, MVT::i32));
1448 // Shift to the right.
1449 Ret = DAG.getNode(ISD::SRL, DL, MVT::i32, Ret, ShiftAmt);
1451 // Eliminate the upper bits by setting them to ...
1452 EVT MemEltVT = MemVT.getScalarType();
1455 if (ExtType == ISD::SEXTLOAD) {
1456 SDValue MemEltVTNode = DAG.getValueType(MemEltVT);
1459 DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, MVT::i32, Ret, MemEltVTNode),
1463 return DAG.getMergeValues(Ops, DL);
1468 DAG.getZeroExtendInReg(Ret, DL, MemEltVT),
1472 return DAG.getMergeValues(Ops, DL);
1475 SDValue AMDGPUTargetLowering::LowerSTORE(SDValue Op, SelectionDAG &DAG) const {
1477 SDValue Result = AMDGPUTargetLowering::MergeVectorStore(Op, DAG);
1478 if (Result.getNode()) {
1482 StoreSDNode *Store = cast<StoreSDNode>(Op);
1483 SDValue Chain = Store->getChain();
1484 if ((Store->getAddressSpace() == AMDGPUAS::LOCAL_ADDRESS ||
1485 Store->getAddressSpace() == AMDGPUAS::PRIVATE_ADDRESS) &&
1486 Store->getValue().getValueType().isVector()) {
1487 return SplitVectorStore(Op, DAG);
1490 EVT MemVT = Store->getMemoryVT();
1491 if (Store->getAddressSpace() == AMDGPUAS::PRIVATE_ADDRESS &&
1492 MemVT.bitsLT(MVT::i32)) {
1494 if (Store->getMemoryVT() == MVT::i8) {
1496 } else if (Store->getMemoryVT() == MVT::i16) {
1499 SDValue BasePtr = Store->getBasePtr();
1500 SDValue Ptr = DAG.getNode(ISD::SRL, DL, MVT::i32, BasePtr,
1501 DAG.getConstant(2, DL, MVT::i32));
1502 SDValue Dst = DAG.getNode(AMDGPUISD::REGISTER_LOAD, DL, MVT::i32,
1504 DAG.getTargetConstant(0, DL, MVT::i32));
1506 SDValue ByteIdx = DAG.getNode(ISD::AND, DL, MVT::i32, BasePtr,
1507 DAG.getConstant(0x3, DL, MVT::i32));
1509 SDValue ShiftAmt = DAG.getNode(ISD::SHL, DL, MVT::i32, ByteIdx,
1510 DAG.getConstant(3, DL, MVT::i32));
1512 SDValue SExtValue = DAG.getNode(ISD::SIGN_EXTEND, DL, MVT::i32,
1515 SDValue MaskedValue = DAG.getZeroExtendInReg(SExtValue, DL, MemVT);
1517 SDValue ShiftedValue = DAG.getNode(ISD::SHL, DL, MVT::i32,
1518 MaskedValue, ShiftAmt);
1520 SDValue DstMask = DAG.getNode(ISD::SHL, DL, MVT::i32,
1521 DAG.getConstant(Mask, DL, MVT::i32),
1523 DstMask = DAG.getNode(ISD::XOR, DL, MVT::i32, DstMask,
1524 DAG.getConstant(0xffffffff, DL, MVT::i32));
1525 Dst = DAG.getNode(ISD::AND, DL, MVT::i32, Dst, DstMask);
1527 SDValue Value = DAG.getNode(ISD::OR, DL, MVT::i32, Dst, ShiftedValue);
1528 return DAG.getNode(AMDGPUISD::REGISTER_STORE, DL, MVT::Other,
1530 DAG.getTargetConstant(0, DL, MVT::i32));
1535 // This is a shortcut for integer division because we have fast i32<->f32
1536 // conversions, and fast f32 reciprocal instructions. The fractional part of a
1537 // float is enough to accurately represent up to a 24-bit integer.
1538 SDValue AMDGPUTargetLowering::LowerDIVREM24(SDValue Op, SelectionDAG &DAG, bool sign) const {
1540 EVT VT = Op.getValueType();
1541 SDValue LHS = Op.getOperand(0);
1542 SDValue RHS = Op.getOperand(1);
1543 MVT IntVT = MVT::i32;
1544 MVT FltVT = MVT::f32;
1546 ISD::NodeType ToFp = sign ? ISD::SINT_TO_FP : ISD::UINT_TO_FP;
1547 ISD::NodeType ToInt = sign ? ISD::FP_TO_SINT : ISD::FP_TO_UINT;
1549 if (VT.isVector()) {
1550 unsigned NElts = VT.getVectorNumElements();
1551 IntVT = MVT::getVectorVT(MVT::i32, NElts);
1552 FltVT = MVT::getVectorVT(MVT::f32, NElts);
1555 unsigned BitSize = VT.getScalarType().getSizeInBits();
1557 SDValue jq = DAG.getConstant(1, DL, IntVT);
1560 // char|short jq = ia ^ ib;
1561 jq = DAG.getNode(ISD::XOR, DL, VT, LHS, RHS);
1563 // jq = jq >> (bitsize - 2)
1564 jq = DAG.getNode(ISD::SRA, DL, VT, jq,
1565 DAG.getConstant(BitSize - 2, DL, VT));
1568 jq = DAG.getNode(ISD::OR, DL, VT, jq, DAG.getConstant(1, DL, VT));
1571 jq = DAG.getSExtOrTrunc(jq, DL, IntVT);
1574 // int ia = (int)LHS;
1576 DAG.getSExtOrTrunc(LHS, DL, IntVT) : DAG.getZExtOrTrunc(LHS, DL, IntVT);
1578 // int ib, (int)RHS;
1580 DAG.getSExtOrTrunc(RHS, DL, IntVT) : DAG.getZExtOrTrunc(RHS, DL, IntVT);
1582 // float fa = (float)ia;
1583 SDValue fa = DAG.getNode(ToFp, DL, FltVT, ia);
1585 // float fb = (float)ib;
1586 SDValue fb = DAG.getNode(ToFp, DL, FltVT, ib);
1588 // TODO: Should this propagate fast-math-flags?
1589 // float fq = native_divide(fa, fb);
1590 SDValue fq = DAG.getNode(ISD::FMUL, DL, FltVT,
1591 fa, DAG.getNode(AMDGPUISD::RCP, DL, FltVT, fb));
1594 fq = DAG.getNode(ISD::FTRUNC, DL, FltVT, fq);
1596 // float fqneg = -fq;
1597 SDValue fqneg = DAG.getNode(ISD::FNEG, DL, FltVT, fq);
1599 // float fr = mad(fqneg, fb, fa);
1600 SDValue fr = DAG.getNode(ISD::FADD, DL, FltVT,
1601 DAG.getNode(ISD::FMUL, DL, FltVT, fqneg, fb), fa);
1603 // int iq = (int)fq;
1604 SDValue iq = DAG.getNode(ToInt, DL, IntVT, fq);
1607 fr = DAG.getNode(ISD::FABS, DL, FltVT, fr);
1610 fb = DAG.getNode(ISD::FABS, DL, FltVT, fb);
1612 EVT SetCCVT = getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT);
1614 // int cv = fr >= fb;
1615 SDValue cv = DAG.getSetCC(DL, SetCCVT, fr, fb, ISD::SETOGE);
1617 // jq = (cv ? jq : 0);
1618 jq = DAG.getNode(ISD::SELECT, DL, VT, cv, jq, DAG.getConstant(0, DL, VT));
1620 // dst = trunc/extend to legal type
1621 iq = sign ? DAG.getSExtOrTrunc(iq, DL, VT) : DAG.getZExtOrTrunc(iq, DL, VT);
1624 SDValue Div = DAG.getNode(ISD::ADD, DL, VT, iq, jq);
1626 // Rem needs compensation, it's easier to recompute it
1627 SDValue Rem = DAG.getNode(ISD::MUL, DL, VT, Div, RHS);
1628 Rem = DAG.getNode(ISD::SUB, DL, VT, LHS, Rem);
1634 return DAG.getMergeValues(Res, DL);
1637 void AMDGPUTargetLowering::LowerUDIVREM64(SDValue Op,
1639 SmallVectorImpl<SDValue> &Results) const {
1640 assert(Op.getValueType() == MVT::i64);
1643 EVT VT = Op.getValueType();
1644 EVT HalfVT = VT.getHalfSizedIntegerVT(*DAG.getContext());
1646 SDValue one = DAG.getConstant(1, DL, HalfVT);
1647 SDValue zero = DAG.getConstant(0, DL, HalfVT);
1650 SDValue LHS = Op.getOperand(0);
1651 SDValue LHS_Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, LHS, zero);
1652 SDValue LHS_Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, LHS, one);
1654 SDValue RHS = Op.getOperand(1);
1655 SDValue RHS_Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, RHS, zero);
1656 SDValue RHS_Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, RHS, one);
1658 if (VT == MVT::i64 &&
1659 DAG.MaskedValueIsZero(RHS, APInt::getHighBitsSet(64, 32)) &&
1660 DAG.MaskedValueIsZero(LHS, APInt::getHighBitsSet(64, 32))) {
1662 SDValue Res = DAG.getNode(ISD::UDIVREM, DL, DAG.getVTList(HalfVT, HalfVT),
1665 SDValue DIV = DAG.getNode(ISD::BUILD_PAIR, DL, VT, Res.getValue(0), zero);
1666 SDValue REM = DAG.getNode(ISD::BUILD_PAIR, DL, VT, Res.getValue(1), zero);
1667 Results.push_back(DIV);
1668 Results.push_back(REM);
1672 // Get Speculative values
1673 SDValue DIV_Part = DAG.getNode(ISD::UDIV, DL, HalfVT, LHS_Hi, RHS_Lo);
1674 SDValue REM_Part = DAG.getNode(ISD::UREM, DL, HalfVT, LHS_Hi, RHS_Lo);
1676 SDValue REM_Lo = DAG.getSelectCC(DL, RHS_Hi, zero, REM_Part, LHS_Hi, ISD::SETEQ);
1677 SDValue REM = DAG.getNode(ISD::BUILD_PAIR, DL, VT, REM_Lo, zero);
1679 SDValue DIV_Hi = DAG.getSelectCC(DL, RHS_Hi, zero, DIV_Part, zero, ISD::SETEQ);
1680 SDValue DIV_Lo = zero;
1682 const unsigned halfBitWidth = HalfVT.getSizeInBits();
1684 for (unsigned i = 0; i < halfBitWidth; ++i) {
1685 const unsigned bitPos = halfBitWidth - i - 1;
1686 SDValue POS = DAG.getConstant(bitPos, DL, HalfVT);
1687 // Get value of high bit
1688 SDValue HBit = DAG.getNode(ISD::SRL, DL, HalfVT, LHS_Lo, POS);
1689 HBit = DAG.getNode(ISD::AND, DL, HalfVT, HBit, one);
1690 HBit = DAG.getNode(ISD::ZERO_EXTEND, DL, VT, HBit);
1693 REM = DAG.getNode(ISD::SHL, DL, VT, REM, DAG.getConstant(1, DL, VT));
1695 REM = DAG.getNode(ISD::OR, DL, VT, REM, HBit);
1697 SDValue BIT = DAG.getConstant(1 << bitPos, DL, HalfVT);
1698 SDValue realBIT = DAG.getSelectCC(DL, REM, RHS, BIT, zero, ISD::SETUGE);
1700 DIV_Lo = DAG.getNode(ISD::OR, DL, HalfVT, DIV_Lo, realBIT);
1703 SDValue REM_sub = DAG.getNode(ISD::SUB, DL, VT, REM, RHS);
1704 REM = DAG.getSelectCC(DL, REM, RHS, REM_sub, REM, ISD::SETUGE);
1707 SDValue DIV = DAG.getNode(ISD::BUILD_PAIR, DL, VT, DIV_Lo, DIV_Hi);
1708 Results.push_back(DIV);
1709 Results.push_back(REM);
1712 SDValue AMDGPUTargetLowering::LowerUDIVREM(SDValue Op,
1713 SelectionDAG &DAG) const {
1715 EVT VT = Op.getValueType();
1717 if (VT == MVT::i64) {
1718 SmallVector<SDValue, 2> Results;
1719 LowerUDIVREM64(Op, DAG, Results);
1720 return DAG.getMergeValues(Results, DL);
1723 SDValue Num = Op.getOperand(0);
1724 SDValue Den = Op.getOperand(1);
1726 if (VT == MVT::i32) {
1727 if (DAG.MaskedValueIsZero(Num, APInt::getHighBitsSet(32, 8)) &&
1728 DAG.MaskedValueIsZero(Den, APInt::getHighBitsSet(32, 8))) {
1729 // TODO: We technically could do this for i64, but shouldn't that just be
1730 // handled by something generally reducing 64-bit division on 32-bit
1731 // values to 32-bit?
1732 return LowerDIVREM24(Op, DAG, false);
1736 // RCP = URECIP(Den) = 2^32 / Den + e
1737 // e is rounding error.
1738 SDValue RCP = DAG.getNode(AMDGPUISD::URECIP, DL, VT, Den);
1740 // RCP_LO = mul(RCP, Den) */
1741 SDValue RCP_LO = DAG.getNode(ISD::MUL, DL, VT, RCP, Den);
1743 // RCP_HI = mulhu (RCP, Den) */
1744 SDValue RCP_HI = DAG.getNode(ISD::MULHU, DL, VT, RCP, Den);
1746 // NEG_RCP_LO = -RCP_LO
1747 SDValue NEG_RCP_LO = DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, DL, VT),
1750 // ABS_RCP_LO = (RCP_HI == 0 ? NEG_RCP_LO : RCP_LO)
1751 SDValue ABS_RCP_LO = DAG.getSelectCC(DL, RCP_HI, DAG.getConstant(0, DL, VT),
1754 // Calculate the rounding error from the URECIP instruction
1755 // E = mulhu(ABS_RCP_LO, RCP)
1756 SDValue E = DAG.getNode(ISD::MULHU, DL, VT, ABS_RCP_LO, RCP);
1758 // RCP_A_E = RCP + E
1759 SDValue RCP_A_E = DAG.getNode(ISD::ADD, DL, VT, RCP, E);
1761 // RCP_S_E = RCP - E
1762 SDValue RCP_S_E = DAG.getNode(ISD::SUB, DL, VT, RCP, E);
1764 // Tmp0 = (RCP_HI == 0 ? RCP_A_E : RCP_SUB_E)
1765 SDValue Tmp0 = DAG.getSelectCC(DL, RCP_HI, DAG.getConstant(0, DL, VT),
1768 // Quotient = mulhu(Tmp0, Num)
1769 SDValue Quotient = DAG.getNode(ISD::MULHU, DL, VT, Tmp0, Num);
1771 // Num_S_Remainder = Quotient * Den
1772 SDValue Num_S_Remainder = DAG.getNode(ISD::MUL, DL, VT, Quotient, Den);
1774 // Remainder = Num - Num_S_Remainder
1775 SDValue Remainder = DAG.getNode(ISD::SUB, DL, VT, Num, Num_S_Remainder);
1777 // Remainder_GE_Den = (Remainder >= Den ? -1 : 0)
1778 SDValue Remainder_GE_Den = DAG.getSelectCC(DL, Remainder, Den,
1779 DAG.getConstant(-1, DL, VT),
1780 DAG.getConstant(0, DL, VT),
1782 // Remainder_GE_Zero = (Num >= Num_S_Remainder ? -1 : 0)
1783 SDValue Remainder_GE_Zero = DAG.getSelectCC(DL, Num,
1785 DAG.getConstant(-1, DL, VT),
1786 DAG.getConstant(0, DL, VT),
1788 // Tmp1 = Remainder_GE_Den & Remainder_GE_Zero
1789 SDValue Tmp1 = DAG.getNode(ISD::AND, DL, VT, Remainder_GE_Den,
1792 // Calculate Division result:
1794 // Quotient_A_One = Quotient + 1
1795 SDValue Quotient_A_One = DAG.getNode(ISD::ADD, DL, VT, Quotient,
1796 DAG.getConstant(1, DL, VT));
1798 // Quotient_S_One = Quotient - 1
1799 SDValue Quotient_S_One = DAG.getNode(ISD::SUB, DL, VT, Quotient,
1800 DAG.getConstant(1, DL, VT));
1802 // Div = (Tmp1 == 0 ? Quotient : Quotient_A_One)
1803 SDValue Div = DAG.getSelectCC(DL, Tmp1, DAG.getConstant(0, DL, VT),
1804 Quotient, Quotient_A_One, ISD::SETEQ);
1806 // Div = (Remainder_GE_Zero == 0 ? Quotient_S_One : Div)
1807 Div = DAG.getSelectCC(DL, Remainder_GE_Zero, DAG.getConstant(0, DL, VT),
1808 Quotient_S_One, Div, ISD::SETEQ);
1810 // Calculate Rem result:
1812 // Remainder_S_Den = Remainder - Den
1813 SDValue Remainder_S_Den = DAG.getNode(ISD::SUB, DL, VT, Remainder, Den);
1815 // Remainder_A_Den = Remainder + Den
1816 SDValue Remainder_A_Den = DAG.getNode(ISD::ADD, DL, VT, Remainder, Den);
1818 // Rem = (Tmp1 == 0 ? Remainder : Remainder_S_Den)
1819 SDValue Rem = DAG.getSelectCC(DL, Tmp1, DAG.getConstant(0, DL, VT),
1820 Remainder, Remainder_S_Den, ISD::SETEQ);
1822 // Rem = (Remainder_GE_Zero == 0 ? Remainder_A_Den : Rem)
1823 Rem = DAG.getSelectCC(DL, Remainder_GE_Zero, DAG.getConstant(0, DL, VT),
1824 Remainder_A_Den, Rem, ISD::SETEQ);
1829 return DAG.getMergeValues(Ops, DL);
1832 SDValue AMDGPUTargetLowering::LowerSDIVREM(SDValue Op,
1833 SelectionDAG &DAG) const {
1835 EVT VT = Op.getValueType();
1837 SDValue LHS = Op.getOperand(0);
1838 SDValue RHS = Op.getOperand(1);
1840 SDValue Zero = DAG.getConstant(0, DL, VT);
1841 SDValue NegOne = DAG.getConstant(-1, DL, VT);
1843 if (VT == MVT::i32 &&
1844 DAG.ComputeNumSignBits(LHS) > 8 &&
1845 DAG.ComputeNumSignBits(RHS) > 8) {
1846 return LowerDIVREM24(Op, DAG, true);
1848 if (VT == MVT::i64 &&
1849 DAG.ComputeNumSignBits(LHS) > 32 &&
1850 DAG.ComputeNumSignBits(RHS) > 32) {
1851 EVT HalfVT = VT.getHalfSizedIntegerVT(*DAG.getContext());
1854 SDValue LHS_Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, LHS, Zero);
1855 SDValue RHS_Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, RHS, Zero);
1856 SDValue DIVREM = DAG.getNode(ISD::SDIVREM, DL, DAG.getVTList(HalfVT, HalfVT),
1859 DAG.getNode(ISD::SIGN_EXTEND, DL, VT, DIVREM.getValue(0)),
1860 DAG.getNode(ISD::SIGN_EXTEND, DL, VT, DIVREM.getValue(1))
1862 return DAG.getMergeValues(Res, DL);
1865 SDValue LHSign = DAG.getSelectCC(DL, LHS, Zero, NegOne, Zero, ISD::SETLT);
1866 SDValue RHSign = DAG.getSelectCC(DL, RHS, Zero, NegOne, Zero, ISD::SETLT);
1867 SDValue DSign = DAG.getNode(ISD::XOR, DL, VT, LHSign, RHSign);
1868 SDValue RSign = LHSign; // Remainder sign is the same as LHS
1870 LHS = DAG.getNode(ISD::ADD, DL, VT, LHS, LHSign);
1871 RHS = DAG.getNode(ISD::ADD, DL, VT, RHS, RHSign);
1873 LHS = DAG.getNode(ISD::XOR, DL, VT, LHS, LHSign);
1874 RHS = DAG.getNode(ISD::XOR, DL, VT, RHS, RHSign);
1876 SDValue Div = DAG.getNode(ISD::UDIVREM, DL, DAG.getVTList(VT, VT), LHS, RHS);
1877 SDValue Rem = Div.getValue(1);
1879 Div = DAG.getNode(ISD::XOR, DL, VT, Div, DSign);
1880 Rem = DAG.getNode(ISD::XOR, DL, VT, Rem, RSign);
1882 Div = DAG.getNode(ISD::SUB, DL, VT, Div, DSign);
1883 Rem = DAG.getNode(ISD::SUB, DL, VT, Rem, RSign);
1889 return DAG.getMergeValues(Res, DL);
1892 // (frem x, y) -> (fsub x, (fmul (ftrunc (fdiv x, y)), y))
1893 SDValue AMDGPUTargetLowering::LowerFREM(SDValue Op, SelectionDAG &DAG) const {
1895 EVT VT = Op.getValueType();
1896 SDValue X = Op.getOperand(0);
1897 SDValue Y = Op.getOperand(1);
1899 // TODO: Should this propagate fast-math-flags?
1901 SDValue Div = DAG.getNode(ISD::FDIV, SL, VT, X, Y);
1902 SDValue Floor = DAG.getNode(ISD::FTRUNC, SL, VT, Div);
1903 SDValue Mul = DAG.getNode(ISD::FMUL, SL, VT, Floor, Y);
1905 return DAG.getNode(ISD::FSUB, SL, VT, X, Mul);
1908 SDValue AMDGPUTargetLowering::LowerFCEIL(SDValue Op, SelectionDAG &DAG) const {
1910 SDValue Src = Op.getOperand(0);
1912 // result = trunc(src)
1913 // if (src > 0.0 && src != result)
1916 SDValue Trunc = DAG.getNode(ISD::FTRUNC, SL, MVT::f64, Src);
1918 const SDValue Zero = DAG.getConstantFP(0.0, SL, MVT::f64);
1919 const SDValue One = DAG.getConstantFP(1.0, SL, MVT::f64);
1922 getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), MVT::f64);
1924 SDValue Lt0 = DAG.getSetCC(SL, SetCCVT, Src, Zero, ISD::SETOGT);
1925 SDValue NeTrunc = DAG.getSetCC(SL, SetCCVT, Src, Trunc, ISD::SETONE);
1926 SDValue And = DAG.getNode(ISD::AND, SL, SetCCVT, Lt0, NeTrunc);
1928 SDValue Add = DAG.getNode(ISD::SELECT, SL, MVT::f64, And, One, Zero);
1929 // TODO: Should this propagate fast-math-flags?
1930 return DAG.getNode(ISD::FADD, SL, MVT::f64, Trunc, Add);
1933 static SDValue extractF64Exponent(SDValue Hi, SDLoc SL, SelectionDAG &DAG) {
1934 const unsigned FractBits = 52;
1935 const unsigned ExpBits = 11;
1937 SDValue ExpPart = DAG.getNode(AMDGPUISD::BFE_U32, SL, MVT::i32,
1939 DAG.getConstant(FractBits - 32, SL, MVT::i32),
1940 DAG.getConstant(ExpBits, SL, MVT::i32));
1941 SDValue Exp = DAG.getNode(ISD::SUB, SL, MVT::i32, ExpPart,
1942 DAG.getConstant(1023, SL, MVT::i32));
1947 SDValue AMDGPUTargetLowering::LowerFTRUNC(SDValue Op, SelectionDAG &DAG) const {
1949 SDValue Src = Op.getOperand(0);
1951 assert(Op.getValueType() == MVT::f64);
1953 const SDValue Zero = DAG.getConstant(0, SL, MVT::i32);
1954 const SDValue One = DAG.getConstant(1, SL, MVT::i32);
1956 SDValue VecSrc = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, Src);
1958 // Extract the upper half, since this is where we will find the sign and
1960 SDValue Hi = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, VecSrc, One);
1962 SDValue Exp = extractF64Exponent(Hi, SL, DAG);
1964 const unsigned FractBits = 52;
1966 // Extract the sign bit.
1967 const SDValue SignBitMask = DAG.getConstant(UINT32_C(1) << 31, SL, MVT::i32);
1968 SDValue SignBit = DAG.getNode(ISD::AND, SL, MVT::i32, Hi, SignBitMask);
1970 // Extend back to to 64-bits.
1971 SDValue SignBit64 = DAG.getNode(ISD::BUILD_VECTOR, SL, MVT::v2i32,
1973 SignBit64 = DAG.getNode(ISD::BITCAST, SL, MVT::i64, SignBit64);
1975 SDValue BcInt = DAG.getNode(ISD::BITCAST, SL, MVT::i64, Src);
1976 const SDValue FractMask
1977 = DAG.getConstant((UINT64_C(1) << FractBits) - 1, SL, MVT::i64);
1979 SDValue Shr = DAG.getNode(ISD::SRA, SL, MVT::i64, FractMask, Exp);
1980 SDValue Not = DAG.getNOT(SL, Shr, MVT::i64);
1981 SDValue Tmp0 = DAG.getNode(ISD::AND, SL, MVT::i64, BcInt, Not);
1984 getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), MVT::i32);
1986 const SDValue FiftyOne = DAG.getConstant(FractBits - 1, SL, MVT::i32);
1988 SDValue ExpLt0 = DAG.getSetCC(SL, SetCCVT, Exp, Zero, ISD::SETLT);
1989 SDValue ExpGt51 = DAG.getSetCC(SL, SetCCVT, Exp, FiftyOne, ISD::SETGT);
1991 SDValue Tmp1 = DAG.getNode(ISD::SELECT, SL, MVT::i64, ExpLt0, SignBit64, Tmp0);
1992 SDValue Tmp2 = DAG.getNode(ISD::SELECT, SL, MVT::i64, ExpGt51, BcInt, Tmp1);
1994 return DAG.getNode(ISD::BITCAST, SL, MVT::f64, Tmp2);
1997 SDValue AMDGPUTargetLowering::LowerFRINT(SDValue Op, SelectionDAG &DAG) const {
1999 SDValue Src = Op.getOperand(0);
2001 assert(Op.getValueType() == MVT::f64);
2003 APFloat C1Val(APFloat::IEEEdouble, "0x1.0p+52");
2004 SDValue C1 = DAG.getConstantFP(C1Val, SL, MVT::f64);
2005 SDValue CopySign = DAG.getNode(ISD::FCOPYSIGN, SL, MVT::f64, C1, Src);
2007 // TODO: Should this propagate fast-math-flags?
2009 SDValue Tmp1 = DAG.getNode(ISD::FADD, SL, MVT::f64, Src, CopySign);
2010 SDValue Tmp2 = DAG.getNode(ISD::FSUB, SL, MVT::f64, Tmp1, CopySign);
2012 SDValue Fabs = DAG.getNode(ISD::FABS, SL, MVT::f64, Src);
2014 APFloat C2Val(APFloat::IEEEdouble, "0x1.fffffffffffffp+51");
2015 SDValue C2 = DAG.getConstantFP(C2Val, SL, MVT::f64);
2018 getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), MVT::f64);
2019 SDValue Cond = DAG.getSetCC(SL, SetCCVT, Fabs, C2, ISD::SETOGT);
2021 return DAG.getSelect(SL, MVT::f64, Cond, Src, Tmp2);
2024 SDValue AMDGPUTargetLowering::LowerFNEARBYINT(SDValue Op, SelectionDAG &DAG) const {
2025 // FNEARBYINT and FRINT are the same, except in their handling of FP
2026 // exceptions. Those aren't really meaningful for us, and OpenCL only has
2027 // rint, so just treat them as equivalent.
2028 return DAG.getNode(ISD::FRINT, SDLoc(Op), Op.getValueType(), Op.getOperand(0));
2031 // XXX - May require not supporting f32 denormals?
2032 SDValue AMDGPUTargetLowering::LowerFROUND32(SDValue Op, SelectionDAG &DAG) const {
2034 SDValue X = Op.getOperand(0);
2036 SDValue T = DAG.getNode(ISD::FTRUNC, SL, MVT::f32, X);
2038 // TODO: Should this propagate fast-math-flags?
2040 SDValue Diff = DAG.getNode(ISD::FSUB, SL, MVT::f32, X, T);
2042 SDValue AbsDiff = DAG.getNode(ISD::FABS, SL, MVT::f32, Diff);
2044 const SDValue Zero = DAG.getConstantFP(0.0, SL, MVT::f32);
2045 const SDValue One = DAG.getConstantFP(1.0, SL, MVT::f32);
2046 const SDValue Half = DAG.getConstantFP(0.5, SL, MVT::f32);
2048 SDValue SignOne = DAG.getNode(ISD::FCOPYSIGN, SL, MVT::f32, One, X);
2051 getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), MVT::f32);
2053 SDValue Cmp = DAG.getSetCC(SL, SetCCVT, AbsDiff, Half, ISD::SETOGE);
2055 SDValue Sel = DAG.getNode(ISD::SELECT, SL, MVT::f32, Cmp, SignOne, Zero);
2057 return DAG.getNode(ISD::FADD, SL, MVT::f32, T, Sel);
2060 SDValue AMDGPUTargetLowering::LowerFROUND64(SDValue Op, SelectionDAG &DAG) const {
2062 SDValue X = Op.getOperand(0);
2064 SDValue L = DAG.getNode(ISD::BITCAST, SL, MVT::i64, X);
2066 const SDValue Zero = DAG.getConstant(0, SL, MVT::i32);
2067 const SDValue One = DAG.getConstant(1, SL, MVT::i32);
2068 const SDValue NegOne = DAG.getConstant(-1, SL, MVT::i32);
2069 const SDValue FiftyOne = DAG.getConstant(51, SL, MVT::i32);
2071 getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), MVT::i32);
2073 SDValue BC = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, X);
2075 SDValue Hi = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, BC, One);
2077 SDValue Exp = extractF64Exponent(Hi, SL, DAG);
2079 const SDValue Mask = DAG.getConstant(INT64_C(0x000fffffffffffff), SL,
2082 SDValue M = DAG.getNode(ISD::SRA, SL, MVT::i64, Mask, Exp);
2083 SDValue D = DAG.getNode(ISD::SRA, SL, MVT::i64,
2084 DAG.getConstant(INT64_C(0x0008000000000000), SL,
2088 SDValue Tmp0 = DAG.getNode(ISD::AND, SL, MVT::i64, L, M);
2089 SDValue Tmp1 = DAG.getSetCC(SL, SetCCVT,
2090 DAG.getConstant(0, SL, MVT::i64), Tmp0,
2093 SDValue Tmp2 = DAG.getNode(ISD::SELECT, SL, MVT::i64, Tmp1,
2094 D, DAG.getConstant(0, SL, MVT::i64));
2095 SDValue K = DAG.getNode(ISD::ADD, SL, MVT::i64, L, Tmp2);
2097 K = DAG.getNode(ISD::AND, SL, MVT::i64, K, DAG.getNOT(SL, M, MVT::i64));
2098 K = DAG.getNode(ISD::BITCAST, SL, MVT::f64, K);
2100 SDValue ExpLt0 = DAG.getSetCC(SL, SetCCVT, Exp, Zero, ISD::SETLT);
2101 SDValue ExpGt51 = DAG.getSetCC(SL, SetCCVT, Exp, FiftyOne, ISD::SETGT);
2102 SDValue ExpEqNegOne = DAG.getSetCC(SL, SetCCVT, NegOne, Exp, ISD::SETEQ);
2104 SDValue Mag = DAG.getNode(ISD::SELECT, SL, MVT::f64,
2106 DAG.getConstantFP(1.0, SL, MVT::f64),
2107 DAG.getConstantFP(0.0, SL, MVT::f64));
2109 SDValue S = DAG.getNode(ISD::FCOPYSIGN, SL, MVT::f64, Mag, X);
2111 K = DAG.getNode(ISD::SELECT, SL, MVT::f64, ExpLt0, S, K);
2112 K = DAG.getNode(ISD::SELECT, SL, MVT::f64, ExpGt51, X, K);
2117 SDValue AMDGPUTargetLowering::LowerFROUND(SDValue Op, SelectionDAG &DAG) const {
2118 EVT VT = Op.getValueType();
2121 return LowerFROUND32(Op, DAG);
2124 return LowerFROUND64(Op, DAG);
2126 llvm_unreachable("unhandled type");
2129 SDValue AMDGPUTargetLowering::LowerFFLOOR(SDValue Op, SelectionDAG &DAG) const {
2131 SDValue Src = Op.getOperand(0);
2133 // result = trunc(src);
2134 // if (src < 0.0 && src != result)
2137 SDValue Trunc = DAG.getNode(ISD::FTRUNC, SL, MVT::f64, Src);
2139 const SDValue Zero = DAG.getConstantFP(0.0, SL, MVT::f64);
2140 const SDValue NegOne = DAG.getConstantFP(-1.0, SL, MVT::f64);
2143 getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), MVT::f64);
2145 SDValue Lt0 = DAG.getSetCC(SL, SetCCVT, Src, Zero, ISD::SETOLT);
2146 SDValue NeTrunc = DAG.getSetCC(SL, SetCCVT, Src, Trunc, ISD::SETONE);
2147 SDValue And = DAG.getNode(ISD::AND, SL, SetCCVT, Lt0, NeTrunc);
2149 SDValue Add = DAG.getNode(ISD::SELECT, SL, MVT::f64, And, NegOne, Zero);
2150 // TODO: Should this propagate fast-math-flags?
2151 return DAG.getNode(ISD::FADD, SL, MVT::f64, Trunc, Add);
2154 SDValue AMDGPUTargetLowering::LowerINT_TO_FP64(SDValue Op, SelectionDAG &DAG,
2155 bool Signed) const {
2157 SDValue Src = Op.getOperand(0);
2159 SDValue BC = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, Src);
2161 SDValue Lo = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, BC,
2162 DAG.getConstant(0, SL, MVT::i32));
2163 SDValue Hi = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, BC,
2164 DAG.getConstant(1, SL, MVT::i32));
2166 SDValue CvtHi = DAG.getNode(Signed ? ISD::SINT_TO_FP : ISD::UINT_TO_FP,
2169 SDValue CvtLo = DAG.getNode(ISD::UINT_TO_FP, SL, MVT::f64, Lo);
2171 SDValue LdExp = DAG.getNode(AMDGPUISD::LDEXP, SL, MVT::f64, CvtHi,
2172 DAG.getConstant(32, SL, MVT::i32));
2173 // TODO: Should this propagate fast-math-flags?
2174 return DAG.getNode(ISD::FADD, SL, MVT::f64, LdExp, CvtLo);
2177 SDValue AMDGPUTargetLowering::LowerUINT_TO_FP(SDValue Op,
2178 SelectionDAG &DAG) const {
2179 SDValue S0 = Op.getOperand(0);
2180 if (S0.getValueType() != MVT::i64)
2183 EVT DestVT = Op.getValueType();
2184 if (DestVT == MVT::f64)
2185 return LowerINT_TO_FP64(Op, DAG, false);
2187 assert(DestVT == MVT::f32);
2191 // f32 uint_to_fp i64
2192 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, S0,
2193 DAG.getConstant(0, DL, MVT::i32));
2194 SDValue FloatLo = DAG.getNode(ISD::UINT_TO_FP, DL, MVT::f32, Lo);
2195 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, S0,
2196 DAG.getConstant(1, DL, MVT::i32));
2197 SDValue FloatHi = DAG.getNode(ISD::UINT_TO_FP, DL, MVT::f32, Hi);
2198 // TODO: Should this propagate fast-math-flags?
2199 FloatHi = DAG.getNode(ISD::FMUL, DL, MVT::f32, FloatHi,
2200 DAG.getConstantFP(4294967296.0f, DL, MVT::f32)); // 2^32
2201 return DAG.getNode(ISD::FADD, DL, MVT::f32, FloatLo, FloatHi);
2204 SDValue AMDGPUTargetLowering::LowerSINT_TO_FP(SDValue Op,
2205 SelectionDAG &DAG) const {
2206 SDValue Src = Op.getOperand(0);
2207 if (Src.getValueType() == MVT::i64 && Op.getValueType() == MVT::f64)
2208 return LowerINT_TO_FP64(Op, DAG, true);
2213 SDValue AMDGPUTargetLowering::LowerFP64_TO_INT(SDValue Op, SelectionDAG &DAG,
2214 bool Signed) const {
2217 SDValue Src = Op.getOperand(0);
2219 SDValue Trunc = DAG.getNode(ISD::FTRUNC, SL, MVT::f64, Src);
2221 SDValue K0 = DAG.getConstantFP(BitsToDouble(UINT64_C(0x3df0000000000000)), SL,
2223 SDValue K1 = DAG.getConstantFP(BitsToDouble(UINT64_C(0xc1f0000000000000)), SL,
2225 // TODO: Should this propagate fast-math-flags?
2226 SDValue Mul = DAG.getNode(ISD::FMUL, SL, MVT::f64, Trunc, K0);
2228 SDValue FloorMul = DAG.getNode(ISD::FFLOOR, SL, MVT::f64, Mul);
2231 SDValue Fma = DAG.getNode(ISD::FMA, SL, MVT::f64, FloorMul, K1, Trunc);
2233 SDValue Hi = DAG.getNode(Signed ? ISD::FP_TO_SINT : ISD::FP_TO_UINT, SL,
2234 MVT::i32, FloorMul);
2235 SDValue Lo = DAG.getNode(ISD::FP_TO_UINT, SL, MVT::i32, Fma);
2237 SDValue Result = DAG.getNode(ISD::BUILD_VECTOR, SL, MVT::v2i32, Lo, Hi);
2239 return DAG.getNode(ISD::BITCAST, SL, MVT::i64, Result);
2242 SDValue AMDGPUTargetLowering::LowerFP_TO_SINT(SDValue Op,
2243 SelectionDAG &DAG) const {
2244 SDValue Src = Op.getOperand(0);
2246 if (Op.getValueType() == MVT::i64 && Src.getValueType() == MVT::f64)
2247 return LowerFP64_TO_INT(Op, DAG, true);
2252 SDValue AMDGPUTargetLowering::LowerFP_TO_UINT(SDValue Op,
2253 SelectionDAG &DAG) const {
2254 SDValue Src = Op.getOperand(0);
2256 if (Op.getValueType() == MVT::i64 && Src.getValueType() == MVT::f64)
2257 return LowerFP64_TO_INT(Op, DAG, false);
2262 SDValue AMDGPUTargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op,
2263 SelectionDAG &DAG) const {
2264 EVT ExtraVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
2265 MVT VT = Op.getSimpleValueType();
2266 MVT ScalarVT = VT.getScalarType();
2271 SDValue Src = Op.getOperand(0);
2274 // TODO: Don't scalarize on Evergreen?
2275 unsigned NElts = VT.getVectorNumElements();
2276 SmallVector<SDValue, 8> Args;
2277 DAG.ExtractVectorElements(Src, Args, 0, NElts);
2279 SDValue VTOp = DAG.getValueType(ExtraVT.getScalarType());
2280 for (unsigned I = 0; I < NElts; ++I)
2281 Args[I] = DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, ScalarVT, Args[I], VTOp);
2283 return DAG.getNode(ISD::BUILD_VECTOR, DL, VT, Args);
2286 //===----------------------------------------------------------------------===//
2287 // Custom DAG optimizations
2288 //===----------------------------------------------------------------------===//
2290 static bool isU24(SDValue Op, SelectionDAG &DAG) {
2291 APInt KnownZero, KnownOne;
2292 EVT VT = Op.getValueType();
2293 DAG.computeKnownBits(Op, KnownZero, KnownOne);
2295 return (VT.getSizeInBits() - KnownZero.countLeadingOnes()) <= 24;
2298 static bool isI24(SDValue Op, SelectionDAG &DAG) {
2299 EVT VT = Op.getValueType();
2301 // In order for this to be a signed 24-bit value, bit 23, must
2303 return VT.getSizeInBits() >= 24 && // Types less than 24-bit should be treated
2304 // as unsigned 24-bit values.
2305 (VT.getSizeInBits() - DAG.ComputeNumSignBits(Op)) < 24;
2308 static void simplifyI24(SDValue Op, TargetLowering::DAGCombinerInfo &DCI) {
2310 SelectionDAG &DAG = DCI.DAG;
2311 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2312 EVT VT = Op.getValueType();
2314 APInt Demanded = APInt::getLowBitsSet(VT.getSizeInBits(), 24);
2315 APInt KnownZero, KnownOne;
2316 TargetLowering::TargetLoweringOpt TLO(DAG, true, true);
2317 if (TLI.SimplifyDemandedBits(Op, Demanded, KnownZero, KnownOne, TLO))
2318 DCI.CommitTargetLoweringOpt(TLO);
2321 template <typename IntTy>
2322 static SDValue constantFoldBFE(SelectionDAG &DAG, IntTy Src0,
2323 uint32_t Offset, uint32_t Width, SDLoc DL) {
2324 if (Width + Offset < 32) {
2325 uint32_t Shl = static_cast<uint32_t>(Src0) << (32 - Offset - Width);
2326 IntTy Result = static_cast<IntTy>(Shl) >> (32 - Width);
2327 return DAG.getConstant(Result, DL, MVT::i32);
2330 return DAG.getConstant(Src0 >> Offset, DL, MVT::i32);
2333 static bool usesAllNormalStores(SDNode *LoadVal) {
2334 for (SDNode::use_iterator I = LoadVal->use_begin(); !I.atEnd(); ++I) {
2335 if (!ISD::isNormalStore(*I))
2342 // If we have a copy of an illegal type, replace it with a load / store of an
2343 // equivalently sized legal type. This avoids intermediate bit pack / unpack
2344 // instructions emitted when handling extloads and truncstores. Ideally we could
2345 // recognize the pack / unpack pattern to eliminate it.
2346 SDValue AMDGPUTargetLowering::performStoreCombine(SDNode *N,
2347 DAGCombinerInfo &DCI) const {
2348 if (!DCI.isBeforeLegalize())
2351 StoreSDNode *SN = cast<StoreSDNode>(N);
2352 SDValue Value = SN->getValue();
2353 EVT VT = Value.getValueType();
2355 if (isTypeLegal(VT) || SN->isVolatile() ||
2356 !ISD::isNormalLoad(Value.getNode()) || VT.getSizeInBits() < 8)
2359 LoadSDNode *LoadVal = cast<LoadSDNode>(Value);
2360 if (LoadVal->isVolatile() || !usesAllNormalStores(LoadVal))
2363 EVT MemVT = LoadVal->getMemoryVT();
2366 SelectionDAG &DAG = DCI.DAG;
2367 EVT LoadVT = getEquivalentMemType(*DAG.getContext(), MemVT);
2369 SDValue NewLoad = DAG.getLoad(ISD::UNINDEXED, ISD::NON_EXTLOAD,
2371 LoadVal->getChain(),
2372 LoadVal->getBasePtr(),
2373 LoadVal->getOffset(),
2375 LoadVal->getMemOperand());
2377 SDValue CastLoad = DAG.getNode(ISD::BITCAST, SL, VT, NewLoad.getValue(0));
2378 DCI.CombineTo(LoadVal, CastLoad, NewLoad.getValue(1), false);
2380 return DAG.getStore(SN->getChain(), SL, NewLoad,
2381 SN->getBasePtr(), SN->getMemOperand());
2384 SDValue AMDGPUTargetLowering::performShlCombine(SDNode *N,
2385 DAGCombinerInfo &DCI) const {
2386 if (N->getValueType(0) != MVT::i64)
2389 // i64 (shl x, 32) -> (build_pair 0, x)
2391 // Doing this with moves theoretically helps MI optimizations that understand
2392 // copies. 2 v_mov_b32_e32 will have the same code size / cycle count as
2393 // v_lshl_b64. In the SALU case, I think this is slightly worse since it
2394 // doubles the code size and I'm unsure about cycle count.
2395 const ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N->getOperand(1));
2396 if (!RHS || RHS->getZExtValue() != 32)
2399 SDValue LHS = N->getOperand(0);
2402 SelectionDAG &DAG = DCI.DAG;
2404 // Extract low 32-bits.
2405 SDValue Lo = DAG.getNode(ISD::TRUNCATE, SL, MVT::i32, LHS);
2407 const SDValue Zero = DAG.getConstant(0, SL, MVT::i32);
2408 return DAG.getNode(ISD::BUILD_PAIR, SL, MVT::i64, Zero, Lo);
2411 SDValue AMDGPUTargetLowering::performMulCombine(SDNode *N,
2412 DAGCombinerInfo &DCI) const {
2413 EVT VT = N->getValueType(0);
2415 if (VT.isVector() || VT.getSizeInBits() > 32)
2418 SelectionDAG &DAG = DCI.DAG;
2421 SDValue N0 = N->getOperand(0);
2422 SDValue N1 = N->getOperand(1);
2425 if (Subtarget->hasMulU24() && isU24(N0, DAG) && isU24(N1, DAG)) {
2426 N0 = DAG.getZExtOrTrunc(N0, DL, MVT::i32);
2427 N1 = DAG.getZExtOrTrunc(N1, DL, MVT::i32);
2428 Mul = DAG.getNode(AMDGPUISD::MUL_U24, DL, MVT::i32, N0, N1);
2429 } else if (Subtarget->hasMulI24() && isI24(N0, DAG) && isI24(N1, DAG)) {
2430 N0 = DAG.getSExtOrTrunc(N0, DL, MVT::i32);
2431 N1 = DAG.getSExtOrTrunc(N1, DL, MVT::i32);
2432 Mul = DAG.getNode(AMDGPUISD::MUL_I24, DL, MVT::i32, N0, N1);
2437 // We need to use sext even for MUL_U24, because MUL_U24 is used
2438 // for signed multiply of 8 and 16-bit types.
2439 return DAG.getSExtOrTrunc(Mul, DL, VT);
2442 SDValue AMDGPUTargetLowering::PerformDAGCombine(SDNode *N,
2443 DAGCombinerInfo &DCI) const {
2444 SelectionDAG &DAG = DCI.DAG;
2447 switch(N->getOpcode()) {
2451 if (DCI.getDAGCombineLevel() < AfterLegalizeDAG)
2454 return performShlCombine(N, DCI);
2457 return performMulCombine(N, DCI);
2458 case AMDGPUISD::MUL_I24:
2459 case AMDGPUISD::MUL_U24: {
2460 SDValue N0 = N->getOperand(0);
2461 SDValue N1 = N->getOperand(1);
2462 simplifyI24(N0, DCI);
2463 simplifyI24(N1, DCI);
2467 SDValue Cond = N->getOperand(0);
2468 if (Cond.getOpcode() == ISD::SETCC && Cond.hasOneUse()) {
2469 EVT VT = N->getValueType(0);
2470 SDValue LHS = Cond.getOperand(0);
2471 SDValue RHS = Cond.getOperand(1);
2472 SDValue CC = Cond.getOperand(2);
2474 SDValue True = N->getOperand(1);
2475 SDValue False = N->getOperand(2);
2478 return CombineFMinMaxLegacy(DL, VT, LHS, RHS, True, False, CC, DCI);
2483 case AMDGPUISD::BFE_I32:
2484 case AMDGPUISD::BFE_U32: {
2485 assert(!N->getValueType(0).isVector() &&
2486 "Vector handling of BFE not implemented");
2487 ConstantSDNode *Width = dyn_cast<ConstantSDNode>(N->getOperand(2));
2491 uint32_t WidthVal = Width->getZExtValue() & 0x1f;
2493 return DAG.getConstant(0, DL, MVT::i32);
2495 ConstantSDNode *Offset = dyn_cast<ConstantSDNode>(N->getOperand(1));
2499 SDValue BitsFrom = N->getOperand(0);
2500 uint32_t OffsetVal = Offset->getZExtValue() & 0x1f;
2502 bool Signed = N->getOpcode() == AMDGPUISD::BFE_I32;
2504 if (OffsetVal == 0) {
2505 // This is already sign / zero extended, so try to fold away extra BFEs.
2506 unsigned SignBits = Signed ? (32 - WidthVal + 1) : (32 - WidthVal);
2508 unsigned OpSignBits = DAG.ComputeNumSignBits(BitsFrom);
2509 if (OpSignBits >= SignBits)
2512 EVT SmallVT = EVT::getIntegerVT(*DAG.getContext(), WidthVal);
2514 // This is a sign_extend_inreg. Replace it to take advantage of existing
2515 // DAG Combines. If not eliminated, we will match back to BFE during
2518 // TODO: The sext_inreg of extended types ends, although we can could
2519 // handle them in a single BFE.
2520 return DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, MVT::i32, BitsFrom,
2521 DAG.getValueType(SmallVT));
2524 return DAG.getZeroExtendInReg(BitsFrom, DL, SmallVT);
2527 if (ConstantSDNode *CVal = dyn_cast<ConstantSDNode>(BitsFrom)) {
2529 return constantFoldBFE<int32_t>(DAG,
2530 CVal->getSExtValue(),
2536 return constantFoldBFE<uint32_t>(DAG,
2537 CVal->getZExtValue(),
2543 if ((OffsetVal + WidthVal) >= 32) {
2544 SDValue ShiftVal = DAG.getConstant(OffsetVal, DL, MVT::i32);
2545 return DAG.getNode(Signed ? ISD::SRA : ISD::SRL, DL, MVT::i32,
2546 BitsFrom, ShiftVal);
2549 if (BitsFrom.hasOneUse()) {
2550 APInt Demanded = APInt::getBitsSet(32,
2552 OffsetVal + WidthVal);
2554 APInt KnownZero, KnownOne;
2555 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
2556 !DCI.isBeforeLegalizeOps());
2557 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2558 if (TLO.ShrinkDemandedConstant(BitsFrom, Demanded) ||
2559 TLI.SimplifyDemandedBits(BitsFrom, Demanded,
2560 KnownZero, KnownOne, TLO)) {
2561 DCI.CommitTargetLoweringOpt(TLO);
2569 return performStoreCombine(N, DCI);
2574 //===----------------------------------------------------------------------===//
2576 //===----------------------------------------------------------------------===//
2578 void AMDGPUTargetLowering::getOriginalFunctionArgs(
2581 const SmallVectorImpl<ISD::InputArg> &Ins,
2582 SmallVectorImpl<ISD::InputArg> &OrigIns) const {
2584 for (unsigned i = 0, e = Ins.size(); i < e; ++i) {
2585 if (Ins[i].ArgVT == Ins[i].VT) {
2586 OrigIns.push_back(Ins[i]);
2591 if (Ins[i].ArgVT.isVector() && !Ins[i].VT.isVector()) {
2592 // Vector has been split into scalars.
2593 VT = Ins[i].ArgVT.getVectorElementType();
2594 } else if (Ins[i].VT.isVector() && Ins[i].ArgVT.isVector() &&
2595 Ins[i].ArgVT.getVectorElementType() !=
2596 Ins[i].VT.getVectorElementType()) {
2597 // Vector elements have been promoted
2600 // Vector has been spilt into smaller vectors.
2604 ISD::InputArg Arg(Ins[i].Flags, VT, VT, Ins[i].Used,
2605 Ins[i].OrigArgIndex, Ins[i].PartOffset);
2606 OrigIns.push_back(Arg);
2610 bool AMDGPUTargetLowering::isHWTrueValue(SDValue Op) const {
2611 if (ConstantFPSDNode * CFP = dyn_cast<ConstantFPSDNode>(Op)) {
2612 return CFP->isExactlyValue(1.0);
2614 return isAllOnesConstant(Op);
2617 bool AMDGPUTargetLowering::isHWFalseValue(SDValue Op) const {
2618 if (ConstantFPSDNode * CFP = dyn_cast<ConstantFPSDNode>(Op)) {
2619 return CFP->getValueAPF().isZero();
2621 return isNullConstant(Op);
2624 SDValue AMDGPUTargetLowering::CreateLiveInRegister(SelectionDAG &DAG,
2625 const TargetRegisterClass *RC,
2626 unsigned Reg, EVT VT) const {
2627 MachineFunction &MF = DAG.getMachineFunction();
2628 MachineRegisterInfo &MRI = MF.getRegInfo();
2629 unsigned VirtualRegister;
2630 if (!MRI.isLiveIn(Reg)) {
2631 VirtualRegister = MRI.createVirtualRegister(RC);
2632 MRI.addLiveIn(Reg, VirtualRegister);
2634 VirtualRegister = MRI.getLiveInVirtReg(Reg);
2636 return DAG.getRegister(VirtualRegister, VT);
2639 uint32_t AMDGPUTargetLowering::getImplicitParameterOffset(
2640 const AMDGPUMachineFunction *MFI, const ImplicitParameter Param) const {
2641 uint64_t ArgOffset = MFI->ABIArgOffset;
2646 return ArgOffset + 4;
2648 llvm_unreachable("unexpected implicit parameter type");
2651 #define NODE_NAME_CASE(node) case AMDGPUISD::node: return #node;
2653 const char* AMDGPUTargetLowering::getTargetNodeName(unsigned Opcode) const {
2654 switch ((AMDGPUISD::NodeType)Opcode) {
2655 case AMDGPUISD::FIRST_NUMBER: break;
2657 NODE_NAME_CASE(CALL);
2658 NODE_NAME_CASE(UMUL);
2659 NODE_NAME_CASE(RET_FLAG);
2660 NODE_NAME_CASE(BRANCH_COND);
2663 NODE_NAME_CASE(DWORDADDR)
2664 NODE_NAME_CASE(FRACT)
2665 NODE_NAME_CASE(CLAMP)
2666 NODE_NAME_CASE(COS_HW)
2667 NODE_NAME_CASE(SIN_HW)
2668 NODE_NAME_CASE(FMAX_LEGACY)
2669 NODE_NAME_CASE(FMIN_LEGACY)
2670 NODE_NAME_CASE(FMAX3)
2671 NODE_NAME_CASE(SMAX3)
2672 NODE_NAME_CASE(UMAX3)
2673 NODE_NAME_CASE(FMIN3)
2674 NODE_NAME_CASE(SMIN3)
2675 NODE_NAME_CASE(UMIN3)
2676 NODE_NAME_CASE(URECIP)
2677 NODE_NAME_CASE(DIV_SCALE)
2678 NODE_NAME_CASE(DIV_FMAS)
2679 NODE_NAME_CASE(DIV_FIXUP)
2680 NODE_NAME_CASE(TRIG_PREOP)
2683 NODE_NAME_CASE(RSQ_LEGACY)
2684 NODE_NAME_CASE(RSQ_CLAMPED)
2685 NODE_NAME_CASE(LDEXP)
2686 NODE_NAME_CASE(FP_CLASS)
2687 NODE_NAME_CASE(DOT4)
2688 NODE_NAME_CASE(CARRY)
2689 NODE_NAME_CASE(BORROW)
2690 NODE_NAME_CASE(BFE_U32)
2691 NODE_NAME_CASE(BFE_I32)
2694 NODE_NAME_CASE(BREV)
2695 NODE_NAME_CASE(MUL_U24)
2696 NODE_NAME_CASE(MUL_I24)
2697 NODE_NAME_CASE(MAD_U24)
2698 NODE_NAME_CASE(MAD_I24)
2699 NODE_NAME_CASE(TEXTURE_FETCH)
2700 NODE_NAME_CASE(EXPORT)
2701 NODE_NAME_CASE(CONST_ADDRESS)
2702 NODE_NAME_CASE(REGISTER_LOAD)
2703 NODE_NAME_CASE(REGISTER_STORE)
2704 NODE_NAME_CASE(LOAD_CONSTANT)
2705 NODE_NAME_CASE(LOAD_INPUT)
2706 NODE_NAME_CASE(SAMPLE)
2707 NODE_NAME_CASE(SAMPLEB)
2708 NODE_NAME_CASE(SAMPLED)
2709 NODE_NAME_CASE(SAMPLEL)
2710 NODE_NAME_CASE(CVT_F32_UBYTE0)
2711 NODE_NAME_CASE(CVT_F32_UBYTE1)
2712 NODE_NAME_CASE(CVT_F32_UBYTE2)
2713 NODE_NAME_CASE(CVT_F32_UBYTE3)
2714 NODE_NAME_CASE(BUILD_VERTICAL_VECTOR)
2715 NODE_NAME_CASE(CONST_DATA_PTR)
2716 case AMDGPUISD::FIRST_MEM_OPCODE_NUMBER: break;
2717 NODE_NAME_CASE(SENDMSG)
2718 NODE_NAME_CASE(INTERP_MOV)
2719 NODE_NAME_CASE(INTERP_P1)
2720 NODE_NAME_CASE(INTERP_P2)
2721 NODE_NAME_CASE(STORE_MSKOR)
2722 NODE_NAME_CASE(TBUFFER_STORE_FORMAT)
2723 case AMDGPUISD::LAST_AMDGPU_ISD_NUMBER: break;
2728 SDValue AMDGPUTargetLowering::getRsqrtEstimate(SDValue Operand,
2729 DAGCombinerInfo &DCI,
2730 unsigned &RefinementSteps,
2731 bool &UseOneConstNR) const {
2732 SelectionDAG &DAG = DCI.DAG;
2733 EVT VT = Operand.getValueType();
2735 if (VT == MVT::f32) {
2736 RefinementSteps = 0;
2737 return DAG.getNode(AMDGPUISD::RSQ, SDLoc(Operand), VT, Operand);
2740 // TODO: There is also f64 rsq instruction, but the documentation is less
2741 // clear on its precision.
2746 SDValue AMDGPUTargetLowering::getRecipEstimate(SDValue Operand,
2747 DAGCombinerInfo &DCI,
2748 unsigned &RefinementSteps) const {
2749 SelectionDAG &DAG = DCI.DAG;
2750 EVT VT = Operand.getValueType();
2752 if (VT == MVT::f32) {
2753 // Reciprocal, < 1 ulp error.
2755 // This reciprocal approximation converges to < 0.5 ulp error with one
2756 // newton rhapson performed with two fused multiple adds (FMAs).
2758 RefinementSteps = 0;
2759 return DAG.getNode(AMDGPUISD::RCP, SDLoc(Operand), VT, Operand);
2762 // TODO: There is also f64 rcp instruction, but the documentation is less
2763 // clear on its precision.
2768 static void computeKnownBitsForMinMax(const SDValue Op0,
2772 const SelectionDAG &DAG,
2774 APInt Op0Zero, Op0One;
2775 APInt Op1Zero, Op1One;
2776 DAG.computeKnownBits(Op0, Op0Zero, Op0One, Depth);
2777 DAG.computeKnownBits(Op1, Op1Zero, Op1One, Depth);
2779 KnownZero = Op0Zero & Op1Zero;
2780 KnownOne = Op0One & Op1One;
2783 void AMDGPUTargetLowering::computeKnownBitsForTargetNode(
2787 const SelectionDAG &DAG,
2788 unsigned Depth) const {
2790 KnownZero = KnownOne = APInt(KnownOne.getBitWidth(), 0); // Don't know anything.
2794 unsigned Opc = Op.getOpcode();
2799 case ISD::INTRINSIC_WO_CHAIN: {
2800 // FIXME: The intrinsic should just use the node.
2801 switch (cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue()) {
2802 case AMDGPUIntrinsic::AMDGPU_imax:
2803 case AMDGPUIntrinsic::AMDGPU_umax:
2804 case AMDGPUIntrinsic::AMDGPU_imin:
2805 case AMDGPUIntrinsic::AMDGPU_umin:
2806 computeKnownBitsForMinMax(Op.getOperand(1), Op.getOperand(2),
2807 KnownZero, KnownOne, DAG, Depth);
2815 case AMDGPUISD::CARRY:
2816 case AMDGPUISD::BORROW: {
2817 KnownZero = APInt::getHighBitsSet(32, 31);
2821 case AMDGPUISD::BFE_I32:
2822 case AMDGPUISD::BFE_U32: {
2823 ConstantSDNode *CWidth = dyn_cast<ConstantSDNode>(Op.getOperand(2));
2827 unsigned BitWidth = 32;
2828 uint32_t Width = CWidth->getZExtValue() & 0x1f;
2830 if (Opc == AMDGPUISD::BFE_U32)
2831 KnownZero = APInt::getHighBitsSet(BitWidth, BitWidth - Width);
2838 unsigned AMDGPUTargetLowering::ComputeNumSignBitsForTargetNode(
2840 const SelectionDAG &DAG,
2841 unsigned Depth) const {
2842 switch (Op.getOpcode()) {
2843 case AMDGPUISD::BFE_I32: {
2844 ConstantSDNode *Width = dyn_cast<ConstantSDNode>(Op.getOperand(2));
2848 unsigned SignBits = 32 - Width->getZExtValue() + 1;
2849 if (!isNullConstant(Op.getOperand(1)))
2852 // TODO: Could probably figure something out with non-0 offsets.
2853 unsigned Op0SignBits = DAG.ComputeNumSignBits(Op.getOperand(0), Depth + 1);
2854 return std::max(SignBits, Op0SignBits);
2857 case AMDGPUISD::BFE_U32: {
2858 ConstantSDNode *Width = dyn_cast<ConstantSDNode>(Op.getOperand(2));
2859 return Width ? 32 - (Width->getZExtValue() & 0x1f) : 1;
2862 case AMDGPUISD::CARRY:
2863 case AMDGPUISD::BORROW: