1 //===-- AMDILISelDAGToDAG.cpp - A dag to dag inst selector for AMDIL ------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //==-----------------------------------------------------------------------===//
11 /// \brief Defines an instruction selector for the AMDGPU target.
13 //===----------------------------------------------------------------------===//
14 #include "AMDGPUInstrInfo.h"
15 #include "AMDGPUISelLowering.h" // For AMDGPUISD
16 #include "AMDGPURegisterInfo.h"
17 #include "AMDGPUSubtarget.h"
18 #include "R600InstrInfo.h"
19 #include "SIDefines.h"
20 #include "SIISelLowering.h"
21 #include "SIMachineFunctionInfo.h"
22 #include "llvm/CodeGen/FunctionLoweringInfo.h"
23 #include "llvm/CodeGen/PseudoSourceValue.h"
24 #include "llvm/CodeGen/MachineFrameInfo.h"
25 #include "llvm/CodeGen/MachineRegisterInfo.h"
26 #include "llvm/CodeGen/SelectionDAG.h"
27 #include "llvm/CodeGen/SelectionDAGISel.h"
28 #include "llvm/IR/Function.h"
32 //===----------------------------------------------------------------------===//
33 // Instruction Selector Implementation
34 //===----------------------------------------------------------------------===//
37 /// AMDGPU specific code to select AMDGPU machine instructions for
38 /// SelectionDAG operations.
39 class AMDGPUDAGToDAGISel : public SelectionDAGISel {
40 // Subtarget - Keep a pointer to the AMDGPU Subtarget around so that we can
41 // make the right decision when generating code for different targets.
42 const AMDGPUSubtarget *Subtarget;
44 AMDGPUDAGToDAGISel(TargetMachine &TM);
45 virtual ~AMDGPUDAGToDAGISel();
46 bool runOnMachineFunction(MachineFunction &MF) override;
47 SDNode *Select(SDNode *N) override;
48 const char *getPassName() const override;
49 void PostprocessISelDAG() override;
52 bool isInlineImmediate(SDNode *N) const;
53 bool FoldOperand(SDValue &Src, SDValue &Sel, SDValue &Neg, SDValue &Abs,
54 const R600InstrInfo *TII);
55 bool FoldOperands(unsigned, const R600InstrInfo *, std::vector<SDValue> &);
56 bool FoldDotOperands(unsigned, const R600InstrInfo *, std::vector<SDValue> &);
58 // Complex pattern selectors
59 bool SelectADDRParam(SDValue Addr, SDValue& R1, SDValue& R2);
60 bool SelectADDR(SDValue N, SDValue &R1, SDValue &R2);
61 bool SelectADDR64(SDValue N, SDValue &R1, SDValue &R2);
63 static bool checkType(const Value *ptr, unsigned int addrspace);
64 static bool checkPrivateAddress(const MachineMemOperand *Op);
66 static bool isGlobalStore(const StoreSDNode *N);
67 static bool isFlatStore(const StoreSDNode *N);
68 static bool isPrivateStore(const StoreSDNode *N);
69 static bool isLocalStore(const StoreSDNode *N);
70 static bool isRegionStore(const StoreSDNode *N);
72 bool isCPLoad(const LoadSDNode *N) const;
73 bool isConstantLoad(const LoadSDNode *N, int cbID) const;
74 bool isGlobalLoad(const LoadSDNode *N) const;
75 bool isFlatLoad(const LoadSDNode *N) const;
76 bool isParamLoad(const LoadSDNode *N) const;
77 bool isPrivateLoad(const LoadSDNode *N) const;
78 bool isLocalLoad(const LoadSDNode *N) const;
79 bool isRegionLoad(const LoadSDNode *N) const;
81 SDNode *glueCopyToM0(SDNode *N) const;
83 const TargetRegisterClass *getOperandRegClass(SDNode *N, unsigned OpNo) const;
84 bool SelectGlobalValueConstantOffset(SDValue Addr, SDValue& IntPtr);
85 bool SelectGlobalValueVariableOffset(SDValue Addr, SDValue &BaseReg,
87 bool SelectADDRVTX_READ(SDValue Addr, SDValue &Base, SDValue &Offset);
88 bool SelectADDRIndirect(SDValue Addr, SDValue &Base, SDValue &Offset);
89 bool isDSOffsetLegal(const SDValue &Base, unsigned Offset,
90 unsigned OffsetBits) const;
91 bool SelectDS1Addr1Offset(SDValue Ptr, SDValue &Base, SDValue &Offset) const;
92 bool SelectDS64Bit4ByteAligned(SDValue Ptr, SDValue &Base, SDValue &Offset0,
93 SDValue &Offset1) const;
94 void SelectMUBUF(SDValue Addr, SDValue &SRsrc, SDValue &VAddr,
95 SDValue &SOffset, SDValue &Offset, SDValue &Offen,
96 SDValue &Idxen, SDValue &Addr64, SDValue &GLC, SDValue &SLC,
98 bool SelectMUBUFAddr64(SDValue Addr, SDValue &SRsrc, SDValue &VAddr,
99 SDValue &SOffset, SDValue &Offset, SDValue &GLC,
100 SDValue &SLC, SDValue &TFE) const;
101 bool SelectMUBUFAddr64(SDValue Addr, SDValue &SRsrc,
102 SDValue &VAddr, SDValue &SOffset, SDValue &Offset,
104 bool SelectMUBUFScratch(SDValue Addr, SDValue &RSrc, SDValue &VAddr,
105 SDValue &SOffset, SDValue &ImmOffset) const;
106 bool SelectMUBUFOffset(SDValue Addr, SDValue &SRsrc, SDValue &SOffset,
107 SDValue &Offset, SDValue &GLC, SDValue &SLC,
109 bool SelectMUBUFOffset(SDValue Addr, SDValue &SRsrc, SDValue &Soffset,
110 SDValue &Offset, SDValue &GLC) const;
111 bool SelectSMRDOffset(SDValue ByteOffsetNode, SDValue &Offset,
113 bool SelectSMRD(SDValue Addr, SDValue &SBase, SDValue &Offset,
115 bool SelectSMRDImm(SDValue Addr, SDValue &SBase, SDValue &Offset) const;
116 bool SelectSMRDImm32(SDValue Addr, SDValue &SBase, SDValue &Offset) const;
117 bool SelectSMRDSgpr(SDValue Addr, SDValue &SBase, SDValue &Offset) const;
118 bool SelectSMRDBufferImm(SDValue Addr, SDValue &Offset) const;
119 bool SelectSMRDBufferImm32(SDValue Addr, SDValue &Offset) const;
120 bool SelectSMRDBufferSgpr(SDValue Addr, SDValue &Offset) const;
121 SDNode *SelectAddrSpaceCast(SDNode *N);
122 bool SelectVOP3Mods(SDValue In, SDValue &Src, SDValue &SrcMods) const;
123 bool SelectVOP3NoMods(SDValue In, SDValue &Src, SDValue &SrcMods) const;
124 bool SelectVOP3Mods0(SDValue In, SDValue &Src, SDValue &SrcMods,
125 SDValue &Clamp, SDValue &Omod) const;
126 bool SelectVOP3NoMods0(SDValue In, SDValue &Src, SDValue &SrcMods,
127 SDValue &Clamp, SDValue &Omod) const;
129 bool SelectVOP3Mods0Clamp(SDValue In, SDValue &Src, SDValue &SrcMods,
130 SDValue &Omod) const;
131 bool SelectVOP3Mods0Clamp0OMod(SDValue In, SDValue &Src, SDValue &SrcMods,
133 SDValue &Omod) const;
135 SDNode *SelectADD_SUB_I64(SDNode *N);
136 SDNode *SelectDIV_SCALE(SDNode *N);
138 SDNode *getS_BFE(unsigned Opcode, SDLoc DL, SDValue Val,
139 uint32_t Offset, uint32_t Width);
140 SDNode *SelectS_BFEFromShifts(SDNode *N);
141 SDNode *SelectS_BFE(SDNode *N);
143 // Include the pieces autogenerated from the target description.
144 #include "AMDGPUGenDAGISel.inc"
146 } // end anonymous namespace
148 /// \brief This pass converts a legalized DAG into a AMDGPU-specific
149 // DAG, ready for instruction scheduling.
150 FunctionPass *llvm::createAMDGPUISelDag(TargetMachine &TM) {
151 return new AMDGPUDAGToDAGISel(TM);
154 AMDGPUDAGToDAGISel::AMDGPUDAGToDAGISel(TargetMachine &TM)
155 : SelectionDAGISel(TM) {}
157 bool AMDGPUDAGToDAGISel::runOnMachineFunction(MachineFunction &MF) {
158 Subtarget = &static_cast<const AMDGPUSubtarget &>(MF.getSubtarget());
159 return SelectionDAGISel::runOnMachineFunction(MF);
162 AMDGPUDAGToDAGISel::~AMDGPUDAGToDAGISel() {
165 bool AMDGPUDAGToDAGISel::isInlineImmediate(SDNode *N) const {
166 const SITargetLowering *TL
167 = static_cast<const SITargetLowering *>(getTargetLowering());
168 return TL->analyzeImmediate(N) == 0;
171 /// \brief Determine the register class for \p OpNo
172 /// \returns The register class of the virtual register that will be used for
173 /// the given operand number \OpNo or NULL if the register class cannot be
175 const TargetRegisterClass *AMDGPUDAGToDAGISel::getOperandRegClass(SDNode *N,
176 unsigned OpNo) const {
177 if (!N->isMachineOpcode())
180 switch (N->getMachineOpcode()) {
182 const MCInstrDesc &Desc =
183 Subtarget->getInstrInfo()->get(N->getMachineOpcode());
184 unsigned OpIdx = Desc.getNumDefs() + OpNo;
185 if (OpIdx >= Desc.getNumOperands())
187 int RegClass = Desc.OpInfo[OpIdx].RegClass;
191 return Subtarget->getRegisterInfo()->getRegClass(RegClass);
193 case AMDGPU::REG_SEQUENCE: {
194 unsigned RCID = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
195 const TargetRegisterClass *SuperRC =
196 Subtarget->getRegisterInfo()->getRegClass(RCID);
198 SDValue SubRegOp = N->getOperand(OpNo + 1);
199 unsigned SubRegIdx = cast<ConstantSDNode>(SubRegOp)->getZExtValue();
200 return Subtarget->getRegisterInfo()->getSubClassWithSubReg(SuperRC,
206 bool AMDGPUDAGToDAGISel::SelectADDRParam(
207 SDValue Addr, SDValue& R1, SDValue& R2) {
209 if (Addr.getOpcode() == ISD::FrameIndex) {
210 if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
211 R1 = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
212 R2 = CurDAG->getTargetConstant(0, SDLoc(Addr), MVT::i32);
215 R2 = CurDAG->getTargetConstant(0, SDLoc(Addr), MVT::i32);
217 } else if (Addr.getOpcode() == ISD::ADD) {
218 R1 = Addr.getOperand(0);
219 R2 = Addr.getOperand(1);
222 R2 = CurDAG->getTargetConstant(0, SDLoc(Addr), MVT::i32);
227 bool AMDGPUDAGToDAGISel::SelectADDR(SDValue Addr, SDValue& R1, SDValue& R2) {
228 if (Addr.getOpcode() == ISD::TargetExternalSymbol ||
229 Addr.getOpcode() == ISD::TargetGlobalAddress) {
232 return SelectADDRParam(Addr, R1, R2);
236 bool AMDGPUDAGToDAGISel::SelectADDR64(SDValue Addr, SDValue& R1, SDValue& R2) {
237 if (Addr.getOpcode() == ISD::TargetExternalSymbol ||
238 Addr.getOpcode() == ISD::TargetGlobalAddress) {
242 if (Addr.getOpcode() == ISD::FrameIndex) {
243 if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
244 R1 = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i64);
245 R2 = CurDAG->getTargetConstant(0, SDLoc(Addr), MVT::i64);
248 R2 = CurDAG->getTargetConstant(0, SDLoc(Addr), MVT::i64);
250 } else if (Addr.getOpcode() == ISD::ADD) {
251 R1 = Addr.getOperand(0);
252 R2 = Addr.getOperand(1);
255 R2 = CurDAG->getTargetConstant(0, SDLoc(Addr), MVT::i64);
260 SDNode *AMDGPUDAGToDAGISel::glueCopyToM0(SDNode *N) const {
261 if (Subtarget->getGeneration() < AMDGPUSubtarget::SOUTHERN_ISLANDS ||
262 !checkType(cast<MemSDNode>(N)->getMemOperand()->getValue(),
263 AMDGPUAS::LOCAL_ADDRESS))
266 const SITargetLowering& Lowering =
267 *static_cast<const SITargetLowering*>(getTargetLowering());
269 // Write max value to m0 before each load operation
271 SDValue M0 = Lowering.copyToM0(*CurDAG, CurDAG->getEntryNode(), SDLoc(N),
272 CurDAG->getTargetConstant(-1, SDLoc(N), MVT::i32));
274 SDValue Glue = M0.getValue(1);
276 SmallVector <SDValue, 8> Ops;
277 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
278 Ops.push_back(N->getOperand(i));
281 CurDAG->MorphNodeTo(N, N->getOpcode(), N->getVTList(), Ops);
286 SDNode *AMDGPUDAGToDAGISel::Select(SDNode *N) {
287 unsigned int Opc = N->getOpcode();
288 if (N->isMachineOpcode()) {
290 return nullptr; // Already selected.
293 if (isa<AtomicSDNode>(N))
298 // We are selecting i64 ADD here instead of custom lower it during
299 // DAG legalization, so we can fold some i64 ADDs used for address
300 // calculation into the LOAD and STORE instructions.
303 if (N->getValueType(0) != MVT::i64 ||
304 Subtarget->getGeneration() < AMDGPUSubtarget::SOUTHERN_ISLANDS)
307 return SelectADD_SUB_I64(N);
309 case ISD::SCALAR_TO_VECTOR:
310 case AMDGPUISD::BUILD_VERTICAL_VECTOR:
311 case ISD::BUILD_VECTOR: {
313 const AMDGPURegisterInfo *TRI = Subtarget->getRegisterInfo();
314 EVT VT = N->getValueType(0);
315 unsigned NumVectorElts = VT.getVectorNumElements();
316 EVT EltVT = VT.getVectorElementType();
317 assert(EltVT.bitsEq(MVT::i32));
318 if (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS) {
320 for (SDNode::use_iterator U = N->use_begin(), E = SDNode::use_end();
322 if (!U->isMachineOpcode()) {
325 const TargetRegisterClass *RC = getOperandRegClass(*U, U.getOperandNo());
329 if (static_cast<const SIRegisterInfo *>(TRI)->isSGPRClass(RC)) {
333 switch(NumVectorElts) {
334 case 1: RegClassID = UseVReg ? AMDGPU::VGPR_32RegClassID :
335 AMDGPU::SReg_32RegClassID;
337 case 2: RegClassID = UseVReg ? AMDGPU::VReg_64RegClassID :
338 AMDGPU::SReg_64RegClassID;
340 case 4: RegClassID = UseVReg ? AMDGPU::VReg_128RegClassID :
341 AMDGPU::SReg_128RegClassID;
343 case 8: RegClassID = UseVReg ? AMDGPU::VReg_256RegClassID :
344 AMDGPU::SReg_256RegClassID;
346 case 16: RegClassID = UseVReg ? AMDGPU::VReg_512RegClassID :
347 AMDGPU::SReg_512RegClassID;
349 default: llvm_unreachable("Do not know how to lower this BUILD_VECTOR");
352 // BUILD_VECTOR was lowered into an IMPLICIT_DEF + 4 INSERT_SUBREG
353 // that adds a 128 bits reg copy when going through TwoAddressInstructions
354 // pass. We want to avoid 128 bits copies as much as possible because they
355 // can't be bundled by our scheduler.
356 switch(NumVectorElts) {
357 case 2: RegClassID = AMDGPU::R600_Reg64RegClassID; break;
359 if (Opc == AMDGPUISD::BUILD_VERTICAL_VECTOR)
360 RegClassID = AMDGPU::R600_Reg128VerticalRegClassID;
362 RegClassID = AMDGPU::R600_Reg128RegClassID;
364 default: llvm_unreachable("Do not know how to lower this BUILD_VECTOR");
369 SDValue RegClass = CurDAG->getTargetConstant(RegClassID, DL, MVT::i32);
371 if (NumVectorElts == 1) {
372 return CurDAG->SelectNodeTo(N, AMDGPU::COPY_TO_REGCLASS, EltVT,
373 N->getOperand(0), RegClass);
376 assert(NumVectorElts <= 16 && "Vectors with more than 16 elements not "
378 // 16 = Max Num Vector Elements
379 // 2 = 2 REG_SEQUENCE operands per element (value, subreg index)
380 // 1 = Vector Register Class
381 SmallVector<SDValue, 16 * 2 + 1> RegSeqArgs(NumVectorElts * 2 + 1);
383 RegSeqArgs[0] = CurDAG->getTargetConstant(RegClassID, DL, MVT::i32);
384 bool IsRegSeq = true;
385 unsigned NOps = N->getNumOperands();
386 for (unsigned i = 0; i < NOps; i++) {
387 // XXX: Why is this here?
388 if (isa<RegisterSDNode>(N->getOperand(i))) {
392 RegSeqArgs[1 + (2 * i)] = N->getOperand(i);
393 RegSeqArgs[1 + (2 * i) + 1] =
394 CurDAG->getTargetConstant(TRI->getSubRegFromChannel(i), DL,
398 if (NOps != NumVectorElts) {
399 // Fill in the missing undef elements if this was a scalar_to_vector.
400 assert(Opc == ISD::SCALAR_TO_VECTOR && NOps < NumVectorElts);
402 MachineSDNode *ImpDef = CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF,
404 for (unsigned i = NOps; i < NumVectorElts; ++i) {
405 RegSeqArgs[1 + (2 * i)] = SDValue(ImpDef, 0);
406 RegSeqArgs[1 + (2 * i) + 1] =
407 CurDAG->getTargetConstant(TRI->getSubRegFromChannel(i), DL, MVT::i32);
413 return CurDAG->SelectNodeTo(N, AMDGPU::REG_SEQUENCE, N->getVTList(),
416 case ISD::BUILD_PAIR: {
417 SDValue RC, SubReg0, SubReg1;
418 if (Subtarget->getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS) {
422 if (N->getValueType(0) == MVT::i128) {
423 RC = CurDAG->getTargetConstant(AMDGPU::SReg_128RegClassID, DL, MVT::i32);
424 SubReg0 = CurDAG->getTargetConstant(AMDGPU::sub0_sub1, DL, MVT::i32);
425 SubReg1 = CurDAG->getTargetConstant(AMDGPU::sub2_sub3, DL, MVT::i32);
426 } else if (N->getValueType(0) == MVT::i64) {
427 RC = CurDAG->getTargetConstant(AMDGPU::SReg_64RegClassID, DL, MVT::i32);
428 SubReg0 = CurDAG->getTargetConstant(AMDGPU::sub0, DL, MVT::i32);
429 SubReg1 = CurDAG->getTargetConstant(AMDGPU::sub1, DL, MVT::i32);
431 llvm_unreachable("Unhandled value type for BUILD_PAIR");
433 const SDValue Ops[] = { RC, N->getOperand(0), SubReg0,
434 N->getOperand(1), SubReg1 };
435 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE,
436 DL, N->getValueType(0), Ops);
440 case ISD::ConstantFP: {
441 if (Subtarget->getGeneration() < AMDGPUSubtarget::SOUTHERN_ISLANDS ||
442 N->getValueType(0).getSizeInBits() != 64 || isInlineImmediate(N))
446 if (ConstantFPSDNode *FP = dyn_cast<ConstantFPSDNode>(N))
447 Imm = FP->getValueAPF().bitcastToAPInt().getZExtValue();
449 ConstantSDNode *C = cast<ConstantSDNode>(N);
450 Imm = C->getZExtValue();
454 SDNode *Lo = CurDAG->getMachineNode(AMDGPU::S_MOV_B32, DL, MVT::i32,
455 CurDAG->getConstant(Imm & 0xFFFFFFFF, DL,
457 SDNode *Hi = CurDAG->getMachineNode(AMDGPU::S_MOV_B32, DL, MVT::i32,
458 CurDAG->getConstant(Imm >> 32, DL, MVT::i32));
459 const SDValue Ops[] = {
460 CurDAG->getTargetConstant(AMDGPU::SReg_64RegClassID, DL, MVT::i32),
461 SDValue(Lo, 0), CurDAG->getTargetConstant(AMDGPU::sub0, DL, MVT::i32),
462 SDValue(Hi, 0), CurDAG->getTargetConstant(AMDGPU::sub1, DL, MVT::i32)
465 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, DL,
466 N->getValueType(0), Ops);
470 LoadSDNode *LD = cast<LoadSDNode>(N);
472 EVT VT = N->getValueType(0);
474 if (VT != MVT::i64 || LD->getExtensionType() != ISD::NON_EXTLOAD) {
479 // To simplify the TableGen patters, we replace all i64 loads with
480 // v2i32 loads. Alternatively, we could promote i64 loads to v2i32
481 // during DAG legalization, however, so places (ExpandUnalignedLoad)
482 // in the DAG legalizer assume that if i64 is legal, so doing this
483 // promotion early can cause problems.
485 SDValue NewLoad = CurDAG->getLoad(MVT::v2i32, SDLoc(N), LD->getChain(),
486 LD->getBasePtr(), LD->getMemOperand());
487 SDValue BitCast = CurDAG->getNode(ISD::BITCAST, SL,
489 CurDAG->ReplaceAllUsesOfValueWith(SDValue(N, 1), NewLoad.getValue(1));
490 CurDAG->ReplaceAllUsesOfValueWith(SDValue(N, 0), BitCast);
491 SDNode *Load = glueCopyToM0(NewLoad.getNode());
493 N = BitCast.getNode();
498 // Handle i64 stores here for the same reason mentioned above for loads.
499 StoreSDNode *ST = cast<StoreSDNode>(N);
500 SDValue Value = ST->getValue();
501 if (Value.getValueType() == MVT::i64 && !ST->isTruncatingStore()) {
503 SDValue NewValue = CurDAG->getNode(ISD::BITCAST, SDLoc(N),
505 SDValue NewStore = CurDAG->getStore(ST->getChain(), SDLoc(N), NewValue,
506 ST->getBasePtr(), ST->getMemOperand());
508 CurDAG->ReplaceAllUsesOfValueWith(SDValue(N, 0), NewStore);
510 if (NewValue.getOpcode() == ISD::BITCAST) {
511 Select(NewStore.getNode());
512 return SelectCode(NewValue.getNode());
515 // getNode() may fold the bitcast if its input was another bitcast. If that
516 // happens we should only select the new store.
517 N = NewStore.getNode();
524 case AMDGPUISD::REGISTER_LOAD: {
525 if (Subtarget->getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS)
527 SDValue Addr, Offset;
530 SelectADDRIndirect(N->getOperand(1), Addr, Offset);
531 const SDValue Ops[] = {
534 CurDAG->getTargetConstant(0, DL, MVT::i32),
537 return CurDAG->getMachineNode(AMDGPU::SI_RegisterLoad, DL,
538 CurDAG->getVTList(MVT::i32, MVT::i64,
542 case AMDGPUISD::REGISTER_STORE: {
543 if (Subtarget->getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS)
545 SDValue Addr, Offset;
546 SelectADDRIndirect(N->getOperand(2), Addr, Offset);
548 const SDValue Ops[] = {
552 CurDAG->getTargetConstant(0, DL, MVT::i32),
555 return CurDAG->getMachineNode(AMDGPU::SI_RegisterStorePseudo, DL,
556 CurDAG->getVTList(MVT::Other),
560 case AMDGPUISD::BFE_I32:
561 case AMDGPUISD::BFE_U32: {
562 if (Subtarget->getGeneration() < AMDGPUSubtarget::SOUTHERN_ISLANDS)
565 // There is a scalar version available, but unlike the vector version which
566 // has a separate operand for the offset and width, the scalar version packs
567 // the width and offset into a single operand. Try to move to the scalar
568 // version if the offsets are constant, so that we can try to keep extended
569 // loads of kernel arguments in SGPRs.
571 // TODO: Technically we could try to pattern match scalar bitshifts of
572 // dynamic values, but it's probably not useful.
573 ConstantSDNode *Offset = dyn_cast<ConstantSDNode>(N->getOperand(1));
577 ConstantSDNode *Width = dyn_cast<ConstantSDNode>(N->getOperand(2));
581 bool Signed = Opc == AMDGPUISD::BFE_I32;
583 uint32_t OffsetVal = Offset->getZExtValue();
584 uint32_t WidthVal = Width->getZExtValue();
586 return getS_BFE(Signed ? AMDGPU::S_BFE_I32 : AMDGPU::S_BFE_U32, SDLoc(N),
587 N->getOperand(0), OffsetVal, WidthVal);
590 case AMDGPUISD::DIV_SCALE: {
591 return SelectDIV_SCALE(N);
593 case ISD::CopyToReg: {
594 const SITargetLowering& Lowering =
595 *static_cast<const SITargetLowering*>(getTargetLowering());
596 Lowering.legalizeTargetIndependentNode(N, *CurDAG);
599 case ISD::ADDRSPACECAST:
600 return SelectAddrSpaceCast(N);
604 if (N->getValueType(0) != MVT::i32 ||
605 Subtarget->getGeneration() < AMDGPUSubtarget::SOUTHERN_ISLANDS)
608 return SelectS_BFE(N);
611 return SelectCode(N);
615 bool AMDGPUDAGToDAGISel::checkType(const Value *Ptr, unsigned AS) {
616 assert(AS != 0 && "Use checkPrivateAddress instead.");
620 return Ptr->getType()->getPointerAddressSpace() == AS;
623 bool AMDGPUDAGToDAGISel::checkPrivateAddress(const MachineMemOperand *Op) {
624 if (Op->getPseudoValue())
627 if (PointerType *PT = dyn_cast<PointerType>(Op->getValue()->getType()))
628 return PT->getAddressSpace() == AMDGPUAS::PRIVATE_ADDRESS;
633 bool AMDGPUDAGToDAGISel::isGlobalStore(const StoreSDNode *N) {
634 return checkType(N->getMemOperand()->getValue(), AMDGPUAS::GLOBAL_ADDRESS);
637 bool AMDGPUDAGToDAGISel::isPrivateStore(const StoreSDNode *N) {
638 const Value *MemVal = N->getMemOperand()->getValue();
639 return (!checkType(MemVal, AMDGPUAS::LOCAL_ADDRESS) &&
640 !checkType(MemVal, AMDGPUAS::GLOBAL_ADDRESS) &&
641 !checkType(MemVal, AMDGPUAS::REGION_ADDRESS));
644 bool AMDGPUDAGToDAGISel::isLocalStore(const StoreSDNode *N) {
645 return checkType(N->getMemOperand()->getValue(), AMDGPUAS::LOCAL_ADDRESS);
648 bool AMDGPUDAGToDAGISel::isFlatStore(const StoreSDNode *N) {
649 return checkType(N->getMemOperand()->getValue(), AMDGPUAS::FLAT_ADDRESS);
652 bool AMDGPUDAGToDAGISel::isRegionStore(const StoreSDNode *N) {
653 return checkType(N->getMemOperand()->getValue(), AMDGPUAS::REGION_ADDRESS);
656 bool AMDGPUDAGToDAGISel::isConstantLoad(const LoadSDNode *N, int CbId) const {
657 const Value *MemVal = N->getMemOperand()->getValue();
659 return checkType(MemVal, AMDGPUAS::CONSTANT_ADDRESS);
661 return checkType(MemVal, AMDGPUAS::CONSTANT_BUFFER_0 + CbId);
664 bool AMDGPUDAGToDAGISel::isGlobalLoad(const LoadSDNode *N) const {
665 if (N->getAddressSpace() == AMDGPUAS::CONSTANT_ADDRESS)
666 if (Subtarget->getGeneration() < AMDGPUSubtarget::SOUTHERN_ISLANDS ||
667 N->getMemoryVT().bitsLT(MVT::i32))
670 return checkType(N->getMemOperand()->getValue(), AMDGPUAS::GLOBAL_ADDRESS);
673 bool AMDGPUDAGToDAGISel::isParamLoad(const LoadSDNode *N) const {
674 return checkType(N->getMemOperand()->getValue(), AMDGPUAS::PARAM_I_ADDRESS);
677 bool AMDGPUDAGToDAGISel::isLocalLoad(const LoadSDNode *N) const {
678 return checkType(N->getMemOperand()->getValue(), AMDGPUAS::LOCAL_ADDRESS);
681 bool AMDGPUDAGToDAGISel::isFlatLoad(const LoadSDNode *N) const {
682 return checkType(N->getMemOperand()->getValue(), AMDGPUAS::FLAT_ADDRESS);
685 bool AMDGPUDAGToDAGISel::isRegionLoad(const LoadSDNode *N) const {
686 return checkType(N->getMemOperand()->getValue(), AMDGPUAS::REGION_ADDRESS);
689 bool AMDGPUDAGToDAGISel::isCPLoad(const LoadSDNode *N) const {
690 MachineMemOperand *MMO = N->getMemOperand();
691 if (checkPrivateAddress(N->getMemOperand())) {
693 const PseudoSourceValue *PSV = MMO->getPseudoValue();
694 if (PSV && PSV->isConstantPool()) {
702 bool AMDGPUDAGToDAGISel::isPrivateLoad(const LoadSDNode *N) const {
703 if (checkPrivateAddress(N->getMemOperand())) {
704 // Check to make sure we are not a constant pool load or a constant load
705 // that is marked as a private load
706 if (isCPLoad(N) || isConstantLoad(N, -1)) {
711 const Value *MemVal = N->getMemOperand()->getValue();
712 if (!checkType(MemVal, AMDGPUAS::LOCAL_ADDRESS) &&
713 !checkType(MemVal, AMDGPUAS::GLOBAL_ADDRESS) &&
714 !checkType(MemVal, AMDGPUAS::FLAT_ADDRESS) &&
715 !checkType(MemVal, AMDGPUAS::REGION_ADDRESS) &&
716 !checkType(MemVal, AMDGPUAS::CONSTANT_ADDRESS) &&
717 !checkType(MemVal, AMDGPUAS::PARAM_D_ADDRESS) &&
718 !checkType(MemVal, AMDGPUAS::PARAM_I_ADDRESS)) {
724 const char *AMDGPUDAGToDAGISel::getPassName() const {
725 return "AMDGPU DAG->DAG Pattern Instruction Selection";
733 //===----------------------------------------------------------------------===//
735 //===----------------------------------------------------------------------===//
737 bool AMDGPUDAGToDAGISel::SelectGlobalValueConstantOffset(SDValue Addr,
739 if (ConstantSDNode *Cst = dyn_cast<ConstantSDNode>(Addr)) {
740 IntPtr = CurDAG->getIntPtrConstant(Cst->getZExtValue() / 4, SDLoc(Addr),
747 bool AMDGPUDAGToDAGISel::SelectGlobalValueVariableOffset(SDValue Addr,
748 SDValue& BaseReg, SDValue &Offset) {
749 if (!isa<ConstantSDNode>(Addr)) {
751 Offset = CurDAG->getIntPtrConstant(0, SDLoc(Addr), true);
757 bool AMDGPUDAGToDAGISel::SelectADDRVTX_READ(SDValue Addr, SDValue &Base,
759 ConstantSDNode *IMMOffset;
761 if (Addr.getOpcode() == ISD::ADD
762 && (IMMOffset = dyn_cast<ConstantSDNode>(Addr.getOperand(1)))
763 && isInt<16>(IMMOffset->getZExtValue())) {
765 Base = Addr.getOperand(0);
766 Offset = CurDAG->getTargetConstant(IMMOffset->getZExtValue(), SDLoc(Addr),
769 // If the pointer address is constant, we can move it to the offset field.
770 } else if ((IMMOffset = dyn_cast<ConstantSDNode>(Addr))
771 && isInt<16>(IMMOffset->getZExtValue())) {
772 Base = CurDAG->getCopyFromReg(CurDAG->getEntryNode(),
773 SDLoc(CurDAG->getEntryNode()),
774 AMDGPU::ZERO, MVT::i32);
775 Offset = CurDAG->getTargetConstant(IMMOffset->getZExtValue(), SDLoc(Addr),
780 // Default case, no offset
782 Offset = CurDAG->getTargetConstant(0, SDLoc(Addr), MVT::i32);
786 bool AMDGPUDAGToDAGISel::SelectADDRIndirect(SDValue Addr, SDValue &Base,
791 if ((C = dyn_cast<ConstantSDNode>(Addr))) {
792 Base = CurDAG->getRegister(AMDGPU::INDIRECT_BASE_ADDR, MVT::i32);
793 Offset = CurDAG->getTargetConstant(C->getZExtValue(), DL, MVT::i32);
794 } else if ((Addr.getOpcode() == ISD::ADD || Addr.getOpcode() == ISD::OR) &&
795 (C = dyn_cast<ConstantSDNode>(Addr.getOperand(1)))) {
796 Base = Addr.getOperand(0);
797 Offset = CurDAG->getTargetConstant(C->getZExtValue(), DL, MVT::i32);
800 Offset = CurDAG->getTargetConstant(0, DL, MVT::i32);
806 SDNode *AMDGPUDAGToDAGISel::SelectADD_SUB_I64(SDNode *N) {
808 SDValue LHS = N->getOperand(0);
809 SDValue RHS = N->getOperand(1);
811 bool IsAdd = (N->getOpcode() == ISD::ADD);
813 SDValue Sub0 = CurDAG->getTargetConstant(AMDGPU::sub0, DL, MVT::i32);
814 SDValue Sub1 = CurDAG->getTargetConstant(AMDGPU::sub1, DL, MVT::i32);
816 SDNode *Lo0 = CurDAG->getMachineNode(TargetOpcode::EXTRACT_SUBREG,
817 DL, MVT::i32, LHS, Sub0);
818 SDNode *Hi0 = CurDAG->getMachineNode(TargetOpcode::EXTRACT_SUBREG,
819 DL, MVT::i32, LHS, Sub1);
821 SDNode *Lo1 = CurDAG->getMachineNode(TargetOpcode::EXTRACT_SUBREG,
822 DL, MVT::i32, RHS, Sub0);
823 SDNode *Hi1 = CurDAG->getMachineNode(TargetOpcode::EXTRACT_SUBREG,
824 DL, MVT::i32, RHS, Sub1);
826 SDVTList VTList = CurDAG->getVTList(MVT::i32, MVT::Glue);
827 SDValue AddLoArgs[] = { SDValue(Lo0, 0), SDValue(Lo1, 0) };
830 unsigned Opc = IsAdd ? AMDGPU::S_ADD_U32 : AMDGPU::S_SUB_U32;
831 unsigned CarryOpc = IsAdd ? AMDGPU::S_ADDC_U32 : AMDGPU::S_SUBB_U32;
833 SDNode *AddLo = CurDAG->getMachineNode( Opc, DL, VTList, AddLoArgs);
834 SDValue Carry(AddLo, 1);
836 = CurDAG->getMachineNode(CarryOpc, DL, MVT::i32,
837 SDValue(Hi0, 0), SDValue(Hi1, 0), Carry);
840 CurDAG->getTargetConstant(AMDGPU::SReg_64RegClassID, DL, MVT::i32),
846 return CurDAG->SelectNodeTo(N, AMDGPU::REG_SEQUENCE, MVT::i64, Args);
849 // We need to handle this here because tablegen doesn't support matching
850 // instructions with multiple outputs.
851 SDNode *AMDGPUDAGToDAGISel::SelectDIV_SCALE(SDNode *N) {
853 EVT VT = N->getValueType(0);
855 assert(VT == MVT::f32 || VT == MVT::f64);
858 = (VT == MVT::f64) ? AMDGPU::V_DIV_SCALE_F64 : AMDGPU::V_DIV_SCALE_F32;
860 // src0_modifiers, src0, src1_modifiers, src1, src2_modifiers, src2, clamp, omod
863 SelectVOP3Mods0(N->getOperand(0), Ops[1], Ops[0], Ops[6], Ops[7]);
864 SelectVOP3Mods(N->getOperand(1), Ops[3], Ops[2]);
865 SelectVOP3Mods(N->getOperand(2), Ops[5], Ops[4]);
866 return CurDAG->SelectNodeTo(N, Opc, VT, MVT::i1, Ops);
869 bool AMDGPUDAGToDAGISel::isDSOffsetLegal(const SDValue &Base, unsigned Offset,
870 unsigned OffsetBits) const {
871 if ((OffsetBits == 16 && !isUInt<16>(Offset)) ||
872 (OffsetBits == 8 && !isUInt<8>(Offset)))
875 if (Subtarget->getGeneration() >= AMDGPUSubtarget::SEA_ISLANDS ||
876 Subtarget->unsafeDSOffsetFoldingEnabled())
879 // On Southern Islands instruction with a negative base value and an offset
880 // don't seem to work.
881 return CurDAG->SignBitIsZero(Base);
884 bool AMDGPUDAGToDAGISel::SelectDS1Addr1Offset(SDValue Addr, SDValue &Base,
885 SDValue &Offset) const {
886 if (CurDAG->isBaseWithConstantOffset(Addr)) {
887 SDValue N0 = Addr.getOperand(0);
888 SDValue N1 = Addr.getOperand(1);
889 ConstantSDNode *C1 = cast<ConstantSDNode>(N1);
890 if (isDSOffsetLegal(N0, C1->getSExtValue(), 16)) {
896 } else if (Addr.getOpcode() == ISD::SUB) {
897 // sub C, x -> add (sub 0, x), C
898 if (const ConstantSDNode *C = dyn_cast<ConstantSDNode>(Addr.getOperand(0))) {
899 int64_t ByteOffset = C->getSExtValue();
900 if (isUInt<16>(ByteOffset)) {
902 SDValue Zero = CurDAG->getTargetConstant(0, DL, MVT::i32);
904 // XXX - This is kind of hacky. Create a dummy sub node so we can check
905 // the known bits in isDSOffsetLegal. We need to emit the selected node
906 // here, so this is thrown away.
907 SDValue Sub = CurDAG->getNode(ISD::SUB, DL, MVT::i32,
908 Zero, Addr.getOperand(1));
910 if (isDSOffsetLegal(Sub, ByteOffset, 16)) {
911 MachineSDNode *MachineSub
912 = CurDAG->getMachineNode(AMDGPU::V_SUB_I32_e32, DL, MVT::i32,
913 Zero, Addr.getOperand(1));
915 Base = SDValue(MachineSub, 0);
916 Offset = Addr.getOperand(0);
921 } else if (const ConstantSDNode *CAddr = dyn_cast<ConstantSDNode>(Addr)) {
922 // If we have a constant address, prefer to put the constant into the
923 // offset. This can save moves to load the constant address since multiple
924 // operations can share the zero base address register, and enables merging
925 // into read2 / write2 instructions.
929 if (isUInt<16>(CAddr->getZExtValue())) {
930 SDValue Zero = CurDAG->getTargetConstant(0, DL, MVT::i32);
931 MachineSDNode *MovZero = CurDAG->getMachineNode(AMDGPU::V_MOV_B32_e32,
933 Base = SDValue(MovZero, 0);
941 Offset = CurDAG->getTargetConstant(0, SDLoc(Addr), MVT::i16);
945 // TODO: If offset is too big, put low 16-bit into offset.
946 bool AMDGPUDAGToDAGISel::SelectDS64Bit4ByteAligned(SDValue Addr, SDValue &Base,
948 SDValue &Offset1) const {
951 if (CurDAG->isBaseWithConstantOffset(Addr)) {
952 SDValue N0 = Addr.getOperand(0);
953 SDValue N1 = Addr.getOperand(1);
954 ConstantSDNode *C1 = cast<ConstantSDNode>(N1);
955 unsigned DWordOffset0 = C1->getZExtValue() / 4;
956 unsigned DWordOffset1 = DWordOffset0 + 1;
958 if (isDSOffsetLegal(N0, DWordOffset1, 8)) {
960 Offset0 = CurDAG->getTargetConstant(DWordOffset0, DL, MVT::i8);
961 Offset1 = CurDAG->getTargetConstant(DWordOffset1, DL, MVT::i8);
964 } else if (Addr.getOpcode() == ISD::SUB) {
965 // sub C, x -> add (sub 0, x), C
966 if (const ConstantSDNode *C = dyn_cast<ConstantSDNode>(Addr.getOperand(0))) {
967 unsigned DWordOffset0 = C->getZExtValue() / 4;
968 unsigned DWordOffset1 = DWordOffset0 + 1;
970 if (isUInt<8>(DWordOffset0)) {
972 SDValue Zero = CurDAG->getTargetConstant(0, DL, MVT::i32);
974 // XXX - This is kind of hacky. Create a dummy sub node so we can check
975 // the known bits in isDSOffsetLegal. We need to emit the selected node
976 // here, so this is thrown away.
977 SDValue Sub = CurDAG->getNode(ISD::SUB, DL, MVT::i32,
978 Zero, Addr.getOperand(1));
980 if (isDSOffsetLegal(Sub, DWordOffset1, 8)) {
981 MachineSDNode *MachineSub
982 = CurDAG->getMachineNode(AMDGPU::V_SUB_I32_e32, DL, MVT::i32,
983 Zero, Addr.getOperand(1));
985 Base = SDValue(MachineSub, 0);
986 Offset0 = CurDAG->getTargetConstant(DWordOffset0, DL, MVT::i8);
987 Offset1 = CurDAG->getTargetConstant(DWordOffset1, DL, MVT::i8);
992 } else if (const ConstantSDNode *CAddr = dyn_cast<ConstantSDNode>(Addr)) {
993 unsigned DWordOffset0 = CAddr->getZExtValue() / 4;
994 unsigned DWordOffset1 = DWordOffset0 + 1;
995 assert(4 * DWordOffset0 == CAddr->getZExtValue());
997 if (isUInt<8>(DWordOffset0) && isUInt<8>(DWordOffset1)) {
998 SDValue Zero = CurDAG->getTargetConstant(0, DL, MVT::i32);
999 MachineSDNode *MovZero
1000 = CurDAG->getMachineNode(AMDGPU::V_MOV_B32_e32,
1001 DL, MVT::i32, Zero);
1002 Base = SDValue(MovZero, 0);
1003 Offset0 = CurDAG->getTargetConstant(DWordOffset0, DL, MVT::i8);
1004 Offset1 = CurDAG->getTargetConstant(DWordOffset1, DL, MVT::i8);
1011 Offset0 = CurDAG->getTargetConstant(0, DL, MVT::i8);
1012 Offset1 = CurDAG->getTargetConstant(1, DL, MVT::i8);
1016 static bool isLegalMUBUFImmOffset(const ConstantSDNode *Imm) {
1017 return isUInt<12>(Imm->getZExtValue());
1020 void AMDGPUDAGToDAGISel::SelectMUBUF(SDValue Addr, SDValue &Ptr,
1021 SDValue &VAddr, SDValue &SOffset,
1022 SDValue &Offset, SDValue &Offen,
1023 SDValue &Idxen, SDValue &Addr64,
1024 SDValue &GLC, SDValue &SLC,
1025 SDValue &TFE) const {
1028 GLC = CurDAG->getTargetConstant(0, DL, MVT::i1);
1029 SLC = CurDAG->getTargetConstant(0, DL, MVT::i1);
1030 TFE = CurDAG->getTargetConstant(0, DL, MVT::i1);
1032 Idxen = CurDAG->getTargetConstant(0, DL, MVT::i1);
1033 Offen = CurDAG->getTargetConstant(0, DL, MVT::i1);
1034 Addr64 = CurDAG->getTargetConstant(0, DL, MVT::i1);
1035 SOffset = CurDAG->getTargetConstant(0, DL, MVT::i32);
1037 if (CurDAG->isBaseWithConstantOffset(Addr)) {
1038 SDValue N0 = Addr.getOperand(0);
1039 SDValue N1 = Addr.getOperand(1);
1040 ConstantSDNode *C1 = cast<ConstantSDNode>(N1);
1042 if (N0.getOpcode() == ISD::ADD) {
1043 // (add (add N2, N3), C1) -> addr64
1044 SDValue N2 = N0.getOperand(0);
1045 SDValue N3 = N0.getOperand(1);
1046 Addr64 = CurDAG->getTargetConstant(1, DL, MVT::i1);
1051 // (add N0, C1) -> offset
1052 VAddr = CurDAG->getTargetConstant(0, DL, MVT::i32);
1056 if (isLegalMUBUFImmOffset(C1)) {
1057 Offset = CurDAG->getTargetConstant(C1->getZExtValue(), DL, MVT::i16);
1059 } else if (isUInt<32>(C1->getZExtValue())) {
1060 // Illegal offset, store it in soffset.
1061 Offset = CurDAG->getTargetConstant(0, DL, MVT::i16);
1062 SOffset = SDValue(CurDAG->getMachineNode(AMDGPU::S_MOV_B32, DL, MVT::i32,
1063 CurDAG->getTargetConstant(C1->getZExtValue(), DL, MVT::i32)),
1069 if (Addr.getOpcode() == ISD::ADD) {
1070 // (add N0, N1) -> addr64
1071 SDValue N0 = Addr.getOperand(0);
1072 SDValue N1 = Addr.getOperand(1);
1073 Addr64 = CurDAG->getTargetConstant(1, DL, MVT::i1);
1076 Offset = CurDAG->getTargetConstant(0, DL, MVT::i16);
1080 // default case -> offset
1081 VAddr = CurDAG->getTargetConstant(0, DL, MVT::i32);
1083 Offset = CurDAG->getTargetConstant(0, DL, MVT::i16);
1087 bool AMDGPUDAGToDAGISel::SelectMUBUFAddr64(SDValue Addr, SDValue &SRsrc,
1088 SDValue &VAddr, SDValue &SOffset,
1089 SDValue &Offset, SDValue &GLC,
1090 SDValue &SLC, SDValue &TFE) const {
1091 SDValue Ptr, Offen, Idxen, Addr64;
1093 // addr64 bit was removed for volcanic islands.
1094 if (Subtarget->getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS)
1097 SelectMUBUF(Addr, Ptr, VAddr, SOffset, Offset, Offen, Idxen, Addr64,
1100 ConstantSDNode *C = cast<ConstantSDNode>(Addr64);
1101 if (C->getSExtValue()) {
1104 const SITargetLowering& Lowering =
1105 *static_cast<const SITargetLowering*>(getTargetLowering());
1107 SRsrc = SDValue(Lowering.wrapAddr64Rsrc(*CurDAG, DL, Ptr), 0);
1114 bool AMDGPUDAGToDAGISel::SelectMUBUFAddr64(SDValue Addr, SDValue &SRsrc,
1115 SDValue &VAddr, SDValue &SOffset,
1117 SDValue &SLC) const {
1118 SLC = CurDAG->getTargetConstant(0, SDLoc(Addr), MVT::i1);
1121 return SelectMUBUFAddr64(Addr, SRsrc, VAddr, SOffset, Offset, GLC, SLC, TFE);
1124 bool AMDGPUDAGToDAGISel::SelectMUBUFScratch(SDValue Addr, SDValue &Rsrc,
1125 SDValue &VAddr, SDValue &SOffset,
1126 SDValue &ImmOffset) const {
1129 MachineFunction &MF = CurDAG->getMachineFunction();
1130 const SIRegisterInfo *TRI =
1131 static_cast<const SIRegisterInfo *>(Subtarget->getRegisterInfo());
1132 MachineRegisterInfo &MRI = MF.getRegInfo();
1133 const SITargetLowering& Lowering =
1134 *static_cast<const SITargetLowering*>(getTargetLowering());
1136 unsigned ScratchOffsetReg =
1137 TRI->getPreloadedValue(MF, SIRegisterInfo::SCRATCH_WAVE_OFFSET);
1138 Lowering.CreateLiveInRegister(*CurDAG, &AMDGPU::SReg_32RegClass,
1139 ScratchOffsetReg, MVT::i32);
1140 SDValue Sym0 = CurDAG->getExternalSymbol("SCRATCH_RSRC_DWORD0", MVT::i32);
1141 SDValue ScratchRsrcDword0 =
1142 SDValue(CurDAG->getMachineNode(AMDGPU::S_MOV_B32, DL, MVT::i32, Sym0), 0);
1144 SDValue Sym1 = CurDAG->getExternalSymbol("SCRATCH_RSRC_DWORD1", MVT::i32);
1145 SDValue ScratchRsrcDword1 =
1146 SDValue(CurDAG->getMachineNode(AMDGPU::S_MOV_B32, DL, MVT::i32, Sym1), 0);
1148 const SDValue RsrcOps[] = {
1149 CurDAG->getTargetConstant(AMDGPU::SReg_64RegClassID, DL, MVT::i32),
1151 CurDAG->getTargetConstant(AMDGPU::sub0, DL, MVT::i32),
1153 CurDAG->getTargetConstant(AMDGPU::sub1, DL, MVT::i32),
1155 SDValue ScratchPtr = SDValue(CurDAG->getMachineNode(AMDGPU::REG_SEQUENCE, DL,
1156 MVT::v2i32, RsrcOps), 0);
1157 Rsrc = SDValue(Lowering.buildScratchRSRC(*CurDAG, DL, ScratchPtr), 0);
1158 SOffset = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), DL,
1159 MRI.getLiveInVirtReg(ScratchOffsetReg), MVT::i32);
1162 if (CurDAG->isBaseWithConstantOffset(Addr)) {
1163 SDValue N0 = Addr.getOperand(0);
1164 SDValue N1 = Addr.getOperand(1);
1165 // Offsets in vaddr must be positive.
1166 if (CurDAG->SignBitIsZero(N0)) {
1167 ConstantSDNode *C1 = cast<ConstantSDNode>(N1);
1168 if (isLegalMUBUFImmOffset(C1)) {
1170 ImmOffset = CurDAG->getTargetConstant(C1->getZExtValue(), DL, MVT::i16);
1178 ImmOffset = CurDAG->getTargetConstant(0, DL, MVT::i16);
1182 bool AMDGPUDAGToDAGISel::SelectMUBUFOffset(SDValue Addr, SDValue &SRsrc,
1183 SDValue &SOffset, SDValue &Offset,
1184 SDValue &GLC, SDValue &SLC,
1185 SDValue &TFE) const {
1186 SDValue Ptr, VAddr, Offen, Idxen, Addr64;
1187 const SIInstrInfo *TII =
1188 static_cast<const SIInstrInfo *>(Subtarget->getInstrInfo());
1190 SelectMUBUF(Addr, Ptr, VAddr, SOffset, Offset, Offen, Idxen, Addr64,
1193 if (!cast<ConstantSDNode>(Offen)->getSExtValue() &&
1194 !cast<ConstantSDNode>(Idxen)->getSExtValue() &&
1195 !cast<ConstantSDNode>(Addr64)->getSExtValue()) {
1196 uint64_t Rsrc = TII->getDefaultRsrcDataFormat() |
1197 APInt::getAllOnesValue(32).getZExtValue(); // Size
1200 const SITargetLowering& Lowering =
1201 *static_cast<const SITargetLowering*>(getTargetLowering());
1203 SRsrc = SDValue(Lowering.buildRSRC(*CurDAG, DL, Ptr, 0, Rsrc), 0);
1209 bool AMDGPUDAGToDAGISel::SelectMUBUFOffset(SDValue Addr, SDValue &SRsrc,
1210 SDValue &Soffset, SDValue &Offset,
1211 SDValue &GLC) const {
1214 return SelectMUBUFOffset(Addr, SRsrc, Soffset, Offset, GLC, SLC, TFE);
1218 /// \param EncodedOffset This is the immediate value that will be encoded
1219 /// directly into the instruction. On SI/CI the \p EncodedOffset
1220 /// will be in units of dwords and on VI+ it will be units of bytes.
1221 static bool isLegalSMRDImmOffset(const AMDGPUSubtarget *ST,
1222 int64_t EncodedOffset) {
1223 return ST->getGeneration() < AMDGPUSubtarget::VOLCANIC_ISLANDS ?
1224 isUInt<8>(EncodedOffset) : isUInt<20>(EncodedOffset);
1227 bool AMDGPUDAGToDAGISel::SelectSMRDOffset(SDValue ByteOffsetNode,
1228 SDValue &Offset, bool &Imm) const {
1230 // FIXME: Handle non-constant offsets.
1231 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ByteOffsetNode);
1235 SDLoc SL(ByteOffsetNode);
1236 AMDGPUSubtarget::Generation Gen = Subtarget->getGeneration();
1237 int64_t ByteOffset = C->getSExtValue();
1238 int64_t EncodedOffset = Gen < AMDGPUSubtarget::VOLCANIC_ISLANDS ?
1239 ByteOffset >> 2 : ByteOffset;
1241 if (isLegalSMRDImmOffset(Subtarget, EncodedOffset)) {
1242 Offset = CurDAG->getTargetConstant(EncodedOffset, SL, MVT::i32);
1247 if (!isUInt<32>(EncodedOffset) || !isUInt<32>(ByteOffset))
1250 if (Gen == AMDGPUSubtarget::SEA_ISLANDS && isUInt<32>(EncodedOffset)) {
1251 // 32-bit Immediates are supported on Sea Islands.
1252 Offset = CurDAG->getTargetConstant(EncodedOffset, SL, MVT::i32);
1254 SDValue C32Bit = CurDAG->getTargetConstant(ByteOffset, SL, MVT::i32);
1255 Offset = SDValue(CurDAG->getMachineNode(AMDGPU::S_MOV_B32, SL, MVT::i32,
1262 bool AMDGPUDAGToDAGISel::SelectSMRD(SDValue Addr, SDValue &SBase,
1263 SDValue &Offset, bool &Imm) const {
1266 if (CurDAG->isBaseWithConstantOffset(Addr)) {
1267 SDValue N0 = Addr.getOperand(0);
1268 SDValue N1 = Addr.getOperand(1);
1270 if (SelectSMRDOffset(N1, Offset, Imm)) {
1276 Offset = CurDAG->getTargetConstant(0, SL, MVT::i32);
1281 bool AMDGPUDAGToDAGISel::SelectSMRDImm(SDValue Addr, SDValue &SBase,
1282 SDValue &Offset) const {
1284 return SelectSMRD(Addr, SBase, Offset, Imm) && Imm;
1287 bool AMDGPUDAGToDAGISel::SelectSMRDImm32(SDValue Addr, SDValue &SBase,
1288 SDValue &Offset) const {
1290 if (Subtarget->getGeneration() != AMDGPUSubtarget::SEA_ISLANDS)
1294 if (!SelectSMRD(Addr, SBase, Offset, Imm))
1297 return !Imm && isa<ConstantSDNode>(Offset);
1300 bool AMDGPUDAGToDAGISel::SelectSMRDSgpr(SDValue Addr, SDValue &SBase,
1301 SDValue &Offset) const {
1303 return SelectSMRD(Addr, SBase, Offset, Imm) && !Imm &&
1304 !isa<ConstantSDNode>(Offset);
1307 bool AMDGPUDAGToDAGISel::SelectSMRDBufferImm(SDValue Addr,
1308 SDValue &Offset) const {
1310 return SelectSMRDOffset(Addr, Offset, Imm) && Imm;
1313 bool AMDGPUDAGToDAGISel::SelectSMRDBufferImm32(SDValue Addr,
1314 SDValue &Offset) const {
1315 if (Subtarget->getGeneration() != AMDGPUSubtarget::SEA_ISLANDS)
1319 if (!SelectSMRDOffset(Addr, Offset, Imm))
1322 return !Imm && isa<ConstantSDNode>(Offset);
1325 bool AMDGPUDAGToDAGISel::SelectSMRDBufferSgpr(SDValue Addr,
1326 SDValue &Offset) const {
1328 return SelectSMRDOffset(Addr, Offset, Imm) && !Imm &&
1329 !isa<ConstantSDNode>(Offset);
1332 // FIXME: This is incorrect and only enough to be able to compile.
1333 SDNode *AMDGPUDAGToDAGISel::SelectAddrSpaceCast(SDNode *N) {
1334 AddrSpaceCastSDNode *ASC = cast<AddrSpaceCastSDNode>(N);
1337 assert(Subtarget->hasFlatAddressSpace() &&
1338 "addrspacecast only supported with flat address space!");
1340 assert((ASC->getSrcAddressSpace() != AMDGPUAS::CONSTANT_ADDRESS &&
1341 ASC->getDestAddressSpace() != AMDGPUAS::CONSTANT_ADDRESS) &&
1342 "Cannot cast address space to / from constant address!");
1344 assert((ASC->getSrcAddressSpace() == AMDGPUAS::FLAT_ADDRESS ||
1345 ASC->getDestAddressSpace() == AMDGPUAS::FLAT_ADDRESS) &&
1346 "Can only cast to / from flat address space!");
1348 // The flat instructions read the address as the index of the VGPR holding the
1349 // address, so casting should just be reinterpreting the base VGPR, so just
1350 // insert trunc / bitcast / zext.
1352 SDValue Src = ASC->getOperand(0);
1353 EVT DestVT = ASC->getValueType(0);
1354 EVT SrcVT = Src.getValueType();
1356 unsigned SrcSize = SrcVT.getSizeInBits();
1357 unsigned DestSize = DestVT.getSizeInBits();
1359 if (SrcSize > DestSize) {
1360 assert(SrcSize == 64 && DestSize == 32);
1361 return CurDAG->getMachineNode(
1362 TargetOpcode::EXTRACT_SUBREG,
1366 CurDAG->getTargetConstant(AMDGPU::sub0, DL, MVT::i32));
1370 if (DestSize > SrcSize) {
1371 assert(SrcSize == 32 && DestSize == 64);
1373 // FIXME: This is probably wrong, we should never be defining
1374 // a register class with both VGPRs and SGPRs
1375 SDValue RC = CurDAG->getTargetConstant(AMDGPU::VS_64RegClassID, DL,
1378 const SDValue Ops[] = {
1381 CurDAG->getTargetConstant(AMDGPU::sub0, DL, MVT::i32),
1382 SDValue(CurDAG->getMachineNode(AMDGPU::S_MOV_B32, DL, MVT::i32,
1383 CurDAG->getConstant(0, DL, MVT::i32)), 0),
1384 CurDAG->getTargetConstant(AMDGPU::sub1, DL, MVT::i32)
1387 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE,
1388 DL, N->getValueType(0), Ops);
1391 assert(SrcSize == 64 && DestSize == 64);
1392 return CurDAG->getNode(ISD::BITCAST, DL, DestVT, Src).getNode();
1395 SDNode *AMDGPUDAGToDAGISel::getS_BFE(unsigned Opcode, SDLoc DL, SDValue Val,
1396 uint32_t Offset, uint32_t Width) {
1397 // Transformation function, pack the offset and width of a BFE into
1398 // the format expected by the S_BFE_I32 / S_BFE_U32. In the second
1399 // source, bits [5:0] contain the offset and bits [22:16] the width.
1400 uint32_t PackedVal = Offset | (Width << 16);
1401 SDValue PackedConst = CurDAG->getTargetConstant(PackedVal, DL, MVT::i32);
1403 return CurDAG->getMachineNode(Opcode, DL, MVT::i32, Val, PackedConst);
1406 SDNode *AMDGPUDAGToDAGISel::SelectS_BFEFromShifts(SDNode *N) {
1407 // "(a << b) srl c)" ---> "BFE_U32 a, (c-b), (32-c)
1408 // "(a << b) sra c)" ---> "BFE_I32 a, (c-b), (32-c)
1409 // Predicate: 0 < b <= c < 32
1411 const SDValue &Shl = N->getOperand(0);
1412 ConstantSDNode *B = dyn_cast<ConstantSDNode>(Shl->getOperand(1));
1413 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
1416 uint32_t BVal = B->getZExtValue();
1417 uint32_t CVal = C->getZExtValue();
1419 if (0 < BVal && BVal <= CVal && CVal < 32) {
1420 bool Signed = N->getOpcode() == ISD::SRA;
1421 unsigned Opcode = Signed ? AMDGPU::S_BFE_I32 : AMDGPU::S_BFE_U32;
1423 return getS_BFE(Opcode, SDLoc(N), Shl.getOperand(0),
1424 CVal - BVal, 32 - CVal);
1427 return SelectCode(N);
1430 SDNode *AMDGPUDAGToDAGISel::SelectS_BFE(SDNode *N) {
1431 switch (N->getOpcode()) {
1433 if (N->getOperand(0).getOpcode() == ISD::SRL) {
1434 // "(a srl b) & mask" ---> "BFE_U32 a, b, popcount(mask)"
1435 // Predicate: isMask(mask)
1436 const SDValue &Srl = N->getOperand(0);
1437 ConstantSDNode *Shift = dyn_cast<ConstantSDNode>(Srl.getOperand(1));
1438 ConstantSDNode *Mask = dyn_cast<ConstantSDNode>(N->getOperand(1));
1440 if (Shift && Mask) {
1441 uint32_t ShiftVal = Shift->getZExtValue();
1442 uint32_t MaskVal = Mask->getZExtValue();
1444 if (isMask_32(MaskVal)) {
1445 uint32_t WidthVal = countPopulation(MaskVal);
1447 return getS_BFE(AMDGPU::S_BFE_U32, SDLoc(N), Srl.getOperand(0),
1448 ShiftVal, WidthVal);
1454 if (N->getOperand(0).getOpcode() == ISD::AND) {
1455 // "(a & mask) srl b)" ---> "BFE_U32 a, b, popcount(mask >> b)"
1456 // Predicate: isMask(mask >> b)
1457 const SDValue &And = N->getOperand(0);
1458 ConstantSDNode *Shift = dyn_cast<ConstantSDNode>(N->getOperand(1));
1459 ConstantSDNode *Mask = dyn_cast<ConstantSDNode>(And->getOperand(1));
1461 if (Shift && Mask) {
1462 uint32_t ShiftVal = Shift->getZExtValue();
1463 uint32_t MaskVal = Mask->getZExtValue() >> ShiftVal;
1465 if (isMask_32(MaskVal)) {
1466 uint32_t WidthVal = countPopulation(MaskVal);
1468 return getS_BFE(AMDGPU::S_BFE_U32, SDLoc(N), And.getOperand(0),
1469 ShiftVal, WidthVal);
1472 } else if (N->getOperand(0).getOpcode() == ISD::SHL)
1473 return SelectS_BFEFromShifts(N);
1476 if (N->getOperand(0).getOpcode() == ISD::SHL)
1477 return SelectS_BFEFromShifts(N);
1481 return SelectCode(N);
1484 bool AMDGPUDAGToDAGISel::SelectVOP3Mods(SDValue In, SDValue &Src,
1485 SDValue &SrcMods) const {
1491 if (Src.getOpcode() == ISD::FNEG) {
1492 Mods |= SISrcMods::NEG;
1493 Src = Src.getOperand(0);
1496 if (Src.getOpcode() == ISD::FABS) {
1497 Mods |= SISrcMods::ABS;
1498 Src = Src.getOperand(0);
1501 SrcMods = CurDAG->getTargetConstant(Mods, SDLoc(In), MVT::i32);
1506 bool AMDGPUDAGToDAGISel::SelectVOP3NoMods(SDValue In, SDValue &Src,
1507 SDValue &SrcMods) const {
1508 bool Res = SelectVOP3Mods(In, Src, SrcMods);
1509 return Res && cast<ConstantSDNode>(SrcMods)->isNullValue();
1512 bool AMDGPUDAGToDAGISel::SelectVOP3Mods0(SDValue In, SDValue &Src,
1513 SDValue &SrcMods, SDValue &Clamp,
1514 SDValue &Omod) const {
1516 // FIXME: Handle Clamp and Omod
1517 Clamp = CurDAG->getTargetConstant(0, DL, MVT::i32);
1518 Omod = CurDAG->getTargetConstant(0, DL, MVT::i32);
1520 return SelectVOP3Mods(In, Src, SrcMods);
1523 bool AMDGPUDAGToDAGISel::SelectVOP3NoMods0(SDValue In, SDValue &Src,
1524 SDValue &SrcMods, SDValue &Clamp,
1525 SDValue &Omod) const {
1526 bool Res = SelectVOP3Mods0(In, Src, SrcMods, Clamp, Omod);
1528 return Res && cast<ConstantSDNode>(SrcMods)->isNullValue() &&
1529 cast<ConstantSDNode>(Clamp)->isNullValue() &&
1530 cast<ConstantSDNode>(Omod)->isNullValue();
1533 bool AMDGPUDAGToDAGISel::SelectVOP3Mods0Clamp(SDValue In, SDValue &Src,
1535 SDValue &Omod) const {
1536 // FIXME: Handle Omod
1537 Omod = CurDAG->getTargetConstant(0, SDLoc(In), MVT::i32);
1539 return SelectVOP3Mods(In, Src, SrcMods);
1542 bool AMDGPUDAGToDAGISel::SelectVOP3Mods0Clamp0OMod(SDValue In, SDValue &Src,
1545 SDValue &Omod) const {
1546 Clamp = Omod = CurDAG->getTargetConstant(0, SDLoc(In), MVT::i32);
1547 return SelectVOP3Mods(In, Src, SrcMods);
1550 void AMDGPUDAGToDAGISel::PostprocessISelDAG() {
1551 const AMDGPUTargetLowering& Lowering =
1552 *static_cast<const AMDGPUTargetLowering*>(getTargetLowering());
1553 bool IsModified = false;
1556 // Go over all selected nodes and try to fold them a bit more
1557 for (SDNode &Node : CurDAG->allnodes()) {
1558 MachineSDNode *MachineNode = dyn_cast<MachineSDNode>(&Node);
1562 SDNode *ResNode = Lowering.PostISelFolding(MachineNode, *CurDAG);
1563 if (ResNode != &Node) {
1564 ReplaceUses(&Node, ResNode);
1568 CurDAG->RemoveDeadNodes();
1569 } while (IsModified);