1 //===-- AMDILISelDAGToDAG.cpp - A dag to dag inst selector for AMDIL ------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //==-----------------------------------------------------------------------===//
11 /// \brief Defines an instruction selector for the AMDGPU target.
13 //===----------------------------------------------------------------------===//
14 #include "AMDGPUInstrInfo.h"
15 #include "AMDGPUISelLowering.h" // For AMDGPUISD
16 #include "AMDGPURegisterInfo.h"
17 #include "AMDGPUSubtarget.h"
18 #include "R600InstrInfo.h"
19 #include "SIDefines.h"
20 #include "SIISelLowering.h"
21 #include "SIMachineFunctionInfo.h"
22 #include "llvm/CodeGen/FunctionLoweringInfo.h"
23 #include "llvm/CodeGen/PseudoSourceValue.h"
24 #include "llvm/CodeGen/MachineFrameInfo.h"
25 #include "llvm/CodeGen/MachineRegisterInfo.h"
26 #include "llvm/CodeGen/SelectionDAG.h"
27 #include "llvm/CodeGen/SelectionDAGISel.h"
28 #include "llvm/IR/Function.h"
32 //===----------------------------------------------------------------------===//
33 // Instruction Selector Implementation
34 //===----------------------------------------------------------------------===//
37 /// AMDGPU specific code to select AMDGPU machine instructions for
38 /// SelectionDAG operations.
39 class AMDGPUDAGToDAGISel : public SelectionDAGISel {
40 // Subtarget - Keep a pointer to the AMDGPU Subtarget around so that we can
41 // make the right decision when generating code for different targets.
42 const AMDGPUSubtarget *Subtarget;
45 AMDGPUDAGToDAGISel(TargetMachine &TM);
46 virtual ~AMDGPUDAGToDAGISel();
47 bool runOnMachineFunction(MachineFunction &MF) override;
48 SDNode *Select(SDNode *N) override;
49 const char *getPassName() const override;
50 void PreprocessISelDAG() override;
51 void PostprocessISelDAG() override;
54 bool isInlineImmediate(SDNode *N) const;
55 bool FoldOperand(SDValue &Src, SDValue &Sel, SDValue &Neg, SDValue &Abs,
56 const R600InstrInfo *TII);
57 bool FoldOperands(unsigned, const R600InstrInfo *, std::vector<SDValue> &);
58 bool FoldDotOperands(unsigned, const R600InstrInfo *, std::vector<SDValue> &);
60 // Complex pattern selectors
61 bool SelectADDRParam(SDValue Addr, SDValue& R1, SDValue& R2);
62 bool SelectADDR(SDValue N, SDValue &R1, SDValue &R2);
63 bool SelectADDR64(SDValue N, SDValue &R1, SDValue &R2);
65 static bool checkType(const Value *ptr, unsigned int addrspace);
66 static bool checkPrivateAddress(const MachineMemOperand *Op);
68 static bool isGlobalStore(const StoreSDNode *N);
69 static bool isFlatStore(const StoreSDNode *N);
70 static bool isPrivateStore(const StoreSDNode *N);
71 static bool isLocalStore(const StoreSDNode *N);
72 static bool isRegionStore(const StoreSDNode *N);
74 bool isCPLoad(const LoadSDNode *N) const;
75 bool isConstantLoad(const LoadSDNode *N, int cbID) const;
76 bool isGlobalLoad(const LoadSDNode *N) const;
77 bool isFlatLoad(const LoadSDNode *N) const;
78 bool isParamLoad(const LoadSDNode *N) const;
79 bool isPrivateLoad(const LoadSDNode *N) const;
80 bool isLocalLoad(const LoadSDNode *N) const;
81 bool isRegionLoad(const LoadSDNode *N) const;
83 SDNode *glueCopyToM0(SDNode *N) const;
85 const TargetRegisterClass *getOperandRegClass(SDNode *N, unsigned OpNo) const;
86 bool SelectGlobalValueConstantOffset(SDValue Addr, SDValue& IntPtr);
87 bool SelectGlobalValueVariableOffset(SDValue Addr, SDValue &BaseReg,
89 bool SelectADDRVTX_READ(SDValue Addr, SDValue &Base, SDValue &Offset);
90 bool SelectADDRIndirect(SDValue Addr, SDValue &Base, SDValue &Offset);
91 bool isDSOffsetLegal(const SDValue &Base, unsigned Offset,
92 unsigned OffsetBits) const;
93 bool SelectDS1Addr1Offset(SDValue Ptr, SDValue &Base, SDValue &Offset) const;
94 bool SelectDS64Bit4ByteAligned(SDValue Ptr, SDValue &Base, SDValue &Offset0,
95 SDValue &Offset1) const;
96 void SelectMUBUF(SDValue Addr, SDValue &SRsrc, SDValue &VAddr,
97 SDValue &SOffset, SDValue &Offset, SDValue &Offen,
98 SDValue &Idxen, SDValue &Addr64, SDValue &GLC, SDValue &SLC,
100 bool SelectMUBUFAddr64(SDValue Addr, SDValue &SRsrc, SDValue &VAddr,
101 SDValue &SOffset, SDValue &Offset, SDValue &GLC,
102 SDValue &SLC, SDValue &TFE) const;
103 bool SelectMUBUFAddr64(SDValue Addr, SDValue &SRsrc,
104 SDValue &VAddr, SDValue &SOffset, SDValue &Offset,
106 bool SelectMUBUFScratch(SDValue Addr, SDValue &RSrc, SDValue &VAddr,
107 SDValue &SOffset, SDValue &ImmOffset) const;
108 bool SelectMUBUFOffset(SDValue Addr, SDValue &SRsrc, SDValue &SOffset,
109 SDValue &Offset, SDValue &GLC, SDValue &SLC,
111 bool SelectMUBUFOffset(SDValue Addr, SDValue &SRsrc, SDValue &Soffset,
112 SDValue &Offset, SDValue &GLC) const;
113 bool SelectSMRDOffset(SDValue ByteOffsetNode, SDValue &Offset,
115 bool SelectSMRD(SDValue Addr, SDValue &SBase, SDValue &Offset,
117 bool SelectSMRDImm(SDValue Addr, SDValue &SBase, SDValue &Offset) const;
118 bool SelectSMRDImm32(SDValue Addr, SDValue &SBase, SDValue &Offset) const;
119 bool SelectSMRDSgpr(SDValue Addr, SDValue &SBase, SDValue &Offset) const;
120 bool SelectSMRDBufferImm(SDValue Addr, SDValue &Offset) const;
121 bool SelectSMRDBufferImm32(SDValue Addr, SDValue &Offset) const;
122 bool SelectSMRDBufferSgpr(SDValue Addr, SDValue &Offset) const;
123 SDNode *SelectAddrSpaceCast(SDNode *N);
124 bool SelectVOP3Mods(SDValue In, SDValue &Src, SDValue &SrcMods) const;
125 bool SelectVOP3NoMods(SDValue In, SDValue &Src, SDValue &SrcMods) const;
126 bool SelectVOP3Mods0(SDValue In, SDValue &Src, SDValue &SrcMods,
127 SDValue &Clamp, SDValue &Omod) const;
128 bool SelectVOP3NoMods0(SDValue In, SDValue &Src, SDValue &SrcMods,
129 SDValue &Clamp, SDValue &Omod) const;
131 bool SelectVOP3Mods0Clamp(SDValue In, SDValue &Src, SDValue &SrcMods,
132 SDValue &Omod) const;
133 bool SelectVOP3Mods0Clamp0OMod(SDValue In, SDValue &Src, SDValue &SrcMods,
135 SDValue &Omod) const;
137 SDNode *SelectADD_SUB_I64(SDNode *N);
138 SDNode *SelectDIV_SCALE(SDNode *N);
140 SDNode *getS_BFE(unsigned Opcode, SDLoc DL, SDValue Val,
141 uint32_t Offset, uint32_t Width);
142 SDNode *SelectS_BFEFromShifts(SDNode *N);
143 SDNode *SelectS_BFE(SDNode *N);
145 // Include the pieces autogenerated from the target description.
146 #include "AMDGPUGenDAGISel.inc"
148 } // end anonymous namespace
150 /// \brief This pass converts a legalized DAG into a AMDGPU-specific
151 // DAG, ready for instruction scheduling.
152 FunctionPass *llvm::createAMDGPUISelDag(TargetMachine &TM) {
153 return new AMDGPUDAGToDAGISel(TM);
156 AMDGPUDAGToDAGISel::AMDGPUDAGToDAGISel(TargetMachine &TM)
157 : SelectionDAGISel(TM) {}
159 bool AMDGPUDAGToDAGISel::runOnMachineFunction(MachineFunction &MF) {
160 Subtarget = &static_cast<const AMDGPUSubtarget &>(MF.getSubtarget());
161 return SelectionDAGISel::runOnMachineFunction(MF);
164 AMDGPUDAGToDAGISel::~AMDGPUDAGToDAGISel() {
167 bool AMDGPUDAGToDAGISel::isInlineImmediate(SDNode *N) const {
168 const SITargetLowering *TL
169 = static_cast<const SITargetLowering *>(getTargetLowering());
170 return TL->analyzeImmediate(N) == 0;
173 /// \brief Determine the register class for \p OpNo
174 /// \returns The register class of the virtual register that will be used for
175 /// the given operand number \OpNo or NULL if the register class cannot be
177 const TargetRegisterClass *AMDGPUDAGToDAGISel::getOperandRegClass(SDNode *N,
178 unsigned OpNo) const {
179 if (!N->isMachineOpcode())
182 switch (N->getMachineOpcode()) {
184 const MCInstrDesc &Desc =
185 Subtarget->getInstrInfo()->get(N->getMachineOpcode());
186 unsigned OpIdx = Desc.getNumDefs() + OpNo;
187 if (OpIdx >= Desc.getNumOperands())
189 int RegClass = Desc.OpInfo[OpIdx].RegClass;
193 return Subtarget->getRegisterInfo()->getRegClass(RegClass);
195 case AMDGPU::REG_SEQUENCE: {
196 unsigned RCID = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
197 const TargetRegisterClass *SuperRC =
198 Subtarget->getRegisterInfo()->getRegClass(RCID);
200 SDValue SubRegOp = N->getOperand(OpNo + 1);
201 unsigned SubRegIdx = cast<ConstantSDNode>(SubRegOp)->getZExtValue();
202 return Subtarget->getRegisterInfo()->getSubClassWithSubReg(SuperRC,
208 bool AMDGPUDAGToDAGISel::SelectADDRParam(
209 SDValue Addr, SDValue& R1, SDValue& R2) {
211 if (Addr.getOpcode() == ISD::FrameIndex) {
212 if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
213 R1 = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
214 R2 = CurDAG->getTargetConstant(0, SDLoc(Addr), MVT::i32);
217 R2 = CurDAG->getTargetConstant(0, SDLoc(Addr), MVT::i32);
219 } else if (Addr.getOpcode() == ISD::ADD) {
220 R1 = Addr.getOperand(0);
221 R2 = Addr.getOperand(1);
224 R2 = CurDAG->getTargetConstant(0, SDLoc(Addr), MVT::i32);
229 bool AMDGPUDAGToDAGISel::SelectADDR(SDValue Addr, SDValue& R1, SDValue& R2) {
230 if (Addr.getOpcode() == ISD::TargetExternalSymbol ||
231 Addr.getOpcode() == ISD::TargetGlobalAddress) {
234 return SelectADDRParam(Addr, R1, R2);
238 bool AMDGPUDAGToDAGISel::SelectADDR64(SDValue Addr, SDValue& R1, SDValue& R2) {
239 if (Addr.getOpcode() == ISD::TargetExternalSymbol ||
240 Addr.getOpcode() == ISD::TargetGlobalAddress) {
244 if (Addr.getOpcode() == ISD::FrameIndex) {
245 if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
246 R1 = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i64);
247 R2 = CurDAG->getTargetConstant(0, SDLoc(Addr), MVT::i64);
250 R2 = CurDAG->getTargetConstant(0, SDLoc(Addr), MVT::i64);
252 } else if (Addr.getOpcode() == ISD::ADD) {
253 R1 = Addr.getOperand(0);
254 R2 = Addr.getOperand(1);
257 R2 = CurDAG->getTargetConstant(0, SDLoc(Addr), MVT::i64);
262 SDNode *AMDGPUDAGToDAGISel::glueCopyToM0(SDNode *N) const {
263 if (Subtarget->getGeneration() < AMDGPUSubtarget::SOUTHERN_ISLANDS ||
264 !checkType(cast<MemSDNode>(N)->getMemOperand()->getValue(),
265 AMDGPUAS::LOCAL_ADDRESS))
268 const SITargetLowering& Lowering =
269 *static_cast<const SITargetLowering*>(getTargetLowering());
271 // Write max value to m0 before each load operation
273 SDValue M0 = Lowering.copyToM0(*CurDAG, CurDAG->getEntryNode(), SDLoc(N),
274 CurDAG->getTargetConstant(-1, SDLoc(N), MVT::i32));
276 SDValue Glue = M0.getValue(1);
278 SmallVector <SDValue, 8> Ops;
279 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
280 Ops.push_back(N->getOperand(i));
283 CurDAG->MorphNodeTo(N, N->getOpcode(), N->getVTList(), Ops);
288 SDNode *AMDGPUDAGToDAGISel::Select(SDNode *N) {
289 unsigned int Opc = N->getOpcode();
290 if (N->isMachineOpcode()) {
292 return nullptr; // Already selected.
295 if (isa<AtomicSDNode>(N))
300 // We are selecting i64 ADD here instead of custom lower it during
301 // DAG legalization, so we can fold some i64 ADDs used for address
302 // calculation into the LOAD and STORE instructions.
305 if (N->getValueType(0) != MVT::i64 ||
306 Subtarget->getGeneration() < AMDGPUSubtarget::SOUTHERN_ISLANDS)
309 return SelectADD_SUB_I64(N);
311 case ISD::SCALAR_TO_VECTOR:
312 case AMDGPUISD::BUILD_VERTICAL_VECTOR:
313 case ISD::BUILD_VECTOR: {
315 const AMDGPURegisterInfo *TRI = Subtarget->getRegisterInfo();
316 EVT VT = N->getValueType(0);
317 unsigned NumVectorElts = VT.getVectorNumElements();
318 EVT EltVT = VT.getVectorElementType();
319 assert(EltVT.bitsEq(MVT::i32));
320 if (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS) {
322 for (SDNode::use_iterator U = N->use_begin(), E = SDNode::use_end();
324 if (!U->isMachineOpcode()) {
327 const TargetRegisterClass *RC = getOperandRegClass(*U, U.getOperandNo());
331 if (static_cast<const SIRegisterInfo *>(TRI)->isSGPRClass(RC)) {
335 switch(NumVectorElts) {
336 case 1: RegClassID = UseVReg ? AMDGPU::VGPR_32RegClassID :
337 AMDGPU::SReg_32RegClassID;
339 case 2: RegClassID = UseVReg ? AMDGPU::VReg_64RegClassID :
340 AMDGPU::SReg_64RegClassID;
342 case 4: RegClassID = UseVReg ? AMDGPU::VReg_128RegClassID :
343 AMDGPU::SReg_128RegClassID;
345 case 8: RegClassID = UseVReg ? AMDGPU::VReg_256RegClassID :
346 AMDGPU::SReg_256RegClassID;
348 case 16: RegClassID = UseVReg ? AMDGPU::VReg_512RegClassID :
349 AMDGPU::SReg_512RegClassID;
351 default: llvm_unreachable("Do not know how to lower this BUILD_VECTOR");
354 // BUILD_VECTOR was lowered into an IMPLICIT_DEF + 4 INSERT_SUBREG
355 // that adds a 128 bits reg copy when going through TwoAddressInstructions
356 // pass. We want to avoid 128 bits copies as much as possible because they
357 // can't be bundled by our scheduler.
358 switch(NumVectorElts) {
359 case 2: RegClassID = AMDGPU::R600_Reg64RegClassID; break;
361 if (Opc == AMDGPUISD::BUILD_VERTICAL_VECTOR)
362 RegClassID = AMDGPU::R600_Reg128VerticalRegClassID;
364 RegClassID = AMDGPU::R600_Reg128RegClassID;
366 default: llvm_unreachable("Do not know how to lower this BUILD_VECTOR");
371 SDValue RegClass = CurDAG->getTargetConstant(RegClassID, DL, MVT::i32);
373 if (NumVectorElts == 1) {
374 return CurDAG->SelectNodeTo(N, AMDGPU::COPY_TO_REGCLASS, EltVT,
375 N->getOperand(0), RegClass);
378 assert(NumVectorElts <= 16 && "Vectors with more than 16 elements not "
380 // 16 = Max Num Vector Elements
381 // 2 = 2 REG_SEQUENCE operands per element (value, subreg index)
382 // 1 = Vector Register Class
383 SmallVector<SDValue, 16 * 2 + 1> RegSeqArgs(NumVectorElts * 2 + 1);
385 RegSeqArgs[0] = CurDAG->getTargetConstant(RegClassID, DL, MVT::i32);
386 bool IsRegSeq = true;
387 unsigned NOps = N->getNumOperands();
388 for (unsigned i = 0; i < NOps; i++) {
389 // XXX: Why is this here?
390 if (isa<RegisterSDNode>(N->getOperand(i))) {
394 RegSeqArgs[1 + (2 * i)] = N->getOperand(i);
395 RegSeqArgs[1 + (2 * i) + 1] =
396 CurDAG->getTargetConstant(TRI->getSubRegFromChannel(i), DL,
400 if (NOps != NumVectorElts) {
401 // Fill in the missing undef elements if this was a scalar_to_vector.
402 assert(Opc == ISD::SCALAR_TO_VECTOR && NOps < NumVectorElts);
404 MachineSDNode *ImpDef = CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF,
406 for (unsigned i = NOps; i < NumVectorElts; ++i) {
407 RegSeqArgs[1 + (2 * i)] = SDValue(ImpDef, 0);
408 RegSeqArgs[1 + (2 * i) + 1] =
409 CurDAG->getTargetConstant(TRI->getSubRegFromChannel(i), DL, MVT::i32);
415 return CurDAG->SelectNodeTo(N, AMDGPU::REG_SEQUENCE, N->getVTList(),
418 case ISD::BUILD_PAIR: {
419 SDValue RC, SubReg0, SubReg1;
420 if (Subtarget->getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS) {
424 if (N->getValueType(0) == MVT::i128) {
425 RC = CurDAG->getTargetConstant(AMDGPU::SReg_128RegClassID, DL, MVT::i32);
426 SubReg0 = CurDAG->getTargetConstant(AMDGPU::sub0_sub1, DL, MVT::i32);
427 SubReg1 = CurDAG->getTargetConstant(AMDGPU::sub2_sub3, DL, MVT::i32);
428 } else if (N->getValueType(0) == MVT::i64) {
429 RC = CurDAG->getTargetConstant(AMDGPU::SReg_64RegClassID, DL, MVT::i32);
430 SubReg0 = CurDAG->getTargetConstant(AMDGPU::sub0, DL, MVT::i32);
431 SubReg1 = CurDAG->getTargetConstant(AMDGPU::sub1, DL, MVT::i32);
433 llvm_unreachable("Unhandled value type for BUILD_PAIR");
435 const SDValue Ops[] = { RC, N->getOperand(0), SubReg0,
436 N->getOperand(1), SubReg1 };
437 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE,
438 DL, N->getValueType(0), Ops);
442 case ISD::ConstantFP: {
443 if (Subtarget->getGeneration() < AMDGPUSubtarget::SOUTHERN_ISLANDS ||
444 N->getValueType(0).getSizeInBits() != 64 || isInlineImmediate(N))
448 if (ConstantFPSDNode *FP = dyn_cast<ConstantFPSDNode>(N))
449 Imm = FP->getValueAPF().bitcastToAPInt().getZExtValue();
451 ConstantSDNode *C = cast<ConstantSDNode>(N);
452 Imm = C->getZExtValue();
456 SDNode *Lo = CurDAG->getMachineNode(AMDGPU::S_MOV_B32, DL, MVT::i32,
457 CurDAG->getConstant(Imm & 0xFFFFFFFF, DL,
459 SDNode *Hi = CurDAG->getMachineNode(AMDGPU::S_MOV_B32, DL, MVT::i32,
460 CurDAG->getConstant(Imm >> 32, DL, MVT::i32));
461 const SDValue Ops[] = {
462 CurDAG->getTargetConstant(AMDGPU::SReg_64RegClassID, DL, MVT::i32),
463 SDValue(Lo, 0), CurDAG->getTargetConstant(AMDGPU::sub0, DL, MVT::i32),
464 SDValue(Hi, 0), CurDAG->getTargetConstant(AMDGPU::sub1, DL, MVT::i32)
467 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, DL,
468 N->getValueType(0), Ops);
475 case AMDGPUISD::REGISTER_LOAD: {
476 if (Subtarget->getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS)
478 SDValue Addr, Offset;
481 SelectADDRIndirect(N->getOperand(1), Addr, Offset);
482 const SDValue Ops[] = {
485 CurDAG->getTargetConstant(0, DL, MVT::i32),
488 return CurDAG->getMachineNode(AMDGPU::SI_RegisterLoad, DL,
489 CurDAG->getVTList(MVT::i32, MVT::i64,
493 case AMDGPUISD::REGISTER_STORE: {
494 if (Subtarget->getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS)
496 SDValue Addr, Offset;
497 SelectADDRIndirect(N->getOperand(2), Addr, Offset);
499 const SDValue Ops[] = {
503 CurDAG->getTargetConstant(0, DL, MVT::i32),
506 return CurDAG->getMachineNode(AMDGPU::SI_RegisterStorePseudo, DL,
507 CurDAG->getVTList(MVT::Other),
511 case AMDGPUISD::BFE_I32:
512 case AMDGPUISD::BFE_U32: {
513 if (Subtarget->getGeneration() < AMDGPUSubtarget::SOUTHERN_ISLANDS)
516 // There is a scalar version available, but unlike the vector version which
517 // has a separate operand for the offset and width, the scalar version packs
518 // the width and offset into a single operand. Try to move to the scalar
519 // version if the offsets are constant, so that we can try to keep extended
520 // loads of kernel arguments in SGPRs.
522 // TODO: Technically we could try to pattern match scalar bitshifts of
523 // dynamic values, but it's probably not useful.
524 ConstantSDNode *Offset = dyn_cast<ConstantSDNode>(N->getOperand(1));
528 ConstantSDNode *Width = dyn_cast<ConstantSDNode>(N->getOperand(2));
532 bool Signed = Opc == AMDGPUISD::BFE_I32;
534 uint32_t OffsetVal = Offset->getZExtValue();
535 uint32_t WidthVal = Width->getZExtValue();
537 return getS_BFE(Signed ? AMDGPU::S_BFE_I32 : AMDGPU::S_BFE_U32, SDLoc(N),
538 N->getOperand(0), OffsetVal, WidthVal);
540 case AMDGPUISD::DIV_SCALE: {
541 return SelectDIV_SCALE(N);
543 case ISD::CopyToReg: {
544 const SITargetLowering& Lowering =
545 *static_cast<const SITargetLowering*>(getTargetLowering());
546 Lowering.legalizeTargetIndependentNode(N, *CurDAG);
549 case ISD::ADDRSPACECAST:
550 return SelectAddrSpaceCast(N);
554 if (N->getValueType(0) != MVT::i32 ||
555 Subtarget->getGeneration() < AMDGPUSubtarget::SOUTHERN_ISLANDS)
558 return SelectS_BFE(N);
561 return SelectCode(N);
564 bool AMDGPUDAGToDAGISel::checkType(const Value *Ptr, unsigned AS) {
565 assert(AS != 0 && "Use checkPrivateAddress instead.");
569 return Ptr->getType()->getPointerAddressSpace() == AS;
572 bool AMDGPUDAGToDAGISel::checkPrivateAddress(const MachineMemOperand *Op) {
573 if (Op->getPseudoValue())
576 if (PointerType *PT = dyn_cast<PointerType>(Op->getValue()->getType()))
577 return PT->getAddressSpace() == AMDGPUAS::PRIVATE_ADDRESS;
582 bool AMDGPUDAGToDAGISel::isGlobalStore(const StoreSDNode *N) {
583 return checkType(N->getMemOperand()->getValue(), AMDGPUAS::GLOBAL_ADDRESS);
586 bool AMDGPUDAGToDAGISel::isPrivateStore(const StoreSDNode *N) {
587 const Value *MemVal = N->getMemOperand()->getValue();
588 return (!checkType(MemVal, AMDGPUAS::LOCAL_ADDRESS) &&
589 !checkType(MemVal, AMDGPUAS::GLOBAL_ADDRESS) &&
590 !checkType(MemVal, AMDGPUAS::REGION_ADDRESS));
593 bool AMDGPUDAGToDAGISel::isLocalStore(const StoreSDNode *N) {
594 return checkType(N->getMemOperand()->getValue(), AMDGPUAS::LOCAL_ADDRESS);
597 bool AMDGPUDAGToDAGISel::isFlatStore(const StoreSDNode *N) {
598 return checkType(N->getMemOperand()->getValue(), AMDGPUAS::FLAT_ADDRESS);
601 bool AMDGPUDAGToDAGISel::isRegionStore(const StoreSDNode *N) {
602 return checkType(N->getMemOperand()->getValue(), AMDGPUAS::REGION_ADDRESS);
605 bool AMDGPUDAGToDAGISel::isConstantLoad(const LoadSDNode *N, int CbId) const {
606 const Value *MemVal = N->getMemOperand()->getValue();
608 return checkType(MemVal, AMDGPUAS::CONSTANT_ADDRESS);
610 return checkType(MemVal, AMDGPUAS::CONSTANT_BUFFER_0 + CbId);
613 bool AMDGPUDAGToDAGISel::isGlobalLoad(const LoadSDNode *N) const {
614 if (N->getAddressSpace() == AMDGPUAS::CONSTANT_ADDRESS)
615 if (Subtarget->getGeneration() < AMDGPUSubtarget::SOUTHERN_ISLANDS ||
616 N->getMemoryVT().bitsLT(MVT::i32))
619 return checkType(N->getMemOperand()->getValue(), AMDGPUAS::GLOBAL_ADDRESS);
622 bool AMDGPUDAGToDAGISel::isParamLoad(const LoadSDNode *N) const {
623 return checkType(N->getMemOperand()->getValue(), AMDGPUAS::PARAM_I_ADDRESS);
626 bool AMDGPUDAGToDAGISel::isLocalLoad(const LoadSDNode *N) const {
627 return checkType(N->getMemOperand()->getValue(), AMDGPUAS::LOCAL_ADDRESS);
630 bool AMDGPUDAGToDAGISel::isFlatLoad(const LoadSDNode *N) const {
631 return checkType(N->getMemOperand()->getValue(), AMDGPUAS::FLAT_ADDRESS);
634 bool AMDGPUDAGToDAGISel::isRegionLoad(const LoadSDNode *N) const {
635 return checkType(N->getMemOperand()->getValue(), AMDGPUAS::REGION_ADDRESS);
638 bool AMDGPUDAGToDAGISel::isCPLoad(const LoadSDNode *N) const {
639 MachineMemOperand *MMO = N->getMemOperand();
640 if (checkPrivateAddress(N->getMemOperand())) {
642 const PseudoSourceValue *PSV = MMO->getPseudoValue();
643 if (PSV && PSV->isConstantPool()) {
651 bool AMDGPUDAGToDAGISel::isPrivateLoad(const LoadSDNode *N) const {
652 if (checkPrivateAddress(N->getMemOperand())) {
653 // Check to make sure we are not a constant pool load or a constant load
654 // that is marked as a private load
655 if (isCPLoad(N) || isConstantLoad(N, -1)) {
660 const Value *MemVal = N->getMemOperand()->getValue();
661 if (!checkType(MemVal, AMDGPUAS::LOCAL_ADDRESS) &&
662 !checkType(MemVal, AMDGPUAS::GLOBAL_ADDRESS) &&
663 !checkType(MemVal, AMDGPUAS::FLAT_ADDRESS) &&
664 !checkType(MemVal, AMDGPUAS::REGION_ADDRESS) &&
665 !checkType(MemVal, AMDGPUAS::CONSTANT_ADDRESS) &&
666 !checkType(MemVal, AMDGPUAS::PARAM_D_ADDRESS) &&
667 !checkType(MemVal, AMDGPUAS::PARAM_I_ADDRESS)) {
673 const char *AMDGPUDAGToDAGISel::getPassName() const {
674 return "AMDGPU DAG->DAG Pattern Instruction Selection";
682 //===----------------------------------------------------------------------===//
684 //===----------------------------------------------------------------------===//
686 bool AMDGPUDAGToDAGISel::SelectGlobalValueConstantOffset(SDValue Addr,
688 if (ConstantSDNode *Cst = dyn_cast<ConstantSDNode>(Addr)) {
689 IntPtr = CurDAG->getIntPtrConstant(Cst->getZExtValue() / 4, SDLoc(Addr),
696 bool AMDGPUDAGToDAGISel::SelectGlobalValueVariableOffset(SDValue Addr,
697 SDValue& BaseReg, SDValue &Offset) {
698 if (!isa<ConstantSDNode>(Addr)) {
700 Offset = CurDAG->getIntPtrConstant(0, SDLoc(Addr), true);
706 bool AMDGPUDAGToDAGISel::SelectADDRVTX_READ(SDValue Addr, SDValue &Base,
708 ConstantSDNode *IMMOffset;
710 if (Addr.getOpcode() == ISD::ADD
711 && (IMMOffset = dyn_cast<ConstantSDNode>(Addr.getOperand(1)))
712 && isInt<16>(IMMOffset->getZExtValue())) {
714 Base = Addr.getOperand(0);
715 Offset = CurDAG->getTargetConstant(IMMOffset->getZExtValue(), SDLoc(Addr),
718 // If the pointer address is constant, we can move it to the offset field.
719 } else if ((IMMOffset = dyn_cast<ConstantSDNode>(Addr))
720 && isInt<16>(IMMOffset->getZExtValue())) {
721 Base = CurDAG->getCopyFromReg(CurDAG->getEntryNode(),
722 SDLoc(CurDAG->getEntryNode()),
723 AMDGPU::ZERO, MVT::i32);
724 Offset = CurDAG->getTargetConstant(IMMOffset->getZExtValue(), SDLoc(Addr),
729 // Default case, no offset
731 Offset = CurDAG->getTargetConstant(0, SDLoc(Addr), MVT::i32);
735 bool AMDGPUDAGToDAGISel::SelectADDRIndirect(SDValue Addr, SDValue &Base,
740 if ((C = dyn_cast<ConstantSDNode>(Addr))) {
741 Base = CurDAG->getRegister(AMDGPU::INDIRECT_BASE_ADDR, MVT::i32);
742 Offset = CurDAG->getTargetConstant(C->getZExtValue(), DL, MVT::i32);
743 } else if ((Addr.getOpcode() == ISD::ADD || Addr.getOpcode() == ISD::OR) &&
744 (C = dyn_cast<ConstantSDNode>(Addr.getOperand(1)))) {
745 Base = Addr.getOperand(0);
746 Offset = CurDAG->getTargetConstant(C->getZExtValue(), DL, MVT::i32);
749 Offset = CurDAG->getTargetConstant(0, DL, MVT::i32);
755 SDNode *AMDGPUDAGToDAGISel::SelectADD_SUB_I64(SDNode *N) {
757 SDValue LHS = N->getOperand(0);
758 SDValue RHS = N->getOperand(1);
760 bool IsAdd = (N->getOpcode() == ISD::ADD);
762 SDValue Sub0 = CurDAG->getTargetConstant(AMDGPU::sub0, DL, MVT::i32);
763 SDValue Sub1 = CurDAG->getTargetConstant(AMDGPU::sub1, DL, MVT::i32);
765 SDNode *Lo0 = CurDAG->getMachineNode(TargetOpcode::EXTRACT_SUBREG,
766 DL, MVT::i32, LHS, Sub0);
767 SDNode *Hi0 = CurDAG->getMachineNode(TargetOpcode::EXTRACT_SUBREG,
768 DL, MVT::i32, LHS, Sub1);
770 SDNode *Lo1 = CurDAG->getMachineNode(TargetOpcode::EXTRACT_SUBREG,
771 DL, MVT::i32, RHS, Sub0);
772 SDNode *Hi1 = CurDAG->getMachineNode(TargetOpcode::EXTRACT_SUBREG,
773 DL, MVT::i32, RHS, Sub1);
775 SDVTList VTList = CurDAG->getVTList(MVT::i32, MVT::Glue);
776 SDValue AddLoArgs[] = { SDValue(Lo0, 0), SDValue(Lo1, 0) };
779 unsigned Opc = IsAdd ? AMDGPU::S_ADD_U32 : AMDGPU::S_SUB_U32;
780 unsigned CarryOpc = IsAdd ? AMDGPU::S_ADDC_U32 : AMDGPU::S_SUBB_U32;
782 SDNode *AddLo = CurDAG->getMachineNode( Opc, DL, VTList, AddLoArgs);
783 SDValue Carry(AddLo, 1);
785 = CurDAG->getMachineNode(CarryOpc, DL, MVT::i32,
786 SDValue(Hi0, 0), SDValue(Hi1, 0), Carry);
789 CurDAG->getTargetConstant(AMDGPU::SReg_64RegClassID, DL, MVT::i32),
795 return CurDAG->SelectNodeTo(N, AMDGPU::REG_SEQUENCE, MVT::i64, Args);
798 // We need to handle this here because tablegen doesn't support matching
799 // instructions with multiple outputs.
800 SDNode *AMDGPUDAGToDAGISel::SelectDIV_SCALE(SDNode *N) {
802 EVT VT = N->getValueType(0);
804 assert(VT == MVT::f32 || VT == MVT::f64);
807 = (VT == MVT::f64) ? AMDGPU::V_DIV_SCALE_F64 : AMDGPU::V_DIV_SCALE_F32;
809 // src0_modifiers, src0, src1_modifiers, src1, src2_modifiers, src2, clamp,
813 SelectVOP3Mods0(N->getOperand(0), Ops[1], Ops[0], Ops[6], Ops[7]);
814 SelectVOP3Mods(N->getOperand(1), Ops[3], Ops[2]);
815 SelectVOP3Mods(N->getOperand(2), Ops[5], Ops[4]);
816 return CurDAG->SelectNodeTo(N, Opc, VT, MVT::i1, Ops);
819 bool AMDGPUDAGToDAGISel::isDSOffsetLegal(const SDValue &Base, unsigned Offset,
820 unsigned OffsetBits) const {
821 if ((OffsetBits == 16 && !isUInt<16>(Offset)) ||
822 (OffsetBits == 8 && !isUInt<8>(Offset)))
825 if (Subtarget->getGeneration() >= AMDGPUSubtarget::SEA_ISLANDS ||
826 Subtarget->unsafeDSOffsetFoldingEnabled())
829 // On Southern Islands instruction with a negative base value and an offset
830 // don't seem to work.
831 return CurDAG->SignBitIsZero(Base);
834 bool AMDGPUDAGToDAGISel::SelectDS1Addr1Offset(SDValue Addr, SDValue &Base,
835 SDValue &Offset) const {
836 if (CurDAG->isBaseWithConstantOffset(Addr)) {
837 SDValue N0 = Addr.getOperand(0);
838 SDValue N1 = Addr.getOperand(1);
839 ConstantSDNode *C1 = cast<ConstantSDNode>(N1);
840 if (isDSOffsetLegal(N0, C1->getSExtValue(), 16)) {
846 } else if (Addr.getOpcode() == ISD::SUB) {
847 // sub C, x -> add (sub 0, x), C
848 if (const ConstantSDNode *C = dyn_cast<ConstantSDNode>(Addr.getOperand(0))) {
849 int64_t ByteOffset = C->getSExtValue();
850 if (isUInt<16>(ByteOffset)) {
852 SDValue Zero = CurDAG->getTargetConstant(0, DL, MVT::i32);
854 // XXX - This is kind of hacky. Create a dummy sub node so we can check
855 // the known bits in isDSOffsetLegal. We need to emit the selected node
856 // here, so this is thrown away.
857 SDValue Sub = CurDAG->getNode(ISD::SUB, DL, MVT::i32,
858 Zero, Addr.getOperand(1));
860 if (isDSOffsetLegal(Sub, ByteOffset, 16)) {
861 MachineSDNode *MachineSub
862 = CurDAG->getMachineNode(AMDGPU::V_SUB_I32_e32, DL, MVT::i32,
863 Zero, Addr.getOperand(1));
865 Base = SDValue(MachineSub, 0);
866 Offset = Addr.getOperand(0);
871 } else if (const ConstantSDNode *CAddr = dyn_cast<ConstantSDNode>(Addr)) {
872 // If we have a constant address, prefer to put the constant into the
873 // offset. This can save moves to load the constant address since multiple
874 // operations can share the zero base address register, and enables merging
875 // into read2 / write2 instructions.
879 if (isUInt<16>(CAddr->getZExtValue())) {
880 SDValue Zero = CurDAG->getTargetConstant(0, DL, MVT::i32);
881 MachineSDNode *MovZero = CurDAG->getMachineNode(AMDGPU::V_MOV_B32_e32,
883 Base = SDValue(MovZero, 0);
891 Offset = CurDAG->getTargetConstant(0, SDLoc(Addr), MVT::i16);
895 // TODO: If offset is too big, put low 16-bit into offset.
896 bool AMDGPUDAGToDAGISel::SelectDS64Bit4ByteAligned(SDValue Addr, SDValue &Base,
898 SDValue &Offset1) const {
901 if (CurDAG->isBaseWithConstantOffset(Addr)) {
902 SDValue N0 = Addr.getOperand(0);
903 SDValue N1 = Addr.getOperand(1);
904 ConstantSDNode *C1 = cast<ConstantSDNode>(N1);
905 unsigned DWordOffset0 = C1->getZExtValue() / 4;
906 unsigned DWordOffset1 = DWordOffset0 + 1;
908 if (isDSOffsetLegal(N0, DWordOffset1, 8)) {
910 Offset0 = CurDAG->getTargetConstant(DWordOffset0, DL, MVT::i8);
911 Offset1 = CurDAG->getTargetConstant(DWordOffset1, DL, MVT::i8);
914 } else if (Addr.getOpcode() == ISD::SUB) {
915 // sub C, x -> add (sub 0, x), C
916 if (const ConstantSDNode *C = dyn_cast<ConstantSDNode>(Addr.getOperand(0))) {
917 unsigned DWordOffset0 = C->getZExtValue() / 4;
918 unsigned DWordOffset1 = DWordOffset0 + 1;
920 if (isUInt<8>(DWordOffset0)) {
922 SDValue Zero = CurDAG->getTargetConstant(0, DL, MVT::i32);
924 // XXX - This is kind of hacky. Create a dummy sub node so we can check
925 // the known bits in isDSOffsetLegal. We need to emit the selected node
926 // here, so this is thrown away.
927 SDValue Sub = CurDAG->getNode(ISD::SUB, DL, MVT::i32,
928 Zero, Addr.getOperand(1));
930 if (isDSOffsetLegal(Sub, DWordOffset1, 8)) {
931 MachineSDNode *MachineSub
932 = CurDAG->getMachineNode(AMDGPU::V_SUB_I32_e32, DL, MVT::i32,
933 Zero, Addr.getOperand(1));
935 Base = SDValue(MachineSub, 0);
936 Offset0 = CurDAG->getTargetConstant(DWordOffset0, DL, MVT::i8);
937 Offset1 = CurDAG->getTargetConstant(DWordOffset1, DL, MVT::i8);
942 } else if (const ConstantSDNode *CAddr = dyn_cast<ConstantSDNode>(Addr)) {
943 unsigned DWordOffset0 = CAddr->getZExtValue() / 4;
944 unsigned DWordOffset1 = DWordOffset0 + 1;
945 assert(4 * DWordOffset0 == CAddr->getZExtValue());
947 if (isUInt<8>(DWordOffset0) && isUInt<8>(DWordOffset1)) {
948 SDValue Zero = CurDAG->getTargetConstant(0, DL, MVT::i32);
949 MachineSDNode *MovZero
950 = CurDAG->getMachineNode(AMDGPU::V_MOV_B32_e32,
952 Base = SDValue(MovZero, 0);
953 Offset0 = CurDAG->getTargetConstant(DWordOffset0, DL, MVT::i8);
954 Offset1 = CurDAG->getTargetConstant(DWordOffset1, DL, MVT::i8);
961 Offset0 = CurDAG->getTargetConstant(0, DL, MVT::i8);
962 Offset1 = CurDAG->getTargetConstant(1, DL, MVT::i8);
966 static bool isLegalMUBUFImmOffset(const ConstantSDNode *Imm) {
967 return isUInt<12>(Imm->getZExtValue());
970 void AMDGPUDAGToDAGISel::SelectMUBUF(SDValue Addr, SDValue &Ptr,
971 SDValue &VAddr, SDValue &SOffset,
972 SDValue &Offset, SDValue &Offen,
973 SDValue &Idxen, SDValue &Addr64,
974 SDValue &GLC, SDValue &SLC,
975 SDValue &TFE) const {
978 GLC = CurDAG->getTargetConstant(0, DL, MVT::i1);
979 SLC = CurDAG->getTargetConstant(0, DL, MVT::i1);
980 TFE = CurDAG->getTargetConstant(0, DL, MVT::i1);
982 Idxen = CurDAG->getTargetConstant(0, DL, MVT::i1);
983 Offen = CurDAG->getTargetConstant(0, DL, MVT::i1);
984 Addr64 = CurDAG->getTargetConstant(0, DL, MVT::i1);
985 SOffset = CurDAG->getTargetConstant(0, DL, MVT::i32);
987 if (CurDAG->isBaseWithConstantOffset(Addr)) {
988 SDValue N0 = Addr.getOperand(0);
989 SDValue N1 = Addr.getOperand(1);
990 ConstantSDNode *C1 = cast<ConstantSDNode>(N1);
992 if (N0.getOpcode() == ISD::ADD) {
993 // (add (add N2, N3), C1) -> addr64
994 SDValue N2 = N0.getOperand(0);
995 SDValue N3 = N0.getOperand(1);
996 Addr64 = CurDAG->getTargetConstant(1, DL, MVT::i1);
1001 // (add N0, C1) -> offset
1002 VAddr = CurDAG->getTargetConstant(0, DL, MVT::i32);
1006 if (isLegalMUBUFImmOffset(C1)) {
1007 Offset = CurDAG->getTargetConstant(C1->getZExtValue(), DL, MVT::i16);
1009 } else if (isUInt<32>(C1->getZExtValue())) {
1010 // Illegal offset, store it in soffset.
1011 Offset = CurDAG->getTargetConstant(0, DL, MVT::i16);
1012 SOffset = SDValue(CurDAG->getMachineNode(AMDGPU::S_MOV_B32, DL, MVT::i32,
1013 CurDAG->getTargetConstant(C1->getZExtValue(), DL, MVT::i32)),
1019 if (Addr.getOpcode() == ISD::ADD) {
1020 // (add N0, N1) -> addr64
1021 SDValue N0 = Addr.getOperand(0);
1022 SDValue N1 = Addr.getOperand(1);
1023 Addr64 = CurDAG->getTargetConstant(1, DL, MVT::i1);
1026 Offset = CurDAG->getTargetConstant(0, DL, MVT::i16);
1030 // default case -> offset
1031 VAddr = CurDAG->getTargetConstant(0, DL, MVT::i32);
1033 Offset = CurDAG->getTargetConstant(0, DL, MVT::i16);
1036 bool AMDGPUDAGToDAGISel::SelectMUBUFAddr64(SDValue Addr, SDValue &SRsrc,
1037 SDValue &VAddr, SDValue &SOffset,
1038 SDValue &Offset, SDValue &GLC,
1039 SDValue &SLC, SDValue &TFE) const {
1040 SDValue Ptr, Offen, Idxen, Addr64;
1042 // addr64 bit was removed for volcanic islands.
1043 if (Subtarget->getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS)
1046 SelectMUBUF(Addr, Ptr, VAddr, SOffset, Offset, Offen, Idxen, Addr64,
1049 ConstantSDNode *C = cast<ConstantSDNode>(Addr64);
1050 if (C->getSExtValue()) {
1053 const SITargetLowering& Lowering =
1054 *static_cast<const SITargetLowering*>(getTargetLowering());
1056 SRsrc = SDValue(Lowering.wrapAddr64Rsrc(*CurDAG, DL, Ptr), 0);
1063 bool AMDGPUDAGToDAGISel::SelectMUBUFAddr64(SDValue Addr, SDValue &SRsrc,
1064 SDValue &VAddr, SDValue &SOffset,
1066 SDValue &SLC) const {
1067 SLC = CurDAG->getTargetConstant(0, SDLoc(Addr), MVT::i1);
1070 return SelectMUBUFAddr64(Addr, SRsrc, VAddr, SOffset, Offset, GLC, SLC, TFE);
1073 bool AMDGPUDAGToDAGISel::SelectMUBUFScratch(SDValue Addr, SDValue &Rsrc,
1074 SDValue &VAddr, SDValue &SOffset,
1075 SDValue &ImmOffset) const {
1078 MachineFunction &MF = CurDAG->getMachineFunction();
1079 const SIRegisterInfo *TRI =
1080 static_cast<const SIRegisterInfo *>(Subtarget->getRegisterInfo());
1081 MachineRegisterInfo &MRI = MF.getRegInfo();
1082 const SITargetLowering& Lowering =
1083 *static_cast<const SITargetLowering*>(getTargetLowering());
1085 unsigned ScratchOffsetReg =
1086 TRI->getPreloadedValue(MF, SIRegisterInfo::SCRATCH_WAVE_OFFSET);
1087 Lowering.CreateLiveInRegister(*CurDAG, &AMDGPU::SReg_32RegClass,
1088 ScratchOffsetReg, MVT::i32);
1089 SDValue Sym0 = CurDAG->getExternalSymbol("SCRATCH_RSRC_DWORD0", MVT::i32);
1090 SDValue ScratchRsrcDword0 =
1091 SDValue(CurDAG->getMachineNode(AMDGPU::S_MOV_B32, DL, MVT::i32, Sym0), 0);
1093 SDValue Sym1 = CurDAG->getExternalSymbol("SCRATCH_RSRC_DWORD1", MVT::i32);
1094 SDValue ScratchRsrcDword1 =
1095 SDValue(CurDAG->getMachineNode(AMDGPU::S_MOV_B32, DL, MVT::i32, Sym1), 0);
1097 const SDValue RsrcOps[] = {
1098 CurDAG->getTargetConstant(AMDGPU::SReg_64RegClassID, DL, MVT::i32),
1100 CurDAG->getTargetConstant(AMDGPU::sub0, DL, MVT::i32),
1102 CurDAG->getTargetConstant(AMDGPU::sub1, DL, MVT::i32),
1104 SDValue ScratchPtr = SDValue(CurDAG->getMachineNode(AMDGPU::REG_SEQUENCE, DL,
1105 MVT::v2i32, RsrcOps), 0);
1106 Rsrc = SDValue(Lowering.buildScratchRSRC(*CurDAG, DL, ScratchPtr), 0);
1107 SOffset = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), DL,
1108 MRI.getLiveInVirtReg(ScratchOffsetReg), MVT::i32);
1111 if (CurDAG->isBaseWithConstantOffset(Addr)) {
1112 SDValue N0 = Addr.getOperand(0);
1113 SDValue N1 = Addr.getOperand(1);
1114 // Offsets in vaddr must be positive.
1115 if (CurDAG->SignBitIsZero(N0)) {
1116 ConstantSDNode *C1 = cast<ConstantSDNode>(N1);
1117 if (isLegalMUBUFImmOffset(C1)) {
1119 ImmOffset = CurDAG->getTargetConstant(C1->getZExtValue(), DL, MVT::i16);
1127 ImmOffset = CurDAG->getTargetConstant(0, DL, MVT::i16);
1131 bool AMDGPUDAGToDAGISel::SelectMUBUFOffset(SDValue Addr, SDValue &SRsrc,
1132 SDValue &SOffset, SDValue &Offset,
1133 SDValue &GLC, SDValue &SLC,
1134 SDValue &TFE) const {
1135 SDValue Ptr, VAddr, Offen, Idxen, Addr64;
1136 const SIInstrInfo *TII =
1137 static_cast<const SIInstrInfo *>(Subtarget->getInstrInfo());
1139 SelectMUBUF(Addr, Ptr, VAddr, SOffset, Offset, Offen, Idxen, Addr64,
1142 if (!cast<ConstantSDNode>(Offen)->getSExtValue() &&
1143 !cast<ConstantSDNode>(Idxen)->getSExtValue() &&
1144 !cast<ConstantSDNode>(Addr64)->getSExtValue()) {
1145 uint64_t Rsrc = TII->getDefaultRsrcDataFormat() |
1146 APInt::getAllOnesValue(32).getZExtValue(); // Size
1149 const SITargetLowering& Lowering =
1150 *static_cast<const SITargetLowering*>(getTargetLowering());
1152 SRsrc = SDValue(Lowering.buildRSRC(*CurDAG, DL, Ptr, 0, Rsrc), 0);
1158 bool AMDGPUDAGToDAGISel::SelectMUBUFOffset(SDValue Addr, SDValue &SRsrc,
1159 SDValue &Soffset, SDValue &Offset,
1160 SDValue &GLC) const {
1163 return SelectMUBUFOffset(Addr, SRsrc, Soffset, Offset, GLC, SLC, TFE);
1167 /// \param EncodedOffset This is the immediate value that will be encoded
1168 /// directly into the instruction. On SI/CI the \p EncodedOffset
1169 /// will be in units of dwords and on VI+ it will be units of bytes.
1170 static bool isLegalSMRDImmOffset(const AMDGPUSubtarget *ST,
1171 int64_t EncodedOffset) {
1172 return ST->getGeneration() < AMDGPUSubtarget::VOLCANIC_ISLANDS ?
1173 isUInt<8>(EncodedOffset) : isUInt<20>(EncodedOffset);
1176 bool AMDGPUDAGToDAGISel::SelectSMRDOffset(SDValue ByteOffsetNode,
1177 SDValue &Offset, bool &Imm) const {
1179 // FIXME: Handle non-constant offsets.
1180 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ByteOffsetNode);
1184 SDLoc SL(ByteOffsetNode);
1185 AMDGPUSubtarget::Generation Gen = Subtarget->getGeneration();
1186 int64_t ByteOffset = C->getSExtValue();
1187 int64_t EncodedOffset = Gen < AMDGPUSubtarget::VOLCANIC_ISLANDS ?
1188 ByteOffset >> 2 : ByteOffset;
1190 if (isLegalSMRDImmOffset(Subtarget, EncodedOffset)) {
1191 Offset = CurDAG->getTargetConstant(EncodedOffset, SL, MVT::i32);
1196 if (!isUInt<32>(EncodedOffset) || !isUInt<32>(ByteOffset))
1199 if (Gen == AMDGPUSubtarget::SEA_ISLANDS && isUInt<32>(EncodedOffset)) {
1200 // 32-bit Immediates are supported on Sea Islands.
1201 Offset = CurDAG->getTargetConstant(EncodedOffset, SL, MVT::i32);
1203 SDValue C32Bit = CurDAG->getTargetConstant(ByteOffset, SL, MVT::i32);
1204 Offset = SDValue(CurDAG->getMachineNode(AMDGPU::S_MOV_B32, SL, MVT::i32,
1211 bool AMDGPUDAGToDAGISel::SelectSMRD(SDValue Addr, SDValue &SBase,
1212 SDValue &Offset, bool &Imm) const {
1215 if (CurDAG->isBaseWithConstantOffset(Addr)) {
1216 SDValue N0 = Addr.getOperand(0);
1217 SDValue N1 = Addr.getOperand(1);
1219 if (SelectSMRDOffset(N1, Offset, Imm)) {
1225 Offset = CurDAG->getTargetConstant(0, SL, MVT::i32);
1230 bool AMDGPUDAGToDAGISel::SelectSMRDImm(SDValue Addr, SDValue &SBase,
1231 SDValue &Offset) const {
1233 return SelectSMRD(Addr, SBase, Offset, Imm) && Imm;
1236 bool AMDGPUDAGToDAGISel::SelectSMRDImm32(SDValue Addr, SDValue &SBase,
1237 SDValue &Offset) const {
1239 if (Subtarget->getGeneration() != AMDGPUSubtarget::SEA_ISLANDS)
1243 if (!SelectSMRD(Addr, SBase, Offset, Imm))
1246 return !Imm && isa<ConstantSDNode>(Offset);
1249 bool AMDGPUDAGToDAGISel::SelectSMRDSgpr(SDValue Addr, SDValue &SBase,
1250 SDValue &Offset) const {
1252 return SelectSMRD(Addr, SBase, Offset, Imm) && !Imm &&
1253 !isa<ConstantSDNode>(Offset);
1256 bool AMDGPUDAGToDAGISel::SelectSMRDBufferImm(SDValue Addr,
1257 SDValue &Offset) const {
1259 return SelectSMRDOffset(Addr, Offset, Imm) && Imm;
1262 bool AMDGPUDAGToDAGISel::SelectSMRDBufferImm32(SDValue Addr,
1263 SDValue &Offset) const {
1264 if (Subtarget->getGeneration() != AMDGPUSubtarget::SEA_ISLANDS)
1268 if (!SelectSMRDOffset(Addr, Offset, Imm))
1271 return !Imm && isa<ConstantSDNode>(Offset);
1274 bool AMDGPUDAGToDAGISel::SelectSMRDBufferSgpr(SDValue Addr,
1275 SDValue &Offset) const {
1277 return SelectSMRDOffset(Addr, Offset, Imm) && !Imm &&
1278 !isa<ConstantSDNode>(Offset);
1281 // FIXME: This is incorrect and only enough to be able to compile.
1282 SDNode *AMDGPUDAGToDAGISel::SelectAddrSpaceCast(SDNode *N) {
1283 AddrSpaceCastSDNode *ASC = cast<AddrSpaceCastSDNode>(N);
1286 assert(Subtarget->hasFlatAddressSpace() &&
1287 "addrspacecast only supported with flat address space!");
1289 assert((ASC->getSrcAddressSpace() != AMDGPUAS::CONSTANT_ADDRESS &&
1290 ASC->getDestAddressSpace() != AMDGPUAS::CONSTANT_ADDRESS) &&
1291 "Cannot cast address space to / from constant address!");
1293 assert((ASC->getSrcAddressSpace() == AMDGPUAS::FLAT_ADDRESS ||
1294 ASC->getDestAddressSpace() == AMDGPUAS::FLAT_ADDRESS) &&
1295 "Can only cast to / from flat address space!");
1297 // The flat instructions read the address as the index of the VGPR holding the
1298 // address, so casting should just be reinterpreting the base VGPR, so just
1299 // insert trunc / bitcast / zext.
1301 SDValue Src = ASC->getOperand(0);
1302 EVT DestVT = ASC->getValueType(0);
1303 EVT SrcVT = Src.getValueType();
1305 unsigned SrcSize = SrcVT.getSizeInBits();
1306 unsigned DestSize = DestVT.getSizeInBits();
1308 if (SrcSize > DestSize) {
1309 assert(SrcSize == 64 && DestSize == 32);
1310 return CurDAG->getMachineNode(
1311 TargetOpcode::EXTRACT_SUBREG,
1315 CurDAG->getTargetConstant(AMDGPU::sub0, DL, MVT::i32));
1318 if (DestSize > SrcSize) {
1319 assert(SrcSize == 32 && DestSize == 64);
1321 // FIXME: This is probably wrong, we should never be defining
1322 // a register class with both VGPRs and SGPRs
1323 SDValue RC = CurDAG->getTargetConstant(AMDGPU::VS_64RegClassID, DL,
1326 const SDValue Ops[] = {
1329 CurDAG->getTargetConstant(AMDGPU::sub0, DL, MVT::i32),
1330 SDValue(CurDAG->getMachineNode(AMDGPU::S_MOV_B32, DL, MVT::i32,
1331 CurDAG->getConstant(0, DL, MVT::i32)), 0),
1332 CurDAG->getTargetConstant(AMDGPU::sub1, DL, MVT::i32)
1335 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE,
1336 DL, N->getValueType(0), Ops);
1339 assert(SrcSize == 64 && DestSize == 64);
1340 return CurDAG->getNode(ISD::BITCAST, DL, DestVT, Src).getNode();
1343 SDNode *AMDGPUDAGToDAGISel::getS_BFE(unsigned Opcode, SDLoc DL, SDValue Val,
1344 uint32_t Offset, uint32_t Width) {
1345 // Transformation function, pack the offset and width of a BFE into
1346 // the format expected by the S_BFE_I32 / S_BFE_U32. In the second
1347 // source, bits [5:0] contain the offset and bits [22:16] the width.
1348 uint32_t PackedVal = Offset | (Width << 16);
1349 SDValue PackedConst = CurDAG->getTargetConstant(PackedVal, DL, MVT::i32);
1351 return CurDAG->getMachineNode(Opcode, DL, MVT::i32, Val, PackedConst);
1354 SDNode *AMDGPUDAGToDAGISel::SelectS_BFEFromShifts(SDNode *N) {
1355 // "(a << b) srl c)" ---> "BFE_U32 a, (c-b), (32-c)
1356 // "(a << b) sra c)" ---> "BFE_I32 a, (c-b), (32-c)
1357 // Predicate: 0 < b <= c < 32
1359 const SDValue &Shl = N->getOperand(0);
1360 ConstantSDNode *B = dyn_cast<ConstantSDNode>(Shl->getOperand(1));
1361 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
1364 uint32_t BVal = B->getZExtValue();
1365 uint32_t CVal = C->getZExtValue();
1367 if (0 < BVal && BVal <= CVal && CVal < 32) {
1368 bool Signed = N->getOpcode() == ISD::SRA;
1369 unsigned Opcode = Signed ? AMDGPU::S_BFE_I32 : AMDGPU::S_BFE_U32;
1371 return getS_BFE(Opcode, SDLoc(N), Shl.getOperand(0),
1372 CVal - BVal, 32 - CVal);
1375 return SelectCode(N);
1378 SDNode *AMDGPUDAGToDAGISel::SelectS_BFE(SDNode *N) {
1379 switch (N->getOpcode()) {
1381 if (N->getOperand(0).getOpcode() == ISD::SRL) {
1382 // "(a srl b) & mask" ---> "BFE_U32 a, b, popcount(mask)"
1383 // Predicate: isMask(mask)
1384 const SDValue &Srl = N->getOperand(0);
1385 ConstantSDNode *Shift = dyn_cast<ConstantSDNode>(Srl.getOperand(1));
1386 ConstantSDNode *Mask = dyn_cast<ConstantSDNode>(N->getOperand(1));
1388 if (Shift && Mask) {
1389 uint32_t ShiftVal = Shift->getZExtValue();
1390 uint32_t MaskVal = Mask->getZExtValue();
1392 if (isMask_32(MaskVal)) {
1393 uint32_t WidthVal = countPopulation(MaskVal);
1395 return getS_BFE(AMDGPU::S_BFE_U32, SDLoc(N), Srl.getOperand(0),
1396 ShiftVal, WidthVal);
1402 if (N->getOperand(0).getOpcode() == ISD::AND) {
1403 // "(a & mask) srl b)" ---> "BFE_U32 a, b, popcount(mask >> b)"
1404 // Predicate: isMask(mask >> b)
1405 const SDValue &And = N->getOperand(0);
1406 ConstantSDNode *Shift = dyn_cast<ConstantSDNode>(N->getOperand(1));
1407 ConstantSDNode *Mask = dyn_cast<ConstantSDNode>(And->getOperand(1));
1409 if (Shift && Mask) {
1410 uint32_t ShiftVal = Shift->getZExtValue();
1411 uint32_t MaskVal = Mask->getZExtValue() >> ShiftVal;
1413 if (isMask_32(MaskVal)) {
1414 uint32_t WidthVal = countPopulation(MaskVal);
1416 return getS_BFE(AMDGPU::S_BFE_U32, SDLoc(N), And.getOperand(0),
1417 ShiftVal, WidthVal);
1420 } else if (N->getOperand(0).getOpcode() == ISD::SHL)
1421 return SelectS_BFEFromShifts(N);
1424 if (N->getOperand(0).getOpcode() == ISD::SHL)
1425 return SelectS_BFEFromShifts(N);
1429 return SelectCode(N);
1432 bool AMDGPUDAGToDAGISel::SelectVOP3Mods(SDValue In, SDValue &Src,
1433 SDValue &SrcMods) const {
1439 if (Src.getOpcode() == ISD::FNEG) {
1440 Mods |= SISrcMods::NEG;
1441 Src = Src.getOperand(0);
1444 if (Src.getOpcode() == ISD::FABS) {
1445 Mods |= SISrcMods::ABS;
1446 Src = Src.getOperand(0);
1449 SrcMods = CurDAG->getTargetConstant(Mods, SDLoc(In), MVT::i32);
1454 bool AMDGPUDAGToDAGISel::SelectVOP3NoMods(SDValue In, SDValue &Src,
1455 SDValue &SrcMods) const {
1456 bool Res = SelectVOP3Mods(In, Src, SrcMods);
1457 return Res && cast<ConstantSDNode>(SrcMods)->isNullValue();
1460 bool AMDGPUDAGToDAGISel::SelectVOP3Mods0(SDValue In, SDValue &Src,
1461 SDValue &SrcMods, SDValue &Clamp,
1462 SDValue &Omod) const {
1464 // FIXME: Handle Clamp and Omod
1465 Clamp = CurDAG->getTargetConstant(0, DL, MVT::i32);
1466 Omod = CurDAG->getTargetConstant(0, DL, MVT::i32);
1468 return SelectVOP3Mods(In, Src, SrcMods);
1471 bool AMDGPUDAGToDAGISel::SelectVOP3NoMods0(SDValue In, SDValue &Src,
1472 SDValue &SrcMods, SDValue &Clamp,
1473 SDValue &Omod) const {
1474 bool Res = SelectVOP3Mods0(In, Src, SrcMods, Clamp, Omod);
1476 return Res && cast<ConstantSDNode>(SrcMods)->isNullValue() &&
1477 cast<ConstantSDNode>(Clamp)->isNullValue() &&
1478 cast<ConstantSDNode>(Omod)->isNullValue();
1481 bool AMDGPUDAGToDAGISel::SelectVOP3Mods0Clamp(SDValue In, SDValue &Src,
1483 SDValue &Omod) const {
1484 // FIXME: Handle Omod
1485 Omod = CurDAG->getTargetConstant(0, SDLoc(In), MVT::i32);
1487 return SelectVOP3Mods(In, Src, SrcMods);
1490 bool AMDGPUDAGToDAGISel::SelectVOP3Mods0Clamp0OMod(SDValue In, SDValue &Src,
1493 SDValue &Omod) const {
1494 Clamp = Omod = CurDAG->getTargetConstant(0, SDLoc(In), MVT::i32);
1495 return SelectVOP3Mods(In, Src, SrcMods);
1498 void AMDGPUDAGToDAGISel::PreprocessISelDAG() {
1499 bool Modified = false;
1501 // XXX - Other targets seem to be able to do this without a worklist.
1502 SmallVector<LoadSDNode *, 8> LoadsToReplace;
1503 SmallVector<StoreSDNode *, 8> StoresToReplace;
1505 for (SDNode &Node : CurDAG->allnodes()) {
1506 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(&Node)) {
1507 EVT VT = LD->getValueType(0);
1508 if (VT != MVT::i64 || LD->getExtensionType() != ISD::NON_EXTLOAD)
1511 // To simplify the TableGen patters, we replace all i64 loads with v2i32
1512 // loads. Alternatively, we could promote i64 loads to v2i32 during DAG
1513 // legalization, however, so places (ExpandUnalignedLoad) in the DAG
1514 // legalizer assume that if i64 is legal, so doing this promotion early
1515 // can cause problems.
1516 LoadsToReplace.push_back(LD);
1517 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(&Node)) {
1518 // Handle i64 stores here for the same reason mentioned above for loads.
1519 SDValue Value = ST->getValue();
1520 if (Value.getValueType() != MVT::i64 || ST->isTruncatingStore())
1522 StoresToReplace.push_back(ST);
1526 for (LoadSDNode *LD : LoadsToReplace) {
1529 SDValue NewLoad = CurDAG->getLoad(MVT::v2i32, SL, LD->getChain(),
1530 LD->getBasePtr(), LD->getMemOperand());
1531 SDValue BitCast = CurDAG->getNode(ISD::BITCAST, SL,
1533 CurDAG->ReplaceAllUsesOfValueWith(SDValue(LD, 1), NewLoad.getValue(1));
1534 CurDAG->ReplaceAllUsesOfValueWith(SDValue(LD, 0), BitCast);
1538 for (StoreSDNode *ST : StoresToReplace) {
1539 SDValue NewValue = CurDAG->getNode(ISD::BITCAST, SDLoc(ST),
1540 MVT::v2i32, ST->getValue());
1541 const SDValue StoreOps[] = {
1548 CurDAG->UpdateNodeOperands(ST, StoreOps);
1552 // XXX - Is this necessary?
1554 CurDAG->RemoveDeadNodes();
1557 void AMDGPUDAGToDAGISel::PostprocessISelDAG() {
1558 const AMDGPUTargetLowering& Lowering =
1559 *static_cast<const AMDGPUTargetLowering*>(getTargetLowering());
1560 bool IsModified = false;
1563 // Go over all selected nodes and try to fold them a bit more
1564 for (SDNode &Node : CurDAG->allnodes()) {
1565 MachineSDNode *MachineNode = dyn_cast<MachineSDNode>(&Node);
1569 SDNode *ResNode = Lowering.PostISelFolding(MachineNode, *CurDAG);
1570 if (ResNode != &Node) {
1571 ReplaceUses(&Node, ResNode);
1575 CurDAG->RemoveDeadNodes();
1576 } while (IsModified);