1 //===-- AMDGPUAsmPrinter.cpp - AMDGPU Assebly printer --------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
12 /// The AMDGPUAsmPrinter is used to print both assembly string and also binary
13 /// code. When passed an MCAsmStreamer it prints assembly and when passed
14 /// an MCObjectStreamer it outputs binary code.
16 //===----------------------------------------------------------------------===//
19 #include "AMDGPUAsmPrinter.h"
20 #include "MCTargetDesc/AMDGPUTargetStreamer.h"
21 #include "InstPrinter/AMDGPUInstPrinter.h"
22 #include "Utils/AMDGPUBaseInfo.h"
24 #include "AMDKernelCodeT.h"
25 #include "AMDGPUSubtarget.h"
26 #include "R600Defines.h"
27 #include "R600MachineFunctionInfo.h"
28 #include "R600RegisterInfo.h"
29 #include "SIDefines.h"
30 #include "SIMachineFunctionInfo.h"
31 #include "SIRegisterInfo.h"
32 #include "llvm/CodeGen/MachineFrameInfo.h"
33 #include "llvm/MC/MCContext.h"
34 #include "llvm/MC/MCSectionELF.h"
35 #include "llvm/MC/MCStreamer.h"
36 #include "llvm/Support/ELF.h"
37 #include "llvm/Support/MathExtras.h"
38 #include "llvm/Support/TargetRegistry.h"
39 #include "llvm/Target/TargetLoweringObjectFile.h"
43 // TODO: This should get the default rounding mode from the kernel. We just set
44 // the default here, but this could change if the OpenCL rounding mode pragmas
47 // The denormal mode here should match what is reported by the OpenCL runtime
48 // for the CL_FP_DENORM bit from CL_DEVICE_{HALF|SINGLE|DOUBLE}_FP_CONFIG, but
49 // can also be override to flush with the -cl-denorms-are-zero compiler flag.
51 // AMD OpenCL only sets flush none and reports CL_FP_DENORM for double
52 // precision, and leaves single precision to flush all and does not report
53 // CL_FP_DENORM for CL_DEVICE_SINGLE_FP_CONFIG. Mesa's OpenCL currently reports
54 // CL_FP_DENORM for both.
56 // FIXME: It seems some instructions do not support single precision denormals
57 // regardless of the mode (exp_*_f32, rcp_*_f32, rsq_*_f32, rsq_*f32, sqrt_f32,
58 // and sin_f32, cos_f32 on most parts).
60 // We want to use these instructions, and using fp32 denormals also causes
61 // instructions to run at the double precision rate for the device so it's
62 // probably best to just report no single precision denormals.
63 static uint32_t getFPMode(const MachineFunction &F) {
64 const AMDGPUSubtarget& ST = F.getSubtarget<AMDGPUSubtarget>();
65 // TODO: Is there any real use for the flush in only / flush out only modes?
67 uint32_t FP32Denormals =
68 ST.hasFP32Denormals() ? FP_DENORM_FLUSH_NONE : FP_DENORM_FLUSH_IN_FLUSH_OUT;
70 uint32_t FP64Denormals =
71 ST.hasFP64Denormals() ? FP_DENORM_FLUSH_NONE : FP_DENORM_FLUSH_IN_FLUSH_OUT;
73 return FP_ROUND_MODE_SP(FP_ROUND_ROUND_TO_NEAREST) |
74 FP_ROUND_MODE_DP(FP_ROUND_ROUND_TO_NEAREST) |
75 FP_DENORM_MODE_SP(FP32Denormals) |
76 FP_DENORM_MODE_DP(FP64Denormals);
80 createAMDGPUAsmPrinterPass(TargetMachine &tm,
81 std::unique_ptr<MCStreamer> &&Streamer) {
82 return new AMDGPUAsmPrinter(tm, std::move(Streamer));
85 extern "C" void LLVMInitializeAMDGPUAsmPrinter() {
86 TargetRegistry::RegisterAsmPrinter(TheAMDGPUTarget, createAMDGPUAsmPrinterPass);
87 TargetRegistry::RegisterAsmPrinter(TheGCNTarget, createAMDGPUAsmPrinterPass);
90 AMDGPUAsmPrinter::AMDGPUAsmPrinter(TargetMachine &TM,
91 std::unique_ptr<MCStreamer> Streamer)
92 : AsmPrinter(TM, std::move(Streamer)) {}
94 void AMDGPUAsmPrinter::EmitStartOfAsmFile(Module &M) {
95 if (TM.getTargetTriple().getOS() != Triple::AMDHSA)
98 // Need to construct an MCSubtargetInfo here in case we have no functions
100 std::unique_ptr<MCSubtargetInfo> STI(TM.getTarget().createMCSubtargetInfo(
101 TM.getTargetTriple().str(), TM.getTargetCPU(),
102 TM.getTargetFeatureString()));
104 AMDGPUTargetStreamer *TS =
105 static_cast<AMDGPUTargetStreamer *>(OutStreamer->getTargetStreamer());
107 TS->EmitDirectiveHSACodeObjectVersion(1, 0);
108 AMDGPU::IsaVersion ISA = AMDGPU::getIsaVersion(STI->getFeatureBits());
109 TS->EmitDirectiveHSACodeObjectISA(ISA.Major, ISA.Minor, ISA.Stepping,
113 void AMDGPUAsmPrinter::EmitFunctionBodyStart() {
114 const AMDGPUSubtarget &STM = MF->getSubtarget<AMDGPUSubtarget>();
115 SIProgramInfo KernelInfo;
116 if (STM.isAmdHsaOS()) {
117 getSIProgramInfo(KernelInfo, *MF);
118 EmitAmdKernelCodeT(*MF, KernelInfo);
122 void AMDGPUAsmPrinter::EmitFunctionEntryLabel() {
123 const SIMachineFunctionInfo *MFI = MF->getInfo<SIMachineFunctionInfo>();
124 const AMDGPUSubtarget &STM = MF->getSubtarget<AMDGPUSubtarget>();
125 if (MFI->isKernel() && STM.isAmdHsaOS()) {
126 AMDGPUTargetStreamer *TS =
127 static_cast<AMDGPUTargetStreamer *>(OutStreamer->getTargetStreamer());
128 TS->EmitAMDGPUSymbolType(CurrentFnSym->getName(),
129 ELF::STT_AMDGPU_HSA_KERNEL);
132 AsmPrinter::EmitFunctionEntryLabel();
135 static bool isModuleLinkage(const GlobalValue *GV) {
136 switch (GV->getLinkage()) {
137 case GlobalValue::InternalLinkage:
138 case GlobalValue::CommonLinkage:
140 case GlobalValue::ExternalLinkage:
142 default: llvm_unreachable("unknown linkage type");
146 void AMDGPUAsmPrinter::EmitGlobalVariable(const GlobalVariable *GV) {
148 if (TM.getTargetTriple().getOS() != Triple::AMDHSA) {
149 AsmPrinter::EmitGlobalVariable(GV);
153 if (GV->isDeclaration() || GV->getLinkage() == GlobalValue::PrivateLinkage) {
154 AsmPrinter::EmitGlobalVariable(GV);
158 // Group segment variables aren't emitted in HSA.
159 if (AMDGPU::isGroupSegment(GV))
162 AMDGPUTargetStreamer *TS =
163 static_cast<AMDGPUTargetStreamer *>(OutStreamer->getTargetStreamer());
164 if (isModuleLinkage(GV)) {
165 TS->EmitAMDGPUHsaModuleScopeGlobal(GV->getName());
167 TS->EmitAMDGPUHsaProgramScopeGlobal(GV->getName());
170 MCSymbolELF *GVSym = cast<MCSymbolELF>(getSymbol(GV));
171 const DataLayout &DL = getDataLayout();
174 uint64_t Size = DL.getTypeAllocSize(GV->getType()->getElementType());
175 OutStreamer->emitELFSize(GVSym, MCConstantExpr::create(Size, OutContext));
176 OutStreamer->PushSection();
177 OutStreamer->SwitchSection(
178 getObjFileLowering().SectionForGlobal(GV, *Mang, TM));
179 const Constant *C = GV->getInitializer();
180 OutStreamer->EmitLabel(GVSym);
181 EmitGlobalConstant(DL, C);
182 OutStreamer->PopSection();
185 bool AMDGPUAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
187 // The starting address of all shader programs must be 256 bytes aligned.
190 SetupMachineFunction(MF);
192 MCContext &Context = getObjFileLowering().getContext();
193 MCSectionELF *ConfigSection =
194 Context.getELFSection(".AMDGPU.config", ELF::SHT_PROGBITS, 0);
195 OutStreamer->SwitchSection(ConfigSection);
197 const AMDGPUSubtarget &STM = MF.getSubtarget<AMDGPUSubtarget>();
198 SIProgramInfo KernelInfo;
199 if (STM.getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS) {
200 getSIProgramInfo(KernelInfo, MF);
201 if (!STM.isAmdHsaOS()) {
202 EmitProgramInfoSI(MF, KernelInfo);
205 EmitProgramInfoR600(MF);
210 DisasmLineMaxLen = 0;
215 MCSectionELF *CommentSection =
216 Context.getELFSection(".AMDGPU.csdata", ELF::SHT_PROGBITS, 0);
217 OutStreamer->SwitchSection(CommentSection);
219 if (STM.getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS) {
220 OutStreamer->emitRawComment(" Kernel info:", false);
221 OutStreamer->emitRawComment(" codeLenInByte = " + Twine(KernelInfo.CodeLen),
223 OutStreamer->emitRawComment(" NumSgprs: " + Twine(KernelInfo.NumSGPR),
225 OutStreamer->emitRawComment(" NumVgprs: " + Twine(KernelInfo.NumVGPR),
227 OutStreamer->emitRawComment(" FloatMode: " + Twine(KernelInfo.FloatMode),
229 OutStreamer->emitRawComment(" IeeeMode: " + Twine(KernelInfo.IEEEMode),
231 OutStreamer->emitRawComment(" ScratchSize: " + Twine(KernelInfo.ScratchSize),
234 OutStreamer->emitRawComment(" COMPUTE_PGM_RSRC2:USER_SGPR: " +
235 Twine(G_00B84C_USER_SGPR(KernelInfo.ComputePGMRSrc2)),
237 OutStreamer->emitRawComment(" COMPUTE_PGM_RSRC2:TGID_X_EN: " +
238 Twine(G_00B84C_TGID_X_EN(KernelInfo.ComputePGMRSrc2)),
240 OutStreamer->emitRawComment(" COMPUTE_PGM_RSRC2:TGID_Y_EN: " +
241 Twine(G_00B84C_TGID_Y_EN(KernelInfo.ComputePGMRSrc2)),
243 OutStreamer->emitRawComment(" COMPUTE_PGM_RSRC2:TGID_Z_EN: " +
244 Twine(G_00B84C_TGID_Z_EN(KernelInfo.ComputePGMRSrc2)),
246 OutStreamer->emitRawComment(" COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: " +
247 Twine(G_00B84C_TIDIG_COMP_CNT(KernelInfo.ComputePGMRSrc2)),
251 R600MachineFunctionInfo *MFI = MF.getInfo<R600MachineFunctionInfo>();
252 OutStreamer->emitRawComment(
253 Twine("SQ_PGM_RESOURCES:STACK_SIZE = " + Twine(MFI->StackSize)));
257 if (STM.dumpCode()) {
259 OutStreamer->SwitchSection(
260 Context.getELFSection(".AMDGPU.disasm", ELF::SHT_NOTE, 0));
262 for (size_t i = 0; i < DisasmLines.size(); ++i) {
263 std::string Comment(DisasmLineMaxLen - DisasmLines[i].size(), ' ');
264 Comment += " ; " + HexLines[i] + "\n";
266 OutStreamer->EmitBytes(StringRef(DisasmLines[i]));
267 OutStreamer->EmitBytes(StringRef(Comment));
274 void AMDGPUAsmPrinter::EmitProgramInfoR600(const MachineFunction &MF) {
276 bool killPixel = false;
277 const AMDGPUSubtarget &STM = MF.getSubtarget<AMDGPUSubtarget>();
278 const R600RegisterInfo *RI =
279 static_cast<const R600RegisterInfo *>(STM.getRegisterInfo());
280 const R600MachineFunctionInfo *MFI = MF.getInfo<R600MachineFunctionInfo>();
282 for (const MachineBasicBlock &MBB : MF) {
283 for (const MachineInstr &MI : MBB) {
284 if (MI.getOpcode() == AMDGPU::KILLGT)
286 unsigned numOperands = MI.getNumOperands();
287 for (unsigned op_idx = 0; op_idx < numOperands; op_idx++) {
288 const MachineOperand &MO = MI.getOperand(op_idx);
291 unsigned HWReg = RI->getEncodingValue(MO.getReg()) & 0xff;
293 // Register with value > 127 aren't GPR
296 MaxGPR = std::max(MaxGPR, HWReg);
302 if (STM.getGeneration() >= AMDGPUSubtarget::EVERGREEN) {
303 // Evergreen / Northern Islands
304 switch (MFI->getShaderType()) {
305 default: // Fall through
306 case ShaderType::COMPUTE: RsrcReg = R_0288D4_SQ_PGM_RESOURCES_LS; break;
307 case ShaderType::GEOMETRY: RsrcReg = R_028878_SQ_PGM_RESOURCES_GS; break;
308 case ShaderType::PIXEL: RsrcReg = R_028844_SQ_PGM_RESOURCES_PS; break;
309 case ShaderType::VERTEX: RsrcReg = R_028860_SQ_PGM_RESOURCES_VS; break;
313 switch (MFI->getShaderType()) {
314 default: // Fall through
315 case ShaderType::GEOMETRY: // Fall through
316 case ShaderType::COMPUTE: // Fall through
317 case ShaderType::VERTEX: RsrcReg = R_028868_SQ_PGM_RESOURCES_VS; break;
318 case ShaderType::PIXEL: RsrcReg = R_028850_SQ_PGM_RESOURCES_PS; break;
322 OutStreamer->EmitIntValue(RsrcReg, 4);
323 OutStreamer->EmitIntValue(S_NUM_GPRS(MaxGPR + 1) |
324 S_STACK_SIZE(MFI->StackSize), 4);
325 OutStreamer->EmitIntValue(R_02880C_DB_SHADER_CONTROL, 4);
326 OutStreamer->EmitIntValue(S_02880C_KILL_ENABLE(killPixel), 4);
328 if (MFI->getShaderType() == ShaderType::COMPUTE) {
329 OutStreamer->EmitIntValue(R_0288E8_SQ_LDS_ALLOC, 4);
330 OutStreamer->EmitIntValue(RoundUpToAlignment(MFI->LDSSize, 4) >> 2, 4);
334 void AMDGPUAsmPrinter::getSIProgramInfo(SIProgramInfo &ProgInfo,
335 const MachineFunction &MF) const {
336 const AMDGPUSubtarget &STM = MF.getSubtarget<AMDGPUSubtarget>();
337 const SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
338 uint64_t CodeSize = 0;
339 unsigned MaxSGPR = 0;
340 unsigned MaxVGPR = 0;
341 bool VCCUsed = false;
342 bool FlatUsed = false;
343 const SIRegisterInfo *RI =
344 static_cast<const SIRegisterInfo *>(STM.getRegisterInfo());
346 for (const MachineBasicBlock &MBB : MF) {
347 for (const MachineInstr &MI : MBB) {
348 // TODO: CodeSize should account for multiple functions.
350 // TODO: Should we count size of debug info?
351 if (MI.isDebugValue())
354 // FIXME: This is reporting 0 for many instructions.
355 CodeSize += MI.getDesc().Size;
357 unsigned numOperands = MI.getNumOperands();
358 for (unsigned op_idx = 0; op_idx < numOperands; op_idx++) {
359 const MachineOperand &MO = MI.getOperand(op_idx);
366 unsigned reg = MO.getReg();
379 case AMDGPU::FLAT_SCR:
380 case AMDGPU::FLAT_SCR_LO:
381 case AMDGPU::FLAT_SCR_HI:
389 if (AMDGPU::SReg_32RegClass.contains(reg)) {
392 } else if (AMDGPU::VGPR_32RegClass.contains(reg)) {
395 } else if (AMDGPU::SReg_64RegClass.contains(reg)) {
398 } else if (AMDGPU::VReg_64RegClass.contains(reg)) {
401 } else if (AMDGPU::VReg_96RegClass.contains(reg)) {
404 } else if (AMDGPU::SReg_128RegClass.contains(reg)) {
407 } else if (AMDGPU::VReg_128RegClass.contains(reg)) {
410 } else if (AMDGPU::SReg_256RegClass.contains(reg)) {
413 } else if (AMDGPU::VReg_256RegClass.contains(reg)) {
416 } else if (AMDGPU::SReg_512RegClass.contains(reg)) {
419 } else if (AMDGPU::VReg_512RegClass.contains(reg)) {
423 llvm_unreachable("Unknown register class");
425 unsigned hwReg = RI->getEncodingValue(reg) & 0xff;
426 unsigned maxUsed = hwReg + width - 1;
428 MaxSGPR = maxUsed > MaxSGPR ? maxUsed : MaxSGPR;
430 MaxVGPR = maxUsed > MaxVGPR ? maxUsed : MaxVGPR;
436 unsigned ExtraSGPRs = 0;
441 if (STM.getGeneration() < AMDGPUSubtarget::VOLCANIC_ISLANDS) {
445 if (STM.isXNACKEnabled())
452 MaxSGPR += ExtraSGPRs;
454 // We found the maximum register index. They start at 0, so add one to get the
455 // number of registers.
456 ProgInfo.NumVGPR = MaxVGPR + 1;
457 ProgInfo.NumSGPR = MaxSGPR + 1;
459 if (STM.hasSGPRInitBug()) {
460 if (ProgInfo.NumSGPR > AMDGPUSubtarget::FIXED_SGPR_COUNT_FOR_INIT_BUG) {
461 LLVMContext &Ctx = MF.getFunction()->getContext();
462 Ctx.emitError("too many SGPRs used with the SGPR init bug");
465 ProgInfo.NumSGPR = AMDGPUSubtarget::FIXED_SGPR_COUNT_FOR_INIT_BUG;
468 if (MFI->NumUserSGPRs > STM.getMaxNumUserSGPRs()) {
469 LLVMContext &Ctx = MF.getFunction()->getContext();
470 Ctx.emitError("too many user SGPRs used");
473 ProgInfo.VGPRBlocks = (ProgInfo.NumVGPR - 1) / 4;
474 ProgInfo.SGPRBlocks = (ProgInfo.NumSGPR - 1) / 8;
475 // Set the value to initialize FP_ROUND and FP_DENORM parts of the mode
477 ProgInfo.FloatMode = getFPMode(MF);
479 // XXX: Not quite sure what this does, but sc seems to unset this.
480 ProgInfo.IEEEMode = 0;
482 // Do not clamp NAN to 0.
483 ProgInfo.DX10Clamp = 0;
485 const MachineFrameInfo *FrameInfo = MF.getFrameInfo();
486 ProgInfo.ScratchSize = FrameInfo->estimateStackSize(MF);
488 ProgInfo.FlatUsed = FlatUsed;
489 ProgInfo.VCCUsed = VCCUsed;
490 ProgInfo.CodeLen = CodeSize;
492 unsigned LDSAlignShift;
493 if (STM.getGeneration() < AMDGPUSubtarget::SEA_ISLANDS) {
494 // LDS is allocated in 64 dword blocks.
497 // LDS is allocated in 128 dword blocks.
501 unsigned LDSSpillSize = MFI->LDSWaveSpillSize *
502 MFI->getMaximumWorkGroupSize(MF);
504 ProgInfo.LDSSize = MFI->LDSSize + LDSSpillSize;
506 RoundUpToAlignment(ProgInfo.LDSSize, 1 << LDSAlignShift) >> LDSAlignShift;
508 // Scratch is allocated in 256 dword blocks.
509 unsigned ScratchAlignShift = 10;
510 // We need to program the hardware with the amount of scratch memory that
511 // is used by the entire wave. ProgInfo.ScratchSize is the amount of
512 // scratch memory used per thread.
513 ProgInfo.ScratchBlocks =
514 RoundUpToAlignment(ProgInfo.ScratchSize * STM.getWavefrontSize(),
515 1 << ScratchAlignShift) >> ScratchAlignShift;
517 ProgInfo.ComputePGMRSrc1 =
518 S_00B848_VGPRS(ProgInfo.VGPRBlocks) |
519 S_00B848_SGPRS(ProgInfo.SGPRBlocks) |
520 S_00B848_PRIORITY(ProgInfo.Priority) |
521 S_00B848_FLOAT_MODE(ProgInfo.FloatMode) |
522 S_00B848_PRIV(ProgInfo.Priv) |
523 S_00B848_DX10_CLAMP(ProgInfo.DX10Clamp) |
524 S_00B848_DEBUG_MODE(ProgInfo.DebugMode) |
525 S_00B848_IEEE_MODE(ProgInfo.IEEEMode);
527 // 0 = X, 1 = XY, 2 = XYZ
528 unsigned TIDIGCompCnt = 0;
529 if (MFI->hasWorkItemIDZ())
531 else if (MFI->hasWorkItemIDY())
534 ProgInfo.ComputePGMRSrc2 =
535 S_00B84C_SCRATCH_EN(ProgInfo.ScratchBlocks > 0) |
536 S_00B84C_USER_SGPR(MFI->getNumUserSGPRs()) |
537 S_00B84C_TGID_X_EN(MFI->hasWorkGroupIDX()) |
538 S_00B84C_TGID_Y_EN(MFI->hasWorkGroupIDY()) |
539 S_00B84C_TGID_Z_EN(MFI->hasWorkGroupIDZ()) |
540 S_00B84C_TG_SIZE_EN(MFI->hasWorkGroupInfo()) |
541 S_00B84C_TIDIG_COMP_CNT(TIDIGCompCnt) |
542 S_00B84C_EXCP_EN_MSB(0) |
543 S_00B84C_LDS_SIZE(ProgInfo.LDSBlocks) |
547 static unsigned getRsrcReg(unsigned ShaderType) {
548 switch (ShaderType) {
549 default: // Fall through
550 case ShaderType::COMPUTE: return R_00B848_COMPUTE_PGM_RSRC1;
551 case ShaderType::GEOMETRY: return R_00B228_SPI_SHADER_PGM_RSRC1_GS;
552 case ShaderType::PIXEL: return R_00B028_SPI_SHADER_PGM_RSRC1_PS;
553 case ShaderType::VERTEX: return R_00B128_SPI_SHADER_PGM_RSRC1_VS;
557 void AMDGPUAsmPrinter::EmitProgramInfoSI(const MachineFunction &MF,
558 const SIProgramInfo &KernelInfo) {
559 const AMDGPUSubtarget &STM = MF.getSubtarget<AMDGPUSubtarget>();
560 const SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
561 unsigned RsrcReg = getRsrcReg(MFI->getShaderType());
563 if (MFI->getShaderType() == ShaderType::COMPUTE) {
564 OutStreamer->EmitIntValue(R_00B848_COMPUTE_PGM_RSRC1, 4);
566 OutStreamer->EmitIntValue(KernelInfo.ComputePGMRSrc1, 4);
568 OutStreamer->EmitIntValue(R_00B84C_COMPUTE_PGM_RSRC2, 4);
569 OutStreamer->EmitIntValue(KernelInfo.ComputePGMRSrc2, 4);
571 OutStreamer->EmitIntValue(R_00B860_COMPUTE_TMPRING_SIZE, 4);
572 OutStreamer->EmitIntValue(S_00B860_WAVESIZE(KernelInfo.ScratchBlocks), 4);
574 // TODO: Should probably note flat usage somewhere. SC emits a "FlatPtr32 =
575 // 0" comment but I don't see a corresponding field in the register spec.
577 OutStreamer->EmitIntValue(RsrcReg, 4);
578 OutStreamer->EmitIntValue(S_00B028_VGPRS(KernelInfo.VGPRBlocks) |
579 S_00B028_SGPRS(KernelInfo.SGPRBlocks), 4);
580 if (STM.isVGPRSpillingEnabled(MFI)) {
581 OutStreamer->EmitIntValue(R_0286E8_SPI_TMPRING_SIZE, 4);
582 OutStreamer->EmitIntValue(S_0286E8_WAVESIZE(KernelInfo.ScratchBlocks), 4);
586 if (MFI->getShaderType() == ShaderType::PIXEL) {
587 OutStreamer->EmitIntValue(R_00B02C_SPI_SHADER_PGM_RSRC2_PS, 4);
588 OutStreamer->EmitIntValue(S_00B02C_EXTRA_LDS_SIZE(KernelInfo.LDSBlocks), 4);
589 OutStreamer->EmitIntValue(R_0286CC_SPI_PS_INPUT_ENA, 4);
590 OutStreamer->EmitIntValue(MFI->PSInputAddr, 4);
594 void AMDGPUAsmPrinter::EmitAmdKernelCodeT(const MachineFunction &MF,
595 const SIProgramInfo &KernelInfo) const {
596 const SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
597 const AMDGPUSubtarget &STM = MF.getSubtarget<AMDGPUSubtarget>();
598 amd_kernel_code_t header;
600 AMDGPU::initDefaultAMDKernelCodeT(header, STM.getFeatureBits());
602 header.compute_pgm_resource_registers =
603 KernelInfo.ComputePGMRSrc1 |
604 (KernelInfo.ComputePGMRSrc2 << 32);
605 header.code_properties = AMD_CODE_PROPERTY_IS_PTR64;
607 if (MFI->hasPrivateSegmentBuffer()) {
608 header.code_properties |=
609 AMD_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER;
612 if (MFI->hasDispatchPtr())
613 header.code_properties |= AMD_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_PTR;
615 if (MFI->hasQueuePtr())
616 header.code_properties |= AMD_CODE_PROPERTY_ENABLE_SGPR_QUEUE_PTR;
618 if (MFI->hasKernargSegmentPtr())
619 header.code_properties |= AMD_CODE_PROPERTY_ENABLE_SGPR_KERNARG_SEGMENT_PTR;
621 if (MFI->hasDispatchID())
622 header.code_properties |= AMD_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_ID;
624 if (MFI->hasFlatScratchInit())
625 header.code_properties |= AMD_CODE_PROPERTY_ENABLE_SGPR_FLAT_SCRATCH_INIT;
627 // TODO: Private segment size
629 if (MFI->hasGridWorkgroupCountX()) {
630 header.code_properties |=
631 AMD_CODE_PROPERTY_ENABLE_SGPR_GRID_WORKGROUP_COUNT_X;
634 if (MFI->hasGridWorkgroupCountY()) {
635 header.code_properties |=
636 AMD_CODE_PROPERTY_ENABLE_SGPR_GRID_WORKGROUP_COUNT_Y;
639 if (MFI->hasGridWorkgroupCountZ()) {
640 header.code_properties |=
641 AMD_CODE_PROPERTY_ENABLE_SGPR_GRID_WORKGROUP_COUNT_Z;
644 if (MFI->hasDispatchPtr())
645 header.code_properties |= AMD_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_PTR;
647 if (STM.isXNACKEnabled())
648 header.code_properties |= AMD_CODE_PROPERTY_IS_XNACK_SUPPORTED;
650 header.kernarg_segment_byte_size = MFI->ABIArgOffset;
651 header.wavefront_sgpr_count = KernelInfo.NumSGPR;
652 header.workitem_vgpr_count = KernelInfo.NumVGPR;
653 header.workitem_private_segment_byte_size = KernelInfo.ScratchSize;
654 header.workgroup_group_segment_byte_size = KernelInfo.LDSSize;
656 AMDGPUTargetStreamer *TS =
657 static_cast<AMDGPUTargetStreamer *>(OutStreamer->getTargetStreamer());
658 TS->EmitAMDKernelCodeT(header);
661 bool AMDGPUAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
663 const char *ExtraCode, raw_ostream &O) {
664 if (ExtraCode && ExtraCode[0]) {
665 if (ExtraCode[1] != 0)
666 return true; // Unknown modifier.
668 switch (ExtraCode[0]) {
670 // See if this is a generic print operand
671 return AsmPrinter::PrintAsmOperand(MI, OpNo, AsmVariant, ExtraCode, O);
677 AMDGPUInstPrinter::printRegOperand(MI->getOperand(OpNo).getReg(), O,
678 *TM.getSubtargetImpl(*MF->getFunction())->getRegisterInfo());