1 //===-- AMDGPUAsmPrinter.cpp - AMDGPU Assebly printer --------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
12 /// The AMDGPUAsmPrinter is used to print both assembly string and also binary
13 /// code. When passed an MCAsmStreamer it prints assembly and when passed
14 /// an MCObjectStreamer it outputs binary code.
16 //===----------------------------------------------------------------------===//
19 #include "AMDGPUAsmPrinter.h"
20 #include "MCTargetDesc/AMDGPUTargetStreamer.h"
21 #include "InstPrinter/AMDGPUInstPrinter.h"
22 #include "Utils/AMDGPUBaseInfo.h"
24 #include "AMDKernelCodeT.h"
25 #include "AMDGPUSubtarget.h"
26 #include "R600Defines.h"
27 #include "R600MachineFunctionInfo.h"
28 #include "R600RegisterInfo.h"
29 #include "SIDefines.h"
30 #include "SIMachineFunctionInfo.h"
31 #include "SIRegisterInfo.h"
32 #include "llvm/CodeGen/MachineFrameInfo.h"
33 #include "llvm/MC/MCContext.h"
34 #include "llvm/MC/MCSectionELF.h"
35 #include "llvm/MC/MCStreamer.h"
36 #include "llvm/Support/ELF.h"
37 #include "llvm/Support/MathExtras.h"
38 #include "llvm/Support/TargetRegistry.h"
39 #include "llvm/Target/TargetLoweringObjectFile.h"
43 // TODO: This should get the default rounding mode from the kernel. We just set
44 // the default here, but this could change if the OpenCL rounding mode pragmas
47 // The denormal mode here should match what is reported by the OpenCL runtime
48 // for the CL_FP_DENORM bit from CL_DEVICE_{HALF|SINGLE|DOUBLE}_FP_CONFIG, but
49 // can also be override to flush with the -cl-denorms-are-zero compiler flag.
51 // AMD OpenCL only sets flush none and reports CL_FP_DENORM for double
52 // precision, and leaves single precision to flush all and does not report
53 // CL_FP_DENORM for CL_DEVICE_SINGLE_FP_CONFIG. Mesa's OpenCL currently reports
54 // CL_FP_DENORM for both.
56 // FIXME: It seems some instructions do not support single precision denormals
57 // regardless of the mode (exp_*_f32, rcp_*_f32, rsq_*_f32, rsq_*f32, sqrt_f32,
58 // and sin_f32, cos_f32 on most parts).
60 // We want to use these instructions, and using fp32 denormals also causes
61 // instructions to run at the double precision rate for the device so it's
62 // probably best to just report no single precision denormals.
63 static uint32_t getFPMode(const MachineFunction &F) {
64 const AMDGPUSubtarget& ST = F.getSubtarget<AMDGPUSubtarget>();
65 // TODO: Is there any real use for the flush in only / flush out only modes?
67 uint32_t FP32Denormals =
68 ST.hasFP32Denormals() ? FP_DENORM_FLUSH_NONE : FP_DENORM_FLUSH_IN_FLUSH_OUT;
70 uint32_t FP64Denormals =
71 ST.hasFP64Denormals() ? FP_DENORM_FLUSH_NONE : FP_DENORM_FLUSH_IN_FLUSH_OUT;
73 return FP_ROUND_MODE_SP(FP_ROUND_ROUND_TO_NEAREST) |
74 FP_ROUND_MODE_DP(FP_ROUND_ROUND_TO_NEAREST) |
75 FP_DENORM_MODE_SP(FP32Denormals) |
76 FP_DENORM_MODE_DP(FP64Denormals);
80 createAMDGPUAsmPrinterPass(TargetMachine &tm,
81 std::unique_ptr<MCStreamer> &&Streamer) {
82 return new AMDGPUAsmPrinter(tm, std::move(Streamer));
85 extern "C" void LLVMInitializeAMDGPUAsmPrinter() {
86 TargetRegistry::RegisterAsmPrinter(TheAMDGPUTarget, createAMDGPUAsmPrinterPass);
87 TargetRegistry::RegisterAsmPrinter(TheGCNTarget, createAMDGPUAsmPrinterPass);
90 AMDGPUAsmPrinter::AMDGPUAsmPrinter(TargetMachine &TM,
91 std::unique_ptr<MCStreamer> Streamer)
92 : AsmPrinter(TM, std::move(Streamer)) {}
94 void AMDGPUAsmPrinter::EmitFunctionBodyStart() {
95 const AMDGPUSubtarget &STM = MF->getSubtarget<AMDGPUSubtarget>();
96 SIProgramInfo KernelInfo;
97 if (STM.isAmdHsaOS()) {
98 getSIProgramInfo(KernelInfo, *MF);
99 EmitAmdKernelCodeT(*MF, KernelInfo);
103 void AMDGPUAsmPrinter::EmitEndOfAsmFile(Module &M) {
105 // This label is used to mark the end of the .text section.
106 const TargetLoweringObjectFile &TLOF = getObjFileLowering();
107 OutStreamer->SwitchSection(TLOF.getTextSection());
108 MCSymbol *EndOfTextLabel =
109 OutContext.getOrCreateSymbol(StringRef(END_OF_TEXT_LABEL_NAME));
110 OutStreamer->EmitLabel(EndOfTextLabel);
113 void AMDGPUAsmPrinter::EmitFunctionEntryLabel() {
114 const SIMachineFunctionInfo *MFI = MF->getInfo<SIMachineFunctionInfo>();
115 const AMDGPUSubtarget &STM = MF->getSubtarget<AMDGPUSubtarget>();
116 if (MFI->isKernel() && STM.isAmdHsaOS()) {
117 AMDGPUTargetStreamer *TS =
118 static_cast<AMDGPUTargetStreamer *>(OutStreamer->getTargetStreamer());
119 TS->EmitAMDGPUSymbolType(CurrentFnSym->getName(),
120 ELF::STT_AMDGPU_HSA_KERNEL);
123 AsmPrinter::EmitFunctionEntryLabel();
126 static bool isModuleLinkage(const GlobalValue *GV) {
127 switch (GV->getLinkage()) {
128 case GlobalValue::InternalLinkage:
129 case GlobalValue::CommonLinkage:
131 case GlobalValue::ExternalLinkage:
133 default: llvm_unreachable("unknown linkage type");
137 void AMDGPUAsmPrinter::EmitGlobalVariable(const GlobalVariable *GV) {
139 if (TM.getTargetTriple().getOS() != Triple::AMDHSA ||
140 GV->isDeclaration()) {
141 AsmPrinter::EmitGlobalVariable(GV);
145 // Group segment variables aren't emitted in HSA.
146 if (AMDGPU::isGroupSegment(GV))
149 AMDGPUTargetStreamer *TS =
150 static_cast<AMDGPUTargetStreamer *>(OutStreamer->getTargetStreamer());
151 if (isModuleLinkage(GV)) {
152 TS->EmitAMDGPUHsaModuleScopeGlobal(GV->getName());
154 TS->EmitAMDGPUHsaProgramScopeGlobal(GV->getName());
157 const DataLayout &DL = getDataLayout();
158 OutStreamer->PushSection();
159 OutStreamer->SwitchSection(
160 getObjFileLowering().SectionForGlobal(GV, *Mang, TM));
161 MCSymbol *GVSym = getSymbol(GV);
162 const Constant *C = GV->getInitializer();
163 OutStreamer->EmitLabel(GVSym);
164 EmitGlobalConstant(DL, C);
165 OutStreamer->PopSection();
168 bool AMDGPUAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
170 // The starting address of all shader programs must be 256 bytes aligned.
173 SetupMachineFunction(MF);
175 MCContext &Context = getObjFileLowering().getContext();
176 MCSectionELF *ConfigSection =
177 Context.getELFSection(".AMDGPU.config", ELF::SHT_PROGBITS, 0);
178 OutStreamer->SwitchSection(ConfigSection);
180 const AMDGPUSubtarget &STM = MF.getSubtarget<AMDGPUSubtarget>();
181 SIProgramInfo KernelInfo;
182 if (STM.getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS) {
183 getSIProgramInfo(KernelInfo, MF);
184 if (!STM.isAmdHsaOS()) {
185 EmitProgramInfoSI(MF, KernelInfo);
188 AMDGPUTargetStreamer *TS =
189 static_cast<AMDGPUTargetStreamer *>(OutStreamer->getTargetStreamer());
190 TS->EmitDirectiveHSACodeObjectVersion(1, 0);
191 AMDGPU::IsaVersion ISA = STM.getIsaVersion();
192 TS->EmitDirectiveHSACodeObjectISA(ISA.Major, ISA.Minor, ISA.Stepping,
195 EmitProgramInfoR600(MF);
200 DisasmLineMaxLen = 0;
205 MCSectionELF *CommentSection =
206 Context.getELFSection(".AMDGPU.csdata", ELF::SHT_PROGBITS, 0);
207 OutStreamer->SwitchSection(CommentSection);
209 if (STM.getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS) {
210 OutStreamer->emitRawComment(" Kernel info:", false);
211 OutStreamer->emitRawComment(" codeLenInByte = " + Twine(KernelInfo.CodeLen),
213 OutStreamer->emitRawComment(" NumSgprs: " + Twine(KernelInfo.NumSGPR),
215 OutStreamer->emitRawComment(" NumVgprs: " + Twine(KernelInfo.NumVGPR),
217 OutStreamer->emitRawComment(" FloatMode: " + Twine(KernelInfo.FloatMode),
219 OutStreamer->emitRawComment(" IeeeMode: " + Twine(KernelInfo.IEEEMode),
221 OutStreamer->emitRawComment(" ScratchSize: " + Twine(KernelInfo.ScratchSize),
224 OutStreamer->emitRawComment(" COMPUTE_PGM_RSRC2:USER_SGPR: " +
225 Twine(G_00B84C_USER_SGPR(KernelInfo.ComputePGMRSrc2)),
227 OutStreamer->emitRawComment(" COMPUTE_PGM_RSRC2:TGID_X_EN: " +
228 Twine(G_00B84C_TGID_X_EN(KernelInfo.ComputePGMRSrc2)),
230 OutStreamer->emitRawComment(" COMPUTE_PGM_RSRC2:TGID_Y_EN: " +
231 Twine(G_00B84C_TGID_Y_EN(KernelInfo.ComputePGMRSrc2)),
233 OutStreamer->emitRawComment(" COMPUTE_PGM_RSRC2:TGID_Z_EN: " +
234 Twine(G_00B84C_TGID_Z_EN(KernelInfo.ComputePGMRSrc2)),
236 OutStreamer->emitRawComment(" COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: " +
237 Twine(G_00B84C_TIDIG_COMP_CNT(KernelInfo.ComputePGMRSrc2)),
241 R600MachineFunctionInfo *MFI = MF.getInfo<R600MachineFunctionInfo>();
242 OutStreamer->emitRawComment(
243 Twine("SQ_PGM_RESOURCES:STACK_SIZE = " + Twine(MFI->StackSize)));
247 if (STM.dumpCode()) {
249 OutStreamer->SwitchSection(
250 Context.getELFSection(".AMDGPU.disasm", ELF::SHT_NOTE, 0));
252 for (size_t i = 0; i < DisasmLines.size(); ++i) {
253 std::string Comment(DisasmLineMaxLen - DisasmLines[i].size(), ' ');
254 Comment += " ; " + HexLines[i] + "\n";
256 OutStreamer->EmitBytes(StringRef(DisasmLines[i]));
257 OutStreamer->EmitBytes(StringRef(Comment));
264 void AMDGPUAsmPrinter::EmitProgramInfoR600(const MachineFunction &MF) {
266 bool killPixel = false;
267 const AMDGPUSubtarget &STM = MF.getSubtarget<AMDGPUSubtarget>();
268 const R600RegisterInfo *RI =
269 static_cast<const R600RegisterInfo *>(STM.getRegisterInfo());
270 const R600MachineFunctionInfo *MFI = MF.getInfo<R600MachineFunctionInfo>();
272 for (const MachineBasicBlock &MBB : MF) {
273 for (const MachineInstr &MI : MBB) {
274 if (MI.getOpcode() == AMDGPU::KILLGT)
276 unsigned numOperands = MI.getNumOperands();
277 for (unsigned op_idx = 0; op_idx < numOperands; op_idx++) {
278 const MachineOperand &MO = MI.getOperand(op_idx);
281 unsigned HWReg = RI->getEncodingValue(MO.getReg()) & 0xff;
283 // Register with value > 127 aren't GPR
286 MaxGPR = std::max(MaxGPR, HWReg);
292 if (STM.getGeneration() >= AMDGPUSubtarget::EVERGREEN) {
293 // Evergreen / Northern Islands
294 switch (MFI->getShaderType()) {
295 default: // Fall through
296 case ShaderType::COMPUTE: RsrcReg = R_0288D4_SQ_PGM_RESOURCES_LS; break;
297 case ShaderType::GEOMETRY: RsrcReg = R_028878_SQ_PGM_RESOURCES_GS; break;
298 case ShaderType::PIXEL: RsrcReg = R_028844_SQ_PGM_RESOURCES_PS; break;
299 case ShaderType::VERTEX: RsrcReg = R_028860_SQ_PGM_RESOURCES_VS; break;
303 switch (MFI->getShaderType()) {
304 default: // Fall through
305 case ShaderType::GEOMETRY: // Fall through
306 case ShaderType::COMPUTE: // Fall through
307 case ShaderType::VERTEX: RsrcReg = R_028868_SQ_PGM_RESOURCES_VS; break;
308 case ShaderType::PIXEL: RsrcReg = R_028850_SQ_PGM_RESOURCES_PS; break;
312 OutStreamer->EmitIntValue(RsrcReg, 4);
313 OutStreamer->EmitIntValue(S_NUM_GPRS(MaxGPR + 1) |
314 S_STACK_SIZE(MFI->StackSize), 4);
315 OutStreamer->EmitIntValue(R_02880C_DB_SHADER_CONTROL, 4);
316 OutStreamer->EmitIntValue(S_02880C_KILL_ENABLE(killPixel), 4);
318 if (MFI->getShaderType() == ShaderType::COMPUTE) {
319 OutStreamer->EmitIntValue(R_0288E8_SQ_LDS_ALLOC, 4);
320 OutStreamer->EmitIntValue(RoundUpToAlignment(MFI->LDSSize, 4) >> 2, 4);
324 void AMDGPUAsmPrinter::getSIProgramInfo(SIProgramInfo &ProgInfo,
325 const MachineFunction &MF) const {
326 const AMDGPUSubtarget &STM = MF.getSubtarget<AMDGPUSubtarget>();
327 const SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
328 uint64_t CodeSize = 0;
329 unsigned MaxSGPR = 0;
330 unsigned MaxVGPR = 0;
331 bool VCCUsed = false;
332 bool FlatUsed = false;
333 const SIRegisterInfo *RI =
334 static_cast<const SIRegisterInfo *>(STM.getRegisterInfo());
336 for (const MachineBasicBlock &MBB : MF) {
337 for (const MachineInstr &MI : MBB) {
338 // TODO: CodeSize should account for multiple functions.
340 // TODO: Should we count size of debug info?
341 if (MI.isDebugValue())
344 // FIXME: This is reporting 0 for many instructions.
345 CodeSize += MI.getDesc().Size;
347 unsigned numOperands = MI.getNumOperands();
348 for (unsigned op_idx = 0; op_idx < numOperands; op_idx++) {
349 const MachineOperand &MO = MI.getOperand(op_idx);
356 unsigned reg = MO.getReg();
369 case AMDGPU::FLAT_SCR:
370 case AMDGPU::FLAT_SCR_LO:
371 case AMDGPU::FLAT_SCR_HI:
379 if (AMDGPU::SReg_32RegClass.contains(reg)) {
382 } else if (AMDGPU::VGPR_32RegClass.contains(reg)) {
385 } else if (AMDGPU::SReg_64RegClass.contains(reg)) {
388 } else if (AMDGPU::VReg_64RegClass.contains(reg)) {
391 } else if (AMDGPU::VReg_96RegClass.contains(reg)) {
394 } else if (AMDGPU::SReg_128RegClass.contains(reg)) {
397 } else if (AMDGPU::VReg_128RegClass.contains(reg)) {
400 } else if (AMDGPU::SReg_256RegClass.contains(reg)) {
403 } else if (AMDGPU::VReg_256RegClass.contains(reg)) {
406 } else if (AMDGPU::SReg_512RegClass.contains(reg)) {
409 } else if (AMDGPU::VReg_512RegClass.contains(reg)) {
413 llvm_unreachable("Unknown register class");
415 unsigned hwReg = RI->getEncodingValue(reg) & 0xff;
416 unsigned maxUsed = hwReg + width - 1;
418 MaxSGPR = maxUsed > MaxSGPR ? maxUsed : MaxSGPR;
420 MaxVGPR = maxUsed > MaxVGPR ? maxUsed : MaxVGPR;
432 // We found the maximum register index. They start at 0, so add one to get the
433 // number of registers.
434 ProgInfo.NumVGPR = MaxVGPR + 1;
435 ProgInfo.NumSGPR = MaxSGPR + 1;
437 if (STM.hasSGPRInitBug()) {
438 if (ProgInfo.NumSGPR > AMDGPUSubtarget::FIXED_SGPR_COUNT_FOR_INIT_BUG) {
439 LLVMContext &Ctx = MF.getFunction()->getContext();
440 Ctx.emitError("too many SGPRs used with the SGPR init bug");
443 ProgInfo.NumSGPR = AMDGPUSubtarget::FIXED_SGPR_COUNT_FOR_INIT_BUG;
446 if (MFI->NumUserSGPRs > STM.getMaxNumUserSGPRs()) {
447 LLVMContext &Ctx = MF.getFunction()->getContext();
448 Ctx.emitError("too many user SGPRs used");
451 ProgInfo.VGPRBlocks = (ProgInfo.NumVGPR - 1) / 4;
452 ProgInfo.SGPRBlocks = (ProgInfo.NumSGPR - 1) / 8;
453 // Set the value to initialize FP_ROUND and FP_DENORM parts of the mode
455 ProgInfo.FloatMode = getFPMode(MF);
457 // XXX: Not quite sure what this does, but sc seems to unset this.
458 ProgInfo.IEEEMode = 0;
460 // Do not clamp NAN to 0.
461 ProgInfo.DX10Clamp = 0;
463 const MachineFrameInfo *FrameInfo = MF.getFrameInfo();
464 ProgInfo.ScratchSize = FrameInfo->estimateStackSize(MF);
466 ProgInfo.FlatUsed = FlatUsed;
467 ProgInfo.VCCUsed = VCCUsed;
468 ProgInfo.CodeLen = CodeSize;
470 unsigned LDSAlignShift;
471 if (STM.getGeneration() < AMDGPUSubtarget::SEA_ISLANDS) {
472 // LDS is allocated in 64 dword blocks.
475 // LDS is allocated in 128 dword blocks.
479 unsigned LDSSpillSize = MFI->LDSWaveSpillSize *
480 MFI->getMaximumWorkGroupSize(MF);
482 ProgInfo.LDSSize = MFI->LDSSize + LDSSpillSize;
484 RoundUpToAlignment(ProgInfo.LDSSize, 1 << LDSAlignShift) >> LDSAlignShift;
486 // Scratch is allocated in 256 dword blocks.
487 unsigned ScratchAlignShift = 10;
488 // We need to program the hardware with the amount of scratch memory that
489 // is used by the entire wave. ProgInfo.ScratchSize is the amount of
490 // scratch memory used per thread.
491 ProgInfo.ScratchBlocks =
492 RoundUpToAlignment(ProgInfo.ScratchSize * STM.getWavefrontSize(),
493 1 << ScratchAlignShift) >> ScratchAlignShift;
495 ProgInfo.ComputePGMRSrc1 =
496 S_00B848_VGPRS(ProgInfo.VGPRBlocks) |
497 S_00B848_SGPRS(ProgInfo.SGPRBlocks) |
498 S_00B848_PRIORITY(ProgInfo.Priority) |
499 S_00B848_FLOAT_MODE(ProgInfo.FloatMode) |
500 S_00B848_PRIV(ProgInfo.Priv) |
501 S_00B848_DX10_CLAMP(ProgInfo.DX10Clamp) |
502 S_00B848_DEBUG_MODE(ProgInfo.DebugMode) |
503 S_00B848_IEEE_MODE(ProgInfo.IEEEMode);
505 // 0 = X, 1 = XY, 2 = XYZ
506 unsigned TIDIGCompCnt = 0;
507 if (MFI->hasWorkItemIDZ())
509 else if (MFI->hasWorkItemIDY())
512 ProgInfo.ComputePGMRSrc2 =
513 S_00B84C_SCRATCH_EN(ProgInfo.ScratchBlocks > 0) |
514 S_00B84C_USER_SGPR(MFI->getNumUserSGPRs()) |
515 S_00B84C_TGID_X_EN(MFI->hasWorkGroupIDX()) |
516 S_00B84C_TGID_Y_EN(MFI->hasWorkGroupIDY()) |
517 S_00B84C_TGID_Z_EN(MFI->hasWorkGroupIDZ()) |
518 S_00B84C_TG_SIZE_EN(MFI->hasWorkGroupInfo()) |
519 S_00B84C_TIDIG_COMP_CNT(TIDIGCompCnt) |
520 S_00B84C_EXCP_EN_MSB(0) |
521 S_00B84C_LDS_SIZE(ProgInfo.LDSBlocks) |
525 static unsigned getRsrcReg(unsigned ShaderType) {
526 switch (ShaderType) {
527 default: // Fall through
528 case ShaderType::COMPUTE: return R_00B848_COMPUTE_PGM_RSRC1;
529 case ShaderType::GEOMETRY: return R_00B228_SPI_SHADER_PGM_RSRC1_GS;
530 case ShaderType::PIXEL: return R_00B028_SPI_SHADER_PGM_RSRC1_PS;
531 case ShaderType::VERTEX: return R_00B128_SPI_SHADER_PGM_RSRC1_VS;
535 void AMDGPUAsmPrinter::EmitProgramInfoSI(const MachineFunction &MF,
536 const SIProgramInfo &KernelInfo) {
537 const AMDGPUSubtarget &STM = MF.getSubtarget<AMDGPUSubtarget>();
538 const SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
539 unsigned RsrcReg = getRsrcReg(MFI->getShaderType());
541 if (MFI->getShaderType() == ShaderType::COMPUTE) {
542 OutStreamer->EmitIntValue(R_00B848_COMPUTE_PGM_RSRC1, 4);
544 OutStreamer->EmitIntValue(KernelInfo.ComputePGMRSrc1, 4);
546 OutStreamer->EmitIntValue(R_00B84C_COMPUTE_PGM_RSRC2, 4);
547 OutStreamer->EmitIntValue(KernelInfo.ComputePGMRSrc2, 4);
549 OutStreamer->EmitIntValue(R_00B860_COMPUTE_TMPRING_SIZE, 4);
550 OutStreamer->EmitIntValue(S_00B860_WAVESIZE(KernelInfo.ScratchBlocks), 4);
552 // TODO: Should probably note flat usage somewhere. SC emits a "FlatPtr32 =
553 // 0" comment but I don't see a corresponding field in the register spec.
555 OutStreamer->EmitIntValue(RsrcReg, 4);
556 OutStreamer->EmitIntValue(S_00B028_VGPRS(KernelInfo.VGPRBlocks) |
557 S_00B028_SGPRS(KernelInfo.SGPRBlocks), 4);
558 if (STM.isVGPRSpillingEnabled(MFI)) {
559 OutStreamer->EmitIntValue(R_0286E8_SPI_TMPRING_SIZE, 4);
560 OutStreamer->EmitIntValue(S_0286E8_WAVESIZE(KernelInfo.ScratchBlocks), 4);
564 if (MFI->getShaderType() == ShaderType::PIXEL) {
565 OutStreamer->EmitIntValue(R_00B02C_SPI_SHADER_PGM_RSRC2_PS, 4);
566 OutStreamer->EmitIntValue(S_00B02C_EXTRA_LDS_SIZE(KernelInfo.LDSBlocks), 4);
567 OutStreamer->EmitIntValue(R_0286CC_SPI_PS_INPUT_ENA, 4);
568 OutStreamer->EmitIntValue(MFI->PSInputAddr, 4);
572 void AMDGPUAsmPrinter::EmitAmdKernelCodeT(const MachineFunction &MF,
573 const SIProgramInfo &KernelInfo) const {
574 const SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
575 const AMDGPUSubtarget &STM = MF.getSubtarget<AMDGPUSubtarget>();
576 amd_kernel_code_t header;
578 AMDGPU::initDefaultAMDKernelCodeT(header, STM.getFeatureBits());
580 header.compute_pgm_resource_registers =
581 KernelInfo.ComputePGMRSrc1 |
582 (KernelInfo.ComputePGMRSrc2 << 32);
583 header.code_properties = AMD_CODE_PROPERTY_IS_PTR64;
585 if (MFI->hasPrivateSegmentBuffer()) {
586 header.code_properties |=
587 AMD_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER;
590 if (MFI->hasDispatchPtr())
591 header.code_properties |= AMD_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_PTR;
593 if (MFI->hasQueuePtr())
594 header.code_properties |= AMD_CODE_PROPERTY_ENABLE_SGPR_QUEUE_PTR;
596 if (MFI->hasKernargSegmentPtr())
597 header.code_properties |= AMD_CODE_PROPERTY_ENABLE_SGPR_KERNARG_SEGMENT_PTR;
599 if (MFI->hasDispatchID())
600 header.code_properties |= AMD_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_ID;
602 if (MFI->hasFlatScratchInit())
603 header.code_properties |= AMD_CODE_PROPERTY_ENABLE_SGPR_FLAT_SCRATCH_INIT;
605 // TODO: Private segment size
607 if (MFI->hasGridWorkgroupCountX()) {
608 header.code_properties |=
609 AMD_CODE_PROPERTY_ENABLE_SGPR_GRID_WORKGROUP_COUNT_X;
612 if (MFI->hasGridWorkgroupCountY()) {
613 header.code_properties |=
614 AMD_CODE_PROPERTY_ENABLE_SGPR_GRID_WORKGROUP_COUNT_Y;
617 if (MFI->hasGridWorkgroupCountZ()) {
618 header.code_properties |=
619 AMD_CODE_PROPERTY_ENABLE_SGPR_GRID_WORKGROUP_COUNT_Z;
622 if (MFI->hasDispatchPtr())
623 header.code_properties |= AMD_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_PTR;
625 header.kernarg_segment_byte_size = MFI->ABIArgOffset;
626 header.wavefront_sgpr_count = KernelInfo.NumSGPR;
627 header.workitem_vgpr_count = KernelInfo.NumVGPR;
629 AMDGPUTargetStreamer *TS =
630 static_cast<AMDGPUTargetStreamer *>(OutStreamer->getTargetStreamer());
631 TS->EmitAMDKernelCodeT(header);
634 bool AMDGPUAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
636 const char *ExtraCode, raw_ostream &O) {
637 if (ExtraCode && ExtraCode[0]) {
638 if (ExtraCode[1] != 0)
639 return true; // Unknown modifier.
641 switch (ExtraCode[0]) {
643 // See if this is a generic print operand
644 return AsmPrinter::PrintAsmOperand(MI, OpNo, AsmVariant, ExtraCode, O);
650 AMDGPUInstPrinter::printRegOperand(MI->getOperand(OpNo).getReg(), O,
651 *TM.getSubtargetImpl(*MF->getFunction())->getRegisterInfo());