1 //===-- AMDGPU.td - AMDGPU Tablegen files ------------------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 include "llvm/Target/Target.td"
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
18 def FeatureDumpCode : SubtargetFeature <"DumpCode",
21 "Dump MachineInstrs in the CodeEmitter">;
23 def FeatureDumpCodeLower : SubtargetFeature <"dumpcode",
26 "Dump MachineInstrs in the CodeEmitter">;
28 def FeatureIRStructurizer : SubtargetFeature <"disable-irstructurizer",
29 "EnableIRStructurizer",
31 "Disable IR Structurizer">;
33 def FeaturePromoteAlloca : SubtargetFeature <"promote-alloca",
34 "EnablePromoteAlloca",
36 "Enable promote alloca pass">;
40 def FeatureIfCvt : SubtargetFeature <"disable-ifcvt",
43 "Disable the if conversion pass">;
45 def FeatureFP64 : SubtargetFeature<"fp64",
48 "Enable double precision operations">;
50 def FeatureFP64Denormals : SubtargetFeature<"fp64-denormals",
53 "Enable double precision denormal handling",
56 def FeatureFastFMAF32 : SubtargetFeature<"fast-fmaf",
59 "Assuming f32 fma is at least as fast as mul + add",
62 // Some instructions do not support denormals despite this flag. Using
63 // fp32 denormals also causes instructions to run at the double
64 // precision rate for the device.
65 def FeatureFP32Denormals : SubtargetFeature<"fp32-denormals",
68 "Enable single precision denormal handling">;
70 def Feature64BitPtr : SubtargetFeature<"64BitPtr",
73 "Specify if 64-bit addressing should be used">;
75 def FeatureR600ALUInst : SubtargetFeature<"R600ALUInst",
78 "Older version of ALU instructions encoding">;
80 def FeatureVertexCache : SubtargetFeature<"HasVertexCache",
83 "Specify use of dedicated vertex cache">;
85 def FeatureCaymanISA : SubtargetFeature<"caymanISA",
90 def FeatureCFALUBug : SubtargetFeature<"cfalubug",
93 "GPU has CF_ALU bug">;
95 // XXX - This should probably be removed once enabled by default
96 def FeatureEnableLoadStoreOpt : SubtargetFeature <"load-store-opt",
99 "Enable SI load/store optimizer pass">;
101 // Performance debugging feature. Allow using DS instruction immediate
102 // offsets even if the base pointer can't be proven to be base. On SI,
103 // base pointer values that won't give the same result as a 16-bit add
104 // are not safe to fold, but this will override the conservative test
105 // for the base pointer.
106 def FeatureEnableUnsafeDSOffsetFolding : SubtargetFeature <"unsafe-ds-offset-folding",
107 "EnableUnsafeDSOffsetFolding",
109 "Force using DS instruction immediate offsets on SI">;
111 def FeatureFlatForGlobal : SubtargetFeature<"flat-for-global",
114 "Force to generate flat instruction for global">;
116 def FeatureFlatAddressSpace : SubtargetFeature<"flat-address-space",
119 "Support flat address space">;
121 def FeatureVGPRSpilling : SubtargetFeature<"vgpr-spilling",
122 "EnableVGPRSpilling",
124 "Enable spilling of VGPRs to scratch memory">;
126 def FeatureSGPRInitBug : SubtargetFeature<"sgpr-init-bug",
129 "VI SGPR initilization bug requiring a fixed SGPR allocation size">;
131 def FeatureEnableHugeScratchBuffer : SubtargetFeature<"huge-scratch-buffer",
132 "EnableHugeScratchBuffer",
134 "Enable scratch buffer sizes greater than 128 GB">;
136 class SubtargetFeatureFetchLimit <string Value> :
137 SubtargetFeature <"fetch"#Value,
140 "Limit the maximum number of fetches in a clause to "#Value>;
142 def FeatureFetchLimit8 : SubtargetFeatureFetchLimit <"8">;
143 def FeatureFetchLimit16 : SubtargetFeatureFetchLimit <"16">;
145 class SubtargetFeatureWavefrontSize <int Value> : SubtargetFeature<
146 "wavefrontsize"#Value,
148 !cast<string>(Value),
149 "The number of threads per wavefront">;
151 def FeatureWavefrontSize16 : SubtargetFeatureWavefrontSize<16>;
152 def FeatureWavefrontSize32 : SubtargetFeatureWavefrontSize<32>;
153 def FeatureWavefrontSize64 : SubtargetFeatureWavefrontSize<64>;
155 class SubtargetFeatureLDSBankCount <int Value> : SubtargetFeature <
156 "ldsbankcount"#Value,
158 !cast<string>(Value),
159 "The number of LDS banks per compute unit.">;
161 def FeatureLDSBankCount16 : SubtargetFeatureLDSBankCount<16>;
162 def FeatureLDSBankCount32 : SubtargetFeatureLDSBankCount<32>;
164 class SubtargetFeatureISAVersion <int Major, int Minor, int Stepping>
166 "isaver"#Major#"."#Minor#"."#Stepping,
168 "ISAVersion"#Major#"_"#Minor#"_"#Stepping,
169 "Instruction set version number"
172 def FeatureISAVersion7_0_0 : SubtargetFeatureISAVersion <7,0,0>;
173 def FeatureISAVersion7_0_1 : SubtargetFeatureISAVersion <7,0,1>;
174 def FeatureISAVersion8_0_0 : SubtargetFeatureISAVersion <8,0,0>;
175 def FeatureISAVersion8_0_1 : SubtargetFeatureISAVersion <8,0,1>;
177 class SubtargetFeatureLocalMemorySize <int Value> : SubtargetFeature<
178 "localmemorysize"#Value,
180 !cast<string>(Value),
181 "The size of local memory in bytes">;
183 def FeatureGCN : SubtargetFeature<"gcn",
188 def FeatureGCN1Encoding : SubtargetFeature<"gcn1-encoding",
191 "Encoding format for SI and CI">;
193 def FeatureGCN3Encoding : SubtargetFeature<"gcn3-encoding",
196 "Encoding format for VI">;
198 def FeatureCIInsts : SubtargetFeature<"ci-insts",
201 "Additional intstructions for CI+">;
203 // Dummy feature used to disable assembler instructions.
204 def FeatureDisable : SubtargetFeature<"",
205 "FeatureDisable","true",
206 "Dummy feature to disable assembler"
209 class SubtargetFeatureGeneration <string Value,
210 list<SubtargetFeature> Implies> :
211 SubtargetFeature <Value, "Gen", "AMDGPUSubtarget::"#Value,
212 Value#" GPU generation", Implies>;
214 def FeatureLocalMemorySize0 : SubtargetFeatureLocalMemorySize<0>;
215 def FeatureLocalMemorySize32768 : SubtargetFeatureLocalMemorySize<32768>;
216 def FeatureLocalMemorySize65536 : SubtargetFeatureLocalMemorySize<65536>;
218 def FeatureR600 : SubtargetFeatureGeneration<"R600",
219 [FeatureR600ALUInst, FeatureFetchLimit8, FeatureLocalMemorySize0]>;
221 def FeatureR700 : SubtargetFeatureGeneration<"R700",
222 [FeatureFetchLimit16, FeatureLocalMemorySize0]>;
224 def FeatureEvergreen : SubtargetFeatureGeneration<"EVERGREEN",
225 [FeatureFetchLimit16, FeatureLocalMemorySize32768]>;
227 def FeatureNorthernIslands : SubtargetFeatureGeneration<"NORTHERN_ISLANDS",
228 [FeatureFetchLimit16, FeatureWavefrontSize64,
229 FeatureLocalMemorySize32768]
232 def FeatureSouthernIslands : SubtargetFeatureGeneration<"SOUTHERN_ISLANDS",
233 [Feature64BitPtr, FeatureFP64, FeatureLocalMemorySize32768,
234 FeatureWavefrontSize64, FeatureGCN, FeatureGCN1Encoding,
235 FeatureLDSBankCount32]>;
237 def FeatureSeaIslands : SubtargetFeatureGeneration<"SEA_ISLANDS",
238 [Feature64BitPtr, FeatureFP64, FeatureLocalMemorySize65536,
239 FeatureWavefrontSize64, FeatureGCN, FeatureFlatAddressSpace,
240 FeatureGCN1Encoding, FeatureCIInsts]>;
242 def FeatureVolcanicIslands : SubtargetFeatureGeneration<"VOLCANIC_ISLANDS",
243 [Feature64BitPtr, FeatureFP64, FeatureLocalMemorySize65536,
244 FeatureWavefrontSize64, FeatureFlatAddressSpace, FeatureGCN,
245 FeatureGCN3Encoding, FeatureCIInsts, FeatureLDSBankCount32]>;
247 //===----------------------------------------------------------------------===//
249 def AMDGPUInstrInfo : InstrInfo {
250 let guessInstructionProperties = 1;
251 let noNamedPositionallyEncodedOperands = 1;
254 def AMDGPUAsmParser : AsmParser {
255 // Some of the R600 registers have the same name, so this crashes.
256 // For example T0_XYZW and T0_XY both have the asm name T0.
257 let ShouldEmitMatchRegisterName = 0;
260 def AMDGPU : Target {
261 // Pull in Instruction Info:
262 let InstructionSet = AMDGPUInstrInfo;
263 let AssemblyParsers = [AMDGPUAsmParser];
266 // Dummy Instruction itineraries for pseudo instructions
267 def ALU_NULL : FuncUnit;
268 def NullALU : InstrItinClass;
270 //===----------------------------------------------------------------------===//
271 // Predicate helper class
272 //===----------------------------------------------------------------------===//
274 def TruePredicate : Predicate<"true">;
275 def isSICI : Predicate<
276 "Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS ||"
277 "Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS"
278 >, AssemblerPredicate<"FeatureGCN1Encoding">;
280 def isVI : Predicate <
281 "Subtarget->getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS">,
282 AssemblerPredicate<"FeatureGCN3Encoding">;
284 class PredicateControl {
285 Predicate SubtargetPredicate;
286 Predicate SIAssemblerPredicate = isSICI;
287 Predicate VIAssemblerPredicate = isVI;
288 list<Predicate> AssemblerPredicates = [];
289 Predicate AssemblerPredicate = TruePredicate;
290 list<Predicate> OtherPredicates = [];
291 list<Predicate> Predicates = !listconcat([SubtargetPredicate, AssemblerPredicate],
296 // Include AMDGPU TD files
297 include "R600Schedule.td"
298 include "SISchedule.td"
299 include "Processors.td"
300 include "AMDGPUInstrInfo.td"
301 include "AMDGPUIntrinsics.td"
302 include "AMDGPURegisterInfo.td"
303 include "AMDGPUInstructions.td"
304 include "AMDGPUCallingConv.td"