1 //===-- AMDGPU.h - MachineFunction passes hw codegen --------------*- C++ -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
9 //===----------------------------------------------------------------------===//
11 #ifndef LLVM_LIB_TARGET_R600_AMDGPU_H
12 #define LLVM_LIB_TARGET_R600_AMDGPU_H
14 #include "llvm/Support/TargetRegistry.h"
15 #include "llvm/Target/TargetMachine.h"
19 class AMDGPUInstrPrinter;
20 class AMDGPUSubtarget;
21 class AMDGPUTargetMachine;
29 FunctionPass *createR600VectorRegMerger(TargetMachine &tm);
30 FunctionPass *createR600TextureIntrinsicsReplacer();
31 FunctionPass *createR600ExpandSpecialInstrsPass(TargetMachine &tm);
32 FunctionPass *createR600EmitClauseMarkers();
33 FunctionPass *createR600ClauseMergePass(TargetMachine &tm);
34 FunctionPass *createR600Packetizer(TargetMachine &tm);
35 FunctionPass *createR600ControlFlowFinalizer(TargetMachine &tm);
36 FunctionPass *createAMDGPUCFGStructurizerPass();
39 FunctionPass *createSITypeRewriter();
40 FunctionPass *createSIAnnotateControlFlowPass();
41 FunctionPass *createSIFoldOperandsPass();
42 FunctionPass *createSILowerI1CopiesPass();
43 FunctionPass *createSIShrinkInstructionsPass();
44 FunctionPass *createSILoadStoreOptimizerPass(TargetMachine &tm);
45 FunctionPass *createSILowerControlFlowPass(TargetMachine &tm);
46 FunctionPass *createSIFixControlFlowLiveIntervalsPass();
47 FunctionPass *createSIFixSGPRCopiesPass();
48 FunctionPass *createSIFixSGPRLiveRangesPass();
49 FunctionPass *createSICodeEmitterPass(formatted_raw_ostream &OS);
50 FunctionPass *createSIInsertWaits(TargetMachine &tm);
51 FunctionPass *createSIPrepareScratchRegs();
53 void initializeSIFoldOperandsPass(PassRegistry &);
54 extern char &SIFoldOperandsID;
56 void initializeSIFixSGPRCopiesPass(PassRegistry &);
57 extern char &SIFixSGPRCopiesID;
59 void initializeSILowerI1CopiesPass(PassRegistry &);
60 extern char &SILowerI1CopiesID;
62 void initializeSILoadStoreOptimizerPass(PassRegistry &);
63 extern char &SILoadStoreOptimizerID;
65 // Passes common to R600 and SI
66 FunctionPass *createAMDGPUPromoteAlloca(const AMDGPUSubtarget &ST);
67 Pass *createAMDGPUStructurizeCFGPass();
68 FunctionPass *createAMDGPUISelDag(TargetMachine &tm);
69 ModulePass *createAMDGPUAlwaysInlinePass();
70 ModulePass *createAMDGPUOpenCLImageTypeLoweringPass();
72 void initializeSIFixControlFlowLiveIntervalsPass(PassRegistry&);
73 extern char &SIFixControlFlowLiveIntervalsID;
75 void initializeSIFixSGPRLiveRangesPass(PassRegistry&);
76 extern char &SIFixSGPRLiveRangesID;
79 extern Target TheAMDGPUTarget;
80 extern Target TheGCNTarget;
85 TI_SCRATCH_RSRC_DWORD0,
86 TI_SCRATCH_RSRC_DWORD1,
87 TI_SCRATCH_RSRC_DWORD2,
88 TI_SCRATCH_RSRC_DWORD3
92 #define END_OF_TEXT_LABEL_NAME "EndOfTextLabel"
94 } // End namespace llvm
96 namespace ShaderType {
105 /// OpenCL uses address spaces to differentiate between
106 /// various memory regions on the hardware. On the CPU
107 /// all of the address spaces point to the same memory,
108 /// however on the GPU, each address space points to
109 /// a separate piece of memory that is unique from other
110 /// memory locations.
112 enum AddressSpaces : unsigned {
113 PRIVATE_ADDRESS = 0, ///< Address space for private memory.
114 GLOBAL_ADDRESS = 1, ///< Address space for global memory (RAT0, VTX0).
115 CONSTANT_ADDRESS = 2, ///< Address space for constant memory
116 LOCAL_ADDRESS = 3, ///< Address space for local memory.
117 FLAT_ADDRESS = 4, ///< Address space for flat memory.
118 REGION_ADDRESS = 5, ///< Address space for region memory.
119 PARAM_D_ADDRESS = 6, ///< Address space for direct addressible parameter memory (CONST0)
120 PARAM_I_ADDRESS = 7, ///< Address space for indirect addressible parameter memory (VTX1)
122 // Do not re-order the CONSTANT_BUFFER_* enums. Several places depend on this
123 // order to be able to dynamically index a constant buffer, for example:
125 // ConstantBufferAS = CONSTANT_BUFFER_0 + CBIdx
127 CONSTANT_BUFFER_0 = 8,
128 CONSTANT_BUFFER_1 = 9,
129 CONSTANT_BUFFER_2 = 10,
130 CONSTANT_BUFFER_3 = 11,
131 CONSTANT_BUFFER_4 = 12,
132 CONSTANT_BUFFER_5 = 13,
133 CONSTANT_BUFFER_6 = 14,
134 CONSTANT_BUFFER_7 = 15,
135 CONSTANT_BUFFER_8 = 16,
136 CONSTANT_BUFFER_9 = 17,
137 CONSTANT_BUFFER_10 = 18,
138 CONSTANT_BUFFER_11 = 19,
139 CONSTANT_BUFFER_12 = 20,
140 CONSTANT_BUFFER_13 = 21,
141 CONSTANT_BUFFER_14 = 22,
142 CONSTANT_BUFFER_15 = 23,
143 ADDRESS_NONE = 24, ///< Address space for unknown memory.
144 LAST_ADDRESS = ADDRESS_NONE,
146 // Some places use this if the address space can't be determined.
147 UNKNOWN_ADDRESS_SPACE = ~0u
150 } // namespace AMDGPUAS