1 //===-- AArch64BaseInfo.h - Top level definitions for AArch64 ---*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains small standalone helper functions and enum definitions for
11 // the AArch64 target useful for the compiler back-end and the MC libraries.
12 // As such, it deliberately does not include references to LLVM core
13 // code gen types, passes, etc..
15 //===----------------------------------------------------------------------===//
17 #ifndef LLVM_LIB_TARGET_AARCH64_UTILS_AARCH64BASEINFO_H
18 #define LLVM_LIB_TARGET_AARCH64_UTILS_AARCH64BASEINFO_H
20 // FIXME: Is it easiest to fix this layering violation by moving the .inc
21 // #includes from AArch64MCTargetDesc.h to here?
22 #include "MCTargetDesc/AArch64MCTargetDesc.h" // For AArch64::X0 and friends.
23 #include "llvm/ADT/STLExtras.h"
24 #include "llvm/ADT/StringSwitch.h"
25 #include "llvm/Support/ErrorHandling.h"
31 inline static unsigned getWRegFromXReg(unsigned Reg) {
33 case AArch64::X0: return AArch64::W0;
34 case AArch64::X1: return AArch64::W1;
35 case AArch64::X2: return AArch64::W2;
36 case AArch64::X3: return AArch64::W3;
37 case AArch64::X4: return AArch64::W4;
38 case AArch64::X5: return AArch64::W5;
39 case AArch64::X6: return AArch64::W6;
40 case AArch64::X7: return AArch64::W7;
41 case AArch64::X8: return AArch64::W8;
42 case AArch64::X9: return AArch64::W9;
43 case AArch64::X10: return AArch64::W10;
44 case AArch64::X11: return AArch64::W11;
45 case AArch64::X12: return AArch64::W12;
46 case AArch64::X13: return AArch64::W13;
47 case AArch64::X14: return AArch64::W14;
48 case AArch64::X15: return AArch64::W15;
49 case AArch64::X16: return AArch64::W16;
50 case AArch64::X17: return AArch64::W17;
51 case AArch64::X18: return AArch64::W18;
52 case AArch64::X19: return AArch64::W19;
53 case AArch64::X20: return AArch64::W20;
54 case AArch64::X21: return AArch64::W21;
55 case AArch64::X22: return AArch64::W22;
56 case AArch64::X23: return AArch64::W23;
57 case AArch64::X24: return AArch64::W24;
58 case AArch64::X25: return AArch64::W25;
59 case AArch64::X26: return AArch64::W26;
60 case AArch64::X27: return AArch64::W27;
61 case AArch64::X28: return AArch64::W28;
62 case AArch64::FP: return AArch64::W29;
63 case AArch64::LR: return AArch64::W30;
64 case AArch64::SP: return AArch64::WSP;
65 case AArch64::XZR: return AArch64::WZR;
67 // For anything else, return it unchanged.
71 inline static unsigned getXRegFromWReg(unsigned Reg) {
73 case AArch64::W0: return AArch64::X0;
74 case AArch64::W1: return AArch64::X1;
75 case AArch64::W2: return AArch64::X2;
76 case AArch64::W3: return AArch64::X3;
77 case AArch64::W4: return AArch64::X4;
78 case AArch64::W5: return AArch64::X5;
79 case AArch64::W6: return AArch64::X6;
80 case AArch64::W7: return AArch64::X7;
81 case AArch64::W8: return AArch64::X8;
82 case AArch64::W9: return AArch64::X9;
83 case AArch64::W10: return AArch64::X10;
84 case AArch64::W11: return AArch64::X11;
85 case AArch64::W12: return AArch64::X12;
86 case AArch64::W13: return AArch64::X13;
87 case AArch64::W14: return AArch64::X14;
88 case AArch64::W15: return AArch64::X15;
89 case AArch64::W16: return AArch64::X16;
90 case AArch64::W17: return AArch64::X17;
91 case AArch64::W18: return AArch64::X18;
92 case AArch64::W19: return AArch64::X19;
93 case AArch64::W20: return AArch64::X20;
94 case AArch64::W21: return AArch64::X21;
95 case AArch64::W22: return AArch64::X22;
96 case AArch64::W23: return AArch64::X23;
97 case AArch64::W24: return AArch64::X24;
98 case AArch64::W25: return AArch64::X25;
99 case AArch64::W26: return AArch64::X26;
100 case AArch64::W27: return AArch64::X27;
101 case AArch64::W28: return AArch64::X28;
102 case AArch64::W29: return AArch64::FP;
103 case AArch64::W30: return AArch64::LR;
104 case AArch64::WSP: return AArch64::SP;
105 case AArch64::WZR: return AArch64::XZR;
107 // For anything else, return it unchanged.
111 static inline unsigned getBRegFromDReg(unsigned Reg) {
113 case AArch64::D0: return AArch64::B0;
114 case AArch64::D1: return AArch64::B1;
115 case AArch64::D2: return AArch64::B2;
116 case AArch64::D3: return AArch64::B3;
117 case AArch64::D4: return AArch64::B4;
118 case AArch64::D5: return AArch64::B5;
119 case AArch64::D6: return AArch64::B6;
120 case AArch64::D7: return AArch64::B7;
121 case AArch64::D8: return AArch64::B8;
122 case AArch64::D9: return AArch64::B9;
123 case AArch64::D10: return AArch64::B10;
124 case AArch64::D11: return AArch64::B11;
125 case AArch64::D12: return AArch64::B12;
126 case AArch64::D13: return AArch64::B13;
127 case AArch64::D14: return AArch64::B14;
128 case AArch64::D15: return AArch64::B15;
129 case AArch64::D16: return AArch64::B16;
130 case AArch64::D17: return AArch64::B17;
131 case AArch64::D18: return AArch64::B18;
132 case AArch64::D19: return AArch64::B19;
133 case AArch64::D20: return AArch64::B20;
134 case AArch64::D21: return AArch64::B21;
135 case AArch64::D22: return AArch64::B22;
136 case AArch64::D23: return AArch64::B23;
137 case AArch64::D24: return AArch64::B24;
138 case AArch64::D25: return AArch64::B25;
139 case AArch64::D26: return AArch64::B26;
140 case AArch64::D27: return AArch64::B27;
141 case AArch64::D28: return AArch64::B28;
142 case AArch64::D29: return AArch64::B29;
143 case AArch64::D30: return AArch64::B30;
144 case AArch64::D31: return AArch64::B31;
146 // For anything else, return it unchanged.
151 static inline unsigned getDRegFromBReg(unsigned Reg) {
153 case AArch64::B0: return AArch64::D0;
154 case AArch64::B1: return AArch64::D1;
155 case AArch64::B2: return AArch64::D2;
156 case AArch64::B3: return AArch64::D3;
157 case AArch64::B4: return AArch64::D4;
158 case AArch64::B5: return AArch64::D5;
159 case AArch64::B6: return AArch64::D6;
160 case AArch64::B7: return AArch64::D7;
161 case AArch64::B8: return AArch64::D8;
162 case AArch64::B9: return AArch64::D9;
163 case AArch64::B10: return AArch64::D10;
164 case AArch64::B11: return AArch64::D11;
165 case AArch64::B12: return AArch64::D12;
166 case AArch64::B13: return AArch64::D13;
167 case AArch64::B14: return AArch64::D14;
168 case AArch64::B15: return AArch64::D15;
169 case AArch64::B16: return AArch64::D16;
170 case AArch64::B17: return AArch64::D17;
171 case AArch64::B18: return AArch64::D18;
172 case AArch64::B19: return AArch64::D19;
173 case AArch64::B20: return AArch64::D20;
174 case AArch64::B21: return AArch64::D21;
175 case AArch64::B22: return AArch64::D22;
176 case AArch64::B23: return AArch64::D23;
177 case AArch64::B24: return AArch64::D24;
178 case AArch64::B25: return AArch64::D25;
179 case AArch64::B26: return AArch64::D26;
180 case AArch64::B27: return AArch64::D27;
181 case AArch64::B28: return AArch64::D28;
182 case AArch64::B29: return AArch64::D29;
183 case AArch64::B30: return AArch64::D30;
184 case AArch64::B31: return AArch64::D31;
186 // For anything else, return it unchanged.
190 namespace AArch64CC {
192 // The CondCodes constants map directly to the 4-bit encoding of the condition
193 // field for predicated instructions.
194 enum CondCode { // Meaning (integer) Meaning (floating-point)
195 EQ = 0x0, // Equal Equal
196 NE = 0x1, // Not equal Not equal, or unordered
197 HS = 0x2, // Unsigned higher or same >, ==, or unordered
198 LO = 0x3, // Unsigned lower Less than
199 MI = 0x4, // Minus, negative Less than
200 PL = 0x5, // Plus, positive or zero >, ==, or unordered
201 VS = 0x6, // Overflow Unordered
202 VC = 0x7, // No overflow Not unordered
203 HI = 0x8, // Unsigned higher Greater than, or unordered
204 LS = 0x9, // Unsigned lower or same Less than or equal
205 GE = 0xa, // Greater than or equal Greater than or equal
206 LT = 0xb, // Less than Less than, or unordered
207 GT = 0xc, // Greater than Greater than
208 LE = 0xd, // Less than or equal <, ==, or unordered
209 AL = 0xe, // Always (unconditional) Always (unconditional)
210 NV = 0xf, // Always (unconditional) Always (unconditional)
211 // Note the NV exists purely to disassemble 0b1111. Execution is "always".
215 inline static const char *getCondCodeName(CondCode Code) {
217 default: llvm_unreachable("Unknown condition code");
218 case EQ: return "eq";
219 case NE: return "ne";
220 case HS: return "hs";
221 case LO: return "lo";
222 case MI: return "mi";
223 case PL: return "pl";
224 case VS: return "vs";
225 case VC: return "vc";
226 case HI: return "hi";
227 case LS: return "ls";
228 case GE: return "ge";
229 case LT: return "lt";
230 case GT: return "gt";
231 case LE: return "le";
232 case AL: return "al";
233 case NV: return "nv";
237 inline static CondCode getInvertedCondCode(CondCode Code) {
238 // To reverse a condition it's necessary to only invert the low bit:
240 return static_cast<CondCode>(static_cast<unsigned>(Code) ^ 0x1);
243 /// Given a condition code, return NZCV flags that would satisfy that condition.
244 /// The flag bits are in the format expected by the ccmp instructions.
245 /// Note that many different flag settings can satisfy a given condition code,
246 /// this function just returns one of them.
247 inline static unsigned getNZCVToSatisfyCondCode(CondCode Code) {
248 // NZCV flags encoded as expected by ccmp instructions, ARMv8 ISA 5.5.7.
249 enum { N = 8, Z = 4, C = 2, V = 1 };
251 default: llvm_unreachable("Unknown condition code");
252 case EQ: return Z; // Z == 1
253 case NE: return 0; // Z == 0
254 case HS: return C; // C == 1
255 case LO: return 0; // C == 0
256 case MI: return N; // N == 1
257 case PL: return 0; // N == 0
258 case VS: return V; // V == 1
259 case VC: return 0; // V == 0
260 case HI: return C; // C == 1 && Z == 0
261 case LS: return 0; // C == 0 || Z == 1
262 case GE: return 0; // N == V
263 case LT: return N; // N != V
264 case GT: return 0; // Z == 0 && N == V
265 case LE: return Z; // Z == 1 || N != V
268 } // end namespace AArch64CC
270 /// Instances of this class can perform bidirectional mapping from random
271 /// identifier strings to operand encodings. For example "MSR" takes a named
272 /// system-register which must be encoded somehow and decoded for printing. This
273 /// central location means that the information for those transformations is not
274 /// duplicated and remains in sync.
276 /// FIXME: currently the algorithm is a completely unoptimised linear
277 /// search. Obviously this could be improved, but we would probably want to work
278 /// out just how often these instructions are emitted before working on it. It
279 /// might even be optimal to just reorder the tables for the common instructions
280 /// rather than changing the algorithm.
281 struct AArch64NamedImmMapper {
288 AArch64NamedImmMapper(const Mapping (&Pairs)[N], uint32_t TooBigImm)
289 : Pairs(&Pairs[0]), NumPairs(N), TooBigImm(TooBigImm) {}
291 StringRef toString(uint32_t Value, bool &Valid) const;
292 uint32_t fromString(StringRef Name, bool &Valid) const;
294 /// Many of the instructions allow an alternative assembly form consisting of
295 /// a simple immediate. Currently the only valid forms are ranges [0, N) where
296 /// N being 0 indicates no immediate syntax-form is allowed.
297 bool validImm(uint32_t Value) const;
299 const Mapping *Pairs;
304 namespace AArch64AT {
306 Invalid = -1, // Op0 Op1 CRn CRm Op2
307 S1E1R = 0x43c0, // 01 000 0111 1000 000
308 S1E2R = 0x63c0, // 01 100 0111 1000 000
309 S1E3R = 0x73c0, // 01 110 0111 1000 000
310 S1E1W = 0x43c1, // 01 000 0111 1000 001
311 S1E2W = 0x63c1, // 01 100 0111 1000 001
312 S1E3W = 0x73c1, // 01 110 0111 1000 001
313 S1E0R = 0x43c2, // 01 000 0111 1000 010
314 S1E0W = 0x43c3, // 01 000 0111 1000 011
315 S12E1R = 0x63c4, // 01 100 0111 1000 100
316 S12E1W = 0x63c5, // 01 100 0111 1000 101
317 S12E0R = 0x63c6, // 01 100 0111 1000 110
318 S12E0W = 0x63c7 // 01 100 0111 1000 111
321 struct ATMapper : AArch64NamedImmMapper {
322 const static Mapping ATPairs[];
328 namespace AArch64DB {
345 struct DBarrierMapper : AArch64NamedImmMapper {
346 const static Mapping DBarrierPairs[];
352 namespace AArch64DC {
354 Invalid = -1, // Op1 CRn CRm Op2
355 ZVA = 0x5ba1, // 01 011 0111 0100 001
356 IVAC = 0x43b1, // 01 000 0111 0110 001
357 ISW = 0x43b2, // 01 000 0111 0110 010
358 CVAC = 0x5bd1, // 01 011 0111 1010 001
359 CSW = 0x43d2, // 01 000 0111 1010 010
360 CVAU = 0x5bd9, // 01 011 0111 1011 001
361 CIVAC = 0x5bf1, // 01 011 0111 1110 001
362 CISW = 0x43f2 // 01 000 0111 1110 010
365 struct DCMapper : AArch64NamedImmMapper {
366 const static Mapping DCPairs[];
373 namespace AArch64IC {
375 Invalid = -1, // Op1 CRn CRm Op2
376 IALLUIS = 0x0388, // 000 0111 0001 000
377 IALLU = 0x03a8, // 000 0111 0101 000
378 IVAU = 0x1ba9 // 011 0111 0101 001
382 struct ICMapper : AArch64NamedImmMapper {
383 const static Mapping ICPairs[];
388 static inline bool NeedsRegister(ICValues Val) {
393 namespace AArch64ISB {
398 struct ISBMapper : AArch64NamedImmMapper {
399 const static Mapping ISBPairs[];
405 namespace AArch64PRFM {
428 struct PRFMMapper : AArch64NamedImmMapper {
429 const static Mapping PRFMPairs[];
435 namespace AArch64PState {
443 struct PStateMapper : AArch64NamedImmMapper {
444 const static Mapping PStatePairs[];
451 namespace AArch64SE {
452 enum ShiftExtSpecifiers {
472 namespace AArch64Layout {
485 // Bare layout for the 128-bit vector
486 // (only show ".b", ".h", ".s", ".d" without vector number)
494 inline static const char *
495 AArch64VectorLayoutToString(AArch64Layout::VectorLayout Layout) {
497 case AArch64Layout::VL_8B: return ".8b";
498 case AArch64Layout::VL_4H: return ".4h";
499 case AArch64Layout::VL_2S: return ".2s";
500 case AArch64Layout::VL_1D: return ".1d";
501 case AArch64Layout::VL_16B: return ".16b";
502 case AArch64Layout::VL_8H: return ".8h";
503 case AArch64Layout::VL_4S: return ".4s";
504 case AArch64Layout::VL_2D: return ".2d";
505 case AArch64Layout::VL_B: return ".b";
506 case AArch64Layout::VL_H: return ".h";
507 case AArch64Layout::VL_S: return ".s";
508 case AArch64Layout::VL_D: return ".d";
509 default: llvm_unreachable("Unknown Vector Layout");
513 inline static AArch64Layout::VectorLayout
514 AArch64StringToVectorLayout(StringRef LayoutStr) {
515 return StringSwitch<AArch64Layout::VectorLayout>(LayoutStr)
516 .Case(".8b", AArch64Layout::VL_8B)
517 .Case(".4h", AArch64Layout::VL_4H)
518 .Case(".2s", AArch64Layout::VL_2S)
519 .Case(".1d", AArch64Layout::VL_1D)
520 .Case(".16b", AArch64Layout::VL_16B)
521 .Case(".8h", AArch64Layout::VL_8H)
522 .Case(".4s", AArch64Layout::VL_4S)
523 .Case(".2d", AArch64Layout::VL_2D)
524 .Case(".b", AArch64Layout::VL_B)
525 .Case(".h", AArch64Layout::VL_H)
526 .Case(".s", AArch64Layout::VL_S)
527 .Case(".d", AArch64Layout::VL_D)
528 .Default(AArch64Layout::Invalid);
531 namespace AArch64SysReg {
532 enum SysRegROValues {
533 MDCCSR_EL0 = 0x9808, // 10 011 0000 0001 000
534 DBGDTRRX_EL0 = 0x9828, // 10 011 0000 0101 000
535 MDRAR_EL1 = 0x8080, // 10 000 0001 0000 000
536 OSLSR_EL1 = 0x808c, // 10 000 0001 0001 100
537 DBGAUTHSTATUS_EL1 = 0x83f6, // 10 000 0111 1110 110
538 PMCEID0_EL0 = 0xdce6, // 11 011 1001 1100 110
539 PMCEID1_EL0 = 0xdce7, // 11 011 1001 1100 111
540 MIDR_EL1 = 0xc000, // 11 000 0000 0000 000
541 CCSIDR_EL1 = 0xc800, // 11 001 0000 0000 000
542 CLIDR_EL1 = 0xc801, // 11 001 0000 0000 001
543 CTR_EL0 = 0xd801, // 11 011 0000 0000 001
544 MPIDR_EL1 = 0xc005, // 11 000 0000 0000 101
545 REVIDR_EL1 = 0xc006, // 11 000 0000 0000 110
546 AIDR_EL1 = 0xc807, // 11 001 0000 0000 111
547 DCZID_EL0 = 0xd807, // 11 011 0000 0000 111
548 ID_PFR0_EL1 = 0xc008, // 11 000 0000 0001 000
549 ID_PFR1_EL1 = 0xc009, // 11 000 0000 0001 001
550 ID_DFR0_EL1 = 0xc00a, // 11 000 0000 0001 010
551 ID_AFR0_EL1 = 0xc00b, // 11 000 0000 0001 011
552 ID_MMFR0_EL1 = 0xc00c, // 11 000 0000 0001 100
553 ID_MMFR1_EL1 = 0xc00d, // 11 000 0000 0001 101
554 ID_MMFR2_EL1 = 0xc00e, // 11 000 0000 0001 110
555 ID_MMFR3_EL1 = 0xc00f, // 11 000 0000 0001 111
556 ID_ISAR0_EL1 = 0xc010, // 11 000 0000 0010 000
557 ID_ISAR1_EL1 = 0xc011, // 11 000 0000 0010 001
558 ID_ISAR2_EL1 = 0xc012, // 11 000 0000 0010 010
559 ID_ISAR3_EL1 = 0xc013, // 11 000 0000 0010 011
560 ID_ISAR4_EL1 = 0xc014, // 11 000 0000 0010 100
561 ID_ISAR5_EL1 = 0xc015, // 11 000 0000 0010 101
562 ID_A64PFR0_EL1 = 0xc020, // 11 000 0000 0100 000
563 ID_A64PFR1_EL1 = 0xc021, // 11 000 0000 0100 001
564 ID_A64DFR0_EL1 = 0xc028, // 11 000 0000 0101 000
565 ID_A64DFR1_EL1 = 0xc029, // 11 000 0000 0101 001
566 ID_A64AFR0_EL1 = 0xc02c, // 11 000 0000 0101 100
567 ID_A64AFR1_EL1 = 0xc02d, // 11 000 0000 0101 101
568 ID_A64ISAR0_EL1 = 0xc030, // 11 000 0000 0110 000
569 ID_A64ISAR1_EL1 = 0xc031, // 11 000 0000 0110 001
570 ID_A64MMFR0_EL1 = 0xc038, // 11 000 0000 0111 000
571 ID_A64MMFR1_EL1 = 0xc039, // 11 000 0000 0111 001
572 MVFR0_EL1 = 0xc018, // 11 000 0000 0011 000
573 MVFR1_EL1 = 0xc019, // 11 000 0000 0011 001
574 MVFR2_EL1 = 0xc01a, // 11 000 0000 0011 010
575 RVBAR_EL1 = 0xc601, // 11 000 1100 0000 001
576 RVBAR_EL2 = 0xe601, // 11 100 1100 0000 001
577 RVBAR_EL3 = 0xf601, // 11 110 1100 0000 001
578 ISR_EL1 = 0xc608, // 11 000 1100 0001 000
579 CNTPCT_EL0 = 0xdf01, // 11 011 1110 0000 001
580 CNTVCT_EL0 = 0xdf02, // 11 011 1110 0000 010
583 TRCSTATR = 0x8818, // 10 001 0000 0011 000
584 TRCIDR8 = 0x8806, // 10 001 0000 0000 110
585 TRCIDR9 = 0x880e, // 10 001 0000 0001 110
586 TRCIDR10 = 0x8816, // 10 001 0000 0010 110
587 TRCIDR11 = 0x881e, // 10 001 0000 0011 110
588 TRCIDR12 = 0x8826, // 10 001 0000 0100 110
589 TRCIDR13 = 0x882e, // 10 001 0000 0101 110
590 TRCIDR0 = 0x8847, // 10 001 0000 1000 111
591 TRCIDR1 = 0x884f, // 10 001 0000 1001 111
592 TRCIDR2 = 0x8857, // 10 001 0000 1010 111
593 TRCIDR3 = 0x885f, // 10 001 0000 1011 111
594 TRCIDR4 = 0x8867, // 10 001 0000 1100 111
595 TRCIDR5 = 0x886f, // 10 001 0000 1101 111
596 TRCIDR6 = 0x8877, // 10 001 0000 1110 111
597 TRCIDR7 = 0x887f, // 10 001 0000 1111 111
598 TRCOSLSR = 0x888c, // 10 001 0001 0001 100
599 TRCPDSR = 0x88ac, // 10 001 0001 0101 100
600 TRCDEVAFF0 = 0x8bd6, // 10 001 0111 1010 110
601 TRCDEVAFF1 = 0x8bde, // 10 001 0111 1011 110
602 TRCLSR = 0x8bee, // 10 001 0111 1101 110
603 TRCAUTHSTATUS = 0x8bf6, // 10 001 0111 1110 110
604 TRCDEVARCH = 0x8bfe, // 10 001 0111 1111 110
605 TRCDEVID = 0x8b97, // 10 001 0111 0010 111
606 TRCDEVTYPE = 0x8b9f, // 10 001 0111 0011 111
607 TRCPIDR4 = 0x8ba7, // 10 001 0111 0100 111
608 TRCPIDR5 = 0x8baf, // 10 001 0111 0101 111
609 TRCPIDR6 = 0x8bb7, // 10 001 0111 0110 111
610 TRCPIDR7 = 0x8bbf, // 10 001 0111 0111 111
611 TRCPIDR0 = 0x8bc7, // 10 001 0111 1000 111
612 TRCPIDR1 = 0x8bcf, // 10 001 0111 1001 111
613 TRCPIDR2 = 0x8bd7, // 10 001 0111 1010 111
614 TRCPIDR3 = 0x8bdf, // 10 001 0111 1011 111
615 TRCCIDR0 = 0x8be7, // 10 001 0111 1100 111
616 TRCCIDR1 = 0x8bef, // 10 001 0111 1101 111
617 TRCCIDR2 = 0x8bf7, // 10 001 0111 1110 111
618 TRCCIDR3 = 0x8bff, // 10 001 0111 1111 111
621 ICC_IAR1_EL1 = 0xc660, // 11 000 1100 1100 000
622 ICC_IAR0_EL1 = 0xc640, // 11 000 1100 1000 000
623 ICC_HPPIR1_EL1 = 0xc662, // 11 000 1100 1100 010
624 ICC_HPPIR0_EL1 = 0xc642, // 11 000 1100 1000 010
625 ICC_RPR_EL1 = 0xc65b, // 11 000 1100 1011 011
626 ICH_VTR_EL2 = 0xe659, // 11 100 1100 1011 001
627 ICH_EISR_EL2 = 0xe65b, // 11 100 1100 1011 011
628 ICH_ELSR_EL2 = 0xe65d // 11 100 1100 1011 101
631 enum SysRegWOValues {
632 DBGDTRTX_EL0 = 0x9828, // 10 011 0000 0101 000
633 OSLAR_EL1 = 0x8084, // 10 000 0001 0000 100
634 PMSWINC_EL0 = 0xdce4, // 11 011 1001 1100 100
637 TRCOSLAR = 0x8884, // 10 001 0001 0000 100
638 TRCLAR = 0x8be6, // 10 001 0111 1100 110
641 ICC_EOIR1_EL1 = 0xc661, // 11 000 1100 1100 001
642 ICC_EOIR0_EL1 = 0xc641, // 11 000 1100 1000 001
643 ICC_DIR_EL1 = 0xc659, // 11 000 1100 1011 001
644 ICC_SGI1R_EL1 = 0xc65d, // 11 000 1100 1011 101
645 ICC_ASGI1R_EL1 = 0xc65e, // 11 000 1100 1011 110
646 ICC_SGI0R_EL1 = 0xc65f // 11 000 1100 1011 111
650 Invalid = -1, // Op0 Op1 CRn CRm Op2
651 OSDTRRX_EL1 = 0x8002, // 10 000 0000 0000 010
652 OSDTRTX_EL1 = 0x801a, // 10 000 0000 0011 010
653 TEECR32_EL1 = 0x9000, // 10 010 0000 0000 000
654 MDCCINT_EL1 = 0x8010, // 10 000 0000 0010 000
655 MDSCR_EL1 = 0x8012, // 10 000 0000 0010 010
656 DBGDTR_EL0 = 0x9820, // 10 011 0000 0100 000
657 OSECCR_EL1 = 0x8032, // 10 000 0000 0110 010
658 DBGVCR32_EL2 = 0xa038, // 10 100 0000 0111 000
659 DBGBVR0_EL1 = 0x8004, // 10 000 0000 0000 100
660 DBGBVR1_EL1 = 0x800c, // 10 000 0000 0001 100
661 DBGBVR2_EL1 = 0x8014, // 10 000 0000 0010 100
662 DBGBVR3_EL1 = 0x801c, // 10 000 0000 0011 100
663 DBGBVR4_EL1 = 0x8024, // 10 000 0000 0100 100
664 DBGBVR5_EL1 = 0x802c, // 10 000 0000 0101 100
665 DBGBVR6_EL1 = 0x8034, // 10 000 0000 0110 100
666 DBGBVR7_EL1 = 0x803c, // 10 000 0000 0111 100
667 DBGBVR8_EL1 = 0x8044, // 10 000 0000 1000 100
668 DBGBVR9_EL1 = 0x804c, // 10 000 0000 1001 100
669 DBGBVR10_EL1 = 0x8054, // 10 000 0000 1010 100
670 DBGBVR11_EL1 = 0x805c, // 10 000 0000 1011 100
671 DBGBVR12_EL1 = 0x8064, // 10 000 0000 1100 100
672 DBGBVR13_EL1 = 0x806c, // 10 000 0000 1101 100
673 DBGBVR14_EL1 = 0x8074, // 10 000 0000 1110 100
674 DBGBVR15_EL1 = 0x807c, // 10 000 0000 1111 100
675 DBGBCR0_EL1 = 0x8005, // 10 000 0000 0000 101
676 DBGBCR1_EL1 = 0x800d, // 10 000 0000 0001 101
677 DBGBCR2_EL1 = 0x8015, // 10 000 0000 0010 101
678 DBGBCR3_EL1 = 0x801d, // 10 000 0000 0011 101
679 DBGBCR4_EL1 = 0x8025, // 10 000 0000 0100 101
680 DBGBCR5_EL1 = 0x802d, // 10 000 0000 0101 101
681 DBGBCR6_EL1 = 0x8035, // 10 000 0000 0110 101
682 DBGBCR7_EL1 = 0x803d, // 10 000 0000 0111 101
683 DBGBCR8_EL1 = 0x8045, // 10 000 0000 1000 101
684 DBGBCR9_EL1 = 0x804d, // 10 000 0000 1001 101
685 DBGBCR10_EL1 = 0x8055, // 10 000 0000 1010 101
686 DBGBCR11_EL1 = 0x805d, // 10 000 0000 1011 101
687 DBGBCR12_EL1 = 0x8065, // 10 000 0000 1100 101
688 DBGBCR13_EL1 = 0x806d, // 10 000 0000 1101 101
689 DBGBCR14_EL1 = 0x8075, // 10 000 0000 1110 101
690 DBGBCR15_EL1 = 0x807d, // 10 000 0000 1111 101
691 DBGWVR0_EL1 = 0x8006, // 10 000 0000 0000 110
692 DBGWVR1_EL1 = 0x800e, // 10 000 0000 0001 110
693 DBGWVR2_EL1 = 0x8016, // 10 000 0000 0010 110
694 DBGWVR3_EL1 = 0x801e, // 10 000 0000 0011 110
695 DBGWVR4_EL1 = 0x8026, // 10 000 0000 0100 110
696 DBGWVR5_EL1 = 0x802e, // 10 000 0000 0101 110
697 DBGWVR6_EL1 = 0x8036, // 10 000 0000 0110 110
698 DBGWVR7_EL1 = 0x803e, // 10 000 0000 0111 110
699 DBGWVR8_EL1 = 0x8046, // 10 000 0000 1000 110
700 DBGWVR9_EL1 = 0x804e, // 10 000 0000 1001 110
701 DBGWVR10_EL1 = 0x8056, // 10 000 0000 1010 110
702 DBGWVR11_EL1 = 0x805e, // 10 000 0000 1011 110
703 DBGWVR12_EL1 = 0x8066, // 10 000 0000 1100 110
704 DBGWVR13_EL1 = 0x806e, // 10 000 0000 1101 110
705 DBGWVR14_EL1 = 0x8076, // 10 000 0000 1110 110
706 DBGWVR15_EL1 = 0x807e, // 10 000 0000 1111 110
707 DBGWCR0_EL1 = 0x8007, // 10 000 0000 0000 111
708 DBGWCR1_EL1 = 0x800f, // 10 000 0000 0001 111
709 DBGWCR2_EL1 = 0x8017, // 10 000 0000 0010 111
710 DBGWCR3_EL1 = 0x801f, // 10 000 0000 0011 111
711 DBGWCR4_EL1 = 0x8027, // 10 000 0000 0100 111
712 DBGWCR5_EL1 = 0x802f, // 10 000 0000 0101 111
713 DBGWCR6_EL1 = 0x8037, // 10 000 0000 0110 111
714 DBGWCR7_EL1 = 0x803f, // 10 000 0000 0111 111
715 DBGWCR8_EL1 = 0x8047, // 10 000 0000 1000 111
716 DBGWCR9_EL1 = 0x804f, // 10 000 0000 1001 111
717 DBGWCR10_EL1 = 0x8057, // 10 000 0000 1010 111
718 DBGWCR11_EL1 = 0x805f, // 10 000 0000 1011 111
719 DBGWCR12_EL1 = 0x8067, // 10 000 0000 1100 111
720 DBGWCR13_EL1 = 0x806f, // 10 000 0000 1101 111
721 DBGWCR14_EL1 = 0x8077, // 10 000 0000 1110 111
722 DBGWCR15_EL1 = 0x807f, // 10 000 0000 1111 111
723 TEEHBR32_EL1 = 0x9080, // 10 010 0001 0000 000
724 OSDLR_EL1 = 0x809c, // 10 000 0001 0011 100
725 DBGPRCR_EL1 = 0x80a4, // 10 000 0001 0100 100
726 DBGCLAIMSET_EL1 = 0x83c6, // 10 000 0111 1000 110
727 DBGCLAIMCLR_EL1 = 0x83ce, // 10 000 0111 1001 110
728 CSSELR_EL1 = 0xd000, // 11 010 0000 0000 000
729 VPIDR_EL2 = 0xe000, // 11 100 0000 0000 000
730 VMPIDR_EL2 = 0xe005, // 11 100 0000 0000 101
731 CPACR_EL1 = 0xc082, // 11 000 0001 0000 010
732 SCTLR_EL1 = 0xc080, // 11 000 0001 0000 000
733 SCTLR_EL2 = 0xe080, // 11 100 0001 0000 000
734 SCTLR_EL3 = 0xf080, // 11 110 0001 0000 000
735 ACTLR_EL1 = 0xc081, // 11 000 0001 0000 001
736 ACTLR_EL2 = 0xe081, // 11 100 0001 0000 001
737 ACTLR_EL3 = 0xf081, // 11 110 0001 0000 001
738 HCR_EL2 = 0xe088, // 11 100 0001 0001 000
739 SCR_EL3 = 0xf088, // 11 110 0001 0001 000
740 MDCR_EL2 = 0xe089, // 11 100 0001 0001 001
741 SDER32_EL3 = 0xf089, // 11 110 0001 0001 001
742 CPTR_EL2 = 0xe08a, // 11 100 0001 0001 010
743 CPTR_EL3 = 0xf08a, // 11 110 0001 0001 010
744 HSTR_EL2 = 0xe08b, // 11 100 0001 0001 011
745 HACR_EL2 = 0xe08f, // 11 100 0001 0001 111
746 MDCR_EL3 = 0xf099, // 11 110 0001 0011 001
747 TTBR0_EL1 = 0xc100, // 11 000 0010 0000 000
748 TTBR0_EL2 = 0xe100, // 11 100 0010 0000 000
749 TTBR0_EL3 = 0xf100, // 11 110 0010 0000 000
750 TTBR1_EL1 = 0xc101, // 11 000 0010 0000 001
751 TCR_EL1 = 0xc102, // 11 000 0010 0000 010
752 TCR_EL2 = 0xe102, // 11 100 0010 0000 010
753 TCR_EL3 = 0xf102, // 11 110 0010 0000 010
754 VTTBR_EL2 = 0xe108, // 11 100 0010 0001 000
755 VTCR_EL2 = 0xe10a, // 11 100 0010 0001 010
756 DACR32_EL2 = 0xe180, // 11 100 0011 0000 000
757 SPSR_EL1 = 0xc200, // 11 000 0100 0000 000
758 SPSR_EL2 = 0xe200, // 11 100 0100 0000 000
759 SPSR_EL3 = 0xf200, // 11 110 0100 0000 000
760 ELR_EL1 = 0xc201, // 11 000 0100 0000 001
761 ELR_EL2 = 0xe201, // 11 100 0100 0000 001
762 ELR_EL3 = 0xf201, // 11 110 0100 0000 001
763 SP_EL0 = 0xc208, // 11 000 0100 0001 000
764 SP_EL1 = 0xe208, // 11 100 0100 0001 000
765 SP_EL2 = 0xf208, // 11 110 0100 0001 000
766 SPSel = 0xc210, // 11 000 0100 0010 000
767 NZCV = 0xda10, // 11 011 0100 0010 000
768 DAIF = 0xda11, // 11 011 0100 0010 001
769 CurrentEL = 0xc212, // 11 000 0100 0010 010
770 SPSR_irq = 0xe218, // 11 100 0100 0011 000
771 SPSR_abt = 0xe219, // 11 100 0100 0011 001
772 SPSR_und = 0xe21a, // 11 100 0100 0011 010
773 SPSR_fiq = 0xe21b, // 11 100 0100 0011 011
774 FPCR = 0xda20, // 11 011 0100 0100 000
775 FPSR = 0xda21, // 11 011 0100 0100 001
776 DSPSR_EL0 = 0xda28, // 11 011 0100 0101 000
777 DLR_EL0 = 0xda29, // 11 011 0100 0101 001
778 IFSR32_EL2 = 0xe281, // 11 100 0101 0000 001
779 AFSR0_EL1 = 0xc288, // 11 000 0101 0001 000
780 AFSR0_EL2 = 0xe288, // 11 100 0101 0001 000
781 AFSR0_EL3 = 0xf288, // 11 110 0101 0001 000
782 AFSR1_EL1 = 0xc289, // 11 000 0101 0001 001
783 AFSR1_EL2 = 0xe289, // 11 100 0101 0001 001
784 AFSR1_EL3 = 0xf289, // 11 110 0101 0001 001
785 ESR_EL1 = 0xc290, // 11 000 0101 0010 000
786 ESR_EL2 = 0xe290, // 11 100 0101 0010 000
787 ESR_EL3 = 0xf290, // 11 110 0101 0010 000
788 FPEXC32_EL2 = 0xe298, // 11 100 0101 0011 000
789 FAR_EL1 = 0xc300, // 11 000 0110 0000 000
790 FAR_EL2 = 0xe300, // 11 100 0110 0000 000
791 FAR_EL3 = 0xf300, // 11 110 0110 0000 000
792 HPFAR_EL2 = 0xe304, // 11 100 0110 0000 100
793 PAR_EL1 = 0xc3a0, // 11 000 0111 0100 000
794 PMCR_EL0 = 0xdce0, // 11 011 1001 1100 000
795 PMCNTENSET_EL0 = 0xdce1, // 11 011 1001 1100 001
796 PMCNTENCLR_EL0 = 0xdce2, // 11 011 1001 1100 010
797 PMOVSCLR_EL0 = 0xdce3, // 11 011 1001 1100 011
798 PMSELR_EL0 = 0xdce5, // 11 011 1001 1100 101
799 PMCCNTR_EL0 = 0xdce8, // 11 011 1001 1101 000
800 PMXEVTYPER_EL0 = 0xdce9, // 11 011 1001 1101 001
801 PMXEVCNTR_EL0 = 0xdcea, // 11 011 1001 1101 010
802 PMUSERENR_EL0 = 0xdcf0, // 11 011 1001 1110 000
803 PMINTENSET_EL1 = 0xc4f1, // 11 000 1001 1110 001
804 PMINTENCLR_EL1 = 0xc4f2, // 11 000 1001 1110 010
805 PMOVSSET_EL0 = 0xdcf3, // 11 011 1001 1110 011
806 MAIR_EL1 = 0xc510, // 11 000 1010 0010 000
807 MAIR_EL2 = 0xe510, // 11 100 1010 0010 000
808 MAIR_EL3 = 0xf510, // 11 110 1010 0010 000
809 AMAIR_EL1 = 0xc518, // 11 000 1010 0011 000
810 AMAIR_EL2 = 0xe518, // 11 100 1010 0011 000
811 AMAIR_EL3 = 0xf518, // 11 110 1010 0011 000
812 VBAR_EL1 = 0xc600, // 11 000 1100 0000 000
813 VBAR_EL2 = 0xe600, // 11 100 1100 0000 000
814 VBAR_EL3 = 0xf600, // 11 110 1100 0000 000
815 RMR_EL1 = 0xc602, // 11 000 1100 0000 010
816 RMR_EL2 = 0xe602, // 11 100 1100 0000 010
817 RMR_EL3 = 0xf602, // 11 110 1100 0000 010
818 CONTEXTIDR_EL1 = 0xc681, // 11 000 1101 0000 001
819 TPIDR_EL0 = 0xde82, // 11 011 1101 0000 010
820 TPIDR_EL2 = 0xe682, // 11 100 1101 0000 010
821 TPIDR_EL3 = 0xf682, // 11 110 1101 0000 010
822 TPIDRRO_EL0 = 0xde83, // 11 011 1101 0000 011
823 TPIDR_EL1 = 0xc684, // 11 000 1101 0000 100
824 CNTFRQ_EL0 = 0xdf00, // 11 011 1110 0000 000
825 CNTVOFF_EL2 = 0xe703, // 11 100 1110 0000 011
826 CNTKCTL_EL1 = 0xc708, // 11 000 1110 0001 000
827 CNTHCTL_EL2 = 0xe708, // 11 100 1110 0001 000
828 CNTP_TVAL_EL0 = 0xdf10, // 11 011 1110 0010 000
829 CNTHP_TVAL_EL2 = 0xe710, // 11 100 1110 0010 000
830 CNTPS_TVAL_EL1 = 0xff10, // 11 111 1110 0010 000
831 CNTP_CTL_EL0 = 0xdf11, // 11 011 1110 0010 001
832 CNTHP_CTL_EL2 = 0xe711, // 11 100 1110 0010 001
833 CNTPS_CTL_EL1 = 0xff11, // 11 111 1110 0010 001
834 CNTP_CVAL_EL0 = 0xdf12, // 11 011 1110 0010 010
835 CNTHP_CVAL_EL2 = 0xe712, // 11 100 1110 0010 010
836 CNTPS_CVAL_EL1 = 0xff12, // 11 111 1110 0010 010
837 CNTV_TVAL_EL0 = 0xdf18, // 11 011 1110 0011 000
838 CNTV_CTL_EL0 = 0xdf19, // 11 011 1110 0011 001
839 CNTV_CVAL_EL0 = 0xdf1a, // 11 011 1110 0011 010
840 PMEVCNTR0_EL0 = 0xdf40, // 11 011 1110 1000 000
841 PMEVCNTR1_EL0 = 0xdf41, // 11 011 1110 1000 001
842 PMEVCNTR2_EL0 = 0xdf42, // 11 011 1110 1000 010
843 PMEVCNTR3_EL0 = 0xdf43, // 11 011 1110 1000 011
844 PMEVCNTR4_EL0 = 0xdf44, // 11 011 1110 1000 100
845 PMEVCNTR5_EL0 = 0xdf45, // 11 011 1110 1000 101
846 PMEVCNTR6_EL0 = 0xdf46, // 11 011 1110 1000 110
847 PMEVCNTR7_EL0 = 0xdf47, // 11 011 1110 1000 111
848 PMEVCNTR8_EL0 = 0xdf48, // 11 011 1110 1001 000
849 PMEVCNTR9_EL0 = 0xdf49, // 11 011 1110 1001 001
850 PMEVCNTR10_EL0 = 0xdf4a, // 11 011 1110 1001 010
851 PMEVCNTR11_EL0 = 0xdf4b, // 11 011 1110 1001 011
852 PMEVCNTR12_EL0 = 0xdf4c, // 11 011 1110 1001 100
853 PMEVCNTR13_EL0 = 0xdf4d, // 11 011 1110 1001 101
854 PMEVCNTR14_EL0 = 0xdf4e, // 11 011 1110 1001 110
855 PMEVCNTR15_EL0 = 0xdf4f, // 11 011 1110 1001 111
856 PMEVCNTR16_EL0 = 0xdf50, // 11 011 1110 1010 000
857 PMEVCNTR17_EL0 = 0xdf51, // 11 011 1110 1010 001
858 PMEVCNTR18_EL0 = 0xdf52, // 11 011 1110 1010 010
859 PMEVCNTR19_EL0 = 0xdf53, // 11 011 1110 1010 011
860 PMEVCNTR20_EL0 = 0xdf54, // 11 011 1110 1010 100
861 PMEVCNTR21_EL0 = 0xdf55, // 11 011 1110 1010 101
862 PMEVCNTR22_EL0 = 0xdf56, // 11 011 1110 1010 110
863 PMEVCNTR23_EL0 = 0xdf57, // 11 011 1110 1010 111
864 PMEVCNTR24_EL0 = 0xdf58, // 11 011 1110 1011 000
865 PMEVCNTR25_EL0 = 0xdf59, // 11 011 1110 1011 001
866 PMEVCNTR26_EL0 = 0xdf5a, // 11 011 1110 1011 010
867 PMEVCNTR27_EL0 = 0xdf5b, // 11 011 1110 1011 011
868 PMEVCNTR28_EL0 = 0xdf5c, // 11 011 1110 1011 100
869 PMEVCNTR29_EL0 = 0xdf5d, // 11 011 1110 1011 101
870 PMEVCNTR30_EL0 = 0xdf5e, // 11 011 1110 1011 110
871 PMCCFILTR_EL0 = 0xdf7f, // 11 011 1110 1111 111
872 PMEVTYPER0_EL0 = 0xdf60, // 11 011 1110 1100 000
873 PMEVTYPER1_EL0 = 0xdf61, // 11 011 1110 1100 001
874 PMEVTYPER2_EL0 = 0xdf62, // 11 011 1110 1100 010
875 PMEVTYPER3_EL0 = 0xdf63, // 11 011 1110 1100 011
876 PMEVTYPER4_EL0 = 0xdf64, // 11 011 1110 1100 100
877 PMEVTYPER5_EL0 = 0xdf65, // 11 011 1110 1100 101
878 PMEVTYPER6_EL0 = 0xdf66, // 11 011 1110 1100 110
879 PMEVTYPER7_EL0 = 0xdf67, // 11 011 1110 1100 111
880 PMEVTYPER8_EL0 = 0xdf68, // 11 011 1110 1101 000
881 PMEVTYPER9_EL0 = 0xdf69, // 11 011 1110 1101 001
882 PMEVTYPER10_EL0 = 0xdf6a, // 11 011 1110 1101 010
883 PMEVTYPER11_EL0 = 0xdf6b, // 11 011 1110 1101 011
884 PMEVTYPER12_EL0 = 0xdf6c, // 11 011 1110 1101 100
885 PMEVTYPER13_EL0 = 0xdf6d, // 11 011 1110 1101 101
886 PMEVTYPER14_EL0 = 0xdf6e, // 11 011 1110 1101 110
887 PMEVTYPER15_EL0 = 0xdf6f, // 11 011 1110 1101 111
888 PMEVTYPER16_EL0 = 0xdf70, // 11 011 1110 1110 000
889 PMEVTYPER17_EL0 = 0xdf71, // 11 011 1110 1110 001
890 PMEVTYPER18_EL0 = 0xdf72, // 11 011 1110 1110 010
891 PMEVTYPER19_EL0 = 0xdf73, // 11 011 1110 1110 011
892 PMEVTYPER20_EL0 = 0xdf74, // 11 011 1110 1110 100
893 PMEVTYPER21_EL0 = 0xdf75, // 11 011 1110 1110 101
894 PMEVTYPER22_EL0 = 0xdf76, // 11 011 1110 1110 110
895 PMEVTYPER23_EL0 = 0xdf77, // 11 011 1110 1110 111
896 PMEVTYPER24_EL0 = 0xdf78, // 11 011 1110 1111 000
897 PMEVTYPER25_EL0 = 0xdf79, // 11 011 1110 1111 001
898 PMEVTYPER26_EL0 = 0xdf7a, // 11 011 1110 1111 010
899 PMEVTYPER27_EL0 = 0xdf7b, // 11 011 1110 1111 011
900 PMEVTYPER28_EL0 = 0xdf7c, // 11 011 1110 1111 100
901 PMEVTYPER29_EL0 = 0xdf7d, // 11 011 1110 1111 101
902 PMEVTYPER30_EL0 = 0xdf7e, // 11 011 1110 1111 110
905 TRCPRGCTLR = 0x8808, // 10 001 0000 0001 000
906 TRCPROCSELR = 0x8810, // 10 001 0000 0010 000
907 TRCCONFIGR = 0x8820, // 10 001 0000 0100 000
908 TRCAUXCTLR = 0x8830, // 10 001 0000 0110 000
909 TRCEVENTCTL0R = 0x8840, // 10 001 0000 1000 000
910 TRCEVENTCTL1R = 0x8848, // 10 001 0000 1001 000
911 TRCSTALLCTLR = 0x8858, // 10 001 0000 1011 000
912 TRCTSCTLR = 0x8860, // 10 001 0000 1100 000
913 TRCSYNCPR = 0x8868, // 10 001 0000 1101 000
914 TRCCCCTLR = 0x8870, // 10 001 0000 1110 000
915 TRCBBCTLR = 0x8878, // 10 001 0000 1111 000
916 TRCTRACEIDR = 0x8801, // 10 001 0000 0000 001
917 TRCQCTLR = 0x8809, // 10 001 0000 0001 001
918 TRCVICTLR = 0x8802, // 10 001 0000 0000 010
919 TRCVIIECTLR = 0x880a, // 10 001 0000 0001 010
920 TRCVISSCTLR = 0x8812, // 10 001 0000 0010 010
921 TRCVIPCSSCTLR = 0x881a, // 10 001 0000 0011 010
922 TRCVDCTLR = 0x8842, // 10 001 0000 1000 010
923 TRCVDSACCTLR = 0x884a, // 10 001 0000 1001 010
924 TRCVDARCCTLR = 0x8852, // 10 001 0000 1010 010
925 TRCSEQEVR0 = 0x8804, // 10 001 0000 0000 100
926 TRCSEQEVR1 = 0x880c, // 10 001 0000 0001 100
927 TRCSEQEVR2 = 0x8814, // 10 001 0000 0010 100
928 TRCSEQRSTEVR = 0x8834, // 10 001 0000 0110 100
929 TRCSEQSTR = 0x883c, // 10 001 0000 0111 100
930 TRCEXTINSELR = 0x8844, // 10 001 0000 1000 100
931 TRCCNTRLDVR0 = 0x8805, // 10 001 0000 0000 101
932 TRCCNTRLDVR1 = 0x880d, // 10 001 0000 0001 101
933 TRCCNTRLDVR2 = 0x8815, // 10 001 0000 0010 101
934 TRCCNTRLDVR3 = 0x881d, // 10 001 0000 0011 101
935 TRCCNTCTLR0 = 0x8825, // 10 001 0000 0100 101
936 TRCCNTCTLR1 = 0x882d, // 10 001 0000 0101 101
937 TRCCNTCTLR2 = 0x8835, // 10 001 0000 0110 101
938 TRCCNTCTLR3 = 0x883d, // 10 001 0000 0111 101
939 TRCCNTVR0 = 0x8845, // 10 001 0000 1000 101
940 TRCCNTVR1 = 0x884d, // 10 001 0000 1001 101
941 TRCCNTVR2 = 0x8855, // 10 001 0000 1010 101
942 TRCCNTVR3 = 0x885d, // 10 001 0000 1011 101
943 TRCIMSPEC0 = 0x8807, // 10 001 0000 0000 111
944 TRCIMSPEC1 = 0x880f, // 10 001 0000 0001 111
945 TRCIMSPEC2 = 0x8817, // 10 001 0000 0010 111
946 TRCIMSPEC3 = 0x881f, // 10 001 0000 0011 111
947 TRCIMSPEC4 = 0x8827, // 10 001 0000 0100 111
948 TRCIMSPEC5 = 0x882f, // 10 001 0000 0101 111
949 TRCIMSPEC6 = 0x8837, // 10 001 0000 0110 111
950 TRCIMSPEC7 = 0x883f, // 10 001 0000 0111 111
951 TRCRSCTLR2 = 0x8890, // 10 001 0001 0010 000
952 TRCRSCTLR3 = 0x8898, // 10 001 0001 0011 000
953 TRCRSCTLR4 = 0x88a0, // 10 001 0001 0100 000
954 TRCRSCTLR5 = 0x88a8, // 10 001 0001 0101 000
955 TRCRSCTLR6 = 0x88b0, // 10 001 0001 0110 000
956 TRCRSCTLR7 = 0x88b8, // 10 001 0001 0111 000
957 TRCRSCTLR8 = 0x88c0, // 10 001 0001 1000 000
958 TRCRSCTLR9 = 0x88c8, // 10 001 0001 1001 000
959 TRCRSCTLR10 = 0x88d0, // 10 001 0001 1010 000
960 TRCRSCTLR11 = 0x88d8, // 10 001 0001 1011 000
961 TRCRSCTLR12 = 0x88e0, // 10 001 0001 1100 000
962 TRCRSCTLR13 = 0x88e8, // 10 001 0001 1101 000
963 TRCRSCTLR14 = 0x88f0, // 10 001 0001 1110 000
964 TRCRSCTLR15 = 0x88f8, // 10 001 0001 1111 000
965 TRCRSCTLR16 = 0x8881, // 10 001 0001 0000 001
966 TRCRSCTLR17 = 0x8889, // 10 001 0001 0001 001
967 TRCRSCTLR18 = 0x8891, // 10 001 0001 0010 001
968 TRCRSCTLR19 = 0x8899, // 10 001 0001 0011 001
969 TRCRSCTLR20 = 0x88a1, // 10 001 0001 0100 001
970 TRCRSCTLR21 = 0x88a9, // 10 001 0001 0101 001
971 TRCRSCTLR22 = 0x88b1, // 10 001 0001 0110 001
972 TRCRSCTLR23 = 0x88b9, // 10 001 0001 0111 001
973 TRCRSCTLR24 = 0x88c1, // 10 001 0001 1000 001
974 TRCRSCTLR25 = 0x88c9, // 10 001 0001 1001 001
975 TRCRSCTLR26 = 0x88d1, // 10 001 0001 1010 001
976 TRCRSCTLR27 = 0x88d9, // 10 001 0001 1011 001
977 TRCRSCTLR28 = 0x88e1, // 10 001 0001 1100 001
978 TRCRSCTLR29 = 0x88e9, // 10 001 0001 1101 001
979 TRCRSCTLR30 = 0x88f1, // 10 001 0001 1110 001
980 TRCRSCTLR31 = 0x88f9, // 10 001 0001 1111 001
981 TRCSSCCR0 = 0x8882, // 10 001 0001 0000 010
982 TRCSSCCR1 = 0x888a, // 10 001 0001 0001 010
983 TRCSSCCR2 = 0x8892, // 10 001 0001 0010 010
984 TRCSSCCR3 = 0x889a, // 10 001 0001 0011 010
985 TRCSSCCR4 = 0x88a2, // 10 001 0001 0100 010
986 TRCSSCCR5 = 0x88aa, // 10 001 0001 0101 010
987 TRCSSCCR6 = 0x88b2, // 10 001 0001 0110 010
988 TRCSSCCR7 = 0x88ba, // 10 001 0001 0111 010
989 TRCSSCSR0 = 0x88c2, // 10 001 0001 1000 010
990 TRCSSCSR1 = 0x88ca, // 10 001 0001 1001 010
991 TRCSSCSR2 = 0x88d2, // 10 001 0001 1010 010
992 TRCSSCSR3 = 0x88da, // 10 001 0001 1011 010
993 TRCSSCSR4 = 0x88e2, // 10 001 0001 1100 010
994 TRCSSCSR5 = 0x88ea, // 10 001 0001 1101 010
995 TRCSSCSR6 = 0x88f2, // 10 001 0001 1110 010
996 TRCSSCSR7 = 0x88fa, // 10 001 0001 1111 010
997 TRCSSPCICR0 = 0x8883, // 10 001 0001 0000 011
998 TRCSSPCICR1 = 0x888b, // 10 001 0001 0001 011
999 TRCSSPCICR2 = 0x8893, // 10 001 0001 0010 011
1000 TRCSSPCICR3 = 0x889b, // 10 001 0001 0011 011
1001 TRCSSPCICR4 = 0x88a3, // 10 001 0001 0100 011
1002 TRCSSPCICR5 = 0x88ab, // 10 001 0001 0101 011
1003 TRCSSPCICR6 = 0x88b3, // 10 001 0001 0110 011
1004 TRCSSPCICR7 = 0x88bb, // 10 001 0001 0111 011
1005 TRCPDCR = 0x88a4, // 10 001 0001 0100 100
1006 TRCACVR0 = 0x8900, // 10 001 0010 0000 000
1007 TRCACVR1 = 0x8910, // 10 001 0010 0010 000
1008 TRCACVR2 = 0x8920, // 10 001 0010 0100 000
1009 TRCACVR3 = 0x8930, // 10 001 0010 0110 000
1010 TRCACVR4 = 0x8940, // 10 001 0010 1000 000
1011 TRCACVR5 = 0x8950, // 10 001 0010 1010 000
1012 TRCACVR6 = 0x8960, // 10 001 0010 1100 000
1013 TRCACVR7 = 0x8970, // 10 001 0010 1110 000
1014 TRCACVR8 = 0x8901, // 10 001 0010 0000 001
1015 TRCACVR9 = 0x8911, // 10 001 0010 0010 001
1016 TRCACVR10 = 0x8921, // 10 001 0010 0100 001
1017 TRCACVR11 = 0x8931, // 10 001 0010 0110 001
1018 TRCACVR12 = 0x8941, // 10 001 0010 1000 001
1019 TRCACVR13 = 0x8951, // 10 001 0010 1010 001
1020 TRCACVR14 = 0x8961, // 10 001 0010 1100 001
1021 TRCACVR15 = 0x8971, // 10 001 0010 1110 001
1022 TRCACATR0 = 0x8902, // 10 001 0010 0000 010
1023 TRCACATR1 = 0x8912, // 10 001 0010 0010 010
1024 TRCACATR2 = 0x8922, // 10 001 0010 0100 010
1025 TRCACATR3 = 0x8932, // 10 001 0010 0110 010
1026 TRCACATR4 = 0x8942, // 10 001 0010 1000 010
1027 TRCACATR5 = 0x8952, // 10 001 0010 1010 010
1028 TRCACATR6 = 0x8962, // 10 001 0010 1100 010
1029 TRCACATR7 = 0x8972, // 10 001 0010 1110 010
1030 TRCACATR8 = 0x8903, // 10 001 0010 0000 011
1031 TRCACATR9 = 0x8913, // 10 001 0010 0010 011
1032 TRCACATR10 = 0x8923, // 10 001 0010 0100 011
1033 TRCACATR11 = 0x8933, // 10 001 0010 0110 011
1034 TRCACATR12 = 0x8943, // 10 001 0010 1000 011
1035 TRCACATR13 = 0x8953, // 10 001 0010 1010 011
1036 TRCACATR14 = 0x8963, // 10 001 0010 1100 011
1037 TRCACATR15 = 0x8973, // 10 001 0010 1110 011
1038 TRCDVCVR0 = 0x8904, // 10 001 0010 0000 100
1039 TRCDVCVR1 = 0x8924, // 10 001 0010 0100 100
1040 TRCDVCVR2 = 0x8944, // 10 001 0010 1000 100
1041 TRCDVCVR3 = 0x8964, // 10 001 0010 1100 100
1042 TRCDVCVR4 = 0x8905, // 10 001 0010 0000 101
1043 TRCDVCVR5 = 0x8925, // 10 001 0010 0100 101
1044 TRCDVCVR6 = 0x8945, // 10 001 0010 1000 101
1045 TRCDVCVR7 = 0x8965, // 10 001 0010 1100 101
1046 TRCDVCMR0 = 0x8906, // 10 001 0010 0000 110
1047 TRCDVCMR1 = 0x8926, // 10 001 0010 0100 110
1048 TRCDVCMR2 = 0x8946, // 10 001 0010 1000 110
1049 TRCDVCMR3 = 0x8966, // 10 001 0010 1100 110
1050 TRCDVCMR4 = 0x8907, // 10 001 0010 0000 111
1051 TRCDVCMR5 = 0x8927, // 10 001 0010 0100 111
1052 TRCDVCMR6 = 0x8947, // 10 001 0010 1000 111
1053 TRCDVCMR7 = 0x8967, // 10 001 0010 1100 111
1054 TRCCIDCVR0 = 0x8980, // 10 001 0011 0000 000
1055 TRCCIDCVR1 = 0x8990, // 10 001 0011 0010 000
1056 TRCCIDCVR2 = 0x89a0, // 10 001 0011 0100 000
1057 TRCCIDCVR3 = 0x89b0, // 10 001 0011 0110 000
1058 TRCCIDCVR4 = 0x89c0, // 10 001 0011 1000 000
1059 TRCCIDCVR5 = 0x89d0, // 10 001 0011 1010 000
1060 TRCCIDCVR6 = 0x89e0, // 10 001 0011 1100 000
1061 TRCCIDCVR7 = 0x89f0, // 10 001 0011 1110 000
1062 TRCVMIDCVR0 = 0x8981, // 10 001 0011 0000 001
1063 TRCVMIDCVR1 = 0x8991, // 10 001 0011 0010 001
1064 TRCVMIDCVR2 = 0x89a1, // 10 001 0011 0100 001
1065 TRCVMIDCVR3 = 0x89b1, // 10 001 0011 0110 001
1066 TRCVMIDCVR4 = 0x89c1, // 10 001 0011 1000 001
1067 TRCVMIDCVR5 = 0x89d1, // 10 001 0011 1010 001
1068 TRCVMIDCVR6 = 0x89e1, // 10 001 0011 1100 001
1069 TRCVMIDCVR7 = 0x89f1, // 10 001 0011 1110 001
1070 TRCCIDCCTLR0 = 0x8982, // 10 001 0011 0000 010
1071 TRCCIDCCTLR1 = 0x898a, // 10 001 0011 0001 010
1072 TRCVMIDCCTLR0 = 0x8992, // 10 001 0011 0010 010
1073 TRCVMIDCCTLR1 = 0x899a, // 10 001 0011 0011 010
1074 TRCITCTRL = 0x8b84, // 10 001 0111 0000 100
1075 TRCCLAIMSET = 0x8bc6, // 10 001 0111 1000 110
1076 TRCCLAIMCLR = 0x8bce, // 10 001 0111 1001 110
1079 ICC_BPR1_EL1 = 0xc663, // 11 000 1100 1100 011
1080 ICC_BPR0_EL1 = 0xc643, // 11 000 1100 1000 011
1081 ICC_PMR_EL1 = 0xc230, // 11 000 0100 0110 000
1082 ICC_CTLR_EL1 = 0xc664, // 11 000 1100 1100 100
1083 ICC_CTLR_EL3 = 0xf664, // 11 110 1100 1100 100
1084 ICC_SRE_EL1 = 0xc665, // 11 000 1100 1100 101
1085 ICC_SRE_EL2 = 0xe64d, // 11 100 1100 1001 101
1086 ICC_SRE_EL3 = 0xf665, // 11 110 1100 1100 101
1087 ICC_IGRPEN0_EL1 = 0xc666, // 11 000 1100 1100 110
1088 ICC_IGRPEN1_EL1 = 0xc667, // 11 000 1100 1100 111
1089 ICC_IGRPEN1_EL3 = 0xf667, // 11 110 1100 1100 111
1090 ICC_SEIEN_EL1 = 0xc668, // 11 000 1100 1101 000
1091 ICC_AP0R0_EL1 = 0xc644, // 11 000 1100 1000 100
1092 ICC_AP0R1_EL1 = 0xc645, // 11 000 1100 1000 101
1093 ICC_AP0R2_EL1 = 0xc646, // 11 000 1100 1000 110
1094 ICC_AP0R3_EL1 = 0xc647, // 11 000 1100 1000 111
1095 ICC_AP1R0_EL1 = 0xc648, // 11 000 1100 1001 000
1096 ICC_AP1R1_EL1 = 0xc649, // 11 000 1100 1001 001
1097 ICC_AP1R2_EL1 = 0xc64a, // 11 000 1100 1001 010
1098 ICC_AP1R3_EL1 = 0xc64b, // 11 000 1100 1001 011
1099 ICH_AP0R0_EL2 = 0xe640, // 11 100 1100 1000 000
1100 ICH_AP0R1_EL2 = 0xe641, // 11 100 1100 1000 001
1101 ICH_AP0R2_EL2 = 0xe642, // 11 100 1100 1000 010
1102 ICH_AP0R3_EL2 = 0xe643, // 11 100 1100 1000 011
1103 ICH_AP1R0_EL2 = 0xe648, // 11 100 1100 1001 000
1104 ICH_AP1R1_EL2 = 0xe649, // 11 100 1100 1001 001
1105 ICH_AP1R2_EL2 = 0xe64a, // 11 100 1100 1001 010
1106 ICH_AP1R3_EL2 = 0xe64b, // 11 100 1100 1001 011
1107 ICH_HCR_EL2 = 0xe658, // 11 100 1100 1011 000
1108 ICH_MISR_EL2 = 0xe65a, // 11 100 1100 1011 010
1109 ICH_VMCR_EL2 = 0xe65f, // 11 100 1100 1011 111
1110 ICH_VSEIR_EL2 = 0xe64c, // 11 100 1100 1001 100
1111 ICH_LR0_EL2 = 0xe660, // 11 100 1100 1100 000
1112 ICH_LR1_EL2 = 0xe661, // 11 100 1100 1100 001
1113 ICH_LR2_EL2 = 0xe662, // 11 100 1100 1100 010
1114 ICH_LR3_EL2 = 0xe663, // 11 100 1100 1100 011
1115 ICH_LR4_EL2 = 0xe664, // 11 100 1100 1100 100
1116 ICH_LR5_EL2 = 0xe665, // 11 100 1100 1100 101
1117 ICH_LR6_EL2 = 0xe666, // 11 100 1100 1100 110
1118 ICH_LR7_EL2 = 0xe667, // 11 100 1100 1100 111
1119 ICH_LR8_EL2 = 0xe668, // 11 100 1100 1101 000
1120 ICH_LR9_EL2 = 0xe669, // 11 100 1100 1101 001
1121 ICH_LR10_EL2 = 0xe66a, // 11 100 1100 1101 010
1122 ICH_LR11_EL2 = 0xe66b, // 11 100 1100 1101 011
1123 ICH_LR12_EL2 = 0xe66c, // 11 100 1100 1101 100
1124 ICH_LR13_EL2 = 0xe66d, // 11 100 1100 1101 101
1125 ICH_LR14_EL2 = 0xe66e, // 11 100 1100 1101 110
1126 ICH_LR15_EL2 = 0xe66f, // 11 100 1100 1101 111
1129 // Cyclone specific system registers
1130 enum CycloneSysRegValues {
1131 CPM_IOACC_CTL_EL3 = 0xff90
1134 // Note that these do not inherit from AArch64NamedImmMapper. This class is
1135 // sufficiently different in its behaviour that I don't believe it's worth
1136 // burdening the common AArch64NamedImmMapper with abstractions only needed in
1138 struct SysRegMapper {
1139 static const AArch64NamedImmMapper::Mapping SysRegPairs[];
1140 static const AArch64NamedImmMapper::Mapping CycloneSysRegPairs[];
1142 const AArch64NamedImmMapper::Mapping *InstPairs;
1143 size_t NumInstPairs;
1144 const FeatureBitset &FeatureBits;
1146 SysRegMapper(const FeatureBitset &FeatureBits) : FeatureBits(FeatureBits) { }
1147 uint32_t fromString(StringRef Name, bool &Valid) const;
1148 std::string toString(uint32_t Bits) const;
1151 struct MSRMapper : SysRegMapper {
1152 static const AArch64NamedImmMapper::Mapping MSRPairs[];
1153 MSRMapper(const FeatureBitset &FeatureBits);
1156 struct MRSMapper : SysRegMapper {
1157 static const AArch64NamedImmMapper::Mapping MRSPairs[];
1158 MRSMapper(const FeatureBitset &FeatureBits);
1161 uint32_t ParseGenericRegister(StringRef Name, bool &Valid);
1164 namespace AArch64TLBI {
1166 Invalid = -1, // Op0 Op1 CRn CRm Op2
1167 IPAS2E1IS = 0x6401, // 01 100 1000 0000 001
1168 IPAS2LE1IS = 0x6405, // 01 100 1000 0000 101
1169 VMALLE1IS = 0x4418, // 01 000 1000 0011 000
1170 ALLE2IS = 0x6418, // 01 100 1000 0011 000
1171 ALLE3IS = 0x7418, // 01 110 1000 0011 000
1172 VAE1IS = 0x4419, // 01 000 1000 0011 001
1173 VAE2IS = 0x6419, // 01 100 1000 0011 001
1174 VAE3IS = 0x7419, // 01 110 1000 0011 001
1175 ASIDE1IS = 0x441a, // 01 000 1000 0011 010
1176 VAAE1IS = 0x441b, // 01 000 1000 0011 011
1177 ALLE1IS = 0x641c, // 01 100 1000 0011 100
1178 VALE1IS = 0x441d, // 01 000 1000 0011 101
1179 VALE2IS = 0x641d, // 01 100 1000 0011 101
1180 VALE3IS = 0x741d, // 01 110 1000 0011 101
1181 VMALLS12E1IS = 0x641e, // 01 100 1000 0011 110
1182 VAALE1IS = 0x441f, // 01 000 1000 0011 111
1183 IPAS2E1 = 0x6421, // 01 100 1000 0100 001
1184 IPAS2LE1 = 0x6425, // 01 100 1000 0100 101
1185 VMALLE1 = 0x4438, // 01 000 1000 0111 000
1186 ALLE2 = 0x6438, // 01 100 1000 0111 000
1187 ALLE3 = 0x7438, // 01 110 1000 0111 000
1188 VAE1 = 0x4439, // 01 000 1000 0111 001
1189 VAE2 = 0x6439, // 01 100 1000 0111 001
1190 VAE3 = 0x7439, // 01 110 1000 0111 001
1191 ASIDE1 = 0x443a, // 01 000 1000 0111 010
1192 VAAE1 = 0x443b, // 01 000 1000 0111 011
1193 ALLE1 = 0x643c, // 01 100 1000 0111 100
1194 VALE1 = 0x443d, // 01 000 1000 0111 101
1195 VALE2 = 0x643d, // 01 100 1000 0111 101
1196 VALE3 = 0x743d, // 01 110 1000 0111 101
1197 VMALLS12E1 = 0x643e, // 01 100 1000 0111 110
1198 VAALE1 = 0x443f // 01 000 1000 0111 111
1201 struct TLBIMapper : AArch64NamedImmMapper {
1202 const static Mapping TLBIPairs[];
1207 static inline bool NeedsRegister(TLBIValues Val) {
1226 namespace AArch64II {
1227 /// Target Operand Flag enum.
1229 //===------------------------------------------------------------------===//
1230 // AArch64 Specific MachineOperand flags.
1236 /// MO_PAGE - A symbol operand with this flag represents the pc-relative
1237 /// offset of the 4K page containing the symbol. This is used with the
1238 /// ADRP instruction.
1241 /// MO_PAGEOFF - A symbol operand with this flag represents the offset of
1242 /// that symbol within a 4K page. This offset is added to the page address
1243 /// to produce the complete address.
1246 /// MO_G3 - A symbol operand with this flag (granule 3) represents the high
1247 /// 16-bits of a 64-bit address, used in a MOVZ or MOVK instruction
1250 /// MO_G2 - A symbol operand with this flag (granule 2) represents the bits
1251 /// 32-47 of a 64-bit address, used in a MOVZ or MOVK instruction
1254 /// MO_G1 - A symbol operand with this flag (granule 1) represents the bits
1255 /// 16-31 of a 64-bit address, used in a MOVZ or MOVK instruction
1258 /// MO_G0 - A symbol operand with this flag (granule 0) represents the bits
1259 /// 0-15 of a 64-bit address, used in a MOVZ or MOVK instruction
1262 /// MO_HI12 - This flag indicates that a symbol operand represents the bits
1263 /// 13-24 of a 64-bit address, used in a arithmetic immediate-shifted-left-
1264 /// by-12-bits instruction.
1267 /// MO_GOT - This flag indicates that a symbol operand represents the
1268 /// address of the GOT entry for the symbol, rather than the address of
1269 /// the symbol itself.
1272 /// MO_NC - Indicates whether the linker is expected to check the symbol
1273 /// reference for overflow. For example in an ADRP/ADD pair of relocations
1274 /// the ADRP usually does check, but not the ADD.
1277 /// MO_TLS - Indicates that the operand being accessed is some kind of
1278 /// thread-local symbol. On Darwin, only one type of thread-local access
1279 /// exists (pre linker-relaxation), but on ELF the TLSModel used for the
1280 /// referee will affect interpretation.
1283 /// MO_CONSTPOOL - This flag indicates that a symbol operand represents
1284 /// the address of a constant pool entry for the symbol, rather than the
1285 /// address of the symbol itself.
1288 } // end namespace AArch64II
1290 } // end namespace llvm