1 //=- AArch64/AArch64MCCodeEmitter.cpp - Convert AArch64 code to machine code-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the AArch64MCCodeEmitter class.
12 //===----------------------------------------------------------------------===//
14 #include "MCTargetDesc/AArch64AddressingModes.h"
15 #include "MCTargetDesc/AArch64FixupKinds.h"
16 #include "MCTargetDesc/AArch64MCExpr.h"
17 #include "Utils/AArch64BaseInfo.h"
18 #include "llvm/ADT/Statistic.h"
19 #include "llvm/MC/MCCodeEmitter.h"
20 #include "llvm/MC/MCContext.h"
21 #include "llvm/MC/MCInst.h"
22 #include "llvm/MC/MCInstrInfo.h"
23 #include "llvm/MC/MCRegisterInfo.h"
24 #include "llvm/MC/MCSubtargetInfo.h"
25 #include "llvm/Support/raw_ostream.h"
28 #define DEBUG_TYPE "mccodeemitter"
30 STATISTIC(MCNumEmitted, "Number of MC instructions emitted.");
31 STATISTIC(MCNumFixups, "Number of MC fixups created.");
35 class AArch64MCCodeEmitter : public MCCodeEmitter {
38 AArch64MCCodeEmitter(const AArch64MCCodeEmitter &); // DO NOT IMPLEMENT
39 void operator=(const AArch64MCCodeEmitter &); // DO NOT IMPLEMENT
41 AArch64MCCodeEmitter(const MCInstrInfo &mcii, MCContext &ctx) : Ctx(ctx) {}
43 ~AArch64MCCodeEmitter() override {}
45 // getBinaryCodeForInstr - TableGen'erated function for getting the
46 // binary encoding for an instruction.
47 uint64_t getBinaryCodeForInstr(const MCInst &MI,
48 SmallVectorImpl<MCFixup> &Fixups,
49 const MCSubtargetInfo &STI) const;
51 /// getMachineOpValue - Return binary encoding of operand. If the machine
52 /// operand requires relocation, record the relocation and return zero.
53 unsigned getMachineOpValue(const MCInst &MI, const MCOperand &MO,
54 SmallVectorImpl<MCFixup> &Fixups,
55 const MCSubtargetInfo &STI) const;
57 /// getLdStUImm12OpValue - Return encoding info for 12-bit unsigned immediate
58 /// attached to a load, store or prfm instruction. If operand requires a
59 /// relocation, record it and return zero in that part of the encoding.
60 template <uint32_t FixupKind>
61 uint32_t getLdStUImm12OpValue(const MCInst &MI, unsigned OpIdx,
62 SmallVectorImpl<MCFixup> &Fixups,
63 const MCSubtargetInfo &STI) const;
65 /// getAdrLabelOpValue - Return encoding info for 21-bit immediate ADR label
67 uint32_t getAdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
68 SmallVectorImpl<MCFixup> &Fixups,
69 const MCSubtargetInfo &STI) const;
71 /// getAddSubImmOpValue - Return encoding for the 12-bit immediate value and
72 /// the 2-bit shift field.
73 uint32_t getAddSubImmOpValue(const MCInst &MI, unsigned OpIdx,
74 SmallVectorImpl<MCFixup> &Fixups,
75 const MCSubtargetInfo &STI) const;
77 /// getCondBranchTargetOpValue - Return the encoded value for a conditional
79 uint32_t getCondBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
80 SmallVectorImpl<MCFixup> &Fixups,
81 const MCSubtargetInfo &STI) const;
83 /// getLoadLiteralOpValue - Return the encoded value for a load-literal
84 /// pc-relative address.
85 uint32_t getLoadLiteralOpValue(const MCInst &MI, unsigned OpIdx,
86 SmallVectorImpl<MCFixup> &Fixups,
87 const MCSubtargetInfo &STI) const;
89 /// getMemExtendOpValue - Return the encoded value for a reg-extend load/store
90 /// instruction: bit 0 is whether a shift is present, bit 1 is whether the
91 /// operation is a sign extend (as opposed to a zero extend).
92 uint32_t getMemExtendOpValue(const MCInst &MI, unsigned OpIdx,
93 SmallVectorImpl<MCFixup> &Fixups,
94 const MCSubtargetInfo &STI) const;
96 /// getTestBranchTargetOpValue - Return the encoded value for a test-bit-and-
98 uint32_t getTestBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
99 SmallVectorImpl<MCFixup> &Fixups,
100 const MCSubtargetInfo &STI) const;
102 /// getBranchTargetOpValue - Return the encoded value for an unconditional
104 uint32_t getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
105 SmallVectorImpl<MCFixup> &Fixups,
106 const MCSubtargetInfo &STI) const;
108 /// getMoveWideImmOpValue - Return the encoded value for the immediate operand
109 /// of a MOVZ or MOVK instruction.
110 uint32_t getMoveWideImmOpValue(const MCInst &MI, unsigned OpIdx,
111 SmallVectorImpl<MCFixup> &Fixups,
112 const MCSubtargetInfo &STI) const;
114 /// getVecShifterOpValue - Return the encoded value for the vector shifter.
115 uint32_t getVecShifterOpValue(const MCInst &MI, unsigned OpIdx,
116 SmallVectorImpl<MCFixup> &Fixups,
117 const MCSubtargetInfo &STI) const;
119 /// getMoveVecShifterOpValue - Return the encoded value for the vector move
121 uint32_t getMoveVecShifterOpValue(const MCInst &MI, unsigned OpIdx,
122 SmallVectorImpl<MCFixup> &Fixups,
123 const MCSubtargetInfo &STI) const;
125 /// getFixedPointScaleOpValue - Return the encoded value for the
126 // FP-to-fixed-point scale factor.
127 uint32_t getFixedPointScaleOpValue(const MCInst &MI, unsigned OpIdx,
128 SmallVectorImpl<MCFixup> &Fixups,
129 const MCSubtargetInfo &STI) const;
131 uint32_t getVecShiftR64OpValue(const MCInst &MI, unsigned OpIdx,
132 SmallVectorImpl<MCFixup> &Fixups,
133 const MCSubtargetInfo &STI) const;
134 uint32_t getVecShiftR32OpValue(const MCInst &MI, unsigned OpIdx,
135 SmallVectorImpl<MCFixup> &Fixups,
136 const MCSubtargetInfo &STI) const;
137 uint32_t getVecShiftR16OpValue(const MCInst &MI, unsigned OpIdx,
138 SmallVectorImpl<MCFixup> &Fixups,
139 const MCSubtargetInfo &STI) const;
140 uint32_t getVecShiftR8OpValue(const MCInst &MI, unsigned OpIdx,
141 SmallVectorImpl<MCFixup> &Fixups,
142 const MCSubtargetInfo &STI) const;
143 uint32_t getVecShiftL64OpValue(const MCInst &MI, unsigned OpIdx,
144 SmallVectorImpl<MCFixup> &Fixups,
145 const MCSubtargetInfo &STI) const;
146 uint32_t getVecShiftL32OpValue(const MCInst &MI, unsigned OpIdx,
147 SmallVectorImpl<MCFixup> &Fixups,
148 const MCSubtargetInfo &STI) const;
149 uint32_t getVecShiftL16OpValue(const MCInst &MI, unsigned OpIdx,
150 SmallVectorImpl<MCFixup> &Fixups,
151 const MCSubtargetInfo &STI) const;
152 uint32_t getVecShiftL8OpValue(const MCInst &MI, unsigned OpIdx,
153 SmallVectorImpl<MCFixup> &Fixups,
154 const MCSubtargetInfo &STI) const;
156 /// getSIMDShift64OpValue - Return the encoded value for the
157 // shift-by-immediate AdvSIMD instructions.
158 uint32_t getSIMDShift64OpValue(const MCInst &MI, unsigned OpIdx,
159 SmallVectorImpl<MCFixup> &Fixups,
160 const MCSubtargetInfo &STI) const;
162 uint32_t getSIMDShift64_32OpValue(const MCInst &MI, unsigned OpIdx,
163 SmallVectorImpl<MCFixup> &Fixups,
164 const MCSubtargetInfo &STI) const;
166 uint32_t getSIMDShift32OpValue(const MCInst &MI, unsigned OpIdx,
167 SmallVectorImpl<MCFixup> &Fixups,
168 const MCSubtargetInfo &STI) const;
170 uint32_t getSIMDShift16OpValue(const MCInst &MI, unsigned OpIdx,
171 SmallVectorImpl<MCFixup> &Fixups,
172 const MCSubtargetInfo &STI) const;
174 unsigned fixMOVZ(const MCInst &MI, unsigned EncodedValue,
175 const MCSubtargetInfo &STI) const;
177 void EmitByte(unsigned char C, raw_ostream &OS) const { OS << (char)C; }
179 void EmitConstant(uint64_t Val, unsigned Size, raw_ostream &OS) const {
180 // Output the constant in little endian byte order.
181 for (unsigned i = 0; i != Size; ++i) {
182 EmitByte(Val & 255, OS);
187 void EncodeInstruction(const MCInst &MI, raw_ostream &OS,
188 SmallVectorImpl<MCFixup> &Fixups,
189 const MCSubtargetInfo &STI) const override;
191 unsigned fixMulHigh(const MCInst &MI, unsigned EncodedValue,
192 const MCSubtargetInfo &STI) const;
194 template<int hasRs, int hasRt2> unsigned
195 fixLoadStoreExclusive(const MCInst &MI, unsigned EncodedValue,
196 const MCSubtargetInfo &STI) const;
198 unsigned fixOneOperandFPComparison(const MCInst &MI, unsigned EncodedValue,
199 const MCSubtargetInfo &STI) const;
202 } // end anonymous namespace
204 MCCodeEmitter *llvm::createAArch64MCCodeEmitter(const MCInstrInfo &MCII,
205 const MCRegisterInfo &MRI,
207 return new AArch64MCCodeEmitter(MCII, Ctx);
210 /// getMachineOpValue - Return binary encoding of operand. If the machine
211 /// operand requires relocation, record the relocation and return zero.
213 AArch64MCCodeEmitter::getMachineOpValue(const MCInst &MI, const MCOperand &MO,
214 SmallVectorImpl<MCFixup> &Fixups,
215 const MCSubtargetInfo &STI) const {
217 return Ctx.getRegisterInfo()->getEncodingValue(MO.getReg());
219 assert(MO.isImm() && "did not expect relocated expression");
220 return static_cast<unsigned>(MO.getImm());
223 template<unsigned FixupKind> uint32_t
224 AArch64MCCodeEmitter::getLdStUImm12OpValue(const MCInst &MI, unsigned OpIdx,
225 SmallVectorImpl<MCFixup> &Fixups,
226 const MCSubtargetInfo &STI) const {
227 const MCOperand &MO = MI.getOperand(OpIdx);
231 ImmVal = static_cast<uint32_t>(MO.getImm());
233 assert(MO.isExpr() && "unable to encode load/store imm operand");
234 MCFixupKind Kind = MCFixupKind(FixupKind);
235 Fixups.push_back(MCFixup::create(0, MO.getExpr(), Kind, MI.getLoc()));
242 /// getAdrLabelOpValue - Return encoding info for 21-bit immediate ADR label
245 AArch64MCCodeEmitter::getAdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
246 SmallVectorImpl<MCFixup> &Fixups,
247 const MCSubtargetInfo &STI) const {
248 const MCOperand &MO = MI.getOperand(OpIdx);
250 // If the destination is an immediate, we have nothing to do.
253 assert(MO.isExpr() && "Unexpected target type!");
254 const MCExpr *Expr = MO.getExpr();
256 MCFixupKind Kind = MI.getOpcode() == AArch64::ADR
257 ? MCFixupKind(AArch64::fixup_aarch64_pcrel_adr_imm21)
258 : MCFixupKind(AArch64::fixup_aarch64_pcrel_adrp_imm21);
259 Fixups.push_back(MCFixup::create(0, Expr, Kind, MI.getLoc()));
263 // All of the information is in the fixup.
267 /// getAddSubImmOpValue - Return encoding for the 12-bit immediate value and
268 /// the 2-bit shift field. The shift field is stored in bits 13-14 of the
271 AArch64MCCodeEmitter::getAddSubImmOpValue(const MCInst &MI, unsigned OpIdx,
272 SmallVectorImpl<MCFixup> &Fixups,
273 const MCSubtargetInfo &STI) const {
274 // Suboperands are [imm, shifter].
275 const MCOperand &MO = MI.getOperand(OpIdx);
276 const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
277 assert(AArch64_AM::getShiftType(MO1.getImm()) == AArch64_AM::LSL &&
278 "unexpected shift type for add/sub immediate");
279 unsigned ShiftVal = AArch64_AM::getShiftValue(MO1.getImm());
280 assert((ShiftVal == 0 || ShiftVal == 12) &&
281 "unexpected shift value for add/sub immediate");
283 return MO.getImm() | (ShiftVal == 0 ? 0 : (1 << 12));
284 assert(MO.isExpr() && "Unable to encode MCOperand!");
285 const MCExpr *Expr = MO.getExpr();
287 // Encode the 12 bits of the fixup.
288 MCFixupKind Kind = MCFixupKind(AArch64::fixup_aarch64_add_imm12);
289 Fixups.push_back(MCFixup::create(0, Expr, Kind, MI.getLoc()));
296 /// getCondBranchTargetOpValue - Return the encoded value for a conditional
298 uint32_t AArch64MCCodeEmitter::getCondBranchTargetOpValue(
299 const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups,
300 const MCSubtargetInfo &STI) const {
301 const MCOperand &MO = MI.getOperand(OpIdx);
303 // If the destination is an immediate, we have nothing to do.
306 assert(MO.isExpr() && "Unexpected target type!");
308 MCFixupKind Kind = MCFixupKind(AArch64::fixup_aarch64_pcrel_branch19);
309 Fixups.push_back(MCFixup::create(0, MO.getExpr(), Kind, MI.getLoc()));
313 // All of the information is in the fixup.
317 /// getLoadLiteralOpValue - Return the encoded value for a load-literal
318 /// pc-relative address.
320 AArch64MCCodeEmitter::getLoadLiteralOpValue(const MCInst &MI, unsigned OpIdx,
321 SmallVectorImpl<MCFixup> &Fixups,
322 const MCSubtargetInfo &STI) const {
323 const MCOperand &MO = MI.getOperand(OpIdx);
325 // If the destination is an immediate, we have nothing to do.
328 assert(MO.isExpr() && "Unexpected target type!");
330 MCFixupKind Kind = MCFixupKind(AArch64::fixup_aarch64_ldr_pcrel_imm19);
331 Fixups.push_back(MCFixup::create(0, MO.getExpr(), Kind, MI.getLoc()));
335 // All of the information is in the fixup.
340 AArch64MCCodeEmitter::getMemExtendOpValue(const MCInst &MI, unsigned OpIdx,
341 SmallVectorImpl<MCFixup> &Fixups,
342 const MCSubtargetInfo &STI) const {
343 unsigned SignExtend = MI.getOperand(OpIdx).getImm();
344 unsigned DoShift = MI.getOperand(OpIdx + 1).getImm();
345 return (SignExtend << 1) | DoShift;
349 AArch64MCCodeEmitter::getMoveWideImmOpValue(const MCInst &MI, unsigned OpIdx,
350 SmallVectorImpl<MCFixup> &Fixups,
351 const MCSubtargetInfo &STI) const {
352 const MCOperand &MO = MI.getOperand(OpIdx);
356 assert(MO.isExpr() && "Unexpected movz/movk immediate");
358 Fixups.push_back(MCFixup::create(
359 0, MO.getExpr(), MCFixupKind(AArch64::fixup_aarch64_movw), MI.getLoc()));
366 /// getTestBranchTargetOpValue - Return the encoded value for a test-bit-and-
368 uint32_t AArch64MCCodeEmitter::getTestBranchTargetOpValue(
369 const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups,
370 const MCSubtargetInfo &STI) const {
371 const MCOperand &MO = MI.getOperand(OpIdx);
373 // If the destination is an immediate, we have nothing to do.
376 assert(MO.isExpr() && "Unexpected ADR target type!");
378 MCFixupKind Kind = MCFixupKind(AArch64::fixup_aarch64_pcrel_branch14);
379 Fixups.push_back(MCFixup::create(0, MO.getExpr(), Kind, MI.getLoc()));
383 // All of the information is in the fixup.
387 /// getBranchTargetOpValue - Return the encoded value for an unconditional
390 AArch64MCCodeEmitter::getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
391 SmallVectorImpl<MCFixup> &Fixups,
392 const MCSubtargetInfo &STI) const {
393 const MCOperand &MO = MI.getOperand(OpIdx);
395 // If the destination is an immediate, we have nothing to do.
398 assert(MO.isExpr() && "Unexpected ADR target type!");
400 MCFixupKind Kind = MI.getOpcode() == AArch64::BL
401 ? MCFixupKind(AArch64::fixup_aarch64_pcrel_call26)
402 : MCFixupKind(AArch64::fixup_aarch64_pcrel_branch26);
403 Fixups.push_back(MCFixup::create(0, MO.getExpr(), Kind, MI.getLoc()));
407 // All of the information is in the fixup.
411 /// getVecShifterOpValue - Return the encoded value for the vector shifter:
418 AArch64MCCodeEmitter::getVecShifterOpValue(const MCInst &MI, unsigned OpIdx,
419 SmallVectorImpl<MCFixup> &Fixups,
420 const MCSubtargetInfo &STI) const {
421 const MCOperand &MO = MI.getOperand(OpIdx);
422 assert(MO.isImm() && "Expected an immediate value for the shift amount!");
424 switch (MO.getImm()) {
437 llvm_unreachable("Invalid value for vector shift amount!");
441 AArch64MCCodeEmitter::getSIMDShift64OpValue(const MCInst &MI, unsigned OpIdx,
442 SmallVectorImpl<MCFixup> &Fixups,
443 const MCSubtargetInfo &STI) const {
444 const MCOperand &MO = MI.getOperand(OpIdx);
445 assert(MO.isImm() && "Expected an immediate value for the shift amount!");
446 return 64 - (MO.getImm());
449 uint32_t AArch64MCCodeEmitter::getSIMDShift64_32OpValue(
450 const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups,
451 const MCSubtargetInfo &STI) const {
452 const MCOperand &MO = MI.getOperand(OpIdx);
453 assert(MO.isImm() && "Expected an immediate value for the shift amount!");
454 return 64 - (MO.getImm() | 32);
458 AArch64MCCodeEmitter::getSIMDShift32OpValue(const MCInst &MI, unsigned OpIdx,
459 SmallVectorImpl<MCFixup> &Fixups,
460 const MCSubtargetInfo &STI) const {
461 const MCOperand &MO = MI.getOperand(OpIdx);
462 assert(MO.isImm() && "Expected an immediate value for the shift amount!");
463 return 32 - (MO.getImm() | 16);
467 AArch64MCCodeEmitter::getSIMDShift16OpValue(const MCInst &MI, unsigned OpIdx,
468 SmallVectorImpl<MCFixup> &Fixups,
469 const MCSubtargetInfo &STI) const {
470 const MCOperand &MO = MI.getOperand(OpIdx);
471 assert(MO.isImm() && "Expected an immediate value for the shift amount!");
472 return 16 - (MO.getImm() | 8);
475 /// getFixedPointScaleOpValue - Return the encoded value for the
476 // FP-to-fixed-point scale factor.
477 uint32_t AArch64MCCodeEmitter::getFixedPointScaleOpValue(
478 const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups,
479 const MCSubtargetInfo &STI) const {
480 const MCOperand &MO = MI.getOperand(OpIdx);
481 assert(MO.isImm() && "Expected an immediate value for the scale amount!");
482 return 64 - MO.getImm();
486 AArch64MCCodeEmitter::getVecShiftR64OpValue(const MCInst &MI, unsigned OpIdx,
487 SmallVectorImpl<MCFixup> &Fixups,
488 const MCSubtargetInfo &STI) const {
489 const MCOperand &MO = MI.getOperand(OpIdx);
490 assert(MO.isImm() && "Expected an immediate value for the scale amount!");
491 return 64 - MO.getImm();
495 AArch64MCCodeEmitter::getVecShiftR32OpValue(const MCInst &MI, unsigned OpIdx,
496 SmallVectorImpl<MCFixup> &Fixups,
497 const MCSubtargetInfo &STI) const {
498 const MCOperand &MO = MI.getOperand(OpIdx);
499 assert(MO.isImm() && "Expected an immediate value for the scale amount!");
500 return 32 - MO.getImm();
504 AArch64MCCodeEmitter::getVecShiftR16OpValue(const MCInst &MI, unsigned OpIdx,
505 SmallVectorImpl<MCFixup> &Fixups,
506 const MCSubtargetInfo &STI) const {
507 const MCOperand &MO = MI.getOperand(OpIdx);
508 assert(MO.isImm() && "Expected an immediate value for the scale amount!");
509 return 16 - MO.getImm();
513 AArch64MCCodeEmitter::getVecShiftR8OpValue(const MCInst &MI, unsigned OpIdx,
514 SmallVectorImpl<MCFixup> &Fixups,
515 const MCSubtargetInfo &STI) const {
516 const MCOperand &MO = MI.getOperand(OpIdx);
517 assert(MO.isImm() && "Expected an immediate value for the scale amount!");
518 return 8 - MO.getImm();
522 AArch64MCCodeEmitter::getVecShiftL64OpValue(const MCInst &MI, unsigned OpIdx,
523 SmallVectorImpl<MCFixup> &Fixups,
524 const MCSubtargetInfo &STI) const {
525 const MCOperand &MO = MI.getOperand(OpIdx);
526 assert(MO.isImm() && "Expected an immediate value for the scale amount!");
527 return MO.getImm() - 64;
531 AArch64MCCodeEmitter::getVecShiftL32OpValue(const MCInst &MI, unsigned OpIdx,
532 SmallVectorImpl<MCFixup> &Fixups,
533 const MCSubtargetInfo &STI) const {
534 const MCOperand &MO = MI.getOperand(OpIdx);
535 assert(MO.isImm() && "Expected an immediate value for the scale amount!");
536 return MO.getImm() - 32;
540 AArch64MCCodeEmitter::getVecShiftL16OpValue(const MCInst &MI, unsigned OpIdx,
541 SmallVectorImpl<MCFixup> &Fixups,
542 const MCSubtargetInfo &STI) const {
543 const MCOperand &MO = MI.getOperand(OpIdx);
544 assert(MO.isImm() && "Expected an immediate value for the scale amount!");
545 return MO.getImm() - 16;
549 AArch64MCCodeEmitter::getVecShiftL8OpValue(const MCInst &MI, unsigned OpIdx,
550 SmallVectorImpl<MCFixup> &Fixups,
551 const MCSubtargetInfo &STI) const {
552 const MCOperand &MO = MI.getOperand(OpIdx);
553 assert(MO.isImm() && "Expected an immediate value for the scale amount!");
554 return MO.getImm() - 8;
557 /// getMoveVecShifterOpValue - Return the encoded value for the vector move
559 uint32_t AArch64MCCodeEmitter::getMoveVecShifterOpValue(
560 const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups,
561 const MCSubtargetInfo &STI) const {
562 const MCOperand &MO = MI.getOperand(OpIdx);
564 "Expected an immediate value for the move shift amount!");
565 unsigned ShiftVal = AArch64_AM::getShiftValue(MO.getImm());
566 assert((ShiftVal == 8 || ShiftVal == 16) && "Invalid shift amount!");
567 return ShiftVal == 8 ? 0 : 1;
570 unsigned AArch64MCCodeEmitter::fixMOVZ(const MCInst &MI, unsigned EncodedValue,
571 const MCSubtargetInfo &STI) const {
572 // If one of the signed fixup kinds is applied to a MOVZ instruction, the
573 // eventual result could be either a MOVZ or a MOVN. It's the MCCodeEmitter's
574 // job to ensure that any bits possibly affected by this are 0. This means we
575 // must zero out bit 30 (essentially emitting a MOVN).
576 MCOperand UImm16MO = MI.getOperand(1);
578 // Nothing to do if there's no fixup.
579 if (UImm16MO.isImm())
582 const AArch64MCExpr *A64E = cast<AArch64MCExpr>(UImm16MO.getExpr());
583 switch (A64E->getKind()) {
584 case AArch64MCExpr::VK_DTPREL_G2:
585 case AArch64MCExpr::VK_DTPREL_G1:
586 case AArch64MCExpr::VK_DTPREL_G0:
587 case AArch64MCExpr::VK_GOTTPREL_G1:
588 case AArch64MCExpr::VK_TPREL_G2:
589 case AArch64MCExpr::VK_TPREL_G1:
590 case AArch64MCExpr::VK_TPREL_G0:
591 return EncodedValue & ~(1u << 30);
593 // Nothing to do for an unsigned fixup.
598 return EncodedValue & ~(1u << 30);
601 void AArch64MCCodeEmitter::EncodeInstruction(const MCInst &MI, raw_ostream &OS,
602 SmallVectorImpl<MCFixup> &Fixups,
603 const MCSubtargetInfo &STI) const {
604 if (MI.getOpcode() == AArch64::TLSDESCCALL) {
605 // This is a directive which applies an R_AARCH64_TLSDESC_CALL to the
606 // following (BLR) instruction. It doesn't emit any code itself so it
607 // doesn't go through the normal TableGenerated channels.
608 MCFixupKind Fixup = MCFixupKind(AArch64::fixup_aarch64_tlsdesc_call);
609 Fixups.push_back(MCFixup::create(0, MI.getOperand(0).getExpr(), Fixup));
613 uint64_t Binary = getBinaryCodeForInstr(MI, Fixups, STI);
614 EmitConstant(Binary, 4, OS);
615 ++MCNumEmitted; // Keep track of the # of mi's emitted.
619 AArch64MCCodeEmitter::fixMulHigh(const MCInst &MI,
620 unsigned EncodedValue,
621 const MCSubtargetInfo &STI) const {
622 // The Ra field of SMULH and UMULH is unused: it should be assembled as 31
623 // (i.e. all bits 1) but is ignored by the processor.
624 EncodedValue |= 0x1f << 10;
628 template<int hasRs, int hasRt2> unsigned
629 AArch64MCCodeEmitter::fixLoadStoreExclusive(const MCInst &MI,
630 unsigned EncodedValue,
631 const MCSubtargetInfo &STI) const {
632 if (!hasRs) EncodedValue |= 0x001F0000;
633 if (!hasRt2) EncodedValue |= 0x00007C00;
638 unsigned AArch64MCCodeEmitter::fixOneOperandFPComparison(
639 const MCInst &MI, unsigned EncodedValue, const MCSubtargetInfo &STI) const {
640 // The Rm field of FCMP and friends is unused - it should be assembled
641 // as 0, but is ignored by the processor.
642 EncodedValue &= ~(0x1f << 16);
646 #include "AArch64GenMCCodeEmitter.inc"