1 //==-- AArch64TargetMachine.h - Define TargetMachine for AArch64 -*- C++ -*-==//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file declares the AArch64 specific subclass of TargetMachine.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_LIB_TARGET_AARCH64_AARCH64TARGETMACHINE_H
15 #define LLVM_LIB_TARGET_AARCH64_AARCH64TARGETMACHINE_H
17 #include "AArch64InstrInfo.h"
18 #include "AArch64Subtarget.h"
19 #include "llvm/IR/DataLayout.h"
20 #include "llvm/Target/TargetMachine.h"
24 class AArch64TargetMachine : public LLVMTargetMachine {
26 AArch64Subtarget Subtarget;
27 mutable StringMap<std::unique_ptr<AArch64Subtarget>> SubtargetMap;
30 AArch64TargetMachine(const Target &T, StringRef TT, StringRef CPU,
31 StringRef FS, const TargetOptions &Options,
32 Reloc::Model RM, CodeModel::Model CM,
33 CodeGenOpt::Level OL, bool IsLittleEndian);
35 const AArch64Subtarget *getSubtargetImpl() const override {
38 const AArch64Subtarget *getSubtargetImpl(const Function &F) const override;
40 // Pass Pipeline Configuration
41 TargetPassConfig *createPassConfig(PassManagerBase &PM) override;
43 /// \brief Register AArch64 analysis passes with a pass manager.
44 void addAnalysisPasses(PassManagerBase &PM) override;
46 /// \brief Query if the PBQP register allocator is being used
47 bool isPBQPUsed() const { return usingPBQP; }
54 // AArch64leTargetMachine - AArch64 little endian target machine.
56 class AArch64leTargetMachine : public AArch64TargetMachine {
57 virtual void anchor();
59 AArch64leTargetMachine(const Target &T, StringRef TT, StringRef CPU,
60 StringRef FS, const TargetOptions &Options,
61 Reloc::Model RM, CodeModel::Model CM,
62 CodeGenOpt::Level OL);
65 // AArch64beTargetMachine - AArch64 big endian target machine.
67 class AArch64beTargetMachine : public AArch64TargetMachine {
68 virtual void anchor();
70 AArch64beTargetMachine(const Target &T, StringRef TT, StringRef CPU,
71 StringRef FS, const TargetOptions &Options,
72 Reloc::Model RM, CodeModel::Model CM,
73 CodeGenOpt::Level OL);
76 } // end namespace llvm