1 //===-- AArch64TargetMachine.cpp - Define TargetMachine for AArch64 -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
14 #include "AArch64TargetMachine.h"
15 #include "AArch64TargetObjectFile.h"
16 #include "AArch64TargetTransformInfo.h"
17 #include "llvm/CodeGen/Passes.h"
18 #include "llvm/CodeGen/RegAllocRegistry.h"
19 #include "llvm/IR/Function.h"
20 #include "llvm/IR/LegacyPassManager.h"
21 #include "llvm/Support/CommandLine.h"
22 #include "llvm/Support/TargetRegistry.h"
23 #include "llvm/Target/TargetOptions.h"
24 #include "llvm/Transforms/Scalar.h"
28 EnableCCMP("aarch64-ccmp", cl::desc("Enable the CCMP formation pass"),
29 cl::init(true), cl::Hidden);
31 static cl::opt<bool> EnableMCR("aarch64-mcr",
32 cl::desc("Enable the machine combiner pass"),
33 cl::init(true), cl::Hidden);
36 EnableStPairSuppress("aarch64-stp-suppress", cl::desc("Suppress STP for AArch64"),
37 cl::init(true), cl::Hidden);
40 EnableAdvSIMDScalar("aarch64-simd-scalar", cl::desc("Enable use of AdvSIMD scalar"
41 " integer instructions"), cl::init(false), cl::Hidden);
44 EnablePromoteConstant("aarch64-promote-const", cl::desc("Enable the promote "
45 "constant pass"), cl::init(true), cl::Hidden);
48 EnableCollectLOH("aarch64-collect-loh", cl::desc("Enable the pass that emits the"
49 " linker optimization hints (LOH)"), cl::init(true),
53 EnableDeadRegisterElimination("aarch64-dead-def-elimination", cl::Hidden,
54 cl::desc("Enable the pass that removes dead"
55 " definitons and replaces stores to"
56 " them with stores to the zero"
61 EnableLoadStoreOpt("aarch64-load-store-opt", cl::desc("Enable the load/store pair"
62 " optimization pass"), cl::init(true), cl::Hidden);
65 EnableAtomicTidy("aarch64-atomic-cfg-tidy", cl::Hidden,
66 cl::desc("Run SimplifyCFG after expanding atomic operations"
67 " to make use of cmpxchg flow-based information"),
70 static cl::opt<bool> AArch64InterleavedAccessOpt(
71 "aarch64-interleaved-access-opt",
72 cl::desc("Optimize interleaved memory accesses in the AArch64 backend"),
73 cl::init(false), cl::Hidden);
76 EnableEarlyIfConversion("aarch64-enable-early-ifcvt", cl::Hidden,
77 cl::desc("Run early if-conversion"),
81 EnableCondOpt("aarch64-condopt",
82 cl::desc("Enable the condition optimizer pass"),
83 cl::init(true), cl::Hidden);
86 EnableA53Fix835769("aarch64-fix-cortex-a53-835769", cl::Hidden,
87 cl::desc("Work around Cortex-A53 erratum 835769"),
91 EnableGEPOpt("aarch64-gep-opt", cl::Hidden,
92 cl::desc("Enable optimizations on complex GEPs"),
95 // FIXME: Unify control over GlobalMerge.
96 static cl::opt<cl::boolOrDefault>
97 EnableGlobalMerge("aarch64-global-merge", cl::Hidden,
98 cl::desc("Enable the global merge pass"));
100 extern "C" void LLVMInitializeAArch64Target() {
101 // Register the target.
102 RegisterTargetMachine<AArch64leTargetMachine> X(TheAArch64leTarget);
103 RegisterTargetMachine<AArch64beTargetMachine> Y(TheAArch64beTarget);
104 RegisterTargetMachine<AArch64leTargetMachine> Z(TheARM64Target);
107 //===----------------------------------------------------------------------===//
108 // AArch64 Lowering public interface.
109 //===----------------------------------------------------------------------===//
110 static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) {
111 if (TT.isOSBinFormatMachO())
112 return make_unique<AArch64_MachoTargetObjectFile>();
114 return make_unique<AArch64_ELFTargetObjectFile>();
117 // Helper function to build a DataLayout string
118 static std::string computeDataLayout(const Triple &TT, bool LittleEndian) {
119 if (TT.isOSBinFormatMachO())
120 return "e-m:o-i64:64-i128:128-n32:64-S128";
122 return "e-m:e-i64:64-i128:128-n32:64-S128";
123 return "E-m:e-i64:64-i128:128-n32:64-S128";
126 /// TargetMachine ctor - Create an AArch64 architecture model.
128 AArch64TargetMachine::AArch64TargetMachine(const Target &T, const Triple &TT,
129 StringRef CPU, StringRef FS,
130 const TargetOptions &Options,
131 Reloc::Model RM, CodeModel::Model CM,
132 CodeGenOpt::Level OL,
134 // This nested ternary is horrible, but DL needs to be properly
135 // initialized before TLInfo is constructed.
136 : LLVMTargetMachine(T, computeDataLayout(Triple(TT), LittleEndian), TT, CPU,
137 FS, Options, RM, CM, OL),
138 TLOF(createTLOF(Triple(getTargetTriple()))),
139 isLittle(LittleEndian) {
143 AArch64TargetMachine::~AArch64TargetMachine() {}
145 const AArch64Subtarget *
146 AArch64TargetMachine::getSubtargetImpl(const Function &F) const {
147 Attribute CPUAttr = F.getFnAttribute("target-cpu");
148 Attribute FSAttr = F.getFnAttribute("target-features");
150 std::string CPU = !CPUAttr.hasAttribute(Attribute::None)
151 ? CPUAttr.getValueAsString().str()
153 std::string FS = !FSAttr.hasAttribute(Attribute::None)
154 ? FSAttr.getValueAsString().str()
157 auto &I = SubtargetMap[CPU + FS];
159 // This needs to be done before we create a new subtarget since any
160 // creation will depend on the TM and the code generation flags on the
161 // function that reside in TargetOptions.
162 resetTargetOptions(F);
163 I = llvm::make_unique<AArch64Subtarget>(Triple(TargetTriple), CPU, FS,
169 void AArch64leTargetMachine::anchor() { }
171 AArch64leTargetMachine::AArch64leTargetMachine(
172 const Target &T, const Triple &TT, StringRef CPU, StringRef FS,
173 const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM,
174 CodeGenOpt::Level OL)
175 : AArch64TargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {}
177 void AArch64beTargetMachine::anchor() { }
179 AArch64beTargetMachine::AArch64beTargetMachine(
180 const Target &T, const Triple &TT, StringRef CPU, StringRef FS,
181 const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM,
182 CodeGenOpt::Level OL)
183 : AArch64TargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {}
186 /// AArch64 Code Generator Pass Configuration Options.
187 class AArch64PassConfig : public TargetPassConfig {
189 AArch64PassConfig(AArch64TargetMachine *TM, PassManagerBase &PM)
190 : TargetPassConfig(TM, PM) {
191 if (TM->getOptLevel() != CodeGenOpt::None)
192 substitutePass(&PostRASchedulerID, &PostMachineSchedulerID);
195 AArch64TargetMachine &getAArch64TargetMachine() const {
196 return getTM<AArch64TargetMachine>();
199 void addIRPasses() override;
200 bool addPreISel() override;
201 bool addInstSelector() override;
202 bool addILPOpts() override;
203 void addPreRegAlloc() override;
204 void addPostRegAlloc() override;
205 void addPreSched2() override;
206 void addPreEmitPass() override;
210 TargetIRAnalysis AArch64TargetMachine::getTargetIRAnalysis() {
211 return TargetIRAnalysis([this](Function &F) {
212 return TargetTransformInfo(AArch64TTIImpl(this, F));
216 TargetPassConfig *AArch64TargetMachine::createPassConfig(PassManagerBase &PM) {
217 return new AArch64PassConfig(this, PM);
220 void AArch64PassConfig::addIRPasses() {
221 // Always expand atomic operations, we don't deal with atomicrmw or cmpxchg
223 addPass(createAtomicExpandPass(TM));
225 // Cmpxchg instructions are often used with a subsequent comparison to
226 // determine whether it succeeded. We can exploit existing control-flow in
227 // ldrex/strex loops to simplify this, but it needs tidying up.
228 if (TM->getOptLevel() != CodeGenOpt::None && EnableAtomicTidy)
229 addPass(createCFGSimplificationPass());
231 if (TM->getOptLevel() != CodeGenOpt::None && AArch64InterleavedAccessOpt)
232 addPass(createAArch64InterleavedAccessPass());
234 TargetPassConfig::addIRPasses();
236 if (TM->getOptLevel() == CodeGenOpt::Aggressive && EnableGEPOpt) {
237 // Call SeparateConstOffsetFromGEP pass to extract constants within indices
238 // and lower a GEP with multiple indices to either arithmetic operations or
239 // multiple GEPs with single index.
240 addPass(createSeparateConstOffsetFromGEPPass(TM, true));
241 // Call EarlyCSE pass to find and remove subexpressions in the lowered
243 addPass(createEarlyCSEPass());
244 // Do loop invariant code motion in case part of the lowered result is
246 addPass(createLICMPass());
250 // Pass Pipeline Configuration
251 bool AArch64PassConfig::addPreISel() {
252 // Run promote constant before global merge, so that the promoted constants
253 // get a chance to be merged
254 if (TM->getOptLevel() != CodeGenOpt::None && EnablePromoteConstant)
255 addPass(createAArch64PromoteConstantPass());
256 // FIXME: On AArch64, this depends on the type.
257 // Basically, the addressable offsets are up to 4095 * Ty.getSizeInBytes().
258 // and the offset has to be a multiple of the related size in bytes.
259 if ((TM->getOptLevel() != CodeGenOpt::None &&
260 EnableGlobalMerge == cl::BOU_UNSET) ||
261 EnableGlobalMerge == cl::BOU_TRUE) {
262 bool OnlyOptimizeForSize = (TM->getOptLevel() < CodeGenOpt::Aggressive) &&
263 (EnableGlobalMerge == cl::BOU_UNSET);
264 addPass(createGlobalMergePass(TM, 4095, OnlyOptimizeForSize));
267 if (TM->getOptLevel() != CodeGenOpt::None)
268 addPass(createAArch64AddressTypePromotionPass());
273 bool AArch64PassConfig::addInstSelector() {
274 addPass(createAArch64ISelDag(getAArch64TargetMachine(), getOptLevel()));
276 // For ELF, cleanup any local-dynamic TLS accesses (i.e. combine as many
277 // references to _TLS_MODULE_BASE_ as possible.
278 if (Triple(TM->getTargetTriple()).isOSBinFormatELF() &&
279 getOptLevel() != CodeGenOpt::None)
280 addPass(createAArch64CleanupLocalDynamicTLSPass());
285 bool AArch64PassConfig::addILPOpts() {
287 addPass(createAArch64ConditionOptimizerPass());
289 addPass(createAArch64ConditionalCompares());
291 addPass(&MachineCombinerID);
292 if (EnableEarlyIfConversion)
293 addPass(&EarlyIfConverterID);
294 if (EnableStPairSuppress)
295 addPass(createAArch64StorePairSuppressPass());
299 void AArch64PassConfig::addPreRegAlloc() {
300 // Use AdvSIMD scalar instructions whenever profitable.
301 if (TM->getOptLevel() != CodeGenOpt::None && EnableAdvSIMDScalar) {
302 addPass(createAArch64AdvSIMDScalar());
303 // The AdvSIMD pass may produce copies that can be rewritten to
304 // be register coaleascer friendly.
305 addPass(&PeepholeOptimizerID);
309 void AArch64PassConfig::addPostRegAlloc() {
310 // Change dead register definitions to refer to the zero register.
311 if (TM->getOptLevel() != CodeGenOpt::None && EnableDeadRegisterElimination)
312 addPass(createAArch64DeadRegisterDefinitions());
313 if (TM->getOptLevel() != CodeGenOpt::None && usingDefaultRegAlloc())
314 // Improve performance for some FP/SIMD code for A57.
315 addPass(createAArch64A57FPLoadBalancing());
318 void AArch64PassConfig::addPreSched2() {
319 // Expand some pseudo instructions to allow proper scheduling.
320 addPass(createAArch64ExpandPseudoPass());
321 // Use load/store pair instructions when possible.
322 if (TM->getOptLevel() != CodeGenOpt::None && EnableLoadStoreOpt)
323 addPass(createAArch64LoadStoreOptimizationPass());
326 void AArch64PassConfig::addPreEmitPass() {
327 if (EnableA53Fix835769)
328 addPass(createAArch64A53Fix835769());
329 // Relax conditional branch instructions if they're otherwise out of
330 // range of their destination.
331 addPass(createAArch64BranchRelaxation());
332 if (TM->getOptLevel() != CodeGenOpt::None && EnableCollectLOH &&
333 Triple(TM->getTargetTriple()).isOSBinFormatMachO())
334 addPass(createAArch64CollectLOHPass());