1 //===-- AArch64Subtarget.cpp - AArch64 Subtarget Information ----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the AArch64 specific subclass of TargetSubtarget.
12 //===----------------------------------------------------------------------===//
14 #include "AArch64InstrInfo.h"
15 #include "AArch64PBQPRegAlloc.h"
16 #include "AArch64Subtarget.h"
17 #include "llvm/ADT/SmallVector.h"
18 #include "llvm/CodeGen/MachineScheduler.h"
19 #include "llvm/IR/GlobalValue.h"
20 #include "llvm/Support/TargetRegistry.h"
24 #define DEBUG_TYPE "aarch64-subtarget"
26 #define GET_SUBTARGETINFO_CTOR
27 #define GET_SUBTARGETINFO_TARGET_DESC
28 #include "AArch64GenSubtargetInfo.inc"
31 EnableEarlyIfConvert("aarch64-early-ifcvt", cl::desc("Enable the early if "
32 "converter pass"), cl::init(true), cl::Hidden);
34 // If OS supports TBI, use this flag to enable it.
36 UseAddressTopByteIgnored("aarch64-use-tbi", cl::desc("Assume that top byte of "
37 "an address is ignored"), cl::init(false), cl::Hidden);
40 AArch64Subtarget::initializeSubtargetDependencies(StringRef FS) {
41 // Determine default and user-specified characteristics
43 if (CPUString.empty())
44 CPUString = "generic";
46 ParseSubtargetFeatures(CPUString, FS);
50 AArch64Subtarget::AArch64Subtarget(const Triple &TT, const std::string &CPU,
51 const std::string &FS,
52 const TargetMachine &TM, bool LittleEndian)
53 : AArch64GenSubtargetInfo(TT, CPU, FS), ARMProcFamily(Others),
54 HasV8_1aOps(false), HasFPARMv8(false), HasNEON(false), HasCrypto(false),
55 HasCRC(false), HasPerfMon(false), HasZeroCycleRegMove(false),
56 HasZeroCycleZeroing(false), StrictAlign(false), ReserveX18(false),
57 IsLittle(LittleEndian), CPUString(CPU), TargetTriple(TT), FrameLowering(),
58 InstrInfo(initializeSubtargetDependencies(FS)), TSInfo(),
61 /// ClassifyGlobalReference - Find the target operand flags that describe
62 /// how a global value should be referenced for the current subtarget.
64 AArch64Subtarget::ClassifyGlobalReference(const GlobalValue *GV,
65 const TargetMachine &TM) const {
66 bool isDef = GV->isStrongDefinitionForLinker();
68 // MachO large model always goes via a GOT, simply to get a single 8-byte
69 // absolute relocation on all global addresses.
70 if (TM.getCodeModel() == CodeModel::Large && isTargetMachO())
71 return AArch64II::MO_GOT;
73 // The small code mode's direct accesses use ADRP, which cannot necessarily
74 // produce the value 0 (if the code is above 4GB).
75 if (TM.getCodeModel() == CodeModel::Small && GV->hasExternalWeakLinkage()) {
76 // In PIC mode use the GOT, but in absolute mode use a constant pool load.
77 if (TM.getRelocationModel() == Reloc::Static)
78 return AArch64II::MO_CONSTPOOL;
80 return AArch64II::MO_GOT;
83 // If symbol visibility is hidden, the extra load is not needed if
84 // the symbol is definitely defined in the current translation unit.
86 // The handling of non-hidden symbols in PIC mode is rather target-dependent:
87 // + On MachO, if the symbol is defined in this module the GOT can be
89 // + On ELF, the R_AARCH64_COPY relocation means that even symbols actually
90 // defined could end up in unexpected places. Use a GOT.
91 if (TM.getRelocationModel() != Reloc::Static && GV->hasDefaultVisibility()) {
93 return isDef ? AArch64II::MO_NO_FLAG : AArch64II::MO_GOT;
95 // No need to go through the GOT for local symbols on ELF.
96 return GV->hasLocalLinkage() ? AArch64II::MO_NO_FLAG : AArch64II::MO_GOT;
99 return AArch64II::MO_NO_FLAG;
102 /// This function returns the name of a function which has an interface
103 /// like the non-standard bzero function, if such a function exists on
104 /// the current subtarget and it is considered prefereable over
105 /// memset with zero passed as the second argument. Otherwise it
107 const char *AArch64Subtarget::getBZeroEntry() const {
108 // Prefer bzero on Darwin only.
115 void AArch64Subtarget::overrideSchedPolicy(MachineSchedPolicy &Policy,
116 MachineInstr *begin, MachineInstr *end,
117 unsigned NumRegionInstrs) const {
118 // LNT run (at least on Cyclone) showed reasonably significant gains for
119 // bi-directional scheduling. 253.perlbmk.
120 Policy.OnlyTopDown = false;
121 Policy.OnlyBottomUp = false;
122 // Enabling or Disabling the latency heuristic is a close call: It seems to
123 // help nearly no benchmark on out-of-order architectures, on the other hand
124 // it regresses register pressure on a few benchmarking.
126 Policy.DisableLatencyHeuristic = true;
129 bool AArch64Subtarget::enableEarlyIfConversion() const {
130 return EnableEarlyIfConvert;
133 bool AArch64Subtarget::supportsAddressTopByteIgnored() const {
134 if (!UseAddressTopByteIgnored)
137 if (TargetTriple.isiOS()) {
138 unsigned Major, Minor, Micro;
139 TargetTriple.getiOSVersion(Major, Minor, Micro);
146 std::unique_ptr<PBQPRAConstraint>
147 AArch64Subtarget::getCustomPBQPConstraints() const {
151 return llvm::make_unique<A57ChainingConstraint>();