1 //=- AArch64SchedA57.td - ARM Cortex-A57 Scheduling Defs -----*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the machine model for ARM Cortex-A57 to support
11 // instruction scheduling and other instruction cost heuristics.
13 //===----------------------------------------------------------------------===//
15 //===----------------------------------------------------------------------===//
16 // The Cortex-A57 is a traditional superscaler microprocessor with a
17 // conservative 3-wide in-order stage for decode and dispatch. Combined with the
18 // much wider out-of-order issue stage, this produced a need to carefully
19 // schedule micro-ops so that all three decoded each cycle are successfully
20 // issued as the reservation station(s) simply don't stay occupied for long.
21 // Therefore, IssueWidth is set to the narrower of the two at three, while still
22 // modeling the machine as out-of-order.
24 def CortexA57Model : SchedMachineModel {
25 let IssueWidth = 3; // 3-way decode and dispatch
26 let MicroOpBufferSize = 128; // 128 micro-op re-order buffer
27 let LoadLatency = 4; // Optimistic load latency
28 let MispredictPenalty = 14; // Fetch + Decode/Rename/Dispatch + Branch
31 //===----------------------------------------------------------------------===//
32 // Define each kind of processor resource and number available on Cortex-A57.
33 // Cortex A-57 has 8 pipelines that each has its own 8-entry queue where
34 // micro-ops wait for their operands and then issue out-of-order.
36 def A57UnitB : ProcResource<1>; // Type B micro-ops
37 def A57UnitI : ProcResource<2>; // Type I micro-ops
38 def A57UnitM : ProcResource<1>; // Type M micro-ops
39 def A57UnitL : ProcResource<1>; // Type L micro-ops
40 def A57UnitS : ProcResource<1>; // Type S micro-ops
41 def A57UnitX : ProcResource<1>; // Type X micro-ops
42 def A57UnitW : ProcResource<1>; // Type W micro-ops
43 let SchedModel = CortexA57Model in {
44 def A57UnitV : ProcResGroup<[A57UnitX, A57UnitW]>; // Type V micro-ops
47 let SchedModel = CortexA57Model in {
49 //===----------------------------------------------------------------------===//
50 // Define customized scheduler read/write types specific to the Cortex-A57.
52 include "AArch64SchedA57WriteRes.td"
54 //===----------------------------------------------------------------------===//
55 // Map the target-defined scheduler read/write resources and latency for
56 // Cortex-A57. The Cortex-A57 types are directly associated with resources, so
57 // defining the aliases precludes the need for mapping them using WriteRes. The
58 // aliases are sufficient for creating a coarse, working model. As the model
59 // evolves, InstRWs will be used to override these SchedAliases.
61 def : SchedAlias<WriteImm, A57Write_1cyc_1I>;
62 def : SchedAlias<WriteI, A57Write_1cyc_1I>;
63 def : SchedAlias<WriteISReg, A57Write_2cyc_1M>;
64 def : SchedAlias<WriteIEReg, A57Write_2cyc_1M>;
65 def : SchedAlias<WriteExtr, A57Write_1cyc_1I>;
66 def : SchedAlias<WriteIS, A57Write_1cyc_1I>;
67 def : SchedAlias<WriteID32, A57Write_19cyc_1M>;
68 def : SchedAlias<WriteID64, A57Write_35cyc_1M>;
69 def : SchedAlias<WriteIM32, A57Write_3cyc_1M>;
70 def : SchedAlias<WriteIM64, A57Write_5cyc_1M>;
71 def : SchedAlias<WriteBr, A57Write_1cyc_1B>;
72 def : SchedAlias<WriteBrReg, A57Write_1cyc_1B>;
73 def : SchedAlias<WriteLD, A57Write_4cyc_1L>;
74 def : SchedAlias<WriteST, A57Write_1cyc_1S>;
75 def : SchedAlias<WriteSTP, A57Write_1cyc_1S>;
76 def : SchedAlias<WriteAdr, A57Write_1cyc_1I>;
77 def : SchedAlias<WriteLDIdx, A57Write_4cyc_1I_1L>;
78 def : SchedAlias<WriteSTIdx, A57Write_1cyc_1I_1S>;
79 def : SchedAlias<WriteF, A57Write_3cyc_1V>;
80 def : SchedAlias<WriteFCmp, A57Write_3cyc_1V>;
81 def : SchedAlias<WriteFCvt, A57Write_5cyc_1V>;
82 def : SchedAlias<WriteFCopy, A57Write_5cyc_1L>;
83 def : SchedAlias<WriteFImm, A57Write_3cyc_1V>;
84 def : SchedAlias<WriteFMul, A57Write_5cyc_1V>;
85 def : SchedAlias<WriteFDiv, A57Write_18cyc_1X>;
86 def : SchedAlias<WriteV, A57Write_3cyc_1V>;
87 def : SchedAlias<WriteVLD, A57Write_5cyc_1L>;
88 def : SchedAlias<WriteVST, A57Write_1cyc_1S>;
90 def : WriteRes<WriteSys, []> { let Latency = 1; }
91 def : WriteRes<WriteBarrier, []> { let Latency = 1; }
92 def : WriteRes<WriteHint, []> { let Latency = 1; }
94 def : WriteRes<WriteLDHi, []> { let Latency = 4; }
96 // Forwarding logic is only modeled for multiply and accumulate
97 def : ReadAdvance<ReadI, 0>;
98 def : ReadAdvance<ReadISReg, 0>;
99 def : ReadAdvance<ReadIEReg, 0>;
100 def : ReadAdvance<ReadIM, 0>;
101 def : ReadAdvance<ReadIMA, 2, [WriteIM32, WriteIM64]>;
102 def : ReadAdvance<ReadID, 0>;
103 def : ReadAdvance<ReadExtrHi, 0>;
104 def : ReadAdvance<ReadAdrBase, 0>;
105 def : ReadAdvance<ReadVLD, 0>;
108 //===----------------------------------------------------------------------===//
109 // Specialize the coarse model by associating instruction groups with the
110 // subtarget-defined types. As the modeled is refined, this will override most
111 // of the above ShchedAlias mappings.
114 // -----------------------------------------------------------------------------
116 def : InstRW<[WriteI], (instrs COPY)>;
119 // Branch Instructions
120 // -----------------------------------------------------------------------------
122 def : InstRW<[A57Write_1cyc_1B_1I], (instrs BL)>;
123 def : InstRW<[A57Write_2cyc_1B_1I], (instrs BLR)>;
126 // Divide and Multiply Instructions
127 // -----------------------------------------------------------------------------
130 def : InstRW<[A57Write_6cyc_1M], (instrs SMULHrr, UMULHrr)>;
133 // Miscellaneous Data-Processing Instructions
134 // -----------------------------------------------------------------------------
136 def : InstRW<[A57Write_1cyc_1I], (instrs EXTRWrri)>;
137 def : InstRW<[A57Write_3cyc_1I_1M], (instrs EXTRXrri)>;
138 def : InstRW<[A57Write_2cyc_1M], (instregex "BFM")>;
141 // Cryptography Extensions
142 // -----------------------------------------------------------------------------
144 def : InstRW<[A57Write_3cyc_1W], (instregex "^AES")>;
145 def : InstRW<[A57Write_6cyc_2V], (instregex "^SHA1SU0")>;
146 def : InstRW<[A57Write_3cyc_1W], (instregex "^SHA1(H|SU1)")>;
147 def : InstRW<[A57Write_6cyc_2W], (instregex "^SHA1[CMP]")>;
148 def : InstRW<[A57Write_3cyc_1W], (instregex "^SHA256SU0")>;
149 def : InstRW<[A57Write_6cyc_2W], (instregex "^SHA256(H|H2|SU1)")>;
150 def : InstRW<[A57Write_3cyc_1W], (instregex "^CRC32")>;
154 // -----------------------------------------------------------------------------
156 def : InstRW<[A57Write_8cyc_1L_1V], (instregex "LD1i(8|16|32)$")>;
157 def : InstRW<[A57Write_8cyc_1L_1V, WriteAdr], (instregex "LD1i(8|16|32)_POST$")>;
158 def : InstRW<[A57Write_5cyc_1L], (instregex "LD1i(64)$")>;
159 def : InstRW<[A57Write_5cyc_1L, WriteAdr], (instregex "LD1i(64)_POST$")>;
161 def : InstRW<[A57Write_8cyc_1L_1V], (instregex "LD1Rv(8b|4h|2s)$")>;
162 def : InstRW<[A57Write_8cyc_1L_1V, WriteAdr], (instregex "LD1Rv(8b|4h|2s)_POST$")>;
163 def : InstRW<[A57Write_5cyc_1L], (instregex "LD1Rv(1d)$")>;
164 def : InstRW<[A57Write_5cyc_1L, WriteAdr], (instregex "LD1Rv(1d)_POST$")>;
165 def : InstRW<[A57Write_8cyc_1L_1V], (instregex "LD1Rv(16b|8h|4s|2d)$")>;
166 def : InstRW<[A57Write_8cyc_1L_1V, WriteAdr], (instregex "LD1Rv(16b|8h|4s|2d)_POST$")>;
168 def : InstRW<[A57Write_5cyc_1L], (instregex "LD1Onev(8b|4h|2s|1d)$")>;
169 def : InstRW<[A57Write_5cyc_1L, WriteAdr], (instregex "LD1Onev(8b|4h|2s|1d)_POST$")>;
170 def : InstRW<[A57Write_5cyc_1L], (instregex "LD1Onev(16b|8h|4s|2d)$")>;
171 def : InstRW<[A57Write_5cyc_1L, WriteAdr], (instregex "LD1Onev(16b|8h|4s|2d)_POST$")>;
172 def : InstRW<[A57Write_5cyc_1L], (instregex "LD1Twov(8b|4h|2s|1d)$")>;
173 def : InstRW<[A57Write_5cyc_1L, WriteAdr], (instregex "LD1Twov(8b|4h|2s|1d)_POST$")>;
174 def : InstRW<[A57Write_6cyc_2L], (instregex "LD1Twov(16b|8h|4s|2d)$")>;
175 def : InstRW<[A57Write_6cyc_2L, WriteAdr], (instregex "LD1Twov(16b|8h|4s|2d)_POST$")>;
176 def : InstRW<[A57Write_6cyc_2L], (instregex "LD1Threev(8b|4h|2s|1d)$")>;
177 def : InstRW<[A57Write_6cyc_2L, WriteAdr], (instregex "LD1Threev(8b|4h|2s|1d)_POST$")>;
178 def : InstRW<[A57Write_7cyc_3L], (instregex "LD1Threev(16b|8h|4s|2d)$")>;
179 def : InstRW<[A57Write_7cyc_3L, WriteAdr], (instregex "LD1Threev(16b|8h|4s|2d)_POST$")>;
180 def : InstRW<[A57Write_6cyc_2L], (instregex "LD1Fourv(8b|4h|2s|1d)$")>;
181 def : InstRW<[A57Write_6cyc_2L, WriteAdr], (instregex "LD1Fourv(8b|4h|2s|1d)_POST$")>;
182 def : InstRW<[A57Write_8cyc_4L], (instregex "LD1Fourv(16b|8h|4s|2d)$")>;
183 def : InstRW<[A57Write_8cyc_4L, WriteAdr], (instregex "LD1Fourv(16b|8h|4s|2d)_POST$")>;
185 def : InstRW<[A57Write_8cyc_1L_2V], (instregex "LD2i(8|16)$")>;
186 def : InstRW<[A57Write_8cyc_1L_2V, WriteAdr], (instregex "LD2i(8|16)_POST$")>;
187 def : InstRW<[A57Write_6cyc_2L], (instregex "LD2i(32)$")>;
188 def : InstRW<[A57Write_6cyc_2L, WriteAdr], (instregex "LD2i(32)_POST$")>;
189 def : InstRW<[A57Write_8cyc_1L_1V], (instregex "LD2i(64)$")>;
190 def : InstRW<[A57Write_8cyc_1L_1V, WriteAdr], (instregex "LD2i(64)_POST$")>;
192 def : InstRW<[A57Write_8cyc_1L_1V], (instregex "LD2Rv(8b|4h|2s)$")>;
193 def : InstRW<[A57Write_8cyc_1L_1V, WriteAdr], (instregex "LD2Rv(8b|4h|2s)_POST$")>;
194 def : InstRW<[A57Write_5cyc_1L], (instregex "LD2Rv(1d)$")>;
195 def : InstRW<[A57Write_5cyc_1L, WriteAdr], (instregex "LD2Rv(1d)_POST$")>;
196 def : InstRW<[A57Write_8cyc_1L_2V], (instregex "LD2Rv(16b|8h|4s|2d)$")>;
197 def : InstRW<[A57Write_8cyc_1L_2V, WriteAdr], (instregex "LD2Rv(16b|8h|4s|2d)_POST$")>;
199 def : InstRW<[A57Write_8cyc_1L_1V], (instregex "LD2Twov(8b|4h|2s)$")>;
200 def : InstRW<[A57Write_8cyc_1L_1V, WriteAdr], (instregex "LD2Twov(8b|4h|2s)_POST$")>;
201 def : InstRW<[A57Write_9cyc_2L_2V], (instregex "LD2Twov(16b|8h|4s)$")>;
202 def : InstRW<[A57Write_9cyc_2L_2V, WriteAdr], (instregex "LD2Twov(16b|8h|4s)_POST$")>;
203 def : InstRW<[A57Write_6cyc_2L], (instregex "LD2Twov(2d)$")>;
204 def : InstRW<[A57Write_6cyc_2L, WriteAdr], (instregex "LD2Twov(2d)_POST$")>;
206 def : InstRW<[A57Write_9cyc_1L_3V], (instregex "LD3i(8|16)$")>;
207 def : InstRW<[A57Write_9cyc_1L_3V, WriteAdr], (instregex "LD3i(8|16)_POST$")>;
208 def : InstRW<[A57Write_8cyc_1L_2V], (instregex "LD3i(32)$")>;
209 def : InstRW<[A57Write_8cyc_1L_2V, WriteAdr], (instregex "LD3i(32)_POST$")>;
210 def : InstRW<[A57Write_6cyc_2L], (instregex "LD3i(64)$")>;
211 def : InstRW<[A57Write_6cyc_2L, WriteAdr], (instregex "LD3i(64)_POST$")>;
213 def : InstRW<[A57Write_8cyc_1L_2V], (instregex "LD3Rv(8b|4h|2s)$")>;
214 def : InstRW<[A57Write_8cyc_1L_2V, WriteAdr], (instregex "LD3Rv(8b|4h|2s)_POST$")>;
215 def : InstRW<[A57Write_6cyc_2L], (instregex "LD3Rv(1d)$")>;
216 def : InstRW<[A57Write_6cyc_2L, WriteAdr], (instregex "LD3Rv(1d)_POST$")>;
217 def : InstRW<[A57Write_9cyc_1L_3V], (instregex "LD3Rv(16b|8h|4s)$")>;
218 def : InstRW<[A57Write_9cyc_1L_3V, WriteAdr], (instregex "LD3Rv(16b|8h|4s)_POST$")>;
219 def : InstRW<[A57Write_9cyc_2L_3V], (instregex "LD3Rv(2d)$")>;
220 def : InstRW<[A57Write_9cyc_2L_3V, WriteAdr], (instregex "LD3Rv(2d)_POST$")>;
222 def : InstRW<[A57Write_9cyc_2L_2V], (instregex "LD3Threev(8b|4h|2s)$")>;
223 def : InstRW<[A57Write_9cyc_2L_2V, WriteAdr], (instregex "LD3Threev(8b|4h|2s)_POST$")>;
224 def : InstRW<[A57Write_10cyc_3L_4V], (instregex "LD3Threev(16b|8h|4s)$")>;
225 def : InstRW<[A57Write_10cyc_3L_4V, WriteAdr], (instregex "LD3Threev(16b|8h|4s)_POST$")>;
226 def : InstRW<[A57Write_8cyc_4L], (instregex "LD3Threev(2d)$")>;
227 def : InstRW<[A57Write_8cyc_4L, WriteAdr], (instregex "LD3Threev(2d)_POST$")>;
229 def : InstRW<[A57Write_9cyc_2L_3V], (instregex "LD4i(8|16)$")>;
230 def : InstRW<[A57Write_9cyc_2L_3V, WriteAdr], (instregex "LD4i(8|16)_POST$")>;
231 def : InstRW<[A57Write_8cyc_1L_2V], (instregex "LD4i(32)$")>;
232 def : InstRW<[A57Write_8cyc_1L_2V, WriteAdr], (instregex "LD4i(32)_POST$")>;
233 def : InstRW<[A57Write_9cyc_2L_3V], (instregex "LD4i(64)$")>;
234 def : InstRW<[A57Write_9cyc_2L_3V, WriteAdr], (instregex "LD4i(64)_POST$")>;
236 def : InstRW<[A57Write_8cyc_1L_2V], (instregex "LD4Rv(8b|4h|2s)$")>;
237 def : InstRW<[A57Write_8cyc_1L_2V, WriteAdr], (instregex "LD4Rv(8b|4h|2s)_POST$")>;
238 def : InstRW<[A57Write_6cyc_2L], (instregex "LD4Rv(1d)$")>;
239 def : InstRW<[A57Write_6cyc_2L, WriteAdr], (instregex "LD4Rv(1d)_POST$")>;
240 def : InstRW<[A57Write_9cyc_2L_3V], (instregex "LD4Rv(16b|8h|4s)$")>;
241 def : InstRW<[A57Write_9cyc_2L_3V, WriteAdr], (instregex "LD4Rv(16b|8h|4s)_POST$")>;
242 def : InstRW<[A57Write_9cyc_2L_4V], (instregex "LD4Rv(2d)$")>;
243 def : InstRW<[A57Write_9cyc_2L_4V, WriteAdr], (instregex "LD4Rv(2d)_POST$")>;
245 def : InstRW<[A57Write_9cyc_2L_2V], (instregex "LD4Fourv(8b|4h|2s)$")>;
246 def : InstRW<[A57Write_9cyc_2L_2V, WriteAdr], (instregex "LD4Fourv(8b|4h|2s)_POST$")>;
247 def : InstRW<[A57Write_11cyc_4L_4V], (instregex "LD4Fourv(16b|8h|4s)$")>;
248 def : InstRW<[A57Write_11cyc_4L_4V, WriteAdr], (instregex "LD4Fourv(16b|8h|4s)_POST$")>;
249 def : InstRW<[A57Write_8cyc_4L], (instregex "LD4Fourv(2d)$")>;
250 def : InstRW<[A57Write_8cyc_4L, WriteAdr], (instregex "LD4Fourv(2d)_POST$")>;
253 // -----------------------------------------------------------------------------
255 def : InstRW<[A57Write_1cyc_1S], (instregex "ST1i(8|16|32)$")>;
256 def : InstRW<[A57Write_1cyc_1S, WriteAdr], (instregex "ST1i(8|16|32)_POST$")>;
257 def : InstRW<[A57Write_3cyc_1S_1V], (instregex "ST1i(64)$")>;
258 def : InstRW<[A57Write_3cyc_1S_1V, WriteAdr], (instregex "ST1i(64)_POST$")>;
260 def : InstRW<[A57Write_1cyc_1S], (instregex "ST1Onev(8b|4h|2s|1d)$")>;
261 def : InstRW<[A57Write_1cyc_1S, WriteAdr], (instregex "ST1Onev(8b|4h|2s|1d)_POST$")>;
262 def : InstRW<[A57Write_2cyc_2S], (instregex "ST1Onev(16b|8h|4s|2d)$")>;
263 def : InstRW<[A57Write_2cyc_2S, WriteAdr], (instregex "ST1Onev(16b|8h|4s|2d)_POST$")>;
264 def : InstRW<[A57Write_2cyc_2S], (instregex "ST1Twov(8b|4h|2s|1d)$")>;
265 def : InstRW<[A57Write_2cyc_2S, WriteAdr], (instregex "ST1Twov(8b|4h|2s|1d)_POST$")>;
266 def : InstRW<[A57Write_4cyc_4S], (instregex "ST1Twov(16b|8h|4s|2d)$")>;
267 def : InstRW<[A57Write_4cyc_4S, WriteAdr], (instregex "ST1Twov(16b|8h|4s|2d)_POST$")>;
268 def : InstRW<[A57Write_3cyc_3S], (instregex "ST1Threev(8b|4h|2s|1d)$")>;
269 def : InstRW<[A57Write_3cyc_3S, WriteAdr], (instregex "ST1Threev(8b|4h|2s|1d)_POST$")>;
270 def : InstRW<[A57Write_6cyc_6S], (instregex "ST1Threev(16b|8h|4s|2d)$")>;
271 def : InstRW<[A57Write_6cyc_6S, WriteAdr], (instregex "ST1Threev(16b|8h|4s|2d)_POST$")>;
272 def : InstRW<[A57Write_4cyc_4S], (instregex "ST1Fourv(8b|4h|2s|1d)$")>;
273 def : InstRW<[A57Write_4cyc_4S, WriteAdr], (instregex "ST1Fourv(8b|4h|2s|1d)_POST$")>;
274 def : InstRW<[A57Write_8cyc_8S], (instregex "ST1Fourv(16b|8h|4s|2d)$")>;
275 def : InstRW<[A57Write_8cyc_8S, WriteAdr], (instregex "ST1Fourv(16b|8h|4s|2d)_POST$")>;
277 def : InstRW<[A57Write_3cyc_1S_1V], (instregex "ST2i(8|16|32)$")>;
278 def : InstRW<[A57Write_3cyc_1S_1V, WriteAdr], (instregex "ST2i(8|16|32)_POST$")>;
279 def : InstRW<[A57Write_2cyc_2S], (instregex "ST2i(64)$")>;
280 def : InstRW<[A57Write_2cyc_2S, WriteAdr], (instregex "ST2i(64)_POST$")>;
282 def : InstRW<[A57Write_3cyc_2S_1V], (instregex "ST2Twov(8b|4h|2s)$")>;
283 def : InstRW<[A57Write_3cyc_2S_1V, WriteAdr], (instregex "ST2Twov(8b|4h|2s)_POST$")>;
284 def : InstRW<[A57Write_4cyc_4S_2V], (instregex "ST2Twov(16b|8h|4s)$")>;
285 def : InstRW<[A57Write_4cyc_4S_2V, WriteAdr], (instregex "ST2Twov(16b|8h|4s)_POST$")>;
286 def : InstRW<[A57Write_4cyc_4S], (instregex "ST2Twov(2d)$")>;
287 def : InstRW<[A57Write_4cyc_4S, WriteAdr], (instregex "ST2Twov(2d)_POST$")>;
289 def : InstRW<[A57Write_3cyc_1S_1V], (instregex "ST3i(8|16)$")>;
290 def : InstRW<[A57Write_3cyc_1S_1V, WriteAdr], (instregex "ST3i(8|16)_POST$")>;
291 def : InstRW<[A57Write_3cyc_3S], (instregex "ST3i(32)$")>;
292 def : InstRW<[A57Write_3cyc_3S, WriteAdr], (instregex "ST3i(32)_POST$")>;
293 def : InstRW<[A57Write_3cyc_2S_1V], (instregex "ST3i(64)$")>;
294 def : InstRW<[A57Write_3cyc_2S_1V, WriteAdr], (instregex "ST3i(64)_POST$")>;
296 def : InstRW<[A57Write_3cyc_3S_2V], (instregex "ST3Threev(8b|4h|2s)$")>;
297 def : InstRW<[A57Write_3cyc_3S_2V, WriteAdr], (instregex "ST3Threev(8b|4h|2s)_POST$")>;
298 def : InstRW<[A57Write_6cyc_6S_4V], (instregex "ST3Threev(16b|8h|4s)$")>;
299 def : InstRW<[A57Write_6cyc_6S_4V, WriteAdr], (instregex "ST3Threev(16b|8h|4s)_POST$")>;
300 def : InstRW<[A57Write_6cyc_6S], (instregex "ST3Threev(2d)$")>;
301 def : InstRW<[A57Write_6cyc_6S, WriteAdr], (instregex "ST3Threev(2d)_POST$")>;
303 def : InstRW<[A57Write_3cyc_1S_1V], (instregex "ST4i(8|16)$")>;
304 def : InstRW<[A57Write_3cyc_1S_1V, WriteAdr], (instregex "ST4i(8|16)_POST$")>;
305 def : InstRW<[A57Write_4cyc_4S], (instregex "ST4i(32)$")>;
306 def : InstRW<[A57Write_4cyc_4S, WriteAdr], (instregex "ST4i(32)_POST$")>;
307 def : InstRW<[A57Write_3cyc_2S_1V], (instregex "ST4i(64)$")>;
308 def : InstRW<[A57Write_3cyc_2S_1V, WriteAdr], (instregex "ST4i(64)_POST$")>;
310 def : InstRW<[A57Write_4cyc_4S_2V], (instregex "ST4Fourv(8b|4h|2s)$")>;
311 def : InstRW<[A57Write_4cyc_4S_2V, WriteAdr], (instregex "ST4Fourv(8b|4h|2s)_POST$")>;
312 def : InstRW<[A57Write_8cyc_8S_4V], (instregex "ST4Fourv(16b|8h|4s)$")>;
313 def : InstRW<[A57Write_8cyc_8S_4V, WriteAdr], (instregex "ST4Fourv(16b|8h|4s)_POST$")>;
314 def : InstRW<[A57Write_8cyc_8S], (instregex "ST4Fourv(2d)$")>;
315 def : InstRW<[A57Write_8cyc_8S, WriteAdr], (instregex "ST4Fourv(2d)_POST$")>;
318 // -----------------------------------------------------------------------------
320 // Reference for forms in this group
321 // D form - v8i8, v4i16, v2i32
322 // Q form - v16i8, v8i16, v4i32
323 // D form - v1i8, v1i16, v1i32, v1i64
324 // Q form - v16i8, v8i16, v4i32, v2i64
325 // D form - v8i8_v8i16, v4i16_v4i32, v2i32_v2i64
326 // Q form - v16i8_v8i16, v8i16_v4i32, v4i32_v2i64
328 // ASIMD absolute diff accum, D-form
329 def : InstRW<[A57Write_4cyc_1X], (instregex "^[SU]ABA(v8i8|v4i16|v2i32)$")>;
330 // ASIMD absolute diff accum, Q-form
331 def : InstRW<[A57Write_5cyc_2X], (instregex "^[SU]ABA(v16i8|v8i16|v4i32)$")>;
332 // ASIMD absolute diff accum long
333 def : InstRW<[A57Write_4cyc_1X], (instregex "^[SU]ABAL")>;
335 // ASIMD arith, reduce, 4H/4S
336 def : InstRW<[A57Write_4cyc_1X], (instregex "^[SU]?ADDL?V(v8i8|v4i16|v2i32)v$")>;
337 // ASIMD arith, reduce, 8B/8H
338 def : InstRW<[A57Write_7cyc_1V_1X], (instregex "^[SU]?ADDL?V(v8i16|v4i32)v$")>;
339 // ASIMD arith, reduce, 16B
340 def : InstRW<[A57Write_8cyc_2X], (instregex "^[SU]?ADDL?Vv16i8v$")>;
342 // ASIMD max/min, reduce, 4H/4S
343 def : InstRW<[A57Write_4cyc_1X], (instregex "^[SU](MIN|MAX)V(v4i16|v4i32)v$")>;
344 // ASIMD max/min, reduce, 8B/8H
345 def : InstRW<[A57Write_7cyc_1V_1X], (instregex "^[SU](MIN|MAX)V(v8i8|v8i16)v$")>;
346 // ASIMD max/min, reduce, 16B
347 def : InstRW<[A57Write_8cyc_2X], (instregex "^[SU](MIN|MAX)Vv16i8v$")>;
349 // ASIMD multiply, D-form
350 def : InstRW<[A57Write_5cyc_1W], (instregex "^(P?MUL|SQR?DMULH)(v8i8|v4i16|v2i32|v1i8|v1i16|v1i32|v1i64)(_indexed)?$")>;
351 // ASIMD multiply, Q-form
352 def : InstRW<[A57Write_6cyc_2W], (instregex "^(P?MUL|SQR?DMULH)(v16i8|v8i16|v4i32)(_indexed)?$")>;
354 // ASIMD multiply accumulate, D-form
355 def : InstRW<[A57Write_5cyc_1W], (instregex "^ML[AS](v8i8|v4i16|v2i32)(_indexed)?$")>;
356 // ASIMD multiply accumulate, Q-form
357 def : InstRW<[A57Write_6cyc_2W], (instregex "^ML[AS](v16i8|v8i16|v4i32)(_indexed)?$")>;
359 // ASIMD multiply accumulate long
360 // ASIMD multiply accumulate saturating long
361 def A57WriteIVMA : SchedWriteRes<[A57UnitW]> { let Latency = 5; }
362 def A57ReadIVMA4 : SchedReadAdvance<4, [A57WriteIVMA]>;
363 def : InstRW<[A57WriteIVMA, A57ReadIVMA4], (instregex "^(S|U|SQD)ML[AS]L")>;
365 // ASIMD multiply long
366 def : InstRW<[A57Write_5cyc_1W], (instregex "^(S|U|SQD)MULL")>;
367 def : InstRW<[A57Write_5cyc_1W], (instregex "^PMULL(v8i8|v16i8)")>;
368 def : InstRW<[A57Write_3cyc_1W], (instregex "^PMULL(v1i64|v2i64)")>;
370 // ASIMD pairwise add and accumulate
371 // ASIMD shift accumulate
372 def A57WriteIVA : SchedWriteRes<[A57UnitX]> { let Latency = 4; }
373 def A57ReadIVA3 : SchedReadAdvance<3, [A57WriteIVA]>;
374 def : InstRW<[A57WriteIVA, A57ReadIVA3], (instregex "^[SU]ADALP")>;
375 def : InstRW<[A57WriteIVA, A57ReadIVA3], (instregex "^(S|SR|U|UR)SRA")>;
377 // ASIMD shift by immed, complex
378 def : InstRW<[A57Write_4cyc_1X], (instregex "^[SU]?(Q|R){1,2}SHR")>;
379 def : InstRW<[A57Write_4cyc_1X], (instregex "^SQSHLU")>;
382 // ASIMD shift by register, basic, Q-form
383 def : InstRW<[A57Write_4cyc_2X], (instregex "^[SU]SHL(v16i8|v8i16|v4i32|v2i64)")>;
385 // ASIMD shift by register, complex, D-form
386 def : InstRW<[A57Write_4cyc_1X], (instregex "^[SU][QR]{1,2}SHL(v1i8|v1i16|v1i32|v1i64|v8i8|v4i16|v2i32|b|d|h|s)")>;
388 // ASIMD shift by register, complex, Q-form
389 def : InstRW<[A57Write_5cyc_2X], (instregex "^[SU][QR]{1,2}SHL(v16i8|v8i16|v4i32|v2i64)")>;
392 // Vector - Floating Point
393 // -----------------------------------------------------------------------------
395 // Reference for forms in this group
397 // Q form - v4f32, v2f64
399 // D form - v1i32, v1i64
401 // Q form - v4i32, v2i64
403 // ASIMD FP arith, normal, D-form
404 def : InstRW<[A57Write_5cyc_1V], (instregex "^(FABD|FADD|FSUB)(v2f32|32|64|v2i32p)")>;
405 // ASIMD FP arith, normal, Q-form
406 def : InstRW<[A57Write_5cyc_2V], (instregex "^(FABD|FADD|FSUB)(v4f32|v2f64|v2i64p)")>;
408 // ASIMD FP arith, pairwise, D-form
409 def : InstRW<[A57Write_5cyc_1V], (instregex "^FADDP(v2f32|32|64|v2i32)")>;
410 // ASIMD FP arith, pairwise, Q-form
411 def : InstRW<[A57Write_9cyc_3V], (instregex "^FADDP(v4f32|v2f64|v2i64)")>;
413 // ASIMD FP compare, D-form
414 def : InstRW<[A57Write_5cyc_1V], (instregex "^(FACGE|FACGT|FCMEQ|FCMGE|FCMGT|FCMLE|FCMLT)(v2f32|32|64|v1i32|v2i32|v1i64)")>;
415 // ASIMD FP compare, Q-form
416 def : InstRW<[A57Write_5cyc_2V], (instregex "^(FACGE|FACGT|FCMEQ|FCMGE|FCMGT|FCMLE|FCMLT)(v4f32|v2f64|v4i32|v2i64)")>;
418 // ASIMD FP convert, long and narrow
419 def : InstRW<[A57Write_8cyc_3V], (instregex "^FCVT(L|N|XN)v")>;
420 // ASIMD FP convert, other, D-form
421 def : InstRW<[A57Write_5cyc_1V], (instregex "^[FVSU]CVT([AMNPZ][SU])?(_Int)?(v2f32|v1i32|v2i32|v1i64)")>;
422 // ASIMD FP convert, other, Q-form
423 def : InstRW<[A57Write_5cyc_2V], (instregex "^[FVSU]CVT([AMNPZ][SU])?(_Int)?(v4f32|v2f64|v4i32|v2i64)")>;
425 // ASIMD FP divide, D-form, F32
426 def : InstRW<[A57Write_18cyc_1X], (instregex "FDIVv2f32")>;
427 // ASIMD FP divide, Q-form, F32
428 def : InstRW<[A57Write_36cyc_2X], (instregex "FDIVv4f32")>;
429 // ASIMD FP divide, Q-form, F64
430 def : InstRW<[A57Write_64cyc_2X], (instregex "FDIVv2f64")>;
432 // Note: These were simply duplicated from ASIMD FDIV because of missing documentation
433 // ASIMD FP square root, D-form, F32
434 def : InstRW<[A57Write_18cyc_1X], (instregex "FSQRTv2f32")>;
435 // ASIMD FP square root, Q-form, F32
436 def : InstRW<[A57Write_36cyc_2X], (instregex "FSQRTv4f32")>;
437 // ASIMD FP square root, Q-form, F64
438 def : InstRW<[A57Write_64cyc_2X], (instregex "FSQRTv2f64")>;
440 // ASIMD FP max/min, normal, D-form
441 def : InstRW<[A57Write_5cyc_1V], (instregex "^(FMAX|FMIN)(NM)?(v2f32)")>;
442 // ASIMD FP max/min, normal, Q-form
443 def : InstRW<[A57Write_5cyc_2V], (instregex "^(FMAX|FMIN)(NM)?(v4f32|v2f64)")>;
444 // ASIMD FP max/min, pairwise, D-form
445 def : InstRW<[A57Write_5cyc_1V], (instregex "^(FMAX|FMIN)(NM)?P(v2f32|v2i32)")>;
446 // ASIMD FP max/min, pairwise, Q-form
447 def : InstRW<[A57Write_9cyc_3V], (instregex "^(FMAX|FMIN)(NM)?P(v4f32|v2f64|v2i64)")>;
448 // ASIMD FP max/min, reduce
449 def : InstRW<[A57Write_10cyc_3V], (instregex "^(FMAX|FMIN)(NM)?Vv")>;
451 // ASIMD FP multiply, D-form, FZ
452 def : InstRW<[A57Write_5cyc_1V], (instregex "^FMULX?(v2f32|v1i32|v2i32|v1i64|32|64)")>;
453 // ASIMD FP multiply, Q-form, FZ
454 def : InstRW<[A57Write_5cyc_2V], (instregex "^FMULX?(v4f32|v2f64|v4i32|v2i64)")>;
456 // ASIMD FP multiply accumulate, D-form, FZ
457 // ASIMD FP multiply accumulate, Q-form, FZ
458 def A57WriteFPVMAD : SchedWriteRes<[A57UnitV]> { let Latency = 9; }
459 def A57WriteFPVMAQ : SchedWriteRes<[A57UnitV, A57UnitV]> { let Latency = 10; }
460 def A57ReadFPVMA5 : SchedReadAdvance<5, [A57WriteFPVMAD, A57WriteFPVMAQ]>;
461 def : InstRW<[A57WriteFPVMAD, A57ReadFPVMA5], (instregex "^FML[AS](v2f32|v1i32|v2i32|v1i64)")>;
462 def : InstRW<[A57WriteFPVMAQ, A57ReadFPVMA5], (instregex "^FML[AS](v4f32|v2f64|v4i32|v2i64)")>;
464 // ASIMD FP round, D-form
465 def : InstRW<[A57Write_5cyc_1V], (instregex "^FRINT[AIMNPXZ](v2f32)")>;
466 // ASIMD FP round, Q-form
467 def : InstRW<[A57Write_5cyc_2V], (instregex "^FRINT[AIMNPXZ](v4f32|v2f64)")>;
470 // Vector - Miscellaneous
471 // -----------------------------------------------------------------------------
473 // Reference for forms in this group
474 // D form - v8i8, v4i16, v2i32
475 // Q form - v16i8, v8i16, v4i32
476 // D form - v1i8, v1i16, v1i32, v1i64
477 // Q form - v16i8, v8i16, v4i32, v2i64
479 // ASIMD bitwise insert, Q-form
480 def : InstRW<[A57Write_3cyc_2V], (instregex "^(BIF|BIT|BSL)v16i8")>;
482 // ASIMD duplicate, gen reg, D-form and Q-form
483 def : InstRW<[A57Write_8cyc_1L_1V], (instregex "^CPY")>;
484 def : InstRW<[A57Write_8cyc_1L_1V], (instregex "^DUPv.+gpr")>;
486 // ASIMD move, saturating
487 def : InstRW<[A57Write_4cyc_1X], (instregex "^[SU]QXTU?N")>;
489 // ASIMD reciprocal estimate, D-form
490 def : InstRW<[A57Write_5cyc_1V], (instregex "^[FU](RECP|RSQRT)(E|X)(v2f32|v1i32|v2i32|v1i64)")>;
491 // ASIMD reciprocal estimate, Q-form
492 def : InstRW<[A57Write_5cyc_2V], (instregex "^[FU](RECP|RSQRT)(E|X)(v2f64|v4f32|v4i32)")>;
494 // ASIMD reciprocal step, D-form, FZ
495 def : InstRW<[A57Write_9cyc_1V], (instregex "^F(RECP|RSQRT)S(v2f32|v1i32|v2i32|v1i64|32|64)")>;
496 // ASIMD reciprocal step, Q-form, FZ
497 def : InstRW<[A57Write_9cyc_2V], (instregex "^F(RECP|RSQRT)S(v2f64|v4f32|v4i32)")>;
499 // ASIMD table lookup, D-form
500 def : InstRW<[A57Write_3cyc_1V], (instregex "^TB[LX]v8i8One")>;
501 def : InstRW<[A57Write_6cyc_2V], (instregex "^TB[LX]v8i8Two")>;
502 def : InstRW<[A57Write_9cyc_3V], (instregex "^TB[LX]v8i8Three")>;
503 def : InstRW<[A57Write_12cyc_4V], (instregex "^TB[LX]v8i8Four")>;
504 // ASIMD table lookup, Q-form
505 def : InstRW<[A57Write_6cyc_3V], (instregex "^TB[LX]v16i8One")>;
506 def : InstRW<[A57Write_9cyc_5V], (instregex "^TB[LX]v16i8Two")>;
507 def : InstRW<[A57Write_12cyc_7V], (instregex "^TB[LX]v16i8Three")>;
508 def : InstRW<[A57Write_15cyc_9V], (instregex "^TB[LX]v16i8Four")>;
510 // ASIMD transfer, element to gen reg
511 def : InstRW<[A57Write_6cyc_1I_1L], (instregex "^[SU]MOVv")>;
513 // ASIMD transfer, gen reg to element
514 def : InstRW<[A57Write_8cyc_1L_1V], (instregex "^INSv")>;
516 // ASIMD unzip/zip, Q-form
517 def : InstRW<[A57Write_6cyc_3V], (instregex "^(UZP|ZIP)(1|2)(v16i8|v8i16|v4i32|v2i64)")>;
521 // -----------------------------------------------------------------------------
523 def : InstRW<[A57Write_5cyc_1V], (instregex "^F(ADD|SUB)[DS]rr")>;
525 def A57WriteFPMA : SchedWriteRes<[A57UnitV]> { let Latency = 9; }
526 def A57ReadFPMA5 : SchedReadAdvance<5, [A57WriteFPMA]>;
527 def A57ReadFPM : SchedReadAdvance<0>;
528 def : InstRW<[A57WriteFPMA, A57ReadFPM, A57ReadFPM, A57ReadFPMA5], (instregex "^FN?M(ADD|SUB)[DS]rrr")>;
530 def : InstRW<[A57Write_10cyc_1L_1V], (instregex "^[FSU]CVT[AMNPZ][SU](_Int)?[SU]?[XW]?[DS]?[rds]i?")>;
531 def : InstRW<[A57Write_10cyc_1L_1V], (instregex "^[SU]CVTF")>;
533 def : InstRW<[A57Write_32cyc_1X], (instrs FDIVDrr)>;
534 def : InstRW<[A57Write_18cyc_1X], (instrs FDIVSrr)>;
536 def : InstRW<[A57Write_5cyc_1V], (instregex "^F(MAX|MIN).+rr")>;
538 def : InstRW<[A57Write_5cyc_1V], (instregex "^FRINT.+r")>;
540 def : InstRW<[A57Write_32cyc_1X], (instrs FSQRTDr)>;
541 def : InstRW<[A57Write_18cyc_1X], (instrs FSQRTSr)>;
543 def : InstRW<[A57Write_5cyc_1L, WriteLDHi], (instrs LDNPDi)>;
544 def : InstRW<[A57Write_6cyc_2L, WriteLDHi], (instrs LDNPQi)>;
545 def : InstRW<[A57Write_5cyc_1L, WriteLDHi], (instrs LDNPSi)>;
546 def : InstRW<[A57Write_5cyc_1L, WriteLDHi], (instrs LDPDi)>;
547 def : InstRW<[A57Write_5cyc_1L, WriteLDHi, WriteAdr], (instrs LDPDpost)>;
548 def : InstRW<[A57Write_5cyc_1L, WriteLDHi, WriteAdr], (instrs LDPDpre)>;
549 def : InstRW<[A57Write_6cyc_2L, WriteLDHi], (instrs LDPQi)>;
550 def : InstRW<[A57Write_6cyc_2L, WriteLDHi, WriteAdr], (instrs LDPQpost)>;
551 def : InstRW<[A57Write_6cyc_2L, WriteLDHi, WriteAdr], (instrs LDPQpre)>;
552 def : InstRW<[A57Write_5cyc_1I_2L, WriteLDHi], (instrs LDPSWi)>;
553 def : InstRW<[A57Write_5cyc_1I_2L, WriteLDHi, WriteAdr], (instrs LDPSWpost)>;
554 def : InstRW<[A57Write_5cyc_1I_2L, WriteLDHi, WriteAdr], (instrs LDPSWpre)>;
555 def : InstRW<[A57Write_5cyc_1L, WriteLDHi], (instrs LDPSi)>;
556 def : InstRW<[A57Write_5cyc_1L, WriteLDHi, WriteAdr], (instrs LDPSpost)>;
557 def : InstRW<[A57Write_5cyc_1L, WriteLDHi, WriteAdr], (instrs LDPSpre)>;
558 def : InstRW<[A57Write_5cyc_1L, WriteI], (instrs LDRBpost)>;
559 def : InstRW<[A57Write_5cyc_1L, WriteAdr], (instrs LDRBpre)>;
560 def : InstRW<[A57Write_5cyc_1L, ReadAdrBase], (instrs LDRBroW)>;
561 def : InstRW<[A57Write_5cyc_1L, ReadAdrBase], (instrs LDRBroX)>;
562 def : InstRW<[A57Write_5cyc_1L], (instrs LDRBui)>;
563 def : InstRW<[A57Write_5cyc_1L], (instrs LDRDl)>;
564 def : InstRW<[A57Write_5cyc_1L, WriteI], (instrs LDRDpost)>;
565 def : InstRW<[A57Write_5cyc_1L, WriteAdr], (instrs LDRDpre)>;
566 def : InstRW<[A57Write_5cyc_1L, ReadAdrBase], (instrs LDRDroW)>;
567 def : InstRW<[A57Write_5cyc_1L, ReadAdrBase], (instrs LDRDroX)>;
568 def : InstRW<[A57Write_5cyc_1L], (instrs LDRDui)>;
569 def : InstRW<[A57Write_5cyc_1I_1L, ReadAdrBase], (instrs LDRHHroW)>;
570 def : InstRW<[A57Write_5cyc_1I_1L, ReadAdrBase], (instrs LDRHHroX)>;
571 def : InstRW<[A57Write_5cyc_1L, WriteI], (instrs LDRHpost)>;
572 def : InstRW<[A57Write_5cyc_1L, WriteAdr], (instrs LDRHpre)>;
573 def : InstRW<[A57Write_6cyc_1I_1L, ReadAdrBase], (instrs LDRHroW)>;
574 def : InstRW<[A57Write_6cyc_1I_1L, ReadAdrBase], (instrs LDRHroX)>;
575 def : InstRW<[A57Write_5cyc_1L], (instrs LDRHui)>;
576 def : InstRW<[A57Write_5cyc_1L], (instrs LDRQl)>;
577 def : InstRW<[A57Write_5cyc_1L, WriteI], (instrs LDRQpost)>;
578 def : InstRW<[A57Write_5cyc_1L, WriteAdr], (instrs LDRQpre)>;
579 def : InstRW<[A57Write_6cyc_1I_1L, ReadAdrBase], (instrs LDRQroW)>;
580 def : InstRW<[A57Write_6cyc_1I_1L, ReadAdrBase], (instrs LDRQroX)>;
581 def : InstRW<[A57Write_5cyc_1L], (instrs LDRQui)>;
582 def : InstRW<[A57Write_5cyc_1I_1L, ReadAdrBase], (instrs LDRSHWroW)>;
583 def : InstRW<[A57Write_5cyc_1I_1L, ReadAdrBase], (instrs LDRSHWroX)>;
584 def : InstRW<[A57Write_5cyc_1I_1L, ReadAdrBase], (instrs LDRSHXroW)>;
585 def : InstRW<[A57Write_5cyc_1I_1L, ReadAdrBase], (instrs LDRSHXroX)>;
586 def : InstRW<[A57Write_5cyc_1L], (instrs LDRSl)>;
587 def : InstRW<[A57Write_5cyc_1L, WriteI], (instrs LDRSpost)>;
588 def : InstRW<[A57Write_5cyc_1L, WriteAdr], (instrs LDRSpre)>;
589 def : InstRW<[A57Write_5cyc_1L, ReadAdrBase], (instrs LDRSroW)>;
590 def : InstRW<[A57Write_5cyc_1L, ReadAdrBase], (instrs LDRSroX)>;
591 def : InstRW<[A57Write_5cyc_1L], (instrs LDRSui)>;
592 def : InstRW<[A57Write_5cyc_1L], (instrs LDURBi)>;
593 def : InstRW<[A57Write_5cyc_1L], (instrs LDURDi)>;
594 def : InstRW<[A57Write_5cyc_1L], (instrs LDURHi)>;
595 def : InstRW<[A57Write_5cyc_1L], (instrs LDURQi)>;
596 def : InstRW<[A57Write_5cyc_1L], (instrs LDURSi)>;
598 def : InstRW<[A57Write_2cyc_2S], (instrs STNPDi)>;
599 def : InstRW<[A57Write_4cyc_1I_4S], (instrs STNPQi)>;
600 def : InstRW<[A57Write_2cyc_2S], (instrs STNPXi)>;
601 def : InstRW<[A57Write_2cyc_2S], (instrs STPDi)>;
602 def : InstRW<[WriteAdr, A57Write_2cyc_1I_2S], (instrs STPDpost)>;
603 def : InstRW<[WriteAdr, A57Write_2cyc_1I_2S], (instrs STPDpre)>;
604 def : InstRW<[A57Write_4cyc_1I_4S], (instrs STPQi)>;
605 def : InstRW<[WriteAdr, A57Write_4cyc_1I_4S], (instrs STPQpost)>;
606 def : InstRW<[WriteAdr, A57Write_4cyc_2I_4S], (instrs STPQpre)>;
607 def : InstRW<[WriteAdr, A57Write_1cyc_1I_1S], (instrs STPSpost)>;
608 def : InstRW<[WriteAdr, A57Write_1cyc_1I_1S], (instrs STPSpre)>;
609 def : InstRW<[WriteAdr, A57Write_1cyc_1I_1S], (instrs STPWpost)>;
610 def : InstRW<[WriteAdr, A57Write_1cyc_1I_1S], (instrs STPWpre)>;
611 def : InstRW<[A57Write_2cyc_2S], (instrs STPXi)>;
612 def : InstRW<[WriteAdr, A57Write_2cyc_1I_2S], (instrs STPXpost)>;
613 def : InstRW<[WriteAdr, A57Write_2cyc_1I_2S], (instrs STPXpre)>;
614 def : InstRW<[WriteAdr, A57Write_1cyc_1I_1S, ReadAdrBase], (instrs STRBBpost)>;
615 def : InstRW<[WriteAdr, A57Write_1cyc_1I_1S, ReadAdrBase], (instrs STRBBpre)>;
616 def : InstRW<[WriteAdr, A57Write_1cyc_1I_1S, ReadAdrBase], (instrs STRBpost)>;
617 def : InstRW<[WriteAdr, A57Write_1cyc_1I_1S], (instrs STRBpre)>;
618 def : InstRW<[A57Write_3cyc_1I_1S, ReadAdrBase], (instrs STRBroW)>;
619 def : InstRW<[A57Write_3cyc_1I_1S, ReadAdrBase], (instrs STRBroX)>;
620 def : InstRW<[WriteAdr, A57Write_1cyc_1I_1S, ReadAdrBase], (instrs STRDpost)>;
621 def : InstRW<[WriteAdr, A57Write_1cyc_1I_1S], (instrs STRDpre)>;
622 def : InstRW<[WriteAdr, A57Write_1cyc_1I_1S, ReadAdrBase], (instrs STRHHpost)>;
623 def : InstRW<[WriteAdr, A57Write_1cyc_1I_1S, ReadAdrBase], (instrs STRHHpre)>;
624 def : InstRW<[A57Write_3cyc_1I_1S, ReadAdrBase], (instrs STRHHroW)>;
625 def : InstRW<[A57Write_3cyc_1I_1S, ReadAdrBase], (instrs STRHHroX)>;
626 def : InstRW<[WriteAdr, A57Write_1cyc_1I_1S, ReadAdrBase], (instrs STRHpost)>;
627 def : InstRW<[WriteAdr, A57Write_1cyc_1I_1S], (instrs STRHpre)>;
628 def : InstRW<[A57Write_3cyc_1I_1S, ReadAdrBase], (instrs STRHroW)>;
629 def : InstRW<[A57Write_3cyc_1I_1S, ReadAdrBase], (instrs STRHroX)>;
630 def : InstRW<[WriteAdr, A57Write_2cyc_1I_2S, ReadAdrBase], (instrs STRQpost)>;
631 def : InstRW<[WriteAdr, A57Write_2cyc_1I_2S], (instrs STRQpre)>;
632 def : InstRW<[A57Write_2cyc_1I_2S, ReadAdrBase], (instrs STRQroW)>;
633 def : InstRW<[A57Write_2cyc_1I_2S, ReadAdrBase], (instrs STRQroX)>;
634 def : InstRW<[A57Write_2cyc_1I_2S], (instrs STRQui)>;
635 def : InstRW<[WriteAdr, A57Write_1cyc_1I_1S, ReadAdrBase], (instrs STRSpost)>;
636 def : InstRW<[WriteAdr, A57Write_1cyc_1I_1S], (instrs STRSpre)>;
637 def : InstRW<[WriteAdr, A57Write_1cyc_1I_1S, ReadAdrBase], (instrs STRWpost)>;
638 def : InstRW<[WriteAdr, A57Write_1cyc_1I_1S, ReadAdrBase], (instrs STRWpre)>;
639 def : InstRW<[WriteAdr, A57Write_1cyc_1I_1S, ReadAdrBase], (instrs STRXpost)>;
640 def : InstRW<[WriteAdr, A57Write_1cyc_1I_1S, ReadAdrBase], (instrs STRXpre)>;
641 def : InstRW<[A57Write_2cyc_2S], (instrs STURQi)>;
643 } // SchedModel = CortexA57Model